2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
13 #include <asm/processor.h>
14 #include <asm/tlbflush.h>
15 #include <asm/sections.h>
16 #include <asm/uaccess.h>
17 #include <asm/pgalloc.h>
33 within(unsigned long addr
, unsigned long start
, unsigned long end
)
35 return addr
>= start
&& addr
< end
;
43 * clflush_cache_range - flush a cache range with clflush
44 * @addr: virtual start address
45 * @size: number of bytes to flush
47 * clflush is an unordered instruction which needs fencing with mfence
48 * to avoid ordering issues.
50 void clflush_cache_range(void *vaddr
, unsigned int size
)
52 void *vend
= vaddr
+ size
- 1;
56 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
59 * Flush any possible final partial cacheline:
66 static void __cpa_flush_all(void *arg
)
68 unsigned long cache
= (unsigned long)arg
;
71 * Flush all to work around Errata in early athlons regarding
72 * large page flushing.
76 if (cache
&& boot_cpu_data
.x86_model
>= 4)
80 static void cpa_flush_all(unsigned long cache
)
82 BUG_ON(irqs_disabled());
84 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1, 1);
87 static void __cpa_flush_range(void *arg
)
90 * We could optimize that further and do individual per page
91 * tlb invalidates for a low number of pages. Caveat: we must
92 * flush the high aliases on 64bit as well.
97 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
99 unsigned int i
, level
;
102 BUG_ON(irqs_disabled());
103 WARN_ON(PAGE_ALIGN(start
) != start
);
105 on_each_cpu(__cpa_flush_range
, NULL
, 1, 1);
111 * We only need to flush on one CPU,
112 * clflush is a MESI-coherent instruction that
113 * will cause all other CPUs to flush the same
116 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
117 pte_t
*pte
= lookup_address(addr
, &level
);
120 * Only flush present addresses:
122 if (pte
&& pte_present(*pte
))
123 clflush_cache_range((void *) addr
, PAGE_SIZE
);
127 #define HIGH_MAP_START __START_KERNEL_map
128 #define HIGH_MAP_END (__START_KERNEL_map + KERNEL_TEXT_SIZE)
132 * Converts a virtual address to a X86-64 highmap address
134 static unsigned long virt_to_highmap(void *address
)
137 return __pa((unsigned long)address
) + HIGH_MAP_START
- phys_base
;
139 return (unsigned long)address
;
144 * Certain areas of memory on x86 require very specific protection flags,
145 * for example the BIOS area or kernel text. Callers don't always get this
146 * right (again, ioremap() on BIOS memory is not uncommon) so this function
147 * checks and fixes these known static required protection bits.
149 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
)
151 pgprot_t forbidden
= __pgprot(0);
154 * The BIOS area between 640k and 1Mb needs to be executable for
155 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
157 if (within(__pa(address
), BIOS_BEGIN
, BIOS_END
))
158 pgprot_val(forbidden
) |= _PAGE_NX
;
161 * The kernel text needs to be executable for obvious reasons
162 * Does not cover __inittext since that is gone later on
164 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
165 pgprot_val(forbidden
) |= _PAGE_NX
;
167 * Do the same for the x86-64 high kernel mapping
169 if (within(address
, virt_to_highmap(_text
), virt_to_highmap(_etext
)))
170 pgprot_val(forbidden
) |= _PAGE_NX
;
173 #ifdef CONFIG_DEBUG_RODATA
174 /* The .rodata section needs to be read-only */
175 if (within(address
, (unsigned long)__start_rodata
,
176 (unsigned long)__end_rodata
))
177 pgprot_val(forbidden
) |= _PAGE_RW
;
179 * Do the same for the x86-64 high kernel mapping
181 if (within(address
, virt_to_highmap(__start_rodata
),
182 virt_to_highmap(__end_rodata
)))
183 pgprot_val(forbidden
) |= _PAGE_RW
;
186 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
192 * Lookup the page table entry for a virtual address. Return a pointer
193 * to the entry and the level of the mapping.
195 * Note: We return pud and pmd either when the entry is marked large
196 * or when the present bit is not set. Otherwise we would return a
197 * pointer to a nonexisting mapping.
199 pte_t
*lookup_address(unsigned long address
, int *level
)
201 pgd_t
*pgd
= pgd_offset_k(address
);
205 *level
= PG_LEVEL_NONE
;
209 pud
= pud_offset(pgd
, address
);
212 pmd
= pmd_offset(pud
, address
);
216 *level
= PG_LEVEL_2M
;
217 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
220 *level
= PG_LEVEL_4K
;
221 return pte_offset_kernel(pmd
, address
);
224 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
227 set_pte_atomic(kpte
, pte
);
229 if (!SHARED_KERNEL_PMD
) {
232 list_for_each_entry(page
, &pgd_list
, lru
) {
237 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
238 pud
= pud_offset(pgd
, address
);
239 pmd
= pmd_offset(pud
, address
);
240 set_pte_atomic((pte_t
*)pmd
, pte
);
246 static int try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
247 struct cpa_data
*cpa
)
249 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
;
250 pte_t new_pte
, old_pte
, *tmp
;
251 pgprot_t old_prot
, new_prot
;
252 int level
, res
= CPA_SPLIT
;
255 * An Athlon 64 X2 showed hard hangs if we tried to preserve
256 * largepages and changed the PSE entry from RW to RO.
258 * As AMD CPUs have a long series of erratas in this area,
259 * (and none of the known ones seem to explain this hang),
260 * disable this code until the hang can be debugged:
262 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
265 spin_lock_irqsave(&pgd_lock
, flags
);
267 * Check for races, another CPU might have split this page
270 tmp
= lookup_address(address
, &level
);
276 psize
= PMD_PAGE_SIZE
;
277 pmask
= PMD_PAGE_MASK
;
286 * Calculate the number of pages, which fit into this large
287 * page starting at address:
289 nextpage_addr
= (address
+ psize
) & pmask
;
290 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
291 if (numpages
< cpa
->numpages
)
292 cpa
->numpages
= numpages
;
295 * We are safe now. Check whether the new pgprot is the same:
298 old_prot
= new_prot
= pte_pgprot(old_pte
);
300 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
301 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
302 new_prot
= static_protections(new_prot
, address
);
305 * If there are no changes, return. maxpages has been updated
308 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
314 * We need to change the attributes. Check, whether we can
315 * change the large page in one go. We request a split, when
316 * the address is not aligned and the number of pages is
317 * smaller than the number of pages in the large page. Note
318 * that we limited the number of possible pages already to
319 * the number of pages in the large page.
321 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
323 * The address is aligned and the number of pages
324 * covers the full page.
326 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
327 __set_pmd_pte(kpte
, address
, new_pte
);
333 spin_unlock_irqrestore(&pgd_lock
, flags
);
337 static int split_large_page(pte_t
*kpte
, unsigned long address
)
340 gfp_t gfp_flags
= GFP_KERNEL
;
341 unsigned long flags
, addr
, pfn
;
344 unsigned int i
, level
;
346 #ifdef CONFIG_DEBUG_PAGEALLOC
347 gfp_flags
= GFP_ATOMIC
| __GFP_NOWARN
;
349 base
= alloc_pages(gfp_flags
, 0);
353 spin_lock_irqsave(&pgd_lock
, flags
);
355 * Check for races, another CPU might have split this page
358 tmp
= lookup_address(address
, &level
);
364 address
= __pa(address
);
365 addr
= address
& PMD_PAGE_MASK
;
366 pbase
= (pte_t
*)page_address(base
);
368 paravirt_alloc_pt(&init_mm
, page_to_pfn(base
));
370 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
373 * Get the target pfn from the original entry:
375 pfn
= pte_pfn(*kpte
);
376 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
++)
377 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
380 * Install the new, split up pagetable. Important details here:
382 * On Intel the NX bit of all levels must be cleared to make a
383 * page executable. See section 4.13.2 of Intel 64 and IA-32
384 * Architectures Software Developer's Manual).
386 * Mark the entry present. The current mapping might be
387 * set to not present, which we preserved above.
389 ref_prot
= pte_pgprot(pte_mkexec(pte_clrhuge(*kpte
)));
390 pgprot_val(ref_prot
) |= _PAGE_PRESENT
;
391 __set_pmd_pte(kpte
, address
, mk_pte(base
, ref_prot
));
395 spin_unlock_irqrestore(&pgd_lock
, flags
);
398 __free_pages(base
, 0);
403 static int __change_page_attr(unsigned long address
, struct cpa_data
*cpa
)
405 struct page
*kpte_page
;
410 kpte
= lookup_address(address
, &level
);
414 kpte_page
= virt_to_page(kpte
);
415 BUG_ON(PageLRU(kpte_page
));
416 BUG_ON(PageCompound(kpte_page
));
418 if (level
== PG_LEVEL_4K
) {
419 pte_t new_pte
, old_pte
= *kpte
;
420 pgprot_t new_prot
= pte_pgprot(old_pte
);
422 if(!pte_val(old_pte
)) {
423 printk(KERN_WARNING
"CPA: called for zero pte. "
424 "vaddr = %lx cpa->vaddr = %lx\n", address
,
430 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
431 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
433 new_prot
= static_protections(new_prot
, address
);
436 * We need to keep the pfn from the existing PTE,
437 * after all we're only going to change it's attributes
438 * not the memory it points to
440 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
443 * Do we really change anything ?
445 if (pte_val(old_pte
) != pte_val(new_pte
)) {
446 set_pte_atomic(kpte
, new_pte
);
454 * Check, whether we can keep the large page intact
455 * and just change the pte:
457 res
= try_preserve_large_page(kpte
, address
, cpa
);
462 * When the range fits into the existing large page,
463 * return. cp->numpages and cpa->tlbflush have been updated in
466 if (res
== CPA_NO_SPLIT
)
470 * We have to split the large page:
472 res
= split_large_page(kpte
, address
);
480 * change_page_attr_addr - Change page table attributes in linear mapping
481 * @address: Virtual address in linear mapping.
482 * @prot: New page table attribute (PAGE_*)
484 * Change page attributes of a page in the direct mapping. This is a variant
485 * of change_page_attr() that also works on memory holes that do not have
486 * mem_map entry (pfn_valid() is false).
488 * See change_page_attr() documentation for more details.
490 * Modules and drivers should use the set_memory_* APIs instead.
493 static int change_page_attr_addr(struct cpa_data
*cpa
)
496 unsigned long address
= cpa
->vaddr
;
499 unsigned long phys_addr
= __pa(address
);
502 * If we are inside the high mapped kernel range, then we
503 * fixup the low mapping first. __va() returns the virtual
504 * address in the linear mapping:
506 if (within(address
, HIGH_MAP_START
, HIGH_MAP_END
))
507 address
= (unsigned long) __va(phys_addr
);
510 err
= __change_page_attr(address
, cpa
);
516 * If the physical address is inside the kernel map, we need
517 * to touch the high mapped kernel as well:
519 if (within(phys_addr
, 0, KERNEL_TEXT_SIZE
)) {
521 * Calc the high mapping address. See __phys_addr()
522 * for the non obvious details.
524 * Note that NX and other required permissions are
525 * checked in static_protections().
527 address
= phys_addr
+ HIGH_MAP_START
- phys_base
;
530 * Our high aliases are imprecise, because we check
531 * everything between 0 and KERNEL_TEXT_SIZE, so do
532 * not propagate lookup failures back to users:
534 __change_page_attr(address
, cpa
);
540 static int __change_page_attr_set_clr(struct cpa_data
*cpa
)
542 int ret
, numpages
= cpa
->numpages
;
546 * Store the remaining nr of pages for the large page
547 * preservation check.
549 cpa
->numpages
= numpages
;
550 ret
= change_page_attr_addr(cpa
);
555 * Adjust the number of pages with the result of the
556 * CPA operation. Either a large page has been
557 * preserved or a single page update happened.
559 BUG_ON(cpa
->numpages
> numpages
);
560 numpages
-= cpa
->numpages
;
561 cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
566 static inline int cache_attr(pgprot_t attr
)
568 return pgprot_val(attr
) &
569 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
572 static int change_page_attr_set_clr(unsigned long addr
, int numpages
,
573 pgprot_t mask_set
, pgprot_t mask_clr
)
579 * Check, if we are requested to change a not supported
582 mask_set
= canon_pgprot(mask_set
);
583 mask_clr
= canon_pgprot(mask_clr
);
584 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
))
588 cpa
.numpages
= numpages
;
589 cpa
.mask_set
= mask_set
;
590 cpa
.mask_clr
= mask_clr
;
593 ret
= __change_page_attr_set_clr(&cpa
);
596 * Check whether we really changed something:
602 * No need to flush, when we did not set any of the caching
605 cache
= cache_attr(mask_set
);
608 * On success we use clflush, when the CPU supports it to
609 * avoid the wbindv. If the CPU does not support it and in the
610 * error case we fall back to cpa_flush_all (which uses
613 if (!ret
&& cpu_has_clflush
)
614 cpa_flush_range(addr
, numpages
, cache
);
616 cpa_flush_all(cache
);
621 static inline int change_page_attr_set(unsigned long addr
, int numpages
,
624 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0));
627 static inline int change_page_attr_clear(unsigned long addr
, int numpages
,
630 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
);
633 int set_memory_uc(unsigned long addr
, int numpages
)
635 return change_page_attr_set(addr
, numpages
,
636 __pgprot(_PAGE_PCD
| _PAGE_PWT
));
638 EXPORT_SYMBOL(set_memory_uc
);
640 int set_memory_wb(unsigned long addr
, int numpages
)
642 return change_page_attr_clear(addr
, numpages
,
643 __pgprot(_PAGE_PCD
| _PAGE_PWT
));
645 EXPORT_SYMBOL(set_memory_wb
);
647 int set_memory_x(unsigned long addr
, int numpages
)
649 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_NX
));
651 EXPORT_SYMBOL(set_memory_x
);
653 int set_memory_nx(unsigned long addr
, int numpages
)
655 return change_page_attr_set(addr
, numpages
, __pgprot(_PAGE_NX
));
657 EXPORT_SYMBOL(set_memory_nx
);
659 int set_memory_ro(unsigned long addr
, int numpages
)
661 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_RW
));
664 int set_memory_rw(unsigned long addr
, int numpages
)
666 return change_page_attr_set(addr
, numpages
, __pgprot(_PAGE_RW
));
669 int set_memory_np(unsigned long addr
, int numpages
)
671 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_PRESENT
));
674 int set_pages_uc(struct page
*page
, int numpages
)
676 unsigned long addr
= (unsigned long)page_address(page
);
678 return set_memory_uc(addr
, numpages
);
680 EXPORT_SYMBOL(set_pages_uc
);
682 int set_pages_wb(struct page
*page
, int numpages
)
684 unsigned long addr
= (unsigned long)page_address(page
);
686 return set_memory_wb(addr
, numpages
);
688 EXPORT_SYMBOL(set_pages_wb
);
690 int set_pages_x(struct page
*page
, int numpages
)
692 unsigned long addr
= (unsigned long)page_address(page
);
694 return set_memory_x(addr
, numpages
);
696 EXPORT_SYMBOL(set_pages_x
);
698 int set_pages_nx(struct page
*page
, int numpages
)
700 unsigned long addr
= (unsigned long)page_address(page
);
702 return set_memory_nx(addr
, numpages
);
704 EXPORT_SYMBOL(set_pages_nx
);
706 int set_pages_ro(struct page
*page
, int numpages
)
708 unsigned long addr
= (unsigned long)page_address(page
);
710 return set_memory_ro(addr
, numpages
);
713 int set_pages_rw(struct page
*page
, int numpages
)
715 unsigned long addr
= (unsigned long)page_address(page
);
717 return set_memory_rw(addr
, numpages
);
720 #ifdef CONFIG_DEBUG_PAGEALLOC
722 static int __set_pages_p(struct page
*page
, int numpages
)
724 struct cpa_data cpa
= { .vaddr
= (unsigned long) page_address(page
),
725 .numpages
= numpages
,
726 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
727 .mask_clr
= __pgprot(0)};
729 return __change_page_attr_set_clr(&cpa
);
732 static int __set_pages_np(struct page
*page
, int numpages
)
734 struct cpa_data cpa
= { .vaddr
= (unsigned long) page_address(page
),
735 .numpages
= numpages
,
736 .mask_set
= __pgprot(0),
737 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
)};
739 return __change_page_attr_set_clr(&cpa
);
742 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
744 if (PageHighMem(page
))
747 debug_check_no_locks_freed(page_address(page
),
748 numpages
* PAGE_SIZE
);
752 * If page allocator is not up yet then do not call c_p_a():
754 if (!debug_pagealloc_enabled
)
758 * The return value is ignored - the calls cannot fail,
759 * large pages are disabled at boot time:
762 __set_pages_p(page
, numpages
);
764 __set_pages_np(page
, numpages
);
767 * We should perform an IPI and flush all tlbs,
768 * but that can deadlock->flush only current cpu:
775 * The testcases use internal knowledge of the implementation that shouldn't
776 * be exposed to the rest of the kernel. Include these directly here.
778 #ifdef CONFIG_CPA_DEBUG
779 #include "pageattr-test.c"