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[PATCH] sata_sil24: convert to new probing mechanism and add hotplug support
[linux-2.6/kmemtrace.git] / drivers / scsi / sata_sil24.c
blob97e93392f928d2c34755a9db58e98291fbf0413b
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31 #include <asm/io.h>
32
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.24"
35
36 /*
37 * Port request block (PRB) 32 bytes
38 */
39 struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44 };
45
46 /*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49 struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53 };
54
55 /*
56 * Port multiplier
57 */
58 struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61 };
62
63 enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
89 /* HOST_CTRL bits */
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95
96 /*
97 * Port registers
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
99 */
100 PORT_REGS_SIZE = 0x2000,
101
102 PORT_LRAM = 0x0000, /* 31 LRAM slots and PM regs */
103 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
104
105 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
106 /* 32 bit regs */
107 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
108 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
109 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
110 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
111 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
112 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
113 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
114 PORT_CMD_ERR = 0x1024, /* command error number */
115 PORT_FIS_CFG = 0x1028,
116 PORT_FIFO_THRES = 0x102c,
117 /* 16 bit regs */
118 PORT_DECODE_ERR_CNT = 0x1040,
119 PORT_DECODE_ERR_THRESH = 0x1042,
120 PORT_CRC_ERR_CNT = 0x1044,
121 PORT_CRC_ERR_THRESH = 0x1046,
122 PORT_HSHK_ERR_CNT = 0x1048,
123 PORT_HSHK_ERR_THRESH = 0x104a,
124 /* 32 bit regs */
125 PORT_PHY_CFG = 0x1050,
126 PORT_SLOT_STAT = 0x1800,
127 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
128 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
129 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
130 PORT_SCONTROL = 0x1f00,
131 PORT_SSTATUS = 0x1f04,
132 PORT_SERROR = 0x1f08,
133 PORT_SACTIVE = 0x1f0c,
134
135 /* PORT_CTRL_STAT bits */
136 PORT_CS_PORT_RST = (1 << 0), /* port reset */
137 PORT_CS_DEV_RST = (1 << 1), /* device reset */
138 PORT_CS_INIT = (1 << 2), /* port initialize */
139 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
140 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
141 PORT_CS_RESUME = (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
145
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
154 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
155 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
156 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
157 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
158 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
159 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
160
161 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
162 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
163 PORT_IRQ_UNK_FIS,
164
165 /* bits[27:16] are unmasked (raw) */
166 PORT_IRQ_RAW_SHIFT = 16,
167 PORT_IRQ_MASKED_MASK = 0x7ff,
168 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
169
170 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
171 PORT_IRQ_STEER_SHIFT = 30,
172 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
173
174 /* PORT_CMD_ERR constants */
175 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
176 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
177 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
178 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
179 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
180 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
181 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
182 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
183 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
184 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
185 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
186 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
187 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
188 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
189 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
190 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
191 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
192 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
193 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
194 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
195 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
196 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
197
198 /* bits of PRB control field */
199 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
200 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
201 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
202 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
203 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
204
205 /* PRB protocol field */
206 PRB_PROT_PACKET = (1 << 0),
207 PRB_PROT_TCQ = (1 << 1),
208 PRB_PROT_NCQ = (1 << 2),
209 PRB_PROT_READ = (1 << 3),
210 PRB_PROT_WRITE = (1 << 4),
211 PRB_PROT_TRANSPARENT = (1 << 5),
212
213 /*
214 * Other constants
215 */
216 SGE_TRM = (1 << 31), /* Last SGE in chain */
217 SGE_LNK = (1 << 30), /* linked list
218 Points to SGT, not SGE */
219 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
220 data address ignored */
221
222 SIL24_MAX_CMDS = 31,
223
224 /* board id */
225 BID_SIL3124 = 0,
226 BID_SIL3132 = 1,
227 BID_SIL3131 = 2,
228
229 /* host flags */
230 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
231 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
232 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
233 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
234
235 IRQ_STAT_4PORTS = 0xf,
236 };
237
238 struct sil24_ata_block {
239 struct sil24_prb prb;
240 struct sil24_sge sge[LIBATA_MAX_PRD];
241 };
242
243 struct sil24_atapi_block {
244 struct sil24_prb prb;
245 u8 cdb[16];
246 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
247 };
248
249 union sil24_cmd_block {
250 struct sil24_ata_block ata;
251 struct sil24_atapi_block atapi;
252 };
253
254 static struct sil24_cerr_info {
255 unsigned int err_mask, action;
256 const char *desc;
257 } sil24_cerr_db[] = {
258 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
259 "device error" },
260 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
261 "device error via D2H FIS" },
262 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
263 "device error via SDB FIS" },
264 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
265 "error in data FIS" },
266 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
267 "failed to transmit command FIS" },
268 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
269 "protocol mismatch" },
270 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
271 "data directon mismatch" },
272 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
273 "ran out of SGEs while writing" },
274 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
275 "ran out of SGEs while reading" },
276 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
277 "invalid data directon for ATAPI CDB" },
278 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
279 "SGT no on qword boundary" },
280 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
281 "PCI target abort while fetching SGT" },
282 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
283 "PCI master abort while fetching SGT" },
284 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
285 "PCI parity error while fetching SGT" },
286 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
287 "PRB not on qword boundary" },
288 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
289 "PCI target abort while fetching PRB" },
290 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI master abort while fetching PRB" },
292 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI parity error while fetching PRB" },
294 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "undefined error while transferring data" },
296 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
297 "PCI target abort while transferring data" },
298 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI master abort while transferring data" },
300 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI parity error while transferring data" },
302 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
303 "FIS received while sending service FIS" },
304 };
305
306 /*
307 * ap->private_data
308 *
309 * The preview driver always returned 0 for status. We emulate it
310 * here from the previous interrupt.
311 */
312 struct sil24_port_priv {
313 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
314 dma_addr_t cmd_block_dma; /* DMA base addr for them */
315 struct ata_taskfile tf; /* Cached taskfile registers */
316 };
317
318 /* ap->host_set->private_data */
319 struct sil24_host_priv {
320 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
321 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
322 };
323
324 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
325 static u8 sil24_check_status(struct ata_port *ap);
326 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
327 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
328 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
329 static void sil24_qc_prep(struct ata_queued_cmd *qc);
330 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
331 static void sil24_irq_clear(struct ata_port *ap);
332 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
333 static void sil24_freeze(struct ata_port *ap);
334 static void sil24_thaw(struct ata_port *ap);
335 static void sil24_error_handler(struct ata_port *ap);
336 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
337 static int sil24_port_start(struct ata_port *ap);
338 static void sil24_port_stop(struct ata_port *ap);
339 static void sil24_host_stop(struct ata_host_set *host_set);
340 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
341
342 static const struct pci_device_id sil24_pci_tbl[] = {
343 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
344 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
345 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
346 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
347 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
348 { } /* terminate list */
349 };
350
351 static struct pci_driver sil24_pci_driver = {
352 .name = DRV_NAME,
353 .id_table = sil24_pci_tbl,
354 .probe = sil24_init_one,
355 .remove = ata_pci_remove_one, /* safe? */
356 };
357
358 static struct scsi_host_template sil24_sht = {
359 .module = THIS_MODULE,
360 .name = DRV_NAME,
361 .ioctl = ata_scsi_ioctl,
362 .queuecommand = ata_scsi_queuecmd,
363 .change_queue_depth = ata_scsi_change_queue_depth,
364 .can_queue = SIL24_MAX_CMDS,
365 .this_id = ATA_SHT_THIS_ID,
366 .sg_tablesize = LIBATA_MAX_PRD,
367 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
368 .emulated = ATA_SHT_EMULATED,
369 .use_clustering = ATA_SHT_USE_CLUSTERING,
370 .proc_name = DRV_NAME,
371 .dma_boundary = ATA_DMA_BOUNDARY,
372 .slave_configure = ata_scsi_slave_config,
373 .slave_destroy = ata_scsi_slave_destroy,
374 .bios_param = ata_std_bios_param,
375 };
376
377 static const struct ata_port_operations sil24_ops = {
378 .port_disable = ata_port_disable,
379
380 .dev_config = sil24_dev_config,
381
382 .check_status = sil24_check_status,
383 .check_altstatus = sil24_check_status,
384 .dev_select = ata_noop_dev_select,
385
386 .tf_read = sil24_tf_read,
387
388 .qc_prep = sil24_qc_prep,
389 .qc_issue = sil24_qc_issue,
390
391 .irq_handler = sil24_interrupt,
392 .irq_clear = sil24_irq_clear,
393
394 .scr_read = sil24_scr_read,
395 .scr_write = sil24_scr_write,
396
397 .freeze = sil24_freeze,
398 .thaw = sil24_thaw,
399 .error_handler = sil24_error_handler,
400 .post_internal_cmd = sil24_post_internal_cmd,
401
402 .port_start = sil24_port_start,
403 .port_stop = sil24_port_stop,
404 .host_stop = sil24_host_stop,
405 };
406
407 /*
408 * Use bits 30-31 of host_flags to encode available port numbers.
409 * Current maxium is 4.
410 */
411 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
412 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
413
414 static struct ata_port_info sil24_port_info[] = {
415 /* sil_3124 */
416 {
417 .sht = &sil24_sht,
418 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
419 SIL24_FLAG_PCIX_IRQ_WOC,
420 .pio_mask = 0x1f, /* pio0-4 */
421 .mwdma_mask = 0x07, /* mwdma0-2 */
422 .udma_mask = 0x3f, /* udma0-5 */
423 .port_ops = &sil24_ops,
424 },
425 /* sil_3132 */
426 {
427 .sht = &sil24_sht,
428 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
429 .pio_mask = 0x1f, /* pio0-4 */
430 .mwdma_mask = 0x07, /* mwdma0-2 */
431 .udma_mask = 0x3f, /* udma0-5 */
432 .port_ops = &sil24_ops,
433 },
434 /* sil_3131/sil_3531 */
435 {
436 .sht = &sil24_sht,
437 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
438 .pio_mask = 0x1f, /* pio0-4 */
439 .mwdma_mask = 0x07, /* mwdma0-2 */
440 .udma_mask = 0x3f, /* udma0-5 */
441 .port_ops = &sil24_ops,
442 },
443 };
444
445 static int sil24_tag(int tag)
446 {
447 if (unlikely(ata_tag_internal(tag)))
448 return 0;
449 return tag;
450 }
451
452 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
453 {
454 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
455
456 if (dev->cdb_len == 16)
457 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
458 else
459 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
460 }
461
462 static inline void sil24_update_tf(struct ata_port *ap)
463 {
464 struct sil24_port_priv *pp = ap->private_data;
465 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
466 struct sil24_prb __iomem *prb = port;
467 u8 fis[6 * 4];
468
469 memcpy_fromio(fis, prb->fis, 6 * 4);
470 ata_tf_from_fis(fis, &pp->tf);
471 }
472
473 static u8 sil24_check_status(struct ata_port *ap)
474 {
475 struct sil24_port_priv *pp = ap->private_data;
476 return pp->tf.command;
477 }
478
479 static int sil24_scr_map[] = {
480 [SCR_CONTROL] = 0,
481 [SCR_STATUS] = 1,
482 [SCR_ERROR] = 2,
483 [SCR_ACTIVE] = 3,
484 };
485
486 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
487 {
488 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
489 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
490 void __iomem *addr;
491 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
492 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
493 }
494 return 0xffffffffU;
495 }
496
497 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
498 {
499 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
500 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
501 void __iomem *addr;
502 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
503 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
504 }
505 }
506
507 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
508 {
509 struct sil24_port_priv *pp = ap->private_data;
510 *tf = pp->tf;
511 }
512
513 static int sil24_init_port(struct ata_port *ap)
514 {
515 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
516 u32 tmp;
517
518 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
519 ata_wait_register(port + PORT_CTRL_STAT,
520 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
521 tmp = ata_wait_register(port + PORT_CTRL_STAT,
522 PORT_CS_RDY, 0, 10, 100);
523
524 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
525 return -EIO;
526 return 0;
527 }
528
529 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
530 {
531 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
532 struct sil24_port_priv *pp = ap->private_data;
533 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
534 dma_addr_t paddr = pp->cmd_block_dma;
535 u32 mask, irq_stat;
536 const char *reason;
537
538 DPRINTK("ENTER\n");
539
540 if (ata_port_offline(ap)) {
541 DPRINTK("PHY reports no device\n");
542 *class = ATA_DEV_NONE;
543 goto out;
544 }
545
546 /* put the port into known state */
547 if (sil24_init_port(ap)) {
548 reason ="port not ready";
549 goto err;
550 }
551
552 /* do SRST */
553 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
554 prb->fis[1] = 0; /* no PM yet */
555
556 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
557 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
558
559 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
560 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
561 100, ATA_TMOUT_BOOT / HZ * 1000);
562
563 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
564 irq_stat >>= PORT_IRQ_RAW_SHIFT;
565
566 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
567 if (irq_stat & PORT_IRQ_ERROR)
568 reason = "SRST command error";
569 else
570 reason = "timeout";
571 goto err;
572 }
573
574 sil24_update_tf(ap);
575 *class = ata_dev_classify(&pp->tf);
576
577 if (*class == ATA_DEV_UNKNOWN)
578 *class = ATA_DEV_NONE;
579
580 out:
581 DPRINTK("EXIT, class=%u\n", *class);
582 return 0;
583
584 err:
585 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
586 return -EIO;
587 }
588
589 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
590 {
591 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
592 const char *reason;
593 int tout_msec, rc;
594 u32 tmp;
595
596 /* sil24 does the right thing(tm) without any protection */
597 sata_set_spd(ap);
598
599 tout_msec = 100;
600 if (ata_port_online(ap))
601 tout_msec = 5000;
602
603 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
604 tmp = ata_wait_register(port + PORT_CTRL_STAT,
605 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
606
607 /* SStatus oscillates between zero and valid status after
608 * DEV_RST, debounce it.
609 */
610 rc = sata_phy_debounce(ap, sata_deb_timing_before_fsrst);
611 if (rc) {
612 reason = "PHY debouncing failed";
613 goto err;
614 }
615
616 if (tmp & PORT_CS_DEV_RST) {
617 if (ata_port_offline(ap))
618 return 0;
619 reason = "link not ready";
620 goto err;
621 }
622
623 /* Sil24 doesn't store signature FIS after hardreset, so we
624 * can't wait for BSY to clear. Some devices take a long time
625 * to get ready and those devices will choke if we don't wait
626 * for BSY clearance here. Tell libata to perform follow-up
627 * softreset.
628 */
629 return -EAGAIN;
630
631 err:
632 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
633 return -EIO;
634 }
635
636 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
637 struct sil24_sge *sge)
638 {
639 struct scatterlist *sg;
640 unsigned int idx = 0;
641
642 ata_for_each_sg(sg, qc) {
643 sge->addr = cpu_to_le64(sg_dma_address(sg));
644 sge->cnt = cpu_to_le32(sg_dma_len(sg));
645 if (ata_sg_is_last(sg, qc))
646 sge->flags = cpu_to_le32(SGE_TRM);
647 else
648 sge->flags = 0;
649
650 sge++;
651 idx++;
652 }
653 }
654
655 static void sil24_qc_prep(struct ata_queued_cmd *qc)
656 {
657 struct ata_port *ap = qc->ap;
658 struct sil24_port_priv *pp = ap->private_data;
659 union sil24_cmd_block *cb;
660 struct sil24_prb *prb;
661 struct sil24_sge *sge;
662 u16 ctrl = 0;
663
664 cb = &pp->cmd_block[sil24_tag(qc->tag)];
665
666 switch (qc->tf.protocol) {
667 case ATA_PROT_PIO:
668 case ATA_PROT_DMA:
669 case ATA_PROT_NCQ:
670 case ATA_PROT_NODATA:
671 prb = &cb->ata.prb;
672 sge = cb->ata.sge;
673 break;
674
675 case ATA_PROT_ATAPI:
676 case ATA_PROT_ATAPI_DMA:
677 case ATA_PROT_ATAPI_NODATA:
678 prb = &cb->atapi.prb;
679 sge = cb->atapi.sge;
680 memset(cb->atapi.cdb, 0, 32);
681 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
682
683 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
684 if (qc->tf.flags & ATA_TFLAG_WRITE)
685 ctrl = PRB_CTRL_PACKET_WRITE;
686 else
687 ctrl = PRB_CTRL_PACKET_READ;
688 }
689 break;
690
691 default:
692 prb = NULL; /* shut up, gcc */
693 sge = NULL;
694 BUG();
695 }
696
697 prb->ctrl = cpu_to_le16(ctrl);
698 ata_tf_to_fis(&qc->tf, prb->fis, 0);
699
700 if (qc->flags & ATA_QCFLAG_DMAMAP)
701 sil24_fill_sg(qc, sge);
702 }
703
704 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
705 {
706 struct ata_port *ap = qc->ap;
707 struct sil24_port_priv *pp = ap->private_data;
708 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
709 unsigned int tag = sil24_tag(qc->tag);
710 dma_addr_t paddr;
711 void __iomem *activate;
712
713 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
714 activate = port + PORT_CMD_ACTIVATE + tag * 8;
715
716 writel((u32)paddr, activate);
717 writel((u64)paddr >> 32, activate + 4);
718
719 return 0;
720 }
721
722 static void sil24_irq_clear(struct ata_port *ap)
723 {
724 /* unused */
725 }
726
727 static void sil24_freeze(struct ata_port *ap)
728 {
729 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
730
731 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
732 * PORT_IRQ_ENABLE instead.
733 */
734 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
735 }
736
737 static void sil24_thaw(struct ata_port *ap)
738 {
739 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
740 u32 tmp;
741
742 /* clear IRQ */
743 tmp = readl(port + PORT_IRQ_STAT);
744 writel(tmp, port + PORT_IRQ_STAT);
745
746 /* turn IRQ back on */
747 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
748 }
749
750 static void sil24_error_intr(struct ata_port *ap)
751 {
752 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
753 struct ata_eh_info *ehi = &ap->eh_info;
754 int freeze = 0;
755 u32 irq_stat;
756
757 /* on error, we need to clear IRQ explicitly */
758 irq_stat = readl(port + PORT_IRQ_STAT);
759 writel(irq_stat, port + PORT_IRQ_STAT);
760
761 /* first, analyze and record host port events */
762 ata_ehi_clear_desc(ehi);
763
764 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
765
766 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
767 ata_ehi_hotplugged(ehi);
768 ata_ehi_push_desc(ehi, ", %s",
769 irq_stat & PORT_IRQ_PHYRDY_CHG ?
770 "PHY RDY changed" : "device exchanged");
771 freeze = 1;
772 }
773
774 if (irq_stat & PORT_IRQ_UNK_FIS) {
775 ehi->err_mask |= AC_ERR_HSM;
776 ehi->action |= ATA_EH_SOFTRESET;
777 ata_ehi_push_desc(ehi , ", unknown FIS");
778 freeze = 1;
779 }
780
781 /* deal with command error */
782 if (irq_stat & PORT_IRQ_ERROR) {
783 struct sil24_cerr_info *ci = NULL;
784 unsigned int err_mask = 0, action = 0;
785 struct ata_queued_cmd *qc;
786 u32 cerr;
787
788 /* analyze CMD_ERR */
789 cerr = readl(port + PORT_CMD_ERR);
790 if (cerr < ARRAY_SIZE(sil24_cerr_db))
791 ci = &sil24_cerr_db[cerr];
792
793 if (ci && ci->desc) {
794 err_mask |= ci->err_mask;
795 action |= ci->action;
796 ata_ehi_push_desc(ehi, ", %s", ci->desc);
797 } else {
798 err_mask |= AC_ERR_OTHER;
799 action |= ATA_EH_SOFTRESET;
800 ata_ehi_push_desc(ehi, ", unknown command error %d",
801 cerr);
802 }
803
804 /* record error info */
805 qc = ata_qc_from_tag(ap, ap->active_tag);
806 if (qc) {
807 sil24_update_tf(ap);
808 qc->err_mask |= err_mask;
809 } else
810 ehi->err_mask |= err_mask;
811
812 ehi->action |= action;
813 }
814
815 /* freeze or abort */
816 if (freeze)
817 ata_port_freeze(ap);
818 else
819 ata_port_abort(ap);
820 }
821
822 static void sil24_finish_qc(struct ata_queued_cmd *qc)
823 {
824 if (qc->flags & ATA_QCFLAG_RESULT_TF)
825 sil24_update_tf(qc->ap);
826 }
827
828 static inline void sil24_host_intr(struct ata_port *ap)
829 {
830 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
831 u32 slot_stat, qc_active;
832 int rc;
833
834 slot_stat = readl(port + PORT_SLOT_STAT);
835
836 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
837 sil24_error_intr(ap);
838 return;
839 }
840
841 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
842 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
843
844 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
845 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
846 if (rc > 0)
847 return;
848 if (rc < 0) {
849 struct ata_eh_info *ehi = &ap->eh_info;
850 ehi->err_mask |= AC_ERR_HSM;
851 ehi->action |= ATA_EH_SOFTRESET;
852 ata_port_freeze(ap);
853 return;
854 }
855
856 if (ata_ratelimit())
857 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
858 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
859 slot_stat, ap->active_tag, ap->sactive);
860 }
861
862 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
863 {
864 struct ata_host_set *host_set = dev_instance;
865 struct sil24_host_priv *hpriv = host_set->private_data;
866 unsigned handled = 0;
867 u32 status;
868 int i;
869
870 status = readl(hpriv->host_base + HOST_IRQ_STAT);
871
872 if (status == 0xffffffff) {
873 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
874 "PCI fault or device removal?\n");
875 goto out;
876 }
877
878 if (!(status & IRQ_STAT_4PORTS))
879 goto out;
880
881 spin_lock(&host_set->lock);
882
883 for (i = 0; i < host_set->n_ports; i++)
884 if (status & (1 << i)) {
885 struct ata_port *ap = host_set->ports[i];
886 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
887 sil24_host_intr(host_set->ports[i]);
888 handled++;
889 } else
890 printk(KERN_ERR DRV_NAME
891 ": interrupt from disabled port %d\n", i);
892 }
893
894 spin_unlock(&host_set->lock);
895 out:
896 return IRQ_RETVAL(handled);
897 }
898
899 static void sil24_error_handler(struct ata_port *ap)
900 {
901 struct ata_eh_context *ehc = &ap->eh_context;
902
903 if (sil24_init_port(ap)) {
904 ata_eh_freeze_port(ap);
905 ehc->i.action |= ATA_EH_HARDRESET;
906 }
907
908 /* perform recovery */
909 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
910 ata_std_postreset);
911 }
912
913 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
914 {
915 struct ata_port *ap = qc->ap;
916
917 if (qc->flags & ATA_QCFLAG_FAILED)
918 qc->err_mask |= AC_ERR_OTHER;
919
920 /* make DMA engine forget about the failed command */
921 if (qc->err_mask)
922 sil24_init_port(ap);
923 }
924
925 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
926 {
927 const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS;
928
929 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
930 }
931
932 static int sil24_port_start(struct ata_port *ap)
933 {
934 struct device *dev = ap->host_set->dev;
935 struct sil24_port_priv *pp;
936 union sil24_cmd_block *cb;
937 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
938 dma_addr_t cb_dma;
939 int rc = -ENOMEM;
940
941 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
942 if (!pp)
943 goto err_out;
944
945 pp->tf.command = ATA_DRDY;
946
947 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
948 if (!cb)
949 goto err_out_pp;
950 memset(cb, 0, cb_size);
951
952 rc = ata_pad_alloc(ap, dev);
953 if (rc)
954 goto err_out_pad;
955
956 pp->cmd_block = cb;
957 pp->cmd_block_dma = cb_dma;
958
959 ap->private_data = pp;
960
961 return 0;
962
963 err_out_pad:
964 sil24_cblk_free(pp, dev);
965 err_out_pp:
966 kfree(pp);
967 err_out:
968 return rc;
969 }
970
971 static void sil24_port_stop(struct ata_port *ap)
972 {
973 struct device *dev = ap->host_set->dev;
974 struct sil24_port_priv *pp = ap->private_data;
975
976 sil24_cblk_free(pp, dev);
977 ata_pad_free(ap, dev);
978 kfree(pp);
979 }
980
981 static void sil24_host_stop(struct ata_host_set *host_set)
982 {
983 struct sil24_host_priv *hpriv = host_set->private_data;
984 struct pci_dev *pdev = to_pci_dev(host_set->dev);
985
986 pci_iounmap(pdev, hpriv->host_base);
987 pci_iounmap(pdev, hpriv->port_base);
988 kfree(hpriv);
989 }
990
991 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
992 {
993 static int printed_version = 0;
994 unsigned int board_id = (unsigned int)ent->driver_data;
995 struct ata_port_info *pinfo = &sil24_port_info[board_id];
996 struct ata_probe_ent *probe_ent = NULL;
997 struct sil24_host_priv *hpriv = NULL;
998 void __iomem *host_base = NULL;
999 void __iomem *port_base = NULL;
1000 int i, rc;
1001 u32 tmp;
1002
1003 if (!printed_version++)
1004 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1005
1006 rc = pci_enable_device(pdev);
1007 if (rc)
1008 return rc;
1009
1010 rc = pci_request_regions(pdev, DRV_NAME);
1011 if (rc)
1012 goto out_disable;
1013
1014 rc = -ENOMEM;
1015 /* map mmio registers */
1016 host_base = pci_iomap(pdev, 0, 0);
1017 if (!host_base)
1018 goto out_free;
1019 port_base = pci_iomap(pdev, 2, 0);
1020 if (!port_base)
1021 goto out_free;
1022
1023 /* allocate & init probe_ent and hpriv */
1024 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1025 if (!probe_ent)
1026 goto out_free;
1027
1028 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1029 if (!hpriv)
1030 goto out_free;
1031
1032 probe_ent->dev = pci_dev_to_dev(pdev);
1033 INIT_LIST_HEAD(&probe_ent->node);
1034
1035 probe_ent->sht = pinfo->sht;
1036 probe_ent->host_flags = pinfo->host_flags;
1037 probe_ent->pio_mask = pinfo->pio_mask;
1038 probe_ent->mwdma_mask = pinfo->mwdma_mask;
1039 probe_ent->udma_mask = pinfo->udma_mask;
1040 probe_ent->port_ops = pinfo->port_ops;
1041 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
1042
1043 probe_ent->irq = pdev->irq;
1044 probe_ent->irq_flags = SA_SHIRQ;
1045 probe_ent->mmio_base = port_base;
1046 probe_ent->private_data = hpriv;
1047
1048 hpriv->host_base = host_base;
1049 hpriv->port_base = port_base;
1050
1051 /*
1052 * Configure the device
1053 */
1054 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1055 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1056 if (rc) {
1057 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1058 if (rc) {
1059 dev_printk(KERN_ERR, &pdev->dev,
1060 "64-bit DMA enable failed\n");
1061 goto out_free;
1062 }
1063 }
1064 } else {
1065 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1066 if (rc) {
1067 dev_printk(KERN_ERR, &pdev->dev,
1068 "32-bit DMA enable failed\n");
1069 goto out_free;
1070 }
1071 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1072 if (rc) {
1073 dev_printk(KERN_ERR, &pdev->dev,
1074 "32-bit consistent DMA enable failed\n");
1075 goto out_free;
1076 }
1077 }
1078
1079 /* GPIO off */
1080 writel(0, host_base + HOST_FLASH_CMD);
1081
1082 /* Apply workaround for completion IRQ loss on PCI-X errata */
1083 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1084 tmp = readl(host_base + HOST_CTRL);
1085 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1086 dev_printk(KERN_INFO, &pdev->dev,
1087 "Applying completion IRQ loss on PCI-X "
1088 "errata fix\n");
1089 else
1090 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1091 }
1092
1093 /* clear global reset & mask interrupts during initialization */
1094 writel(0, host_base + HOST_CTRL);
1095
1096 for (i = 0; i < probe_ent->n_ports; i++) {
1097 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1098 unsigned long portu = (unsigned long)port;
1099
1100 probe_ent->port[i].cmd_addr = portu;
1101 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1102
1103 ata_std_ports(&probe_ent->port[i]);
1104
1105 /* Initial PHY setting */
1106 writel(0x20c, port + PORT_PHY_CFG);
1107
1108 /* Clear port RST */
1109 tmp = readl(port + PORT_CTRL_STAT);
1110 if (tmp & PORT_CS_PORT_RST) {
1111 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1112 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1113 PORT_CS_PORT_RST,
1114 PORT_CS_PORT_RST, 10, 100);
1115 if (tmp & PORT_CS_PORT_RST)
1116 dev_printk(KERN_ERR, &pdev->dev,
1117 "failed to clear port RST\n");
1118 }
1119
1120 /* Configure IRQ WoC */
1121 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1122 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1123 else
1124 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1125
1126 /* Zero error counters. */
1127 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1128 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1129 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1130 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1131 writel(0x0000, port + PORT_CRC_ERR_CNT);
1132 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1133
1134 /* Always use 64bit activation */
1135 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1136
1137 /* Clear port multiplier enable and resume bits */
1138 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
1139 }
1140
1141 /* Turn on interrupts */
1142 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1143
1144 pci_set_master(pdev);
1145
1146 /* FIXME: check ata_device_add return value */
1147 ata_device_add(probe_ent);
1148
1149 kfree(probe_ent);
1150 return 0;
1151
1152 out_free:
1153 if (host_base)
1154 pci_iounmap(pdev, host_base);
1155 if (port_base)
1156 pci_iounmap(pdev, port_base);
1157 kfree(probe_ent);
1158 kfree(hpriv);
1159 pci_release_regions(pdev);
1160 out_disable:
1161 pci_disable_device(pdev);
1162 return rc;
1163 }
1164
1165 static int __init sil24_init(void)
1166 {
1167 return pci_module_init(&sil24_pci_driver);
1168 }
1169
1170 static void __exit sil24_exit(void)
1171 {
1172 pci_unregister_driver(&sil24_pci_driver);
1173 }
1174
1175 MODULE_AUTHOR("Tejun Heo");
1176 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1177 MODULE_LICENSE("GPL");
1178 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1179
1180 module_init(sil24_init);
1181 module_exit(sil24_exit);
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