drivers/net/sungem.h

   1 /* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $
   2  * sungem.h: Definitions for Sun GEM ethernet driver.
   3  *
   4  * Copyright (C) 2000 David S. Miller (davem@redhat.com)
   5  */
   6
   7 #ifndef _SUNGEM_H
   8 #define _SUNGEM_H
   9
  10 /* Global Registers */
  11 #define GREG_SEBSTATE   0x0000UL        /* SEB State Register           */
  12 #define GREG_CFG        0x0004UL        /* Configuration Register       */
  13 #define GREG_STAT       0x000CUL        /* Status Register              */
  14 #define GREG_IMASK      0x0010UL        /* Interrupt Mask Register      */
  15 #define GREG_IACK       0x0014UL        /* Interrupt ACK Register       */
  16 #define GREG_STAT2      0x001CUL        /* Alias of GREG_STAT           */
  17 #define GREG_PCIESTAT   0x1000UL        /* PCI Error Status Register    */
  18 #define GREG_PCIEMASK   0x1004UL        /* PCI Error Mask Register      */
  19 #define GREG_BIFCFG     0x1008UL        /* BIF Configuration Register   */
  20 #define GREG_BIFDIAG    0x100CUL        /* BIF Diagnostics Register     */
  21 #define GREG_SWRST      0x1010UL        /* Software Reset Register      */
  22
  23 /* Global SEB State Register */
  24 #define GREG_SEBSTATE_ARB       0x00000003      /* State of Arbiter             */
  25 #define GREG_SEBSTATE_RXWON     0x00000004      /* RX won internal arbitration  */
  26
  27 /* Global Configuration Register */
  28 #define GREG_CFG_IBURST         0x00000001      /* Infinite Burst               */
  29 #define GREG_CFG_TXDMALIM       0x0000003e      /* TX DMA grant limit           */
  30 #define GREG_CFG_RXDMALIM       0x000007c0      /* RX DMA grant limit           */
  31 #define GREG_CFG_RONPAULBIT     0x00000800      /* Use mem read multiple for PCI read
  32                                                  * after infinite burst (Apple) */
  33 #define GREG_CFG_ENBUG2FIX      0x00001000      /* Fix Rx hang after overflow */
  34
  35 /* Global Interrupt Status Register.
  36  *
  37  * Reading this register automatically clears bits 0 through 6.
  38  * This auto-clearing does not occur when the alias at GREG_STAT2
  39  * is read instead.  The rest of the interrupt bits only clear when
  40  * the secondary interrupt status register corresponding to that
  41  * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by
  42  * reading PCS_ISTAT).
  43  */
  44 #define GREG_STAT_TXINTME       0x00000001      /* TX INTME frame transferred   */
  45 #define GREG_STAT_TXALL         0x00000002      /* All TX frames transferred    */
  46 #define GREG_STAT_TXDONE        0x00000004      /* One TX frame transferred     */
  47 #define GREG_STAT_RXDONE        0x00000010      /* One RX frame arrived         */
  48 #define GREG_STAT_RXNOBUF       0x00000020      /* No free RX buffers available */
  49 #define GREG_STAT_RXTAGERR      0x00000040      /* RX tag framing is corrupt    */
  50 #define GREG_STAT_PCS           0x00002000      /* PCS signalled interrupt      */
  51 #define GREG_STAT_TXMAC         0x00004000      /* TX MAC signalled interrupt   */
  52 #define GREG_STAT_RXMAC         0x00008000      /* RX MAC signalled interrupt   */
  53 #define GREG_STAT_MAC           0x00010000      /* MAC Control signalled irq    */
  54 #define GREG_STAT_MIF           0x00020000      /* MIF signalled interrupt      */
  55 #define GREG_STAT_PCIERR        0x00040000      /* PCI Error interrupt          */
  56 #define GREG_STAT_TXNR          0xfff80000      /* == TXDMA_TXDONE reg val      */
  57 #define GREG_STAT_TXNR_SHIFT    19
  58
  59 #define GREG_STAT_ABNORMAL      (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \
  60                                  GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \
  61                                  GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR)
  62
  63 /* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT.
  64  * Bits set in GREG_IMASK will prevent that interrupt type from being
  65  * signalled to the cpu.  GREG_IACK can be used to clear specific top-level
  66  * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6.
  67  * Setting the bit will clear that interrupt, clear bits will have no effect
  68  * on GREG_STAT.
  69  */
  70
  71 /* Global PCI Error Status Register */
  72 #define GREG_PCIESTAT_BADACK    0x00000001      /* No ACK64# during ABS64 cycle */
  73 #define GREG_PCIESTAT_DTRTO     0x00000002      /* Delayed transaction timeout  */
  74 #define GREG_PCIESTAT_OTHER     0x00000004      /* Other PCI error, check cfg space */
  75
  76 /* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT.
  77  * Bits set in GREG_PCIEMASK will prevent that interrupt type from being
  78  * signalled to the cpu.
  79  */
  80
  81 /* Global BIF Configuration Register */
  82 #define GREG_BIFCFG_SLOWCLK     0x00000001      /* Set if PCI runs < 25Mhz      */
  83 #define GREG_BIFCFG_B64DIS      0x00000002      /* Disable 64bit wide data cycle*/
  84 #define GREG_BIFCFG_M66EN       0x00000004      /* Set if on 66Mhz PCI segment  */
  85
  86 /* Global BIF Diagnostics Register */
  87 #define GREG_BIFDIAG_BURSTSM    0x007f0000      /* PCI Burst state machine      */
  88 #define GREG_BIFDIAG_BIFSM      0xff000000      /* BIF state machine            */
  89
  90 /* Global Software Reset Register.
  91  *
  92  * This register is used to perform a global reset of the RX and TX portions
  93  * of the GEM asic.  Setting the RX or TX reset bit will start the reset.
  94  * The driver _MUST_ poll these bits until they clear.  One may not attempt
  95  * to program any other part of GEM until the bits clear.
  96  */
  97 #define GREG_SWRST_TXRST        0x00000001      /* TX Software Reset            */
  98 #define GREG_SWRST_RXRST        0x00000002      /* RX Software Reset            */
  99 #define GREG_SWRST_RSTOUT       0x00000004      /* Force RST# pin active        */
 100 #define GREG_SWRST_CACHESIZE    0x00ff0000      /* RIO only: cache line size    */
 101 #define GREG_SWRST_CACHE_SHIFT  16
 102
 103 /* TX DMA Registers */
 104 #define TXDMA_KICK      0x2000UL        /* TX Kick Register             */
 105 #define TXDMA_CFG       0x2004UL        /* TX Configuration Register    */
 106 #define TXDMA_DBLOW     0x2008UL        /* TX Desc. Base Low            */
 107 #define TXDMA_DBHI      0x200CUL        /* TX Desc. Base High           */
 108 #define TXDMA_FWPTR     0x2014UL        /* TX FIFO Write Pointer        */
 109 #define TXDMA_FSWPTR    0x2018UL        /* TX FIFO Shadow Write Pointer */
 110 #define TXDMA_FRPTR     0x201CUL        /* TX FIFO Read Pointer         */
 111 #define TXDMA_FSRPTR    0x2020UL        /* TX FIFO Shadow Read Pointer  */
 112 #define TXDMA_PCNT      0x2024UL        /* TX FIFO Packet Counter       */
 113 #define TXDMA_SMACHINE  0x2028UL        /* TX State Machine Register    */
 114 #define TXDMA_DPLOW     0x2030UL        /* TX Data Pointer Low          */
 115 #define TXDMA_DPHI      0x2034UL        /* TX Data Pointer High         */
 116 #define TXDMA_TXDONE    0x2100UL        /* TX Completion Register       */
 117 #define TXDMA_FADDR     0x2104UL        /* TX FIFO Address              */
 118 #define TXDMA_FTAG      0x2108UL        /* TX FIFO Tag                  */
 119 #define TXDMA_DLOW      0x210CUL        /* TX FIFO Data Low             */
 120 #define TXDMA_DHIT1     0x2110UL        /* TX FIFO Data HighT1          */
 121 #define TXDMA_DHIT0     0x2114UL        /* TX FIFO Data HighT0          */
 122 #define TXDMA_FSZ       0x2118UL        /* TX FIFO Size                 */
 123
 124 /* TX Kick Register.
 125  *
 126  * This 13-bit register is programmed by the driver to hold the descriptor
 127  * entry index which follows the last valid transmit descriptor.
 128  */
 129
 130 /* TX Completion Register.
 131  *
 132  * This 13-bit register is updated by GEM to hold to descriptor entry index
 133  * which follows the last descriptor already processed by GEM.  Note that
 134  * this value is mirrored in GREG_STAT which eliminates the need to even
 135  * access this register in the driver during interrupt processing.
 136  */
 137
 138 /* TX Configuration Register.
 139  *
 140  * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature
 141  * that was meant to be used with jumbo packets.  It should be set to the
 142  * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors.
 143  */
 144 #define TXDMA_CFG_ENABLE        0x00000001      /* Enable TX DMA channel        */
 145 #define TXDMA_CFG_RINGSZ        0x0000001e      /* TX descriptor ring size      */
 146 #define TXDMA_CFG_RINGSZ_32     0x00000000      /* 32 TX descriptors            */
 147 #define TXDMA_CFG_RINGSZ_64     0x00000002      /* 64 TX descriptors            */
 148 #define TXDMA_CFG_RINGSZ_128    0x00000004      /* 128 TX descriptors           */
 149 #define TXDMA_CFG_RINGSZ_256    0x00000006      /* 256 TX descriptors           */
 150 #define TXDMA_CFG_RINGSZ_512    0x00000008      /* 512 TX descriptors           */
 151 #define TXDMA_CFG_RINGSZ_1K     0x0000000a      /* 1024 TX descriptors          */
 152 #define TXDMA_CFG_RINGSZ_2K     0x0000000c      /* 2048 TX descriptors          */
 153 #define TXDMA_CFG_RINGSZ_4K     0x0000000e      /* 4096 TX descriptors          */
 154 #define TXDMA_CFG_RINGSZ_8K     0x00000010      /* 8192 TX descriptors          */
 155 #define TXDMA_CFG_PIOSEL        0x00000020      /* Enable TX FIFO PIO from cpu  */
 156 #define TXDMA_CFG_FTHRESH       0x001ffc00      /* TX FIFO Threshold, obsolete  */
 157 #define TXDMA_CFG_PMODE         0x00200000      /* TXALL irq means TX FIFO empty*/
 158
 159 /* TX Descriptor Base Low/High.
 160  *
 161  * These two registers store the 53 most significant bits of the base address
 162  * of the TX descriptor table.  The 11 least significant bits are always
 163  * zero.  As a result, the TX descriptor table must be 2K aligned.
 164  */
 165
 166 /* The rest of the TXDMA_* registers are for diagnostics and debug, I will document
 167  * them later. -DaveM
 168  */
 169
 170 /* Receive DMA Registers */
 171 #define RXDMA_CFG       0x4000UL        /* RX Configuration Register    */
 172 #define RXDMA_DBLOW     0x4004UL        /* RX Descriptor Base Low       */
 173 #define RXDMA_DBHI      0x4008UL        /* RX Descriptor Base High      */
 174 #define RXDMA_FWPTR     0x400CUL        /* RX FIFO Write Pointer        */
 175 #define RXDMA_FSWPTR    0x4010UL        /* RX FIFO Shadow Write Pointer */
 176 #define RXDMA_FRPTR     0x4014UL        /* RX FIFO Read Pointer         */
 177 #define RXDMA_PCNT      0x4018UL        /* RX FIFO Packet Counter       */
 178 #define RXDMA_SMACHINE  0x401CUL        /* RX State Machine Register    */
 179 #define RXDMA_PTHRESH   0x4020UL        /* Pause Thresholds             */
 180 #define RXDMA_DPLOW     0x4024UL        /* RX Data Pointer Low          */
 181 #define RXDMA_DPHI      0x4028UL        /* RX Data Pointer High         */
 182 #define RXDMA_KICK      0x4100UL        /* RX Kick Register             */
 183 #define RXDMA_DONE      0x4104UL        /* RX Completion Register       */
 184 #define RXDMA_BLANK     0x4108UL        /* RX Blanking Register         */
 185 #define RXDMA_FADDR     0x410CUL        /* RX FIFO Address              */
 186 #define RXDMA_FTAG      0x4110UL        /* RX FIFO Tag                  */
 187 #define RXDMA_DLOW      0x4114UL        /* RX FIFO Data Low             */
 188 #define RXDMA_DHIT1     0x4118UL        /* RX FIFO Data HighT0          */
 189 #define RXDMA_DHIT0     0x411CUL        /* RX FIFO Data HighT1          */
 190 #define RXDMA_FSZ       0x4120UL        /* RX FIFO Size                 */
 191
 192 /* RX Configuration Register. */
 193 #define RXDMA_CFG_ENABLE        0x00000001      /* Enable RX DMA channel        */
 194 #define RXDMA_CFG_RINGSZ        0x0000001e      /* RX descriptor ring size      */
 195 #define RXDMA_CFG_RINGSZ_32     0x00000000      /* - 32   entries               */
 196 #define RXDMA_CFG_RINGSZ_64     0x00000002      /* - 64   entries               */
 197 #define RXDMA_CFG_RINGSZ_128    0x00000004      /* - 128  entries               */
 198 #define RXDMA_CFG_RINGSZ_256    0x00000006      /* - 256  entries               */
 199 #define RXDMA_CFG_RINGSZ_512    0x00000008      /* - 512  entries               */
 200 #define RXDMA_CFG_RINGSZ_1K     0x0000000a      /* - 1024 entries               */
 201 #define RXDMA_CFG_RINGSZ_2K     0x0000000c      /* - 2048 entries               */
 202 #define RXDMA_CFG_RINGSZ_4K     0x0000000e      /* - 4096 entries               */
 203 #define RXDMA_CFG_RINGSZ_8K     0x00000010      /* - 8192 entries               */
 204 #define RXDMA_CFG_RINGSZ_BDISAB 0x00000020      /* Disable RX desc batching     */
 205 #define RXDMA_CFG_FBOFF         0x00001c00      /* Offset of first data byte    */
 206 #define RXDMA_CFG_CSUMOFF       0x000fe000      /* Skip bytes before csum calc  */
 207 #define RXDMA_CFG_FTHRESH       0x07000000      /* RX FIFO dma start threshold  */
 208 #define RXDMA_CFG_FTHRESH_64    0x00000000      /* - 64   bytes                 */
 209 #define RXDMA_CFG_FTHRESH_128   0x01000000      /* - 128  bytes                 */
 210 #define RXDMA_CFG_FTHRESH_256   0x02000000      /* - 256  bytes                 */
 211 #define RXDMA_CFG_FTHRESH_512   0x03000000      /* - 512  bytes                 */
 212 #define RXDMA_CFG_FTHRESH_1K    0x04000000      /* - 1024 bytes                 */
 213 #define RXDMA_CFG_FTHRESH_2K    0x05000000      /* - 2048 bytes                 */
 214
 215 /* RX Descriptor Base Low/High.
 216  *
 217  * These two registers store the 53 most significant bits of the base address
 218  * of the RX descriptor table.  The 11 least significant bits are always
 219  * zero.  As a result, the RX descriptor table must be 2K aligned.
 220  */
 221
 222 /* RX PAUSE Thresholds.
 223  *
 224  * These values determine when XOFF and XON PAUSE frames are emitted by
 225  * GEM.  The thresholds measure RX FIFO occupancy in units of 64 bytes.
 226  */
 227 #define RXDMA_PTHRESH_OFF       0x000001ff      /* XOFF emitted w/FIFO > this   */
 228 #define RXDMA_PTHRESH_ON        0x001ff000      /* XON emitted w/FIFO < this    */
 229
 230 /* RX Kick Register.
 231  *
 232  * This 13-bit register is written by the host CPU and holds the last
 233  * valid RX descriptor number plus one.  This is, if 'N' is written to
 234  * this register, it means that all RX descriptors up to but excluding
 235  * 'N' are valid.
 236  *
 237  * The hardware requires that RX descriptors are posted in increments
 238  * of 4.  This means 'N' must be a multiple of four.  For the best
 239  * performance, the first new descriptor being posted should be (PCI)
 240  * cache line aligned.
 241  */
 242
 243 /* RX Completion Register.
 244  *
 245  * This 13-bit register is updated by GEM to indicate which RX descriptors
 246  * have already been used for receive frames.  All descriptors up to but
 247  * excluding the value in this register are ready to be processed.  GEM
 248  * updates this register value after the RX FIFO empties completely into
 249  * the RX descriptor's buffer, but before the RX_DONE bit is set in the
 250  * interrupt status register.
 251  */
 252
 253 /* RX Blanking Register. */
 254 #define RXDMA_BLANK_IPKTS       0x000001ff      /* RX_DONE asserted after this
 255                                                  * many packets received since
 256                                                  * previous RX_DONE.
 257                                                  */
 258 #define RXDMA_BLANK_ITIME       0x000ff000      /* RX_DONE asserted after this
 259                                                  * many clocks (measured in 2048
 260                                                  * PCI clocks) were counted since
 261                                                  * the previous RX_DONE.
 262                                                  */
 263
 264 /* RX FIFO Size.
 265  *
 266  * This 11-bit read-only register indicates how large, in units of 64-bytes,
 267  * the RX FIFO is.  The driver uses this to properly configure the RX PAUSE
 268  * thresholds.
 269  */
 270
 271 /* The rest of the RXDMA_* registers are for diagnostics and debug, I will document
 272  * them later. -DaveM
 273  */
 274
 275 /* MAC Registers */
 276 #define MAC_TXRST       0x6000UL        /* TX MAC Software Reset Command*/
 277 #define MAC_RXRST       0x6004UL        /* RX MAC Software Reset Command*/
 278 #define MAC_SNDPAUSE    0x6008UL        /* Send Pause Command Register  */
 279 #define MAC_TXSTAT      0x6010UL        /* TX MAC Status Register       */
 280 #define MAC_RXSTAT      0x6014UL        /* RX MAC Status Register       */
 281 #define MAC_CSTAT       0x6018UL        /* MAC Control Status Register  */
 282 #define MAC_TXMASK      0x6020UL        /* TX MAC Mask Register         */
 283 #define MAC_RXMASK      0x6024UL        /* RX MAC Mask Register         */
 284 #define MAC_MCMASK      0x6028UL        /* MAC Control Mask Register    */
 285 #define MAC_TXCFG       0x6030UL        /* TX MAC Configuration Register*/
 286 #define MAC_RXCFG       0x6034UL        /* RX MAC Configuration Register*/
 287 #define MAC_MCCFG       0x6038UL        /* MAC Control Config Register  */
 288 #define MAC_XIFCFG      0x603CUL        /* XIF Configuration Register   */
 289 #define MAC_IPG0        0x6040UL        /* InterPacketGap0 Register     */
 290 #define MAC_IPG1        0x6044UL        /* InterPacketGap1 Register     */
 291 #define MAC_IPG2        0x6048UL        /* InterPacketGap2 Register     */
 292 #define MAC_STIME       0x604CUL        /* SlotTime Register            */
 293 #define MAC_MINFSZ      0x6050UL        /* MinFrameSize Register        */
 294 #define MAC_MAXFSZ      0x6054UL        /* MaxFrameSize Register        */
 295 #define MAC_PASIZE      0x6058UL        /* PA Size Register             */
 296 #define MAC_JAMSIZE     0x605CUL        /* JamSize Register             */
 297 #define MAC_ATTLIM      0x6060UL        /* Attempt Limit Register       */
 298 #define MAC_MCTYPE      0x6064UL        /* MAC Control Type Register    */
 299 #define MAC_ADDR0       0x6080UL        /* MAC Address 0 Register       */
 300 #define MAC_ADDR1       0x6084UL        /* MAC Address 1 Register       */
 301 #define MAC_ADDR2       0x6088UL        /* MAC Address 2 Register       */
 302 #define MAC_ADDR3       0x608CUL        /* MAC Address 3 Register       */
 303 #define MAC_ADDR4       0x6090UL        /* MAC Address 4 Register       */
 304 #define MAC_ADDR5       0x6094UL        /* MAC Address 5 Register       */
 305 #define MAC_ADDR6       0x6098UL        /* MAC Address 6 Register       */
 306 #define MAC_ADDR7       0x609CUL        /* MAC Address 7 Register       */
 307 #define MAC_ADDR8       0x60A0UL        /* MAC Address 8 Register       */
 308 #define MAC_AFILT0      0x60A4UL        /* Address Filter 0 Register    */
 309 #define MAC_AFILT1      0x60A8UL        /* Address Filter 1 Register    */
 310 #define MAC_AFILT2      0x60ACUL        /* Address Filter 2 Register    */
 311 #define MAC_AF21MSK     0x60B0UL        /* Address Filter 2&1 Mask Reg  */
 312 #define MAC_AF0MSK      0x60B4UL        /* Address Filter 0 Mask Reg    */
 313 #define MAC_HASH0       0x60C0UL        /* Hash Table 0 Register        */
 314 #define MAC_HASH1       0x60C4UL        /* Hash Table 1 Register        */
 315 #define MAC_HASH2       0x60C8UL        /* Hash Table 2 Register        */
 316 #define MAC_HASH3       0x60CCUL        /* Hash Table 3 Register        */
 317 #define MAC_HASH4       0x60D0UL        /* Hash Table 4 Register        */
 318 #define MAC_HASH5       0x60D4UL        /* Hash Table 5 Register        */
 319 #define MAC_HASH6       0x60D8UL        /* Hash Table 6 Register        */
 320 #define MAC_HASH7       0x60DCUL        /* Hash Table 7 Register        */
 321 #define MAC_HASH8       0x60E0UL        /* Hash Table 8 Register        */
 322 #define MAC_HASH9       0x60E4UL        /* Hash Table 9 Register        */
 323 #define MAC_HASH10      0x60E8UL        /* Hash Table 10 Register       */
 324 #define MAC_HASH11      0x60ECUL        /* Hash Table 11 Register       */
 325 #define MAC_HASH12      0x60F0UL        /* Hash Table 12 Register       */
 326 #define MAC_HASH13      0x60F4UL        /* Hash Table 13 Register       */
 327 #define MAC_HASH14      0x60F8UL        /* Hash Table 14 Register       */
 328 #define MAC_HASH15      0x60FCUL        /* Hash Table 15 Register       */
 329 #define MAC_NCOLL       0x6100UL        /* Normal Collision Counter     */
 330 #define MAC_FASUCC      0x6104UL        /* First Attmpt. Succ Coll Ctr. */
 331 #define MAC_ECOLL       0x6108UL        /* Excessive Collision Counter  */
 332 #define MAC_LCOLL       0x610CUL        /* Late Collision Counter       */
 333 #define MAC_DTIMER      0x6110UL        /* Defer Timer                  */
 334 #define MAC_PATMPS      0x6114UL        /* Peak Attempts Register       */
 335 #define MAC_RFCTR       0x6118UL        /* Receive Frame Counter        */
 336 #define MAC_LERR        0x611CUL        /* Length Error Counter         */
 337 #define MAC_AERR        0x6120UL        /* Alignment Error Counter      */
 338 #define MAC_FCSERR      0x6124UL        /* FCS Error Counter            */
 339 #define MAC_RXCVERR     0x6128UL        /* RX code Violation Error Ctr  */
 340 #define MAC_RANDSEED    0x6130UL        /* Random Number Seed Register  */
 341 #define MAC_SMACHINE    0x6134UL        /* State Machine Register       */
 342
 343 /* TX MAC Software Reset Command. */
 344 #define MAC_TXRST_CMD   0x00000001      /* Start sw reset, self-clears  */
 345
 346 /* RX MAC Software Reset Command. */
 347 #define MAC_RXRST_CMD   0x00000001      /* Start sw reset, self-clears  */
 348
 349 /* Send Pause Command. */
 350 #define MAC_SNDPAUSE_TS 0x0000ffff      /* The pause_time operand used in
 351                                          * Send_Pause and flow-control
 352                                          * handshakes.
 353                                          */
 354 #define MAC_SNDPAUSE_SP 0x00010000      /* Setting this bit instructs the MAC
 355                                          * to send a Pause Flow Control
 356                                          * frame onto the network.
 357                                          */
 358
 359 /* TX MAC Status Register. */
 360 #define MAC_TXSTAT_XMIT 0x00000001      /* Frame Transmitted            */
 361 #define MAC_TXSTAT_URUN 0x00000002      /* TX Underrun                  */
 362 #define MAC_TXSTAT_MPE  0x00000004      /* Max Packet Size Error        */
 363 #define MAC_TXSTAT_NCE  0x00000008      /* Normal Collision Cntr Expire */
 364 #define MAC_TXSTAT_ECE  0x00000010      /* Excess Collision Cntr Expire */
 365 #define MAC_TXSTAT_LCE  0x00000020      /* Late Collision Cntr Expire   */
 366 #define MAC_TXSTAT_FCE  0x00000040      /* First Collision Cntr Expire  */
 367 #define MAC_TXSTAT_DTE  0x00000080      /* Defer Timer Expire           */
 368 #define MAC_TXSTAT_PCE  0x00000100      /* Peak Attempts Cntr Expire    */
 369
 370 /* RX MAC Status Register. */
 371 #define MAC_RXSTAT_RCV  0x00000001      /* Frame Received               */
 372 #define MAC_RXSTAT_OFLW 0x00000002      /* Receive Overflow             */
 373 #define MAC_RXSTAT_FCE  0x00000004      /* Frame Cntr Expire            */
 374 #define MAC_RXSTAT_ACE  0x00000008      /* Align Error Cntr Expire      */
 375 #define MAC_RXSTAT_CCE  0x00000010      /* CRC Error Cntr Expire        */
 376 #define MAC_RXSTAT_LCE  0x00000020      /* Length Error Cntr Expire     */
 377 #define MAC_RXSTAT_VCE  0x00000040      /* Code Violation Cntr Expire   */
 378
 379 /* MAC Control Status Register. */
 380 #define MAC_CSTAT_PRCV  0x00000001      /* Pause Received               */
 381 #define MAC_CSTAT_PS    0x00000002      /* Paused State                 */
 382 #define MAC_CSTAT_NPS   0x00000004      /* Not Paused State             */
 383 #define MAC_CSTAT_PTR   0xffff0000      /* Pause Time Received          */
 384
 385 /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that
 386  * of MAC_{TX,RX,C}STAT.  Bits set in MAC_{TX,RX,C}MASK will prevent
 387  * that interrupt type from being signalled to front end of GEM.  For
 388  * the interrupt to actually get sent to the cpu, it is necessary to
 389  * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
 390  */
 391
 392 /* TX MAC Configuration Register.
 393  *
 394  * NOTE: The TX MAC Enable bit must be cleared and polled until
 395  *       zero before any other bits in this register are changed.
 396  *
 397  *       Also, enabling the Carrier Extension feature of GEM is
 398  *       a 3 step process 1) Set TX Carrier Extension 2) Set
 399  *       RX Carrier Extension 3) Set Slot Time to 0x200.  This
 400  *       mode must be enabled when in half-duplex at 1Gbps, else
 401  *       it must be disabled.
 402  */
 403 #define MAC_TXCFG_ENAB  0x00000001      /* TX MAC Enable                */
 404 #define MAC_TXCFG_ICS   0x00000002      /* Ignore Carrier Sense         */
 405 #define MAC_TXCFG_ICOLL 0x00000004      /* Ignore Collisions            */
 406 #define MAC_TXCFG_EIPG0 0x00000008      /* Enable IPG0                  */
 407 #define MAC_TXCFG_NGU   0x00000010      /* Never Give Up                */
 408 #define MAC_TXCFG_NGUL  0x00000020      /* Never Give Up Limit          */
 409 #define MAC_TXCFG_NBO   0x00000040      /* No Backoff                   */
 410 #define MAC_TXCFG_SD    0x00000080      /* Slow Down                    */
 411 #define MAC_TXCFG_NFCS  0x00000100      /* No FCS                       */
 412 #define MAC_TXCFG_TCE   0x00000200      /* TX Carrier Extension         */
 413
 414 /* RX MAC Configuration Register.
 415  *
 416  * NOTE: The RX MAC Enable bit must be cleared and polled until
 417  *       zero before any other bits in this register are changed.
 418  *
 419  *       Similar rules apply to the Hash Filter Enable bit when
 420  *       programming the hash table registers, and the Address Filter
 421  *       Enable bit when programming the address filter registers.
 422  */
 423 #define MAC_RXCFG_ENAB  0x00000001      /* RX MAC Enable                */
 424 #define MAC_RXCFG_SPAD  0x00000002      /* Strip Pad                    */
 425 #define MAC_RXCFG_SFCS  0x00000004      /* Strip FCS                    */
 426 #define MAC_RXCFG_PROM  0x00000008      /* Promiscuous Mode             */
 427 #define MAC_RXCFG_PGRP  0x00000010      /* Promiscuous Group            */
 428 #define MAC_RXCFG_HFE   0x00000020      /* Hash Filter Enable           */
 429 #define MAC_RXCFG_AFE   0x00000040      /* Address Filter Enable        */
 430 #define MAC_RXCFG_DDE   0x00000080      /* Disable Discard on Error     */
 431 #define MAC_RXCFG_RCE   0x00000100      /* RX Carrier Extension         */
 432
 433 /* MAC Control Config Register. */
 434 #define MAC_MCCFG_SPE   0x00000001      /* Send Pause Enable            */
 435 #define MAC_MCCFG_RPE   0x00000002      /* Receive Pause Enable         */
 436 #define MAC_MCCFG_PMC   0x00000004      /* Pass MAC Control             */
 437
 438 /* XIF Configuration Register.
 439  *
 440  * NOTE: When leaving or entering loopback mode, a global hardware
 441  *       init of GEM should be performed.
 442  */
 443 #define MAC_XIFCFG_OE   0x00000001      /* MII TX Output Driver Enable  */
 444 #define MAC_XIFCFG_LBCK 0x00000002      /* Loopback TX to RX            */
 445 #define MAC_XIFCFG_DISE 0x00000004      /* Disable RX path during TX    */
 446 #define MAC_XIFCFG_GMII 0x00000008      /* Use GMII clocks + datapath   */
 447 #define MAC_XIFCFG_MBOE 0x00000010      /* Controls MII_BUF_EN pin      */
 448 #define MAC_XIFCFG_LLED 0x00000020      /* Force LINKLED# active (low)  */
 449 #define MAC_XIFCFG_FLED 0x00000040      /* Force FDPLXLED# active (low) */
 450
 451 /* InterPacketGap0 Register.  This 8-bit value is used as an extension
 452  * to the InterPacketGap1 Register.  Specifically it contributes to the
 453  * timing of the RX-to-TX IPG.  This value is ignored and presumed to
 454  * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
 455  * is cleared in the TX MAC Configuration Register.
 456  *
 457  * This value in this register in terms of media byte time.
 458  *
 459  * Recommended value: 0x00
 460  */
 461
 462 /* InterPacketGap1 Register.  This 8-bit value defines the first 2/3
 463  * portion of the Inter Packet Gap.
 464  *
 465  * This value in this register in terms of media byte time.
 466  *
 467  * Recommended value: 0x08
 468  */
 469
 470 /* InterPacketGap2 Register.  This 8-bit value defines the second 1/3
 471  * portion of the Inter Packet Gap.
 472  *
 473  * This value in this register in terms of media byte time.
 474  *
 475  * Recommended value: 0x04
 476  */
 477
 478 /* Slot Time Register.  This 10-bit value specifies the slot time
 479  * parameter in units of media byte time.  It determines the physical
 480  * span of the network.
 481  *
 482  * Recommended value: 0x40
 483  */
 484
 485 /* Minimum Frame Size Register.  This 10-bit register specifies the
 486  * smallest sized frame the TXMAC will send onto the medium, and the
 487  * RXMAC will receive from the medium.
 488  *
 489  * Recommended value: 0x40
 490  */
 491
 492 /* Maximum Frame and Burst Size Register.
 493  *
 494  * This register specifies two things.  First it specifies the maximum
 495  * sized frame the TXMAC will send and the RXMAC will recognize as
 496  * valid.  Second, it specifies the maximum run length of a burst of
 497  * packets sent in half-duplex gigabit modes.
 498  *
 499  * Recommended value: 0x200005ee
 500  */
 501 #define MAC_MAXFSZ_MFS  0x00007fff      /* Max Frame Size               */
 502 #define MAC_MAXFSZ_MBS  0x7fff0000      /* Max Burst Size               */
 503
 504 /* PA Size Register.  This 10-bit register specifies the number of preamble
 505  * bytes which will be transmitted at the beginning of each frame.  A
 506  * value of two or greater should be programmed here.
 507  *
 508  * Recommended value: 0x07
 509  */
 510
 511 /* Jam Size Register.  This 4-bit register specifies the duration of
 512  * the jam in units of media byte time.
 513  *
 514  * Recommended value: 0x04
 515  */
 516
 517 /* Attempts Limit Register.  This 8-bit register specifies the number
 518  * of attempts that the TXMAC will make to transmit a frame, before it
 519  * resets its Attempts Counter.  After reaching the Attempts Limit the
 520  * TXMAC may or may not drop the frame, as determined by the NGU
 521  * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC
 522  * Configuration Register.
 523  *
 524  * Recommended value: 0x10
 525  */
 526
 527 /* MAX Control Type Register.  This 16-bit register specifies the
 528  * "type" field of a MAC Control frame.  The TXMAC uses this field to
 529  * encapsulate the MAC Control frame for transmission, and the RXMAC
 530  * uses it for decoding valid MAC Control frames received from the
 531  * network.
 532  *
 533  * Recommended value: 0x8808
 534  */
 535
 536 /* MAC Address Registers.  Each of these registers specify the
 537  * ethernet MAC of the interface, 16-bits at a time.  Register
 538  * 0 specifies bits [47:32], register 1 bits [31:16], and register
 539  * 2 bits [15:0].
 540  *
 541  * Registers 3 through and including 5 specify an alternate
 542  * MAC address for the interface.
 543  *
 544  * Registers 6 through and including 8 specify the MAC Control
 545  * Address, which must be the reserved multicast address for MAC
 546  * Control frames.
 547  *
 548  * Example: To program primary station address a:b:c:d:e:f into
 549  *          the chip.
 550  *              MAC_Address_2 = (a << 8) | b
 551  *              MAC_Address_1 = (c << 8) | d
 552  *              MAC_Address_0 = (e << 8) | f
 553  */
 554
 555 /* Address Filter Registers.  Registers 0 through 2 specify bit
 556  * fields [47:32] through [15:0], respectively, of the address
 557  * filter.  The Address Filter 2&1 Mask Register denotes the 8-bit
 558  * nibble mask for Address Filter Registers 2 and 1.  The Address
 559  * Filter 0 Mask Register denotes the 16-bit mask for the Address
 560  * Filter Register 0.
 561  */
 562
 563 /* Hash Table Registers.  Registers 0 through 15 specify bit fields
 564  * [255:240] through [15:0], respectively, of the hash table.
 565  */
 566
 567 /* Statistics Registers.  All of these registers are 16-bits and
 568  * track occurrences of a specific event.  GEM can be configured
 569  * to interrupt the host cpu when any of these counters overflow.
 570  * They should all be explicitly initialized to zero when the interface
 571  * is brought up.
 572  */
 573
 574 /* Random Number Seed Register.  This 10-bit value is used as the
 575  * RNG seed inside GEM for the CSMA/CD backoff algorithm.  It is
 576  * recommended to program this register to the 10 LSB of the
 577  * interfaces MAC address.
 578  */
 579
 580 /* Pause Timer, read-only.  This 16-bit timer is used to time the pause
 581  * interval as indicated by a received pause flow control frame.
 582  * A non-zero value in this timer indicates that the MAC is currently in
 583  * the paused state.
 584  */
 585
 586 /* MIF Registers */
 587 #define MIF_BBCLK       0x6200UL        /* MIF Bit-Bang Clock           */
 588 #define MIF_BBDATA      0x6204UL        /* MIF Bit-Band Data            */
 589 #define MIF_BBOENAB     0x6208UL        /* MIF Bit-Bang Output Enable   */
 590 #define MIF_FRAME       0x620CUL        /* MIF Frame/Output Register    */
 591 #define MIF_CFG         0x6210UL        /* MIF Configuration Register   */
 592 #define MIF_MASK        0x6214UL        /* MIF Mask Register            */
 593 #define MIF_STATUS      0x6218UL        /* MIF Status Register          */
 594 #define MIF_SMACHINE    0x621CUL        /* MIF State Machine Register   */
 595
 596 /* MIF Bit-Bang Clock.  This 1-bit register is used to generate the
 597  * MDC clock waveform on the MII Management Interface when the MIF is
 598  * programmed in the "Bit-Bang" mode.  Writing a '1' after a '0' into
 599  * this register will create a rising edge on the MDC, while writing
 600  * a '0' after a '1' will create a falling edge.  For every bit that
 601  * is transferred on the management interface, both edges have to be
 602  * generated.
 603  */
 604
 605 /* MIF Bit-Bang Data.  This 1-bit register is used to generate the
 606  * outgoing data (MDO) on the MII Management Interface when the MIF
 607  * is programmed in the "Bit-Bang" mode.  The daa will be steered to the
 608  * appropriate MDIO based on the state of the PHY_Select bit in the MIF
 609  * Configuration Register.
 610  */
 611
 612 /* MIF Big-Band Output Enable.  THis 1-bit register is used to enable
 613  * ('1') or disable ('0') the I-directional driver on the MII when the
 614  * MIF is programmed in the "Bit-Bang" mode.  The MDIO should be enabled
 615  * when data bits are transferred from the MIF to the transceiver, and it
 616  * should be disabled when the interface is idle or when data bits are
 617  * transferred from the transceiver to the MIF (data portion of a read
 618  * instruction).  Only one MDIO will be enabled at a given time, depending
 619  * on the state of the PHY_Select bit in the MIF Configuration Register.
 620  */
 621
 622 /* MIF Configuration Register.  This 15-bit register controls the operation
 623  * of the MIF.
 624  */
 625 #define MIF_CFG_PSELECT 0x00000001      /* Xcvr slct: 0=mdio0 1=mdio1   */
 626 #define MIF_CFG_POLL    0x00000002      /* Enable polling mechanism     */
 627 #define MIF_CFG_BBMODE  0x00000004      /* 1=bit-bang 0=frame mode      */
 628 #define MIF_CFG_PRADDR  0x000000f8      /* Xcvr poll register address   */
 629 #define MIF_CFG_MDI0    0x00000100      /* MDIO_0 present or read-bit   */
 630 #define MIF_CFG_MDI1    0x00000200      /* MDIO_1 present or read-bit   */
 631 #define MIF_CFG_PPADDR  0x00007c00      /* Xcvr poll PHY address        */
 632
 633 /* MIF Frame/Output Register.  This 32-bit register allows the host to
 634  * communicate with a transceiver in frame mode (as opposed to big-bang
 635  * mode).  Writes by the host specify an instrution.  After being issued
 636  * the host must poll this register for completion.  Also, after
 637  * completion this register holds the data returned by the transceiver
 638  * if applicable.
 639  */
 640 #define MIF_FRAME_ST    0xc0000000      /* STart of frame               */
 641 #define MIF_FRAME_OP    0x30000000      /* OPcode                       */
 642 #define MIF_FRAME_PHYAD 0x0f800000      /* PHY ADdress                  */
 643 #define MIF_FRAME_REGAD 0x007c0000      /* REGister ADdress             */
 644 #define MIF_FRAME_TAMSB 0x00020000      /* Turn Around MSB              */
 645 #define MIF_FRAME_TALSB 0x00010000      /* Turn Around LSB              */
 646 #define MIF_FRAME_DATA  0x0000ffff      /* Instruction Payload          */
 647
 648 /* MIF Status Register.  This register reports status when the MIF is
 649  * operating in the poll mode.  The poll status field is auto-clearing
 650  * on read.
 651  */
 652 #define MIF_STATUS_DATA 0xffff0000      /* Live image of XCVR reg       */
 653 #define MIF_STATUS_STAT 0x0000ffff      /* Which bits have changed      */
 654
 655 /* MIF Mask Register.  This 16-bit register is used when in poll mode
 656  * to say which bits of the polled register will cause an interrupt
 657  * when changed.
 658  */
 659
 660 /* PCS/Serialink Registers */
 661 #define PCS_MIICTRL     0x9000UL        /* PCS MII Control Register     */
 662 #define PCS_MIISTAT     0x9004UL        /* PCS MII Status Register      */
 663 #define PCS_MIIADV      0x9008UL        /* PCS MII Advertisement Reg    */
 664 #define PCS_MIILP       0x900CUL        /* PCS MII Link Partner Ability */
 665 #define PCS_CFG         0x9010UL        /* PCS Configuration Register   */
 666 #define PCS_SMACHINE    0x9014UL        /* PCS State Machine Register   */
 667 #define PCS_ISTAT       0x9018UL        /* PCS Interrupt Status Reg     */
 668 #define PCS_DMODE       0x9050UL        /* Datapath Mode Register       */
 669 #define PCS_SCTRL       0x9054UL        /* Serialink Control Register   */
 670 #define PCS_SOS         0x9058UL        /* Shared Output Select Reg     */
 671 #define PCS_SSTATE      0x905CUL        /* Serialink State Register     */
 672
 673 /* PCD MII Control Register. */
 674 #define PCS_MIICTRL_SPD 0x00000040      /* Read as one, writes ignored  */
 675 #define PCS_MIICTRL_CT  0x00000080      /* Force COL signal active      */
 676 #define PCS_MIICTRL_DM  0x00000100      /* Duplex mode, forced low      */
 677 #define PCS_MIICTRL_RAN 0x00000200      /* Restart auto-neg, self clear */
 678 #define PCS_MIICTRL_ISO 0x00000400      /* Read as zero, writes ignored */
 679 #define PCS_MIICTRL_PD  0x00000800      /* Read as zero, writes ignored */
 680 #define PCS_MIICTRL_ANE 0x00001000      /* Auto-neg enable              */
 681 #define PCS_MIICTRL_SS  0x00002000      /* Read as zero, writes ignored */
 682 #define PCS_MIICTRL_WB  0x00004000      /* Wrapback, loopback at 10-bit
 683                                          * input side of Serialink
 684                                          */
 685 #define PCS_MIICTRL_RST 0x00008000      /* Resets PCS, self clearing    */
 686
 687 /* PCS MII Status Register. */
 688 #define PCS_MIISTAT_EC  0x00000001      /* Ext Capability: Read as zero */
 689 #define PCS_MIISTAT_JD  0x00000002      /* Jabber Detect: Read as zero  */
 690 #define PCS_MIISTAT_LS  0x00000004      /* Link Status: 1=up 0=down     */
 691 #define PCS_MIISTAT_ANA 0x00000008      /* Auto-neg Ability, always 1   */
 692 #define PCS_MIISTAT_RF  0x00000010      /* Remote Fault                 */
 693 #define PCS_MIISTAT_ANC 0x00000020      /* Auto-neg complete            */
 694 #define PCS_MIISTAT_ES  0x00000100      /* Extended Status, always 1    */
 695
 696 /* PCS MII Advertisement Register. */
 697 #define PCS_MIIADV_FD   0x00000020      /* Advertise Full Duplex        */
 698 #define PCS_MIIADV_HD   0x00000040      /* Advertise Half Duplex        */
 699 #define PCS_MIIADV_SP   0x00000080      /* Advertise Symmetric Pause    */
 700 #define PCS_MIIADV_AP   0x00000100      /* Advertise Asymmetric Pause   */
 701 #define PCS_MIIADV_RF   0x00003000      /* Remote Fault                 */
 702 #define PCS_MIIADV_ACK  0x00004000      /* Read-only                    */
 703 #define PCS_MIIADV_NP   0x00008000      /* Next-page, forced low        */
 704
 705 /* PCS MII Link Partner Ability Register.   This register is equivalent
 706  * to the Link Partnet Ability Register of the standard MII register set.
 707  * It's layout corresponds to the PCS MII Advertisement Register.
 708  */
 709
 710 /* PCS Configuration Register. */
 711 #define PCS_CFG_ENABLE  0x00000001      /* Must be zero while changing
 712                                          * PCS MII advertisement reg.
 713                                          */
 714 #define PCS_CFG_SDO     0x00000002      /* Signal detect override       */
 715 #define PCS_CFG_SDL     0x00000004      /* Signal detect active low     */
 716 #define PCS_CFG_JS      0x00000018      /* Jitter-study:
 717                                          * 0 = normal operation
 718                                          * 1 = high-frequency test pattern
 719                                          * 2 = low-frequency test pattern
 720                                          * 3 = reserved
 721                                          */
 722 #define PCS_CFG_TO      0x00000020      /* 10ms auto-neg timer override */
 723
 724 /* PCS Interrupt Status Register.  This register is self-clearing
 725  * when read.
 726  */
 727 #define PCS_ISTAT_LSC   0x00000004      /* Link Status Change           */
 728
 729 /* Datapath Mode Register. */
 730 #define PCS_DMODE_SM    0x00000001      /* 1 = use internal Serialink   */
 731 #define PCS_DMODE_ESM   0x00000002      /* External SERDES mode         */
 732 #define PCS_DMODE_MGM   0x00000004      /* MII/GMII mode                */
 733 #define PCS_DMODE_GMOE  0x00000008      /* GMII Output Enable           */
 734
 735 /* Serialink Control Register.
 736  *
 737  * NOTE: When in SERDES mode, the loopback bit has inverse logic.
 738  */
 739 #define PCS_SCTRL_LOOP  0x00000001      /* Loopback enable              */
 740 #define PCS_SCTRL_ESCD  0x00000002      /* Enable sync char detection   */
 741 #define PCS_SCTRL_LOCK  0x00000004      /* Lock to reference clock      */
 742 #define PCS_SCTRL_EMP   0x00000018      /* Output driver emphasis       */
 743 #define PCS_SCTRL_STEST 0x000001c0      /* Self test patterns           */
 744 #define PCS_SCTRL_PDWN  0x00000200      /* Software power-down          */
 745 #define PCS_SCTRL_RXZ   0x00000c00      /* PLL input to Serialink       */
 746 #define PCS_SCTRL_RXP   0x00003000      /* PLL input to Serialink       */
 747 #define PCS_SCTRL_TXZ   0x0000c000      /* PLL input to Serialink       */
 748 #define PCS_SCTRL_TXP   0x00030000      /* PLL input to Serialink       */
 749
 750 /* Shared Output Select Register.  For test and debug, allows multiplexing
 751  * test outputs into the PROM address pins.  Set to zero for normal
 752  * operation.
 753  */
 754 #define PCS_SOS_PADDR   0x00000003      /* PROM Address                 */
 755
 756 /* PROM Image Space */
 757 #define PROM_START      0x100000UL      /* Expansion ROM run time access*/
 758 #define PROM_SIZE       0x0fffffUL      /* Size of ROM                  */
 759 #define PROM_END        0x200000UL      /* End of ROM                   */
 760
 761 /* MII definitions missing from mii.h */
 762
 763 #define BMCR_SPD2       0x0040          /* Gigabit enable? (bcm5411)    */
 764 #define LPA_PAUSE       0x0400
 765
 766 /* More PHY registers (specific to Broadcom models) */
 767
 768 /* MII BCM5201 MULTIPHY interrupt register */
 769 #define MII_BCM5201_INTERRUPT                   0x1A
 770 #define MII_BCM5201_INTERRUPT_INTENABLE         0x4000
 771
 772 #define MII_BCM5201_AUXMODE2                    0x1B
 773 #define MII_BCM5201_AUXMODE2_LOWPOWER           0x0008
 774
 775 #define MII_BCM5201_MULTIPHY                    0x1E
 776
 777 /* MII BCM5201 MULTIPHY register bits */
 778 #define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
 779 #define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008
 780
 781 /* MII BCM5400 1000-BASET Control register */
 782 #define MII_BCM5400_GB_CONTROL                  0x09
 783 #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP    0x0200
 784
 785 /* MII BCM5400 AUXCONTROL register */
 786 #define MII_BCM5400_AUXCONTROL                  0x18
 787 #define MII_BCM5400_AUXCONTROL_PWR10BASET       0x0004
 788
 789 /* MII BCM5400 AUXSTATUS register */
 790 #define MII_BCM5400_AUXSTATUS                   0x19
 791 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK     0x0700
 792 #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT    8
 793
 794 /* When it can, GEM internally caches 4 aligned TX descriptors
 795  * at a time, so that it can use full cacheline DMA reads.
 796  *
 797  * Note that unlike HME, there is no ownership bit in the descriptor
 798  * control word.  The same functionality is obtained via the TX-Kick
 799  * and TX-Complete registers.  As a result, GEM need not write back
 800  * updated values to the TX descriptor ring, it only performs reads.
 801  *
 802  * Since TX descriptors are never modified by GEM, the driver can
 803  * use the buffer DMA address as a place to keep track of allocated
 804  * DMA mappings for a transmitted packet.
 805  */
 806 struct gem_txd {
 807         u64     control_word;
 808         u64     buffer;
 809 };
 810
 811 #define TXDCTRL_BUFSZ   0x0000000000007fffULL   /* Buffer Size          */
 812 #define TXDCTRL_CSTART  0x00000000001f8000ULL   /* CSUM Start Offset    */
 813 #define TXDCTRL_COFF    0x000000001fe00000ULL   /* CSUM Stuff Offset    */
 814 #define TXDCTRL_CENAB   0x0000000020000000ULL   /* CSUM Enable          */
 815 #define TXDCTRL_EOF     0x0000000040000000ULL   /* End of Frame         */
 816 #define TXDCTRL_SOF     0x0000000080000000ULL   /* Start of Frame       */
 817 #define TXDCTRL_INTME   0x0000000100000000ULL   /* "Interrupt Me"       */
 818 #define TXDCTRL_NOCRC   0x0000000200000000ULL   /* No CRC Present       */
 819
 820 /* GEM requires that RX descriptors are provided four at a time,
 821  * aligned.  Also, the RX ring may not wrap around.  This means that
 822  * there will be at least 4 unused desciptor entries in the middle
 823  * of the RX ring at all times.
 824  *
 825  * Similar to HME, GEM assumes that it can write garbage bytes before
 826  * the beginning of the buffer and right after the end in order to DMA
 827  * whole cachelines.
 828  *
 829  * Unlike for TX, GEM does update the status word in the RX descriptors
 830  * when packets arrive.  Therefore an ownership bit does exist in the
 831  * RX descriptors.  It is advisory, GEM clears it but does not check
 832  * it in any way.  So when buffers are posted to the RX ring (via the
 833  * RX Kick register) by the driver it must make sure the buffers are
 834  * truly ready and that the ownership bits are set properly.
 835  *
 836  * Even though GEM modifies the RX descriptors, it guarantees that the
 837  * buffer DMA address field will stay the same when it performs these
 838  * updates.  Therefore it can be used to keep track of DMA mappings
 839  * by the host driver just as in the TX descriptor case above.
 840  */
 841 struct gem_rxd {
 842         u64     status_word;
 843         u64     buffer;
 844 };
 845
 846 #define RXDCTRL_TCPCSUM 0x000000000000ffffULL   /* TCP Pseudo-CSUM      */
 847 #define RXDCTRL_BUFSZ   0x000000007fff0000ULL   /* Buffer Size          */
 848 #define RXDCTRL_OWN     0x0000000080000000ULL   /* GEM owns this entry  */
 849 #define RXDCTRL_HASHVAL 0x0ffff00000000000ULL   /* Hash Value           */
 850 #define RXDCTRL_HPASS   0x1000000000000000ULL   /* Passed Hash Filter   */
 851 #define RXDCTRL_ALTMAC  0x2000000000000000ULL   /* Matched ALT MAC      */
 852 #define RXDCTRL_BAD     0x4000000000000000ULL   /* Frame has bad CRC    */
 853
 854 #define RXDCTRL_FRESH(gp)       \
 855         ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
 856          RXDCTRL_OWN)
 857
 858 #define TX_RING_SIZE 128
 859 #define RX_RING_SIZE 128
 860
 861 #if TX_RING_SIZE == 32
 862 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_32
 863 #elif TX_RING_SIZE == 64
 864 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_64
 865 #elif TX_RING_SIZE == 128
 866 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_128
 867 #elif TX_RING_SIZE == 256
 868 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_256
 869 #elif TX_RING_SIZE == 512
 870 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_512
 871 #elif TX_RING_SIZE == 1024
 872 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_1K
 873 #elif TX_RING_SIZE == 2048
 874 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_2K
 875 #elif TX_RING_SIZE == 4096
 876 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_4K
 877 #elif TX_RING_SIZE == 8192
 878 #define TXDMA_CFG_BASE  TXDMA_CFG_RINGSZ_8K
 879 #else
 880 #error TX_RING_SIZE value is illegal...
 881 #endif
 882
 883 #if RX_RING_SIZE == 32
 884 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_32
 885 #elif RX_RING_SIZE == 64
 886 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_64
 887 #elif RX_RING_SIZE == 128
 888 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_128
 889 #elif RX_RING_SIZE == 256
 890 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_256
 891 #elif RX_RING_SIZE == 512
 892 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_512
 893 #elif RX_RING_SIZE == 1024
 894 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_1K
 895 #elif RX_RING_SIZE == 2048
 896 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_2K
 897 #elif RX_RING_SIZE == 4096
 898 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_4K
 899 #elif RX_RING_SIZE == 8192
 900 #define RXDMA_CFG_BASE  RXDMA_CFG_RINGSZ_8K
 901 #else
 902 #error RX_RING_SIZE is illegal...
 903 #endif
 904
 905 #define NEXT_TX(N)      (((N) + 1) & (TX_RING_SIZE - 1))
 906 #define NEXT_RX(N)      (((N) + 1) & (RX_RING_SIZE - 1))
 907
 908 #define TX_BUFFS_AVAIL(GP)                                      \
 909         (((GP)->tx_old <= (GP)->tx_new) ?                       \
 910           (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new :    \
 911           (GP)->tx_old - (GP)->tx_new - 1)
 912
 913 #define RX_OFFSET          2
 914 #define RX_BUF_ALLOC_SIZE(gp)   ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)
 915
 916 #define RX_COPY_THRESHOLD  256
 917
 918 #if TX_RING_SIZE < 128
 919 #define INIT_BLOCK_TX_RING_SIZE         128
 920 #else
 921 #define INIT_BLOCK_TX_RING_SIZE         TX_RING_SIZE
 922 #endif
 923
 924 #if RX_RING_SIZE < 128
 925 #define INIT_BLOCK_RX_RING_SIZE         128
 926 #else
 927 #define INIT_BLOCK_RX_RING_SIZE         RX_RING_SIZE
 928 #endif
 929
 930 struct gem_init_block {
 931         struct gem_txd  txd[INIT_BLOCK_TX_RING_SIZE];
 932         struct gem_rxd  rxd[INIT_BLOCK_RX_RING_SIZE];
 933 };
 934
 935 enum gem_phy_type {
 936         phy_mii_mdio0,
 937         phy_mii_mdio1,
 938         phy_serialink,
 939         phy_serdes,
 940 };
 941
 942 enum link_state {
 943         link_down = 0,  /* No link, will retry */
 944         link_aneg,      /* Autoneg in progress */
 945         link_force_try, /* Try Forced link speed */
 946         link_force_ret, /* Forced mode worked, retrying autoneg */
 947         link_force_ok,  /* Stay in forced mode */
 948         link_up         /* Link is up */
 949 };
 950
 951 struct gem {
 952         spinlock_t lock;
 953         unsigned long regs;
 954         int rx_new, rx_old;
 955         int tx_new, tx_old;
 956
 957         /* Set when chip is actually in operational state
 958          * (ie. not power managed)
 959          */
 960         int hw_running;
 961         int opened;
 962         struct semaphore pm_sem;
 963         struct work_struct pm_task;
 964         struct timer_list pm_timer;
 965
 966         struct gem_init_block *init_block;
 967
 968         struct sk_buff *rx_skbs[RX_RING_SIZE];
 969         struct sk_buff *tx_skbs[RX_RING_SIZE];
 970
 971         u32                     msg_enable;
 972
 973         struct net_device_stats net_stats;
 974
 975         enum gem_phy_type       phy_type;
 976         struct mii_phy          phy_mii;
 977
 978         int                     tx_fifo_sz;
 979         int                     rx_fifo_sz;
 980         int                     rx_pause_off;
 981         int                     rx_pause_on;
 982         int                     rx_buf_sz;
 983         int                     mii_phy_addr;
 984
 985         u32                     mac_rx_cfg;
 986         u32                     swrst_base;
 987
 988         /* Autoneg & PHY control */
 989         int                     want_autoneg;
 990         int                     last_forced_speed;
 991         enum link_state         lstate;
 992         struct timer_list       link_timer;
 993         int                     timer_ticks;
 994         int                     wake_on_lan;
 995         struct work_struct      reset_task;
 996         volatile int            reset_task_pending;
 997
 998         /* Diagnostic counters and state. */
 999         u64                     pause_entered;
1000         u16                     pause_last_time_recvd;
1001
1002         dma_addr_t gblock_dvma;
1003         struct pci_dev *pdev;
1004         struct net_device *dev;
1005 #ifdef CONFIG_PPC_PMAC
1006         struct device_node      *of_node;
1007 #endif
1008 };
1009
1010 #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) \
1011                                 && gp->phy_mii.def && gp->phy_mii.def->ops)
1012
1013 #define ALIGNED_RX_SKB_ADDR(addr) \
1014         ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
1015 static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags)
1016 {
1017         struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
1018
1019         if (skb) {
1020                 int offset = (int) ALIGNED_RX_SKB_ADDR(skb->data);
1021                 if (offset)
1022                         skb_reserve(skb, offset);
1023         }
1024
1025         return skb;
1026 }
1027
1028 #endif /* _SUNGEM_H */