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[PATCH] CREDITS update
[linux-2.6/history.git] / drivers / net / sb1250-mac.c
blob39b09cd6ba13a2229269b77fc13c959b6c3977a2
1 /*
2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19 /*
20 This driver is designed for the Broadcom SiByte SOC built-in
21 Ethernet controllers.
22
23 Written by Mitch Lichtenberg at Broadcom Corp.
24 */
25
26
27
28 #define CONFIG_SBMAC_COALESCE
29
30 /* A few user-configurable values.
31 These may be modified when a driver module is loaded. */
32
33 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
34 static int noisy_mii = 1; /* mii status msgs */
35
36 /* Used to pass the media type, etc.
37 Both 'options[]' and 'full_duplex[]' should exist for driver
38 interoperability.
39 The media type is usually passed in 'options[]'.
40 */
41
42 #define MAX_UNITS 3 /* More are supported, limit only on options */
43 #ifdef MODULE
44 static int options[MAX_UNITS] = {-1, -1, -1};
45 static int full_duplex[MAX_UNITS] = {-1, -1, -1};
46 #endif
47
48 #ifdef CONFIG_SBMAC_COALESCE
49 static int int_pktcnt = 0;
50 static int int_timeout = 0;
51 #endif
52
53 /* Operational parameters that usually are not changed. */
54
55 /* Time in jiffies before concluding the transmitter is hung. */
56 #define TX_TIMEOUT (2*HZ)
57
58 #if !defined(__OPTIMIZE__) || !defined(__KERNEL__)
59 #warning You must compile this file with the correct options!
60 #warning See the last lines of the source file.
61 #error You must compile this driver with "-O".
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/timer.h>
68 #include <linux/errno.h>
69 #include <linux/ioport.h>
70 #include <linux/slab.h>
71 #include <linux/interrupt.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/init.h>
76 #include <linux/config.h>
77 #include <asm/processor.h> /* Processor type for cache alignment. */
78 #include <asm/bitops.h>
79 #include <asm/io.h>
80 #include <asm/cache.h>
81
82 /* This is only here until the firmware is ready. In that case,
83 the firmware leaves the ethernet address in the register for us. */
84 #ifdef CONFIG_SIBYTE_STANDALONE
85 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
86 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
87 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
88 #endif
89
90
91 /* These identify the driver base version and may not be removed. */
92 #if 0
93 static char version1[] __devinitdata =
94 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
95 #endif
96
97
98
99 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
100 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
101 MODULE_PARM(debug, "i");
102 MODULE_PARM(noisy_mii, "i");
103 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
104 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
105
106 MODULE_PARM(int_pktcnt, "i");
107 MODULE_PARM(int_timeout, "i");
108
109 #include <asm/sibyte/sb1250.h>
110 #include <asm/sibyte/sb1250_defs.h>
111 #include <asm/sibyte/sb1250_regs.h>
112 #include <asm/sibyte/sb1250_mac.h>
113 #include <asm/sibyte/sb1250_dma.h>
114 #include <asm/sibyte/sb1250_int.h>
115 #include <asm/sibyte/sb1250_scd.h>
116
117
118 /**********************************************************************
119 * Simple types
120 ********************************************************************* */
121
122
123 typedef unsigned long sbmac_port_t;
124
125 typedef enum { sbmac_speed_auto, sbmac_speed_10,
126 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
127
128 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
129 sbmac_duplex_full } sbmac_duplex_t;
130
131 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
132 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
133
134 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
135 sbmac_state_broken } sbmac_state_t;
136
137
138 /**********************************************************************
139 * Macros
140 ********************************************************************* */
141
142
143 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
144 (d)->sbdma_dscrtable : (d)->f+1)
145
146
147 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
148
149 #define SBMAC_READCSR(t) __raw_readq((unsigned long)t)
150 #define SBMAC_WRITECSR(t,v) __raw_writeq(v, (unsigned long)t)
151
152
153 #define SBMAC_MAX_TXDESCR 32
154 #define SBMAC_MAX_RXDESCR 32
155
156 #define ETHER_ALIGN 2
157 #define ETHER_ADDR_LEN 6
158 #define ENET_PACKET_SIZE 1518
159 /*#define ENET_PACKET_SIZE 9216 */
160
161 /**********************************************************************
162 * DMA Descriptor structure
163 ********************************************************************* */
164
165 typedef struct sbdmadscr_s {
166 uint64_t dscr_a;
167 uint64_t dscr_b;
168 } sbdmadscr_t;
169
170 typedef unsigned long paddr_t;
171
172 /**********************************************************************
173 * DMA Controller structure
174 ********************************************************************* */
175
176 typedef struct sbmacdma_s {
177
178 /*
179 * This stuff is used to identify the channel and the registers
180 * associated with it.
181 */
182
183 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
184 int sbdma_channel; /* channel number */
185 int sbdma_txdir; /* direction (1=transmit) */
186 int sbdma_maxdescr; /* total # of descriptors in ring */
187 #ifdef CONFIG_SBMAC_COALESCE
188 int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/
189 int sbdma_int_timeout; /* # usec rx/tx interrupt */
190 #endif
191
192 sbmac_port_t sbdma_config0; /* DMA config register 0 */
193 sbmac_port_t sbdma_config1; /* DMA config register 1 */
194 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */
195 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */
196 sbmac_port_t sbdma_curdscr; /* current descriptor address */
197
198 /*
199 * This stuff is for maintenance of the ring
200 */
201
202 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
203 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
204
205 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
206
207 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
208 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
209 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
210 } sbmacdma_t;
211
212
213 /**********************************************************************
214 * Ethernet softc structure
215 ********************************************************************* */
216
217 struct sbmac_softc {
218
219 /*
220 * Linux-specific things
221 */
222
223 struct net_device *sbm_dev; /* pointer to linux device */
224 spinlock_t sbm_lock; /* spin lock */
225 struct timer_list sbm_timer; /* for monitoring MII */
226 struct net_device_stats sbm_stats;
227 int sbm_devflags; /* current device flags */
228
229 int sbm_phy_oldbmsr;
230 int sbm_phy_oldanlpar;
231 int sbm_phy_oldk1stsr;
232 int sbm_phy_oldlinkstat;
233 int sbm_buffersize;
234
235 unsigned char sbm_phys[2];
236
237 /*
238 * Controller-specific things
239 */
240
241 unsigned long sbm_base; /* MAC's base address */
242 sbmac_state_t sbm_state; /* current state */
243
244 sbmac_port_t sbm_macenable; /* MAC Enable Register */
245 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */
246 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */
247 sbmac_port_t sbm_framecfg; /* Frame configuration register */
248 sbmac_port_t sbm_rxfilter; /* receive filter register */
249 sbmac_port_t sbm_isr; /* Interrupt status register */
250 sbmac_port_t sbm_imr; /* Interrupt mask register */
251 sbmac_port_t sbm_mdio; /* MDIO register */
252
253 sbmac_speed_t sbm_speed; /* current speed */
254 sbmac_duplex_t sbm_duplex; /* current duplex */
255 sbmac_fc_t sbm_fc; /* current flow control setting */
256
257 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
258
259 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
260 sbmacdma_t sbm_rxdma;
261 int rx_hw_checksum;
262 int sbe_idx;
263 };
264
265
266 /**********************************************************************
267 * Externs
268 ********************************************************************* */
269
270 /**********************************************************************
271 * Prototypes
272 ********************************************************************* */
273
274 static void sbdma_initctx(sbmacdma_t *d,
275 struct sbmac_softc *s,
276 int chan,
277 int txrx,
278 int maxdescr);
279 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
280 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
281 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
282 static void sbdma_emptyring(sbmacdma_t *d);
283 static void sbdma_fillring(sbmacdma_t *d);
284 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
285 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
286 static int sbmac_initctx(struct sbmac_softc *s);
287 static void sbmac_channel_start(struct sbmac_softc *s);
288 static void sbmac_channel_stop(struct sbmac_softc *s);
289 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
290 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
291 static uint64_t sbmac_addr2reg(unsigned char *ptr);
292 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
293 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
294 static void sbmac_setmulti(struct sbmac_softc *sc);
295 static int sbmac_init(struct net_device *dev, int idx);
296 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
297 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
298
299 static int sbmac_open(struct net_device *dev);
300 static void sbmac_timer(unsigned long data);
301 static void sbmac_tx_timeout (struct net_device *dev);
302 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
303 static void sbmac_set_rx_mode(struct net_device *dev);
304 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
305 static int sbmac_close(struct net_device *dev);
306 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
307
308 static void sbmac_mii_sync(struct sbmac_softc *s);
309 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
310 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
311 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
312 unsigned int regval);
313
314
315 /**********************************************************************
316 * Globals
317 ********************************************************************* */
318
319 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
320
321
322 /**********************************************************************
323 * MDIO constants
324 ********************************************************************* */
325
326 #define MII_COMMAND_START 0x01
327 #define MII_COMMAND_READ 0x02
328 #define MII_COMMAND_WRITE 0x01
329 #define MII_COMMAND_ACK 0x02
330
331 #define BMCR_RESET 0x8000
332 #define BMCR_LOOPBACK 0x4000
333 #define BMCR_SPEED0 0x2000
334 #define BMCR_ANENABLE 0x1000
335 #define BMCR_POWERDOWN 0x0800
336 #define BMCR_ISOLATE 0x0400
337 #define BMCR_RESTARTAN 0x0200
338 #define BMCR_DUPLEX 0x0100
339 #define BMCR_COLTEST 0x0080
340 #define BMCR_SPEED1 0x0040
341 #define BMCR_SPEED1000 BMCR_SPEED1
342 #define BMCR_SPEED100 BMCR_SPEED0
343 #define BMCR_SPEED10 0
344
345 #define BMSR_100BT4 0x8000
346 #define BMSR_100BT_FDX 0x4000
347 #define BMSR_100BT_HDX 0x2000
348 #define BMSR_10BT_FDX 0x1000
349 #define BMSR_10BT_HDX 0x0800
350 #define BMSR_100BT2_FDX 0x0400
351 #define BMSR_100BT2_HDX 0x0200
352 #define BMSR_1000BT_XSR 0x0100
353 #define BMSR_PRESUP 0x0040
354 #define BMSR_ANCOMPLT 0x0020
355 #define BMSR_REMFAULT 0x0010
356 #define BMSR_AUTONEG 0x0008
357 #define BMSR_LINKSTAT 0x0004
358 #define BMSR_JABDETECT 0x0002
359 #define BMSR_EXTCAPAB 0x0001
360
361 #define PHYIDR1 0x2000
362 #define PHYIDR2 0x5C60
363
364 #define ANAR_NP 0x8000
365 #define ANAR_RF 0x2000
366 #define ANAR_ASYPAUSE 0x0800
367 #define ANAR_PAUSE 0x0400
368 #define ANAR_T4 0x0200
369 #define ANAR_TXFD 0x0100
370 #define ANAR_TXHD 0x0080
371 #define ANAR_10FD 0x0040
372 #define ANAR_10HD 0x0020
373 #define ANAR_PSB 0x0001
374
375 #define ANLPAR_NP 0x8000
376 #define ANLPAR_ACK 0x4000
377 #define ANLPAR_RF 0x2000
378 #define ANLPAR_ASYPAUSE 0x0800
379 #define ANLPAR_PAUSE 0x0400
380 #define ANLPAR_T4 0x0200
381 #define ANLPAR_TXFD 0x0100
382 #define ANLPAR_TXHD 0x0080
383 #define ANLPAR_10FD 0x0040
384 #define ANLPAR_10HD 0x0020
385 #define ANLPAR_PSB 0x0001 /* 802.3 */
386
387 #define ANER_PDF 0x0010
388 #define ANER_LPNPABLE 0x0008
389 #define ANER_NPABLE 0x0004
390 #define ANER_PAGERX 0x0002
391 #define ANER_LPANABLE 0x0001
392
393 #define ANNPTR_NP 0x8000
394 #define ANNPTR_MP 0x2000
395 #define ANNPTR_ACK2 0x1000
396 #define ANNPTR_TOGTX 0x0800
397 #define ANNPTR_CODE 0x0008
398
399 #define ANNPRR_NP 0x8000
400 #define ANNPRR_MP 0x2000
401 #define ANNPRR_ACK3 0x1000
402 #define ANNPRR_TOGTX 0x0800
403 #define ANNPRR_CODE 0x0008
404
405 #define K1TCR_TESTMODE 0x0000
406 #define K1TCR_MSMCE 0x1000
407 #define K1TCR_MSCV 0x0800
408 #define K1TCR_RPTR 0x0400
409 #define K1TCR_1000BT_FDX 0x200
410 #define K1TCR_1000BT_HDX 0x100
411
412 #define K1STSR_MSMCFLT 0x8000
413 #define K1STSR_MSCFGRES 0x4000
414 #define K1STSR_LRSTAT 0x2000
415 #define K1STSR_RRSTAT 0x1000
416 #define K1STSR_LP1KFD 0x0800
417 #define K1STSR_LP1KHD 0x0400
418 #define K1STSR_LPASMDIR 0x0200
419
420 #define K1SCR_1KX_FDX 0x8000
421 #define K1SCR_1KX_HDX 0x4000
422 #define K1SCR_1KT_FDX 0x2000
423 #define K1SCR_1KT_HDX 0x1000
424
425 #define STRAP_PHY1 0x0800
426 #define STRAP_NCMODE 0x0400
427 #define STRAP_MANMSCFG 0x0200
428 #define STRAP_ANENABLE 0x0100
429 #define STRAP_MSVAL 0x0080
430 #define STRAP_1KHDXADV 0x0010
431 #define STRAP_1KFDXADV 0x0008
432 #define STRAP_100ADV 0x0004
433 #define STRAP_SPEEDSEL 0x0000
434 #define STRAP_SPEED100 0x0001
435
436 #define PHYSUP_SPEED1000 0x10
437 #define PHYSUP_SPEED100 0x08
438 #define PHYSUP_SPEED10 0x00
439 #define PHYSUP_LINKUP 0x04
440 #define PHYSUP_FDX 0x02
441
442 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
443 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
444 #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
445 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
446
447
448 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
449
450 #define ENABLE 1
451 #define DISABLE 0
452
453 /**********************************************************************
454 * SBMAC_MII_SYNC(s)
455 *
456 * Synchronize with the MII - send a pattern of bits to the MII
457 * that will guarantee that it is ready to accept a command.
458 *
459 * Input parameters:
460 * s - sbmac structure
461 *
462 * Return value:
463 * nothing
464 ********************************************************************* */
465
466 static void sbmac_mii_sync(struct sbmac_softc *s)
467 {
468 int cnt;
469 uint64_t bits;
470 int mac_mdio_genc;
471
472 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
473
474 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
475
476 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
477
478 for (cnt = 0; cnt < 32; cnt++) {
479 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
480 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
481 }
482 }
483
484 /**********************************************************************
485 * SBMAC_MII_SENDDATA(s,data,bitcnt)
486 *
487 * Send some bits to the MII. The bits to be sent are right-
488 * justified in the 'data' parameter.
489 *
490 * Input parameters:
491 * s - sbmac structure
492 * data - data to send
493 * bitcnt - number of bits to send
494 ********************************************************************* */
495
496 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
497 {
498 int i;
499 uint64_t bits;
500 unsigned int curmask;
501 int mac_mdio_genc;
502
503 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
504
505 bits = M_MAC_MDIO_DIR_OUTPUT;
506 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
507
508 curmask = 1 << (bitcnt - 1);
509
510 for (i = 0; i < bitcnt; i++) {
511 if (data & curmask)
512 bits |= M_MAC_MDIO_OUT;
513 else bits &= ~M_MAC_MDIO_OUT;
514 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
515 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
516 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
517 curmask >>= 1;
518 }
519 }
520
521
522
523 /**********************************************************************
524 * SBMAC_MII_READ(s,phyaddr,regidx)
525 *
526 * Read a PHY register.
527 *
528 * Input parameters:
529 * s - sbmac structure
530 * phyaddr - PHY's address
531 * regidx = index of register to read
532 *
533 * Return value:
534 * value read, or 0 if an error occurred.
535 ********************************************************************* */
536
537 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
538 {
539 int idx;
540 int error;
541 int regval;
542 int mac_mdio_genc;
543
544 /*
545 * Synchronize ourselves so that the PHY knows the next
546 * thing coming down is a command
547 */
548
549 sbmac_mii_sync(s);
550
551 /*
552 * Send the data to the PHY. The sequence is
553 * a "start" command (2 bits)
554 * a "read" command (2 bits)
555 * the PHY addr (5 bits)
556 * the register index (5 bits)
557 */
558
559 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
560 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
561 sbmac_mii_senddata(s,phyaddr, 5);
562 sbmac_mii_senddata(s,regidx, 5);
563
564 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
565
566 /*
567 * Switch the port around without a clock transition.
568 */
569 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
570
571 /*
572 * Send out a clock pulse to signal we want the status
573 */
574
575 SBMAC_WRITECSR(s->sbm_mdio,
576 M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
577 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
578
579 /*
580 * If an error occurred, the PHY will signal '1' back
581 */
582 error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN;
583
584 /*
585 * Issue an 'idle' clock pulse, but keep the direction
586 * the same.
587 */
588 SBMAC_WRITECSR(s->sbm_mdio,
589 M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
590 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
591
592 regval = 0;
593
594 for (idx = 0; idx < 16; idx++) {
595 regval <<= 1;
596
597 if (error == 0) {
598 if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN)
599 regval |= 1;
600 }
601
602 SBMAC_WRITECSR(s->sbm_mdio,
603 M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc);
604 SBMAC_WRITECSR(s->sbm_mdio,
605 M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
606 }
607
608 /* Switch back to output */
609 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
610
611 if (error == 0)
612 return regval;
613 return 0;
614 }
615
616
617 /**********************************************************************
618 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
619 *
620 * Write a value to a PHY register.
621 *
622 * Input parameters:
623 * s - sbmac structure
624 * phyaddr - PHY to use
625 * regidx - register within the PHY
626 * regval - data to write to register
627 *
628 * Return value:
629 * nothing
630 ********************************************************************* */
631
632 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
633 unsigned int regval)
634 {
635 int mac_mdio_genc;
636
637 sbmac_mii_sync(s);
638
639 sbmac_mii_senddata(s,MII_COMMAND_START,2);
640 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
641 sbmac_mii_senddata(s,phyaddr, 5);
642 sbmac_mii_senddata(s,regidx, 5);
643 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
644 sbmac_mii_senddata(s,regval,16);
645
646 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
647
648 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
649 }
650
651
652
653 /**********************************************************************
654 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
655 *
656 * Initialize a DMA channel context. Since there are potentially
657 * eight DMA channels per MAC, it's nice to do this in a standard
658 * way.
659 *
660 * Input parameters:
661 * d - sbmacdma_t structure (DMA channel context)
662 * s - sbmac_softc structure (pointer to a MAC)
663 * chan - channel number (0..1 right now)
664 * txrx - Identifies DMA_TX or DMA_RX for channel direction
665 * maxdescr - number of descriptors
666 *
667 * Return value:
668 * nothing
669 ********************************************************************* */
670
671 static void sbdma_initctx(sbmacdma_t *d,
672 struct sbmac_softc *s,
673 int chan,
674 int txrx,
675 int maxdescr)
676 {
677 /*
678 * Save away interesting stuff in the structure
679 */
680
681 d->sbdma_eth = s;
682 d->sbdma_channel = chan;
683 d->sbdma_txdir = txrx;
684
685 #if 0
686 /* RMON clearing */
687 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
688 #endif
689
690 SBMAC_WRITECSR(IOADDR(
691 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
692 SBMAC_WRITECSR(IOADDR(
693 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
694 SBMAC_WRITECSR(IOADDR(
695 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
696 SBMAC_WRITECSR(IOADDR(
697 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
698 SBMAC_WRITECSR(IOADDR(
699 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
700 SBMAC_WRITECSR(IOADDR(
701 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
702 SBMAC_WRITECSR(IOADDR(
703 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
704 SBMAC_WRITECSR(IOADDR(
705 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
706 SBMAC_WRITECSR(IOADDR(
707 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
708 SBMAC_WRITECSR(IOADDR(
709 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
710 SBMAC_WRITECSR(IOADDR(
711 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
712 SBMAC_WRITECSR(IOADDR(
713 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
714 SBMAC_WRITECSR(IOADDR(
715 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
716 SBMAC_WRITECSR(IOADDR(
717 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
718 SBMAC_WRITECSR(IOADDR(
719 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
720 SBMAC_WRITECSR(IOADDR(
721 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
722 SBMAC_WRITECSR(IOADDR(
723 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
724 SBMAC_WRITECSR(IOADDR(
725 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
726 SBMAC_WRITECSR(IOADDR(
727 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
728 SBMAC_WRITECSR(IOADDR(
729 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
730 SBMAC_WRITECSR(IOADDR(
731 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
732
733 /*
734 * initialize register pointers
735 */
736
737 d->sbdma_config0 =
738 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
739 d->sbdma_config1 =
740 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
741 d->sbdma_dscrbase =
742 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
743 d->sbdma_dscrcnt =
744 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
745 d->sbdma_curdscr =
746 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
747
748 /*
749 * Allocate memory for the ring
750 */
751
752 d->sbdma_maxdescr = maxdescr;
753
754 d->sbdma_dscrtable = (sbdmadscr_t *)
755 kmalloc(d->sbdma_maxdescr*sizeof(sbdmadscr_t), GFP_KERNEL);
756
757 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
758
759 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
760
761 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
762
763 /*
764 * And context table
765 */
766
767 d->sbdma_ctxtable = (struct sk_buff **)
768 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
769
770 memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
771
772 #ifdef CONFIG_SBMAC_COALESCE
773 /*
774 * Setup Rx/Tx DMA coalescing defaults
775 */
776
777 if ( int_pktcnt ) {
778 d->sbdma_int_pktcnt = int_pktcnt;
779 } else {
780 d->sbdma_int_pktcnt = 1;
781 }
782
783 if ( int_timeout ) {
784 d->sbdma_int_timeout = int_timeout;
785 } else {
786 d->sbdma_int_timeout = 0;
787 }
788 #endif
789
790 }
791
792 /**********************************************************************
793 * SBDMA_CHANNEL_START(d)
794 *
795 * Initialize the hardware registers for a DMA channel.
796 *
797 * Input parameters:
798 * d - DMA channel to init (context must be previously init'd
799 * rxtx - DMA_RX or DMA_TX depending on what type of channel
800 *
801 * Return value:
802 * nothing
803 ********************************************************************* */
804
805 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
806 {
807 /*
808 * Turn on the DMA channel
809 */
810
811 #ifdef CONFIG_SBMAC_COALESCE
812 SBMAC_WRITECSR(d->sbdma_config1,
813 V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
814 0);
815 SBMAC_WRITECSR(d->sbdma_config0,
816 M_DMA_EOP_INT_EN |
817 V_DMA_RINGSZ(d->sbdma_maxdescr) |
818 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
819 0);
820 #else
821 SBMAC_WRITECSR(d->sbdma_config1,0);
822 SBMAC_WRITECSR(d->sbdma_config0,
823 V_DMA_RINGSZ(d->sbdma_maxdescr) |
824 0);
825 #endif
826
827 SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
828
829 /*
830 * Initialize ring pointers
831 */
832
833 d->sbdma_addptr = d->sbdma_dscrtable;
834 d->sbdma_remptr = d->sbdma_dscrtable;
835 }
836
837 /**********************************************************************
838 * SBDMA_CHANNEL_STOP(d)
839 *
840 * Initialize the hardware registers for a DMA channel.
841 *
842 * Input parameters:
843 * d - DMA channel to init (context must be previously init'd
844 *
845 * Return value:
846 * nothing
847 ********************************************************************* */
848
849 static void sbdma_channel_stop(sbmacdma_t *d)
850 {
851 /*
852 * Turn off the DMA channel
853 */
854
855 SBMAC_WRITECSR(d->sbdma_config1,0);
856
857 SBMAC_WRITECSR(d->sbdma_dscrbase,0);
858
859 SBMAC_WRITECSR(d->sbdma_config0,0);
860
861 /*
862 * Zero ring pointers
863 */
864
865 d->sbdma_addptr = 0;
866 d->sbdma_remptr = 0;
867 }
868
869 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
870 {
871 unsigned long addr;
872 unsigned long newaddr;
873
874 addr = (unsigned long) skb->data;
875
876 newaddr = (addr + power2 - 1) & ~(power2 - 1);
877
878 skb_reserve(skb,newaddr-addr+offset);
879 }
880
881
882 /**********************************************************************
883 * SBDMA_ADD_RCVBUFFER(d,sb)
884 *
885 * Add a buffer to the specified DMA channel. For receive channels,
886 * this queues a buffer for inbound packets.
887 *
888 * Input parameters:
889 * d - DMA channel descriptor
890 * sb - sk_buff to add, or NULL if we should allocate one
891 *
892 * Return value:
893 * 0 if buffer could not be added (ring is full)
894 * 1 if buffer added successfully
895 ********************************************************************* */
896
897
898 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
899 {
900 sbdmadscr_t *dsc;
901 sbdmadscr_t *nextdsc;
902 struct sk_buff *sb_new = NULL;
903 int pktsize = ENET_PACKET_SIZE;
904
905 /* get pointer to our current place in the ring */
906
907 dsc = d->sbdma_addptr;
908 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
909
910 /*
911 * figure out if the ring is full - if the next descriptor
912 * is the same as the one that we're going to remove from
913 * the ring, the ring is full
914 */
915
916 if (nextdsc == d->sbdma_remptr) {
917 return -ENOSPC;
918 }
919
920 /*
921 * Allocate a sk_buff if we don't already have one.
922 * If we do have an sk_buff, reset it so that it's empty.
923 *
924 * Note: sk_buffs don't seem to be guaranteed to have any sort
925 * of alignment when they are allocated. Therefore, allocate enough
926 * extra space to make sure that:
927 *
928 * 1. the data does not start in the middle of a cache line.
929 * 2. The data does not end in the middle of a cache line
930 * 3. The buffer can be aligned such that the IP addresses are
931 * naturally aligned.
932 *
933 * Remember, the SOCs MAC writes whole cache lines at a time,
934 * without reading the old contents first. So, if the sk_buff's
935 * data portion starts in the middle of a cache line, the SOC
936 * DMA will trash the beginning (and ending) portions.
937 */
938
939 if (sb == NULL) {
940 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
941 if (sb_new == NULL) {
942 printk(KERN_INFO "%s: sk_buff allocation failed\n",
943 d->sbdma_eth->sbm_dev->name);
944 return -ENOBUFS;
945 }
946
947 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
948
949 /* mark skbuff owned by our device */
950 sb_new->dev = d->sbdma_eth->sbm_dev;
951 }
952 else {
953 sb_new = sb;
954 /*
955 * nothing special to reinit buffer, it's already aligned
956 * and sb->data already points to a good place.
957 */
958 }
959
960 /*
961 * fill in the descriptor
962 */
963
964 #ifdef CONFIG_SBMAC_COALESCE
965 /*
966 * Do not interrupt per DMA transfer.
967 */
968 dsc->dscr_a = virt_to_phys(sb_new->tail) |
969 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
970 0;
971 #else
972 dsc->dscr_a = virt_to_phys(sb_new->tail) |
973 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
974 M_DMA_DSCRA_INTERRUPT;
975 #endif
976
977 /* receiving: no options */
978 dsc->dscr_b = 0;
979
980 /*
981 * fill in the context
982 */
983
984 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
985
986 /*
987 * point at next packet
988 */
989
990 d->sbdma_addptr = nextdsc;
991
992 /*
993 * Give the buffer to the DMA engine.
994 */
995
996 SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
997
998 return 0; /* we did it */
999 }
1000
1001 /**********************************************************************
1002 * SBDMA_ADD_TXBUFFER(d,sb)
1003 *
1004 * Add a transmit buffer to the specified DMA channel, causing a
1005 * transmit to start.
1006 *
1007 * Input parameters:
1008 * d - DMA channel descriptor
1009 * sb - sk_buff to add
1010 *
1011 * Return value:
1012 * 0 transmit queued successfully
1013 * otherwise error code
1014 ********************************************************************* */
1015
1016
1017 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1018 {
1019 sbdmadscr_t *dsc;
1020 sbdmadscr_t *nextdsc;
1021 uint64_t phys;
1022 uint64_t ncb;
1023 int length;
1024
1025 /* get pointer to our current place in the ring */
1026
1027 dsc = d->sbdma_addptr;
1028 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1029
1030 /*
1031 * figure out if the ring is full - if the next descriptor
1032 * is the same as the one that we're going to remove from
1033 * the ring, the ring is full
1034 */
1035
1036 if (nextdsc == d->sbdma_remptr) {
1037 return -ENOSPC;
1038 }
1039
1040 /*
1041 * Under Linux, it's not necessary to copy/coalesce buffers
1042 * like it is on NetBSD. We think they're all contiguous,
1043 * but that may not be true for GBE.
1044 */
1045
1046 length = sb->len;
1047
1048 /*
1049 * fill in the descriptor. Note that the number of cache
1050 * blocks in the descriptor is the number of blocks
1051 * *spanned*, so we need to add in the offset (if any)
1052 * while doing the calculation.
1053 */
1054
1055 phys = virt_to_phys(sb->data);
1056 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1057
1058 dsc->dscr_a = phys |
1059 V_DMA_DSCRA_A_SIZE(ncb) |
1060 #ifndef CONFIG_SBMAC_COALESCE
1061 M_DMA_DSCRA_INTERRUPT |
1062 #endif
1063 M_DMA_ETHTX_SOP;
1064
1065 /* transmitting: set outbound options and length */
1066
1067 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1068 V_DMA_DSCRB_PKT_SIZE(length);
1069
1070 /*
1071 * fill in the context
1072 */
1073
1074 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1075
1076 /*
1077 * point at next packet
1078 */
1079
1080 d->sbdma_addptr = nextdsc;
1081
1082 /*
1083 * Give the buffer to the DMA engine.
1084 */
1085
1086 SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1087
1088 return 0; /* we did it */
1089 }
1090
1091
1092
1093
1094 /**********************************************************************
1095 * SBDMA_EMPTYRING(d)
1096 *
1097 * Free all allocated sk_buffs on the specified DMA channel;
1098 *
1099 * Input parameters:
1100 * d - DMA channel
1101 *
1102 * Return value:
1103 * nothing
1104 ********************************************************************* */
1105
1106 static void sbdma_emptyring(sbmacdma_t *d)
1107 {
1108 int idx;
1109 struct sk_buff *sb;
1110
1111 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1112 sb = d->sbdma_ctxtable[idx];
1113 if (sb) {
1114 dev_kfree_skb(sb);
1115 d->sbdma_ctxtable[idx] = NULL;
1116 }
1117 }
1118 }
1119
1120
1121 /**********************************************************************
1122 * SBDMA_FILLRING(d)
1123 *
1124 * Fill the specified DMA channel (must be receive channel)
1125 * with sk_buffs
1126 *
1127 * Input parameters:
1128 * d - DMA channel
1129 *
1130 * Return value:
1131 * nothing
1132 ********************************************************************* */
1133
1134 static void sbdma_fillring(sbmacdma_t *d)
1135 {
1136 int idx;
1137
1138 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1139 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1140 break;
1141 }
1142 }
1143
1144
1145 /**********************************************************************
1146 * SBDMA_RX_PROCESS(sc,d)
1147 *
1148 * Process "completed" receive buffers on the specified DMA channel.
1149 * Note that this isn't really ideal for priority channels, since
1150 * it processes all of the packets on a given channel before
1151 * returning.
1152 *
1153 * Input parameters:
1154 * sc - softc structure
1155 * d - DMA channel context
1156 *
1157 * Return value:
1158 * nothing
1159 ********************************************************************* */
1160
1161 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1162 {
1163 int curidx;
1164 int hwidx;
1165 sbdmadscr_t *dsc;
1166 struct sk_buff *sb;
1167 int len;
1168
1169 for (;;) {
1170 /*
1171 * figure out where we are (as an index) and where
1172 * the hardware is (also as an index)
1173 *
1174 * This could be done faster if (for example) the
1175 * descriptor table was page-aligned and contiguous in
1176 * both virtual and physical memory -- you could then
1177 * just compare the low-order bits of the virtual address
1178 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1179 */
1180
1181 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1182 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1183 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1184
1185 /*
1186 * If they're the same, that means we've processed all
1187 * of the descriptors up to (but not including) the one that
1188 * the hardware is working on right now.
1189 */
1190
1191 if (curidx == hwidx)
1192 break;
1193
1194 /*
1195 * Otherwise, get the packet's sk_buff ptr back
1196 */
1197
1198 dsc = &(d->sbdma_dscrtable[curidx]);
1199 sb = d->sbdma_ctxtable[curidx];
1200 d->sbdma_ctxtable[curidx] = NULL;
1201
1202 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1203
1204 /*
1205 * Check packet status. If good, process it.
1206 * If not, silently drop it and put it back on the
1207 * receive ring.
1208 */
1209
1210 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1211
1212 /*
1213 * Add a new buffer to replace the old one. If we fail
1214 * to allocate a buffer, we're going to drop this
1215 * packet and put it right back on the receive ring.
1216 */
1217
1218 if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1219 sc->sbm_stats.rx_dropped++;
1220 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1221 } else {
1222 /*
1223 * Set length into the packet
1224 */
1225 skb_put(sb,len);
1226
1227 /*
1228 * Buffer has been replaced on the
1229 * receive ring. Pass the buffer to
1230 * the kernel
1231 */
1232 sc->sbm_stats.rx_bytes += len;
1233 sc->sbm_stats.rx_packets++;
1234 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1235 /* Check hw IPv4/TCP checksum if supported */
1236 if (sc->rx_hw_checksum == ENABLE) {
1237 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1238 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1239 sb->ip_summed = CHECKSUM_UNNECESSARY;
1240 /* don't need to set sb->csum */
1241 } else {
1242 sb->ip_summed = CHECKSUM_NONE;
1243 }
1244 }
1245
1246 netif_rx(sb);
1247 }
1248 } else {
1249 /*
1250 * Packet was mangled somehow. Just drop it and
1251 * put it back on the receive ring.
1252 */
1253 sc->sbm_stats.rx_errors++;
1254 sbdma_add_rcvbuffer(d,sb);
1255 }
1256
1257
1258 /*
1259 * .. and advance to the next buffer.
1260 */
1261
1262 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1263
1264 }
1265 }
1266
1267
1268
1269 /**********************************************************************
1270 * SBDMA_TX_PROCESS(sc,d)
1271 *
1272 * Process "completed" transmit buffers on the specified DMA channel.
1273 * This is normally called within the interrupt service routine.
1274 * Note that this isn't really ideal for priority channels, since
1275 * it processes all of the packets on a given channel before
1276 * returning.
1277 *
1278 * Input parameters:
1279 * sc - softc structure
1280 * d - DMA channel context
1281 *
1282 * Return value:
1283 * nothing
1284 ********************************************************************* */
1285
1286 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1287 {
1288 int curidx;
1289 int hwidx;
1290 sbdmadscr_t *dsc;
1291 struct sk_buff *sb;
1292 unsigned long flags;
1293
1294 spin_lock_irqsave(&(sc->sbm_lock), flags);
1295
1296 for (;;) {
1297 /*
1298 * figure out where we are (as an index) and where
1299 * the hardware is (also as an index)
1300 *
1301 * This could be done faster if (for example) the
1302 * descriptor table was page-aligned and contiguous in
1303 * both virtual and physical memory -- you could then
1304 * just compare the low-order bits of the virtual address
1305 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1306 */
1307
1308 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1309 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1310 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1311
1312 /*
1313 * If they're the same, that means we've processed all
1314 * of the descriptors up to (but not including) the one that
1315 * the hardware is working on right now.
1316 */
1317
1318 if (curidx == hwidx)
1319 break;
1320
1321 /*
1322 * Otherwise, get the packet's sk_buff ptr back
1323 */
1324
1325 dsc = &(d->sbdma_dscrtable[curidx]);
1326 sb = d->sbdma_ctxtable[curidx];
1327 d->sbdma_ctxtable[curidx] = NULL;
1328
1329 /*
1330 * Stats
1331 */
1332
1333 sc->sbm_stats.tx_bytes += sb->len;
1334 sc->sbm_stats.tx_packets++;
1335
1336 /*
1337 * for transmits, we just free buffers.
1338 */
1339
1340 dev_kfree_skb_irq(sb);
1341
1342 /*
1343 * .. and advance to the next buffer.
1344 */
1345
1346 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1347
1348 }
1349
1350 /*
1351 * Decide if we should wake up the protocol or not.
1352 * Other drivers seem to do this when we reach a low
1353 * watermark on the transmit queue.
1354 */
1355
1356 netif_wake_queue(d->sbdma_eth->sbm_dev);
1357
1358 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1359
1360 }
1361
1362
1363
1364 /**********************************************************************
1365 * SBMAC_INITCTX(s)
1366 *
1367 * Initialize an Ethernet context structure - this is called
1368 * once per MAC on the 1250. Memory is allocated here, so don't
1369 * call it again from inside the ioctl routines that bring the
1370 * interface up/down
1371 *
1372 * Input parameters:
1373 * s - sbmac context structure
1374 *
1375 * Return value:
1376 * 0
1377 ********************************************************************* */
1378
1379 static int sbmac_initctx(struct sbmac_softc *s)
1380 {
1381
1382 /*
1383 * figure out the addresses of some ports
1384 */
1385
1386 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1387 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1388 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1389 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1390 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1391 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1392 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1393 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1394
1395 s->sbm_phys[0] = 1;
1396 s->sbm_phys[1] = 0;
1397
1398 s->sbm_phy_oldbmsr = 0;
1399 s->sbm_phy_oldanlpar = 0;
1400 s->sbm_phy_oldk1stsr = 0;
1401 s->sbm_phy_oldlinkstat = 0;
1402
1403 /*
1404 * Initialize the DMA channels. Right now, only one per MAC is used
1405 * Note: Only do this _once_, as it allocates memory from the kernel!
1406 */
1407
1408 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1409 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1410
1411 /*
1412 * initial state is OFF
1413 */
1414
1415 s->sbm_state = sbmac_state_off;
1416
1417 /*
1418 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1419 */
1420
1421 s->sbm_speed = sbmac_speed_10;
1422 s->sbm_duplex = sbmac_duplex_half;
1423 s->sbm_fc = sbmac_fc_disabled;
1424
1425 return 0;
1426 }
1427
1428
1429 static void sbdma_uninitctx(struct sbmacdma_s *d)
1430 {
1431 if (d->sbdma_dscrtable) {
1432 kfree(d->sbdma_dscrtable);
1433 d->sbdma_dscrtable = NULL;
1434 }
1435
1436 if (d->sbdma_ctxtable) {
1437 kfree(d->sbdma_ctxtable);
1438 d->sbdma_ctxtable = NULL;
1439 }
1440 }
1441
1442
1443 static void sbmac_uninitctx(struct sbmac_softc *sc)
1444 {
1445 sbdma_uninitctx(&(sc->sbm_txdma));
1446 sbdma_uninitctx(&(sc->sbm_rxdma));
1447 }
1448
1449
1450 /**********************************************************************
1451 * SBMAC_CHANNEL_START(s)
1452 *
1453 * Start packet processing on this MAC.
1454 *
1455 * Input parameters:
1456 * s - sbmac structure
1457 *
1458 * Return value:
1459 * nothing
1460 ********************************************************************* */
1461
1462 static void sbmac_channel_start(struct sbmac_softc *s)
1463 {
1464 uint64_t reg;
1465 sbmac_port_t port;
1466 uint64_t cfg,fifo,framecfg;
1467 int idx, th_value;
1468
1469 /*
1470 * Don't do this if running
1471 */
1472
1473 if (s->sbm_state == sbmac_state_on)
1474 return;
1475
1476 /*
1477 * Bring the controller out of reset, but leave it off.
1478 */
1479
1480 SBMAC_WRITECSR(s->sbm_macenable,0);
1481
1482 /*
1483 * Ignore all received packets
1484 */
1485
1486 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1487
1488 /*
1489 * Calculate values for various control registers.
1490 */
1491
1492 cfg = M_MAC_RETRY_EN |
1493 M_MAC_TX_HOLD_SOP_EN |
1494 V_MAC_TX_PAUSE_CNT_16K |
1495 M_MAC_AP_STAT_EN |
1496 M_MAC_FAST_SYNC |
1497 M_MAC_SS_EN |
1498 0;
1499
1500 /*
1501 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1502 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1503 * Use a larger RD_THRSH for gigabit
1504 */
1505 if (periph_rev >= 2)
1506 th_value = 64;
1507 else
1508 th_value = 28;
1509
1510 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1511 ((s->sbm_speed == sbmac_speed_1000)
1512 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1513 V_MAC_TX_RL_THRSH(4) |
1514 V_MAC_RX_PL_THRSH(4) |
1515 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1516 V_MAC_RX_PL_THRSH(4) |
1517 V_MAC_RX_RL_THRSH(8) |
1518 0;
1519
1520 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1521 V_MAC_MAX_FRAMESZ_DEFAULT |
1522 V_MAC_BACKOFF_SEL(1);
1523
1524 /*
1525 * Clear out the hash address map
1526 */
1527
1528 port = s->sbm_base + R_MAC_HASH_BASE;
1529 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1530 SBMAC_WRITECSR(port,0);
1531 port += sizeof(uint64_t);
1532 }
1533
1534 /*
1535 * Clear out the exact-match table
1536 */
1537
1538 port = s->sbm_base + R_MAC_ADDR_BASE;
1539 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1540 SBMAC_WRITECSR(port,0);
1541 port += sizeof(uint64_t);
1542 }
1543
1544 /*
1545 * Clear out the DMA Channel mapping table registers
1546 */
1547
1548 port = s->sbm_base + R_MAC_CHUP0_BASE;
1549 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1550 SBMAC_WRITECSR(port,0);
1551 port += sizeof(uint64_t);
1552 }
1553
1554
1555 port = s->sbm_base + R_MAC_CHLO0_BASE;
1556 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1557 SBMAC_WRITECSR(port,0);
1558 port += sizeof(uint64_t);
1559 }
1560
1561 /*
1562 * Program the hardware address. It goes into the hardware-address
1563 * register as well as the first filter register.
1564 */
1565
1566 reg = sbmac_addr2reg(s->sbm_hwaddr);
1567
1568 port = s->sbm_base + R_MAC_ADDR_BASE;
1569 SBMAC_WRITECSR(port,reg);
1570 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1571
1572 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1573 /*
1574 * Pass1 SOCs do not receive packets addressed to the
1575 * destination address in the R_MAC_ETHERNET_ADDR register.
1576 * Set the value to zero.
1577 */
1578 SBMAC_WRITECSR(port,0);
1579 #else
1580 SBMAC_WRITECSR(port,reg);
1581 #endif
1582
1583 /*
1584 * Set the receive filter for no packets, and write values
1585 * to the various config registers
1586 */
1587
1588 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1589 SBMAC_WRITECSR(s->sbm_imr,0);
1590 SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1591 SBMAC_WRITECSR(s->sbm_fifocfg,fifo);
1592 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1593
1594 /*
1595 * Initialize DMA channels (rings should be ok now)
1596 */
1597
1598 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1599 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1600
1601 /*
1602 * Configure the speed, duplex, and flow control
1603 */
1604
1605 sbmac_set_speed(s,s->sbm_speed);
1606 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1607
1608 /*
1609 * Fill the receive ring
1610 */
1611
1612 sbdma_fillring(&(s->sbm_rxdma));
1613
1614 /*
1615 * Turn on the rest of the bits in the enable register
1616 */
1617
1618 SBMAC_WRITECSR(s->sbm_macenable,
1619 M_MAC_RXDMA_EN0 |
1620 M_MAC_TXDMA_EN0 |
1621 M_MAC_RX_ENABLE |
1622 M_MAC_TX_ENABLE);
1623
1624
1625
1626
1627 #ifdef CONFIG_SBMAC_COALESCE
1628 /*
1629 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1630 */
1631 SBMAC_WRITECSR(s->sbm_imr,
1632 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1633 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
1634 #else
1635 /*
1636 * Accept any kind of interrupt on TX and RX DMA channel 0
1637 */
1638 SBMAC_WRITECSR(s->sbm_imr,
1639 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1640 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
1641 #endif
1642
1643 /*
1644 * Enable receiving unicasts and broadcasts
1645 */
1646
1647 SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);
1648
1649 /*
1650 * we're running now.
1651 */
1652
1653 s->sbm_state = sbmac_state_on;
1654
1655 /*
1656 * Program multicast addresses
1657 */
1658
1659 sbmac_setmulti(s);
1660
1661 /*
1662 * If channel was in promiscuous mode before, turn that on
1663 */
1664
1665 if (s->sbm_devflags & IFF_PROMISC) {
1666 sbmac_promiscuous_mode(s,1);
1667 }
1668
1669 }
1670
1671
1672 /**********************************************************************
1673 * SBMAC_CHANNEL_STOP(s)
1674 *
1675 * Stop packet processing on this MAC.
1676 *
1677 * Input parameters:
1678 * s - sbmac structure
1679 *
1680 * Return value:
1681 * nothing
1682 ********************************************************************* */
1683
1684 static void sbmac_channel_stop(struct sbmac_softc *s)
1685 {
1686 /* don't do this if already stopped */
1687
1688 if (s->sbm_state == sbmac_state_off)
1689 return;
1690
1691 /* don't accept any packets, disable all interrupts */
1692
1693 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1694 SBMAC_WRITECSR(s->sbm_imr,0);
1695
1696 /* Turn off ticker */
1697
1698 /* XXX */
1699
1700 /* turn off receiver and transmitter */
1701
1702 SBMAC_WRITECSR(s->sbm_macenable,0);
1703
1704 /* We're stopped now. */
1705
1706 s->sbm_state = sbmac_state_off;
1707
1708 /*
1709 * Stop DMA channels (rings should be ok now)
1710 */
1711
1712 sbdma_channel_stop(&(s->sbm_rxdma));
1713 sbdma_channel_stop(&(s->sbm_txdma));
1714
1715 /* Empty the receive and transmit rings */
1716
1717 sbdma_emptyring(&(s->sbm_rxdma));
1718 sbdma_emptyring(&(s->sbm_txdma));
1719
1720 }
1721
1722 /**********************************************************************
1723 * SBMAC_SET_CHANNEL_STATE(state)
1724 *
1725 * Set the channel's state ON or OFF
1726 *
1727 * Input parameters:
1728 * state - new state
1729 *
1730 * Return value:
1731 * old state
1732 ********************************************************************* */
1733 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1734 sbmac_state_t state)
1735 {
1736 sbmac_state_t oldstate = sc->sbm_state;
1737
1738 /*
1739 * If same as previous state, return
1740 */
1741
1742 if (state == oldstate) {
1743 return oldstate;
1744 }
1745
1746 /*
1747 * If new state is ON, turn channel on
1748 */
1749
1750 if (state == sbmac_state_on) {
1751 sbmac_channel_start(sc);
1752 }
1753 else {
1754 sbmac_channel_stop(sc);
1755 }
1756
1757 /*
1758 * Return previous state
1759 */
1760
1761 return oldstate;
1762 }
1763
1764
1765 /**********************************************************************
1766 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1767 *
1768 * Turn on or off promiscuous mode
1769 *
1770 * Input parameters:
1771 * sc - softc
1772 * onoff - 1 to turn on, 0 to turn off
1773 *
1774 * Return value:
1775 * nothing
1776 ********************************************************************* */
1777
1778 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1779 {
1780 uint64_t reg;
1781
1782 if (sc->sbm_state != sbmac_state_on)
1783 return;
1784
1785 if (onoff) {
1786 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1787 reg |= M_MAC_ALLPKT_EN;
1788 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1789 }
1790 else {
1791 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1792 reg &= ~M_MAC_ALLPKT_EN;
1793 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1794 }
1795 }
1796
1797 /**********************************************************************
1798 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1799 *
1800 * Set the iphdr offset as 15 assuming ethernet encapsulation
1801 *
1802 * Input parameters:
1803 * sc - softc
1804 *
1805 * Return value:
1806 * nothing
1807 ********************************************************************* */
1808
1809 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1810 {
1811 uint64_t reg;
1812
1813 /* Hard code the off set to 15 for now */
1814 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1815 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1816 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1817
1818 /* read system identification to determine revision */
1819 if (periph_rev >= 2) {
1820 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
1821 sc->sbm_dev->name);
1822 sc->rx_hw_checksum = ENABLE;
1823 } else {
1824 sc->rx_hw_checksum = DISABLE;
1825 }
1826 }
1827
1828
1829 /**********************************************************************
1830 * SBMAC_ADDR2REG(ptr)
1831 *
1832 * Convert six bytes into the 64-bit register value that
1833 * we typically write into the SBMAC's address/mcast registers
1834 *
1835 * Input parameters:
1836 * ptr - pointer to 6 bytes
1837 *
1838 * Return value:
1839 * register value
1840 ********************************************************************* */
1841
1842 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1843 {
1844 uint64_t reg = 0;
1845
1846 ptr += 6;
1847
1848 reg |= (uint64_t) *(--ptr);
1849 reg <<= 8;
1850 reg |= (uint64_t) *(--ptr);
1851 reg <<= 8;
1852 reg |= (uint64_t) *(--ptr);
1853 reg <<= 8;
1854 reg |= (uint64_t) *(--ptr);
1855 reg <<= 8;
1856 reg |= (uint64_t) *(--ptr);
1857 reg <<= 8;
1858 reg |= (uint64_t) *(--ptr);
1859
1860 return reg;
1861 }
1862
1863
1864 /**********************************************************************
1865 * SBMAC_SET_SPEED(s,speed)
1866 *
1867 * Configure LAN speed for the specified MAC.
1868 * Warning: must be called when MAC is off!
1869 *
1870 * Input parameters:
1871 * s - sbmac structure
1872 * speed - speed to set MAC to (see sbmac_speed_t enum)
1873 *
1874 * Return value:
1875 * 1 if successful
1876 * 0 indicates invalid parameters
1877 ********************************************************************* */
1878
1879 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1880 {
1881 uint64_t cfg;
1882 uint64_t framecfg;
1883
1884 /*
1885 * Save new current values
1886 */
1887
1888 s->sbm_speed = speed;
1889
1890 if (s->sbm_state == sbmac_state_on)
1891 return 0; /* save for next restart */
1892
1893 /*
1894 * Read current register values
1895 */
1896
1897 cfg = SBMAC_READCSR(s->sbm_maccfg);
1898 framecfg = SBMAC_READCSR(s->sbm_framecfg);
1899
1900 /*
1901 * Mask out the stuff we want to change
1902 */
1903
1904 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1905 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1906 M_MAC_SLOT_SIZE);
1907
1908 /*
1909 * Now add in the new bits
1910 */
1911
1912 switch (speed) {
1913 case sbmac_speed_10:
1914 framecfg |= V_MAC_IFG_RX_10 |
1915 V_MAC_IFG_TX_10 |
1916 K_MAC_IFG_THRSH_10 |
1917 V_MAC_SLOT_SIZE_10;
1918 cfg |= V_MAC_SPEED_SEL_10MBPS;
1919 break;
1920
1921 case sbmac_speed_100:
1922 framecfg |= V_MAC_IFG_RX_100 |
1923 V_MAC_IFG_TX_100 |
1924 V_MAC_IFG_THRSH_100 |
1925 V_MAC_SLOT_SIZE_100;
1926 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1927 break;
1928
1929 case sbmac_speed_1000:
1930 framecfg |= V_MAC_IFG_RX_1000 |
1931 V_MAC_IFG_TX_1000 |
1932 V_MAC_IFG_THRSH_1000 |
1933 V_MAC_SLOT_SIZE_1000;
1934 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1935 break;
1936
1937 case sbmac_speed_auto: /* XXX not implemented */
1938 /* fall through */
1939 default:
1940 return 0;
1941 }
1942
1943 /*
1944 * Send the bits back to the hardware
1945 */
1946
1947 SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1948 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1949
1950 return 1;
1951 }
1952
1953 /**********************************************************************
1954 * SBMAC_SET_DUPLEX(s,duplex,fc)
1955 *
1956 * Set Ethernet duplex and flow control options for this MAC
1957 * Warning: must be called when MAC is off!
1958 *
1959 * Input parameters:
1960 * s - sbmac structure
1961 * duplex - duplex setting (see sbmac_duplex_t)
1962 * fc - flow control setting (see sbmac_fc_t)
1963 *
1964 * Return value:
1965 * 1 if ok
1966 * 0 if an invalid parameter combination was specified
1967 ********************************************************************* */
1968
1969 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1970 {
1971 uint64_t cfg;
1972
1973 /*
1974 * Save new current values
1975 */
1976
1977 s->sbm_duplex = duplex;
1978 s->sbm_fc = fc;
1979
1980 if (s->sbm_state == sbmac_state_on)
1981 return 0; /* save for next restart */
1982
1983 /*
1984 * Read current register values
1985 */
1986
1987 cfg = SBMAC_READCSR(s->sbm_maccfg);
1988
1989 /*
1990 * Mask off the stuff we're about to change
1991 */
1992
1993 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1994
1995
1996 switch (duplex) {
1997 case sbmac_duplex_half:
1998 switch (fc) {
1999 case sbmac_fc_disabled:
2000 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2001 break;
2002
2003 case sbmac_fc_collision:
2004 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2005 break;
2006
2007 case sbmac_fc_carrier:
2008 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2009 break;
2010
2011 case sbmac_fc_auto: /* XXX not implemented */
2012 /* fall through */
2013 case sbmac_fc_frame: /* not valid in half duplex */
2014 default: /* invalid selection */
2015 return 0;
2016 }
2017 break;
2018
2019 case sbmac_duplex_full:
2020 switch (fc) {
2021 case sbmac_fc_disabled:
2022 cfg |= V_MAC_FC_CMD_DISABLED;
2023 break;
2024
2025 case sbmac_fc_frame:
2026 cfg |= V_MAC_FC_CMD_ENABLED;
2027 break;
2028
2029 case sbmac_fc_collision: /* not valid in full duplex */
2030 case sbmac_fc_carrier: /* not valid in full duplex */
2031 case sbmac_fc_auto: /* XXX not implemented */
2032 /* fall through */
2033 default:
2034 return 0;
2035 }
2036 break;
2037 case sbmac_duplex_auto:
2038 /* XXX not implemented */
2039 break;
2040 }
2041
2042 /*
2043 * Send the bits back to the hardware
2044 */
2045
2046 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
2047
2048 return 1;
2049 }
2050
2051
2052
2053
2054 /**********************************************************************
2055 * SBMAC_INTR()
2056 *
2057 * Interrupt handler for MAC interrupts
2058 *
2059 * Input parameters:
2060 * MAC structure
2061 *
2062 * Return value:
2063 * nothing
2064 ********************************************************************* */
2065 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2066 {
2067 struct net_device *dev = (struct net_device *) dev_instance;
2068 struct sbmac_softc *sc = netdev_priv(dev);
2069 uint64_t isr;
2070 int handled = 0;
2071
2072 for (;;) {
2073
2074 /*
2075 * Read the ISR (this clears the bits in the real
2076 * register, except for counter addr)
2077 */
2078
2079 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2080
2081 if (isr == 0)
2082 break;
2083
2084 handled = 1;
2085
2086 /*
2087 * Transmits on channel 0
2088 */
2089
2090 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2091 sbdma_tx_process(sc,&(sc->sbm_txdma));
2092 }
2093
2094 /*
2095 * Receives on channel 0
2096 */
2097
2098 /*
2099 * It's important to test all the bits (or at least the
2100 * EOP_SEEN bit) when deciding to do the RX process
2101 * particularly when coalescing, to make sure we
2102 * take care of the following:
2103 *
2104 * If you have some packets waiting (have been received
2105 * but no interrupt) and get a TX interrupt before
2106 * the RX timer or counter expires, reading the ISR
2107 * above will clear the timer and counter, and you
2108 * won't get another interrupt until a packet shows
2109 * up to start the timer again. Testing
2110 * EOP_SEEN here takes care of this case.
2111 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2112 */
2113
2114
2115 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2116 sbdma_rx_process(sc,&(sc->sbm_rxdma));
2117 }
2118 }
2119 return IRQ_RETVAL(handled);
2120 }
2121
2122
2123 /**********************************************************************
2124 * SBMAC_START_TX(skb,dev)
2125 *
2126 * Start output on the specified interface. Basically, we
2127 * queue as many buffers as we can until the ring fills up, or
2128 * we run off the end of the queue, whichever comes first.
2129 *
2130 * Input parameters:
2131 *
2132 *
2133 * Return value:
2134 * nothing
2135 ********************************************************************* */
2136 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2137 {
2138 struct sbmac_softc *sc = netdev_priv(dev);
2139
2140 /* lock eth irq */
2141 spin_lock_irq (&sc->sbm_lock);
2142
2143 /*
2144 * Put the buffer on the transmit ring. If we
2145 * don't have room, stop the queue.
2146 */
2147
2148 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2149 /* XXX save skb that we could not send */
2150 netif_stop_queue(dev);
2151 spin_unlock_irq(&sc->sbm_lock);
2152
2153 return 1;
2154 }
2155
2156 dev->trans_start = jiffies;
2157
2158 spin_unlock_irq (&sc->sbm_lock);
2159
2160 return 0;
2161 }
2162
2163 /**********************************************************************
2164 * SBMAC_SETMULTI(sc)
2165 *
2166 * Reprogram the multicast table into the hardware, given
2167 * the list of multicasts associated with the interface
2168 * structure.
2169 *
2170 * Input parameters:
2171 * sc - softc
2172 *
2173 * Return value:
2174 * nothing
2175 ********************************************************************* */
2176
2177 static void sbmac_setmulti(struct sbmac_softc *sc)
2178 {
2179 uint64_t reg;
2180 sbmac_port_t port;
2181 int idx;
2182 struct dev_mc_list *mclist;
2183 struct net_device *dev = sc->sbm_dev;
2184
2185 /*
2186 * Clear out entire multicast table. We do this by nuking
2187 * the entire hash table and all the direct matches except
2188 * the first one, which is used for our station address
2189 */
2190
2191 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2192 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2193 SBMAC_WRITECSR(port,0);
2194 }
2195
2196 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2197 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2198 SBMAC_WRITECSR(port,0);
2199 }
2200
2201 /*
2202 * Clear the filter to say we don't want any multicasts.
2203 */
2204
2205 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2206 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2207 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2208
2209 if (dev->flags & IFF_ALLMULTI) {
2210 /*
2211 * Enable ALL multicasts. Do this by inverting the
2212 * multicast enable bit.
2213 */
2214 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2215 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2216 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2217 return;
2218 }
2219
2220
2221 /*
2222 * Progam new multicast entries. For now, only use the
2223 * perfect filter. In the future we'll need to use the
2224 * hash filter if the perfect filter overflows
2225 */
2226
2227 /* XXX only using perfect filter for now, need to use hash
2228 * XXX if the table overflows */
2229
2230 idx = 1; /* skip station address */
2231 mclist = dev->mc_list;
2232 while (mclist && (idx < MAC_ADDR_COUNT)) {
2233 reg = sbmac_addr2reg(mclist->dmi_addr);
2234 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2235 SBMAC_WRITECSR(port,reg);
2236 idx++;
2237 mclist = mclist->next;
2238 }
2239
2240 /*
2241 * Enable the "accept multicast bits" if we programmed at least one
2242 * multicast.
2243 */
2244
2245 if (idx > 1) {
2246 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2247 reg |= M_MAC_MCAST_EN;
2248 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2249 }
2250 }
2251
2252
2253
2254 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2255 /**********************************************************************
2256 * SBMAC_PARSE_XDIGIT(str)
2257 *
2258 * Parse a hex digit, returning its value
2259 *
2260 * Input parameters:
2261 * str - character
2262 *
2263 * Return value:
2264 * hex value, or -1 if invalid
2265 ********************************************************************* */
2266
2267 static int sbmac_parse_xdigit(char str)
2268 {
2269 int digit;
2270
2271 if ((str >= '0') && (str <= '9'))
2272 digit = str - '0';
2273 else if ((str >= 'a') && (str <= 'f'))
2274 digit = str - 'a' + 10;
2275 else if ((str >= 'A') && (str <= 'F'))
2276 digit = str - 'A' + 10;
2277 else
2278 return -1;
2279
2280 return digit;
2281 }
2282
2283 /**********************************************************************
2284 * SBMAC_PARSE_HWADDR(str,hwaddr)
2285 *
2286 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2287 * Ethernet address.
2288 *
2289 * Input parameters:
2290 * str - string
2291 * hwaddr - pointer to hardware address
2292 *
2293 * Return value:
2294 * 0 if ok, else -1
2295 ********************************************************************* */
2296
2297 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2298 {
2299 int digit1,digit2;
2300 int idx = 6;
2301
2302 while (*str && (idx > 0)) {
2303 digit1 = sbmac_parse_xdigit(*str);
2304 if (digit1 < 0)
2305 return -1;
2306 str++;
2307 if (!*str)
2308 return -1;
2309
2310 if ((*str == ':') || (*str == '-')) {
2311 digit2 = digit1;
2312 digit1 = 0;
2313 }
2314 else {
2315 digit2 = sbmac_parse_xdigit(*str);
2316 if (digit2 < 0)
2317 return -1;
2318 str++;
2319 }
2320
2321 *hwaddr++ = (digit1 << 4) | digit2;
2322 idx--;
2323
2324 if (*str == '-')
2325 str++;
2326 if (*str == ':')
2327 str++;
2328 }
2329 return 0;
2330 }
2331 #endif
2332
2333 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2334 {
2335 if (new_mtu > ENET_PACKET_SIZE)
2336 return -EINVAL;
2337 _dev->mtu = new_mtu;
2338 printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2339 return 0;
2340 }
2341
2342 /**********************************************************************
2343 * SBMAC_INIT(dev)
2344 *
2345 * Attach routine - init hardware and hook ourselves into linux
2346 *
2347 * Input parameters:
2348 * dev - net_device structure
2349 *
2350 * Return value:
2351 * status
2352 ********************************************************************* */
2353
2354 static int sbmac_init(struct net_device *dev, int idx)
2355 {
2356 struct sbmac_softc *sc;
2357 unsigned char *eaddr;
2358 uint64_t ea_reg;
2359 int i;
2360 int err;
2361
2362 sc = netdev_priv(dev);
2363
2364 /* Determine controller base address */
2365
2366 sc->sbm_base = IOADDR(dev->base_addr);
2367 sc->sbm_dev = dev;
2368 sc->sbe_idx = idx;
2369
2370 eaddr = sc->sbm_hwaddr;
2371
2372 /*
2373 * Read the ethernet address. The firwmare left this programmed
2374 * for us in the ethernet address register for each mac.
2375 */
2376
2377 ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2378 SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0);
2379 for (i = 0; i < 6; i++) {
2380 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2381 ea_reg >>= 8;
2382 }
2383
2384 for (i = 0; i < 6; i++) {
2385 dev->dev_addr[i] = eaddr[i];
2386 }
2387
2388
2389 /*
2390 * Init packet size
2391 */
2392
2393 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2394
2395 /*
2396 * Initialize context (get pointers to registers and stuff), then
2397 * allocate the memory for the descriptor tables.
2398 */
2399
2400 sbmac_initctx(sc);
2401
2402 /*
2403 * Set up Linux device callins
2404 */
2405
2406 spin_lock_init(&(sc->sbm_lock));
2407
2408 dev->open = sbmac_open;
2409 dev->hard_start_xmit = sbmac_start_tx;
2410 dev->stop = sbmac_close;
2411 dev->get_stats = sbmac_get_stats;
2412 dev->set_multicast_list = sbmac_set_rx_mode;
2413 dev->do_ioctl = sbmac_mii_ioctl;
2414 dev->tx_timeout = sbmac_tx_timeout;
2415 dev->watchdog_timeo = TX_TIMEOUT;
2416
2417 dev->change_mtu = sb1250_change_mtu;
2418
2419 /* This is needed for PASS2 for Rx H/W checksum feature */
2420 sbmac_set_iphdr_offset(sc);
2421
2422 err = register_netdev(dev);
2423 if (err)
2424 goto out_uninit;
2425
2426 /*
2427 * Display Ethernet address (this is called during the config
2428 * process so we need to finish off the config message that
2429 * was being displayed)
2430 */
2431 printk(KERN_INFO
2432 "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2433 dev->name, dev->base_addr,
2434 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2435
2436
2437 return 0;
2438
2439 out_uninit:
2440 sbmac_uninitctx(sc);
2441
2442 return err;
2443 }
2444
2445
2446 static int sbmac_open(struct net_device *dev)
2447 {
2448 struct sbmac_softc *sc = netdev_priv(dev);
2449
2450 if (debug > 1) {
2451 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2452 }
2453
2454 /*
2455 * map/route interrupt (clear status first, in case something
2456 * weird is pending; we haven't initialized the mac registers
2457 * yet)
2458 */
2459
2460 SBMAC_READCSR(sc->sbm_isr);
2461 if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev))
2462 return -EBUSY;
2463
2464 /*
2465 * Configure default speed
2466 */
2467
2468 sbmac_mii_poll(sc,noisy_mii);
2469
2470 /*
2471 * Turn on the channel
2472 */
2473
2474 sbmac_set_channel_state(sc,sbmac_state_on);
2475
2476 /*
2477 * XXX Station address is in dev->dev_addr
2478 */
2479
2480 if (dev->if_port == 0)
2481 dev->if_port = 0;
2482
2483 netif_start_queue(dev);
2484
2485 sbmac_set_rx_mode(dev);
2486
2487 /* Set the timer to check for link beat. */
2488 init_timer(&sc->sbm_timer);
2489 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2490 sc->sbm_timer.data = (unsigned long)dev;
2491 sc->sbm_timer.function = &sbmac_timer;
2492 add_timer(&sc->sbm_timer);
2493
2494 return 0;
2495 }
2496
2497
2498
2499 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2500 {
2501 int bmsr,bmcr,k1stsr,anlpar;
2502 int chg;
2503 char buffer[100];
2504 char *p = buffer;
2505
2506 /* Read the mode status and mode control registers. */
2507 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2508 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2509
2510 /* get the link partner status */
2511 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2512
2513 /* if supported, read the 1000baseT register */
2514 if (bmsr & BMSR_1000BT_XSR) {
2515 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2516 }
2517 else {
2518 k1stsr = 0;
2519 }
2520
2521 chg = 0;
2522
2523 if ((bmsr & BMSR_LINKSTAT) == 0) {
2524 /*
2525 * If link status is down, clear out old info so that when
2526 * it comes back up it will force us to reconfigure speed
2527 */
2528 s->sbm_phy_oldbmsr = 0;
2529 s->sbm_phy_oldanlpar = 0;
2530 s->sbm_phy_oldk1stsr = 0;
2531 return 0;
2532 }
2533
2534 if ((s->sbm_phy_oldbmsr != bmsr) ||
2535 (s->sbm_phy_oldanlpar != anlpar) ||
2536 (s->sbm_phy_oldk1stsr != k1stsr)) {
2537 if (debug > 1) {
2538 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2539 s->sbm_dev->name,
2540 s->sbm_phy_oldbmsr,bmsr,
2541 s->sbm_phy_oldanlpar,anlpar,
2542 s->sbm_phy_oldk1stsr,k1stsr);
2543 }
2544 s->sbm_phy_oldbmsr = bmsr;
2545 s->sbm_phy_oldanlpar = anlpar;
2546 s->sbm_phy_oldk1stsr = k1stsr;
2547 chg = 1;
2548 }
2549
2550 if (chg == 0)
2551 return 0;
2552
2553 p += sprintf(p,"Link speed: ");
2554
2555 if (k1stsr & K1STSR_LP1KFD) {
2556 s->sbm_speed = sbmac_speed_1000;
2557 s->sbm_duplex = sbmac_duplex_full;
2558 s->sbm_fc = sbmac_fc_frame;
2559 p += sprintf(p,"1000BaseT FDX");
2560 }
2561 else if (k1stsr & K1STSR_LP1KHD) {
2562 s->sbm_speed = sbmac_speed_1000;
2563 s->sbm_duplex = sbmac_duplex_half;
2564 s->sbm_fc = sbmac_fc_disabled;
2565 p += sprintf(p,"1000BaseT HDX");
2566 }
2567 else if (anlpar & ANLPAR_TXFD) {
2568 s->sbm_speed = sbmac_speed_100;
2569 s->sbm_duplex = sbmac_duplex_full;
2570 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2571 p += sprintf(p,"100BaseT FDX");
2572 }
2573 else if (anlpar & ANLPAR_TXHD) {
2574 s->sbm_speed = sbmac_speed_100;
2575 s->sbm_duplex = sbmac_duplex_half;
2576 s->sbm_fc = sbmac_fc_disabled;
2577 p += sprintf(p,"100BaseT HDX");
2578 }
2579 else if (anlpar & ANLPAR_10FD) {
2580 s->sbm_speed = sbmac_speed_10;
2581 s->sbm_duplex = sbmac_duplex_full;
2582 s->sbm_fc = sbmac_fc_frame;
2583 p += sprintf(p,"10BaseT FDX");
2584 }
2585 else if (anlpar & ANLPAR_10HD) {
2586 s->sbm_speed = sbmac_speed_10;
2587 s->sbm_duplex = sbmac_duplex_half;
2588 s->sbm_fc = sbmac_fc_collision;
2589 p += sprintf(p,"10BaseT HDX");
2590 }
2591 else {
2592 p += sprintf(p,"Unknown");
2593 }
2594
2595 if (noisy) {
2596 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2597 }
2598
2599 return 1;
2600 }
2601
2602
2603 static void sbmac_timer(unsigned long data)
2604 {
2605 struct net_device *dev = (struct net_device *)data;
2606 struct sbmac_softc *sc = netdev_priv(dev);
2607 int next_tick = HZ;
2608 int mii_status;
2609
2610 spin_lock_irq (&sc->sbm_lock);
2611
2612 /* make IFF_RUNNING follow the MII status bit "Link established" */
2613 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2614
2615 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2616 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2617 if (mii_status & BMSR_LINKSTAT) {
2618 netif_carrier_on(dev);
2619 }
2620 else {
2621 netif_carrier_off(dev);
2622 }
2623 }
2624
2625 /*
2626 * Poll the PHY to see what speed we should be running at
2627 */
2628
2629 if (sbmac_mii_poll(sc,noisy_mii)) {
2630 if (sc->sbm_state != sbmac_state_off) {
2631 /*
2632 * something changed, restart the channel
2633 */
2634 if (debug > 1) {
2635 printk("%s: restarting channel because speed changed\n",
2636 sc->sbm_dev->name);
2637 }
2638 sbmac_channel_stop(sc);
2639 sbmac_channel_start(sc);
2640 }
2641 }
2642
2643 spin_unlock_irq (&sc->sbm_lock);
2644
2645 sc->sbm_timer.expires = jiffies + next_tick;
2646 add_timer(&sc->sbm_timer);
2647 }
2648
2649
2650 static void sbmac_tx_timeout (struct net_device *dev)
2651 {
2652 struct sbmac_softc *sc = netdev_priv(dev);
2653
2654 spin_lock_irq (&sc->sbm_lock);
2655
2656
2657 dev->trans_start = jiffies;
2658 sc->sbm_stats.tx_errors++;
2659
2660 spin_unlock_irq (&sc->sbm_lock);
2661
2662 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2663 }
2664
2665
2666
2667
2668 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2669 {
2670 struct sbmac_softc *sc = netdev_priv(dev);
2671 unsigned long flags;
2672
2673 spin_lock_irqsave(&sc->sbm_lock, flags);
2674
2675 /* XXX update other stats here */
2676
2677 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2678
2679 return &sc->sbm_stats;
2680 }
2681
2682
2683
2684 static void sbmac_set_rx_mode(struct net_device *dev)
2685 {
2686 unsigned long flags;
2687 int msg_flag = 0;
2688 struct sbmac_softc *sc = netdev_priv(dev);
2689
2690 spin_lock_irqsave(&sc->sbm_lock, flags);
2691 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2692 /*
2693 * Promiscuous changed.
2694 */
2695
2696 if (dev->flags & IFF_PROMISC) {
2697 /* Unconditionally log net taps. */
2698 msg_flag = 1;
2699 sbmac_promiscuous_mode(sc,1);
2700 }
2701 else {
2702 msg_flag = 2;
2703 sbmac_promiscuous_mode(sc,0);
2704 }
2705 }
2706 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2707
2708 if (msg_flag) {
2709 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2710 dev->name,(msg_flag==1)?"en":"dis");
2711 }
2712
2713 /*
2714 * Program the multicasts. Do this every time.
2715 */
2716
2717 sbmac_setmulti(sc);
2718
2719 }
2720
2721 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2722 {
2723 struct sbmac_softc *sc = netdev_priv(dev);
2724 u16 *data = (u16 *)&rq->ifr_ifru;
2725 unsigned long flags;
2726 int retval;
2727
2728 spin_lock_irqsave(&sc->sbm_lock, flags);
2729 retval = 0;
2730
2731 switch(cmd) {
2732 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2733 data[0] = sc->sbm_phys[0] & 0x1f;
2734 /* Fall Through */
2735 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2736 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2737 break;
2738 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2739 if (!capable(CAP_NET_ADMIN)) {
2740 retval = -EPERM;
2741 break;
2742 }
2743 if (debug > 1) {
2744 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2745 data[0],data[1],data[2]);
2746 }
2747 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2748 break;
2749 default:
2750 retval = -EOPNOTSUPP;
2751 }
2752
2753 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2754 return retval;
2755 }
2756
2757 static int sbmac_close(struct net_device *dev)
2758 {
2759 struct sbmac_softc *sc = netdev_priv(dev);
2760 unsigned long flags;
2761 int irq;
2762
2763 sbmac_set_channel_state(sc,sbmac_state_off);
2764
2765 del_timer_sync(&sc->sbm_timer);
2766
2767 spin_lock_irqsave(&sc->sbm_lock, flags);
2768
2769 netif_stop_queue(dev);
2770
2771 if (debug > 1) {
2772 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2773 }
2774
2775 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2776
2777 irq = dev->irq;
2778 synchronize_irq(irq);
2779 free_irq(irq, dev);
2780
2781 sbdma_emptyring(&(sc->sbm_txdma));
2782 sbdma_emptyring(&(sc->sbm_rxdma));
2783
2784 return 0;
2785 }
2786
2787
2788
2789 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2790 static void
2791 sbmac_setup_hwaddr(int chan,char *addr)
2792 {
2793 uint8_t eaddr[6];
2794 uint64_t val;
2795 sbmac_port_t port;
2796
2797 port = A_MAC_CHANNEL_BASE(chan);
2798 sbmac_parse_hwaddr(addr,eaddr);
2799 val = sbmac_addr2reg(eaddr);
2800 SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR),val);
2801 val = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
2802 }
2803 #endif
2804
2805 static struct net_device *dev_sbmac[MAX_UNITS];
2806
2807 static int __init
2808 sbmac_init_module(void)
2809 {
2810 int idx;
2811 struct net_device *dev;
2812 sbmac_port_t port;
2813 int chip_max_units;
2814
2815 /*
2816 * For bringup when not using the firmware, we can pre-fill
2817 * the MAC addresses using the environment variables
2818 * specified in this file (or maybe from the config file?)
2819 */
2820 #ifdef SBMAC_ETH0_HWADDR
2821 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2822 #endif
2823 #ifdef SBMAC_ETH1_HWADDR
2824 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2825 #endif
2826 #ifdef SBMAC_ETH2_HWADDR
2827 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2828 #endif
2829
2830 /*
2831 * Walk through the Ethernet controllers and find
2832 * those who have their MAC addresses set.
2833 */
2834 switch (soc_type) {
2835 case K_SYS_SOC_TYPE_BCM1250:
2836 case K_SYS_SOC_TYPE_BCM1250_ALT:
2837 chip_max_units = 3;
2838 break;
2839 case K_SYS_SOC_TYPE_BCM1120:
2840 case K_SYS_SOC_TYPE_BCM1125:
2841 case K_SYS_SOC_TYPE_BCM1125H:
2842 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2843 chip_max_units = 2;
2844 break;
2845 default:
2846 chip_max_units = 0;
2847 break;
2848 }
2849 if (chip_max_units > MAX_UNITS)
2850 chip_max_units = MAX_UNITS;
2851
2852 for (idx = 0; idx < chip_max_units; idx++) {
2853
2854 /*
2855 * This is the base address of the MAC.
2856 */
2857
2858 port = A_MAC_CHANNEL_BASE(idx);
2859
2860 /*
2861 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2862 * value for us by the firmware if we're going to use this MAC.
2863 * If we find a zero, skip this MAC.
2864 */
2865
2866 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
2867 if (sbmac_orig_hwaddr[idx] == 0) {
2868 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2869 "%lx\n", port);
2870 continue;
2871 }
2872
2873 /*
2874 * Okay, cool. Initialize this MAC.
2875 */
2876
2877 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2878 if (!dev)
2879 return -ENOMEM; /* return ENOMEM */
2880
2881 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2882
2883 dev->irq = K_INT_MAC_0 + idx;
2884 dev->base_addr = port;
2885 dev->mem_end = 0;
2886 if (sbmac_init(dev, idx)) {
2887 port = A_MAC_CHANNEL_BASE(idx);
2888 SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR),
2889 sbmac_orig_hwaddr[idx] );
2890 free_netdev(dev);
2891 continue;
2892 }
2893 dev_sbmac[idx++] = dev;
2894 }
2895 return 0;
2896 }
2897
2898
2899 static void __exit
2900 sbmac_cleanup_module(void)
2901 {
2902 struct net_device *dev;
2903 int idx;
2904
2905 for (idx = 0; idx < MAX_UNITS; idx++) {
2906 struct sbmac_softc *sc;
2907 dev = dev_sbmac[idx];
2908 if (!dev)
2909 continue;
2910
2911 sc = netdev_priv(dev);
2912 unregister_netdev(dev);
2913 sbmac_uninitctx(sc);
2914 free_netdev(dev);
2915 }
2916 }
2917
2918 module_init(sbmac_init_module);
2919 module_exit(sbmac_cleanup_module);
Historical 2.5/2.6 development