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[ARM] Don't sleep in cpufreq code if IRQs are disabled (during resume.)
[linux-2.6/history.git] / sound / pci / rme32.c
blobee6feb9ce3022cc408ff2d42fd9634df5417f2d0
1 /*
2 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3 *
4 * Copyright (c) 2002, 2003 Martin Langer <martin-langer@gmx.de>
5 *
6 * Thanks to : Anders Torger <torger@ludd.luth.se>,
7 * Henk Hesselink <henk@anda.nl>
8 * for writing the digi96-driver
9 * and RME for all informations.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * ****************************************************************************
27 *
28 * Note #1 "Sek'd models" ................................... martin 2002-12-07
29 *
30 * Identical soundcards by Sek'd were labeled:
31 * RME Digi 32 = Sek'd Prodif 32
32 * RME Digi 32 Pro = Sek'd Prodif 96
33 * RME Digi 32/8 = Sek'd Prodif Gold
34 *
35 * ****************************************************************************
36 *
37 * Note #2 "full duplex mode" ............................... martin 2002-12-07
38 *
39 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
40 * in this mode. Rec data and play data are using the same buffer therefore. At
41 * first you have got the playing bits in the buffer and then (after playing
42 * them) they were overwitten by the captured sound of the CS8412/14. Both
43 * modes (play/record) are running harmonically hand in hand in the same buffer
44 * and you have only one start bit plus one interrupt bit to control this
45 * paired action.
46 * This is opposite to the latter rme96 where playing and capturing is totally
47 * separated and so their full duplex mode is supported by alsa (using two
48 * start bits and two interrupts for two different buffers).
49 * But due to the wrong sequence of playing and capturing ALSA shows no solved
50 * full duplex support for the rme32 at the moment. That's bad, but I'm not
51 * able to solve it. Are you motivated enough to solve this problem now? Your
52 * patch would be welcome!
53 *
54 * ****************************************************************************
55 */
56
57
58 #include <sound/driver.h>
59 #include <linux/delay.h>
60 #include <linux/init.h>
61 #include <linux/interrupt.h>
62 #include <linux/pci.h>
63 #include <linux/slab.h>
64
65 #include <sound/core.h>
66 #include <sound/info.h>
67 #include <sound/control.h>
68 #include <sound/pcm.h>
69 #include <sound/pcm_params.h>
70 #include <sound/asoundef.h>
71 #define SNDRV_GET_ID
72 #include <sound/initval.h>
73
74 #include <asm/io.h>
75
76 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
77 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
78 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
79
80 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
81 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
82 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
83 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
84 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
85 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
86 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
87 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
88 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
89 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>");
90 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
91 MODULE_LICENSE("GPL");
92 MODULE_CLASSES("{sound}");
93 MODULE_DEVICES("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
94
95 /* Defines for RME Digi32 series */
96 #define RME32_SPDIF_NCHANNELS 2
97
98 /* Playback and capture buffer size */
99 #define RME32_BUFFER_SIZE 0x20000
100
101 /* IO area size */
102 #define RME32_IO_SIZE 0x30000
103
104 /* IO area offsets */
105 #define RME32_IO_DATA_BUFFER 0x0
106 #define RME32_IO_CONTROL_REGISTER 0x20000
107 #define RME32_IO_GET_POS 0x20000
108 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
109 #define RME32_IO_RESET_POS 0x20100
110
111 /* Write control register bits */
112 #define RME32_WCR_START (1 << 0) /* startbit */
113 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
114 Setting the whole card to mono
115 doesn't seem to be very useful.
116 A software-solution can handle
117 full-duplex with one direction in
118 stereo and the other way in mono.
119 So, the hardware should work all
120 the time in stereo! */
121 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
122 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
123 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
124 #define RME32_WCR_FREQ_1 (1 << 5)
125 #define RME32_WCR_INP_0 (1 << 6) /* input switch */
126 #define RME32_WCR_INP_1 (1 << 7)
127 #define RME32_WCR_RESET (1 << 8) /* Reset address */
128 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
129 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
130 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
131 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
132 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
133 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
134 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
135
136 #define RME32_WCR_BITPOS_FREQ_0 4
137 #define RME32_WCR_BITPOS_FREQ_1 5
138 #define RME32_WCR_BITPOS_INP_0 6
139 #define RME32_WCR_BITPOS_INP_1 7
140
141 /* Read control register bits */
142 #define RME32_RCR_AUDIO_ADDR_MASK 0x10001
143 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
144 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
145 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
146 #define RME32_RCR_FREQ_1 (1 << 28)
147 #define RME32_RCR_FREQ_2 (1 << 29)
148 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
149 #define RME32_RCR_IRQ (1 << 31) /* interrupt */
150
151 #define RME32_RCR_BITPOS_F0 27
152 #define RME32_RCR_BITPOS_F1 28
153 #define RME32_RCR_BITPOS_F2 29
154
155 /* Input types */
156 #define RME32_INPUT_OPTICAL 0
157 #define RME32_INPUT_COAXIAL 1
158 #define RME32_INPUT_INTERNAL 2
159 #define RME32_INPUT_XLR 3
160
161 /* Clock modes */
162 #define RME32_CLOCKMODE_SLAVE 0
163 #define RME32_CLOCKMODE_MASTER_32 1
164 #define RME32_CLOCKMODE_MASTER_44 2
165 #define RME32_CLOCKMODE_MASTER_48 3
166
167 /* Block sizes in bytes */
168 #define RME32_BLOCK_SIZE 8192
169
170 /* Hardware revisions */
171 #define RME32_32_REVISION 192
172 #define RME32_328_REVISION_OLD 100
173 #define RME32_328_REVISION_NEW 101
174 #define RME32_PRO_REVISION_WITH_8412 192
175 #define RME32_PRO_REVISION_WITH_8414 150
176
177
178 /* PCI vendor/device ID's */
179 #ifndef PCI_VENDOR_ID_XILINX_RME
180 # define PCI_VENDOR_ID_XILINX_RME 0xea60
181 #endif
182 #ifndef PCI_DEVICE_ID_DIGI32
183 # define PCI_DEVICE_ID_DIGI32 0x9896
184 #endif
185 #ifndef PCI_DEVICE_ID_DIGI32_PRO
186 # define PCI_DEVICE_ID_DIGI32_PRO 0x9897
187 #endif
188 #ifndef PCI_DEVICE_ID_DIGI32_8
189 # define PCI_DEVICE_ID_DIGI32_8 0x9898
190 #endif
191
192 typedef struct snd_rme32 {
193 spinlock_t lock;
194 int irq;
195 unsigned long port;
196 struct resource *res_port;
197 unsigned long iobase;
198
199 u32 wcreg; /* cached write control register value */
200 u32 wcreg_spdif; /* S/PDIF setup */
201 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
202 u32 rcreg; /* cached read control register value */
203
204 u8 rev; /* card revision number */
205
206 snd_pcm_substream_t *playback_substream;
207 snd_pcm_substream_t *capture_substream;
208
209 int playback_frlog; /* log2 of framesize */
210 int capture_frlog;
211
212 size_t playback_periodsize; /* in bytes, zero if not used */
213 size_t capture_periodsize; /* in bytes, zero if not used */
214
215 snd_pcm_uframes_t playback_last_appl_ptr;
216 size_t playback_ptr;
217 size_t capture_ptr;
218
219 snd_card_t *card;
220 snd_pcm_t *spdif_pcm;
221 snd_pcm_t *adat_pcm;
222 struct pci_dev *pci;
223 snd_kcontrol_t *spdif_ctl;
224 } rme32_t;
225
226 static struct pci_device_id snd_rme32_ids[] = {
227 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
229 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_8,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
231 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_PRO,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
233 {0,}
234 };
235
236 MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
237
238 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
239 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
240
241 static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream);
242
243 static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream);
244
245 static int
246 snd_rme32_playback_trigger(snd_pcm_substream_t * substream, int cmd);
247
248 static int
249 snd_rme32_capture_trigger(snd_pcm_substream_t * substream, int cmd);
250
251 static snd_pcm_uframes_t
252 snd_rme32_playback_pointer(snd_pcm_substream_t * substream);
253
254 static snd_pcm_uframes_t
255 snd_rme32_capture_pointer(snd_pcm_substream_t * substream);
256
257 static void snd_rme32_proc_init(rme32_t * rme32);
258
259 static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32);
260
261 static inline unsigned int snd_rme32_playback_ptr(rme32_t * rme32)
262 {
263
264 return (readl(rme32->iobase + RME32_IO_GET_POS)
265 & RME32_RCR_AUDIO_ADDR_MASK) >> rme32->playback_frlog;
266 }
267
268 static inline unsigned int snd_rme32_capture_ptr(rme32_t * rme32)
269 {
270 return (readl(rme32->iobase + RME32_IO_GET_POS)
271 & RME32_RCR_AUDIO_ADDR_MASK) >> rme32->capture_frlog;
272 }
273
274 static int snd_rme32_ratecode(int rate)
275 {
276 switch (rate) {
277 case 32000: return SNDRV_PCM_RATE_32000;
278 case 44100: return SNDRV_PCM_RATE_44100;
279 case 48000: return SNDRV_PCM_RATE_48000;
280 case 64000: return SNDRV_PCM_RATE_64000;
281 case 88200: return SNDRV_PCM_RATE_88200;
282 case 96000: return SNDRV_PCM_RATE_96000;
283 }
284 return 0;
285 }
286
287 static int snd_rme32_playback_silence(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
288 snd_pcm_uframes_t pos,
289 snd_pcm_uframes_t count)
290 {
291 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
292 count <<= rme32->playback_frlog;
293 pos <<= rme32->playback_frlog;
294 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
295 return 0;
296 }
297
298 static int snd_rme32_playback_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
299 snd_pcm_uframes_t pos,
300 void *src, snd_pcm_uframes_t count)
301 {
302 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
303 count <<= rme32->playback_frlog;
304 pos <<= rme32->playback_frlog;
305 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
306 src, count))
307 return -EFAULT;
308 return 0;
309 }
310
311 static int snd_rme32_capture_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
312 snd_pcm_uframes_t pos,
313 void *dst, snd_pcm_uframes_t count)
314 {
315 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
316 count <<= rme32->capture_frlog;
317 pos <<= rme32->capture_frlog;
318 if (copy_to_user_fromio(dst,
319 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
320 count))
321 return -EFAULT;
322 return 0;
323 }
324
325 /*
326 * Digital output capabilites (S/PDIF)
327 */
328 static snd_pcm_hardware_t snd_rme32_playback_spdif_info = {
329 .info = (SNDRV_PCM_INFO_MMAP |
330 SNDRV_PCM_INFO_MMAP_VALID |
331 SNDRV_PCM_INFO_INTERLEAVED |
332 SNDRV_PCM_INFO_PAUSE),
333 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
334 SNDRV_PCM_FMTBIT_S32_LE),
335 .rates = (SNDRV_PCM_RATE_32000 |
336 SNDRV_PCM_RATE_44100 |
337 SNDRV_PCM_RATE_48000),
338 .rate_min = 32000,
339 .rate_max = 48000,
340 .channels_min = 2,
341 .channels_max = 2,
342 .buffer_bytes_max = RME32_BUFFER_SIZE,
343 .period_bytes_min = RME32_BLOCK_SIZE,
344 .period_bytes_max = RME32_BLOCK_SIZE,
345 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
346 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
347 .fifo_size = 0,
348 };
349
350 /*
351 * Digital input capabilites (S/PDIF)
352 */
353 static snd_pcm_hardware_t snd_rme32_capture_spdif_info = {
354 .info = (SNDRV_PCM_INFO_MMAP |
355 SNDRV_PCM_INFO_MMAP_VALID |
356 SNDRV_PCM_INFO_INTERLEAVED |
357 SNDRV_PCM_INFO_PAUSE),
358 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
359 SNDRV_PCM_FMTBIT_S32_LE),
360 .rates = (SNDRV_PCM_RATE_32000 |
361 SNDRV_PCM_RATE_44100 |
362 SNDRV_PCM_RATE_48000),
363 .rate_min = 32000,
364 .rate_max = 48000,
365 .channels_min = 2,
366 .channels_max = 2,
367 .buffer_bytes_max = RME32_BUFFER_SIZE,
368 .period_bytes_min = RME32_BLOCK_SIZE,
369 .period_bytes_max = RME32_BLOCK_SIZE,
370 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
371 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
372 .fifo_size = 0,
373 };
374
375 /*
376 * Digital output capabilites (ADAT)
377 */
378 static snd_pcm_hardware_t snd_rme32_playback_adat_info =
379 {
380 .info = (SNDRV_PCM_INFO_MMAP |
381 SNDRV_PCM_INFO_MMAP_VALID |
382 SNDRV_PCM_INFO_INTERLEAVED |
383 SNDRV_PCM_INFO_PAUSE),
384 .formats= SNDRV_PCM_FMTBIT_S16_LE,
385 .rates = (SNDRV_PCM_RATE_44100 |
386 SNDRV_PCM_RATE_48000),
387 .rate_min = 44100,
388 .rate_max = 48000,
389 .channels_min = 8,
390 .channels_max = 8,
391 .buffer_bytes_max = RME32_BUFFER_SIZE,
392 .period_bytes_min = RME32_BLOCK_SIZE,
393 .period_bytes_max = RME32_BLOCK_SIZE,
394 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
395 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
396 .fifo_size = 0,
397 };
398
399 /*
400 * Digital input capabilites (ADAT)
401 */
402 static snd_pcm_hardware_t snd_rme32_capture_adat_info =
403 {
404 .info = (SNDRV_PCM_INFO_MMAP |
405 SNDRV_PCM_INFO_MMAP_VALID |
406 SNDRV_PCM_INFO_INTERLEAVED |
407 SNDRV_PCM_INFO_PAUSE),
408 .formats = SNDRV_PCM_FMTBIT_S16_LE,
409 .rates = (SNDRV_PCM_RATE_44100 |
410 SNDRV_PCM_RATE_48000),
411 .rate_min = 44100,
412 .rate_max = 48000,
413 .channels_min = 8,
414 .channels_max = 8,
415 .buffer_bytes_max = RME32_BUFFER_SIZE,
416 .period_bytes_min = RME32_BLOCK_SIZE,
417 .period_bytes_max = RME32_BLOCK_SIZE,
418 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
419 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
420 .fifo_size = 0,
421 };
422
423 static void snd_rme32_reset_dac(rme32_t *rme32)
424 {
425 writel(rme32->wcreg | RME32_WCR_PD,
426 rme32->iobase + RME32_IO_CONTROL_REGISTER);
427 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
428 }
429
430 static int snd_rme32_playback_getrate(rme32_t * rme32)
431 {
432 int rate;
433
434 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
435 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
436 switch (rate) {
437 case 1:
438 rate = 32000;
439 break;
440 case 2:
441 rate = 44100;
442 break;
443 case 3:
444 rate = 48000;
445 break;
446 default:
447 return -1;
448 }
449 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
450 }
451
452 static int snd_rme32_capture_getrate(rme32_t * rme32, int *is_adat)
453 {
454 int n;
455
456 *is_adat = 0;
457 if (rme32->rcreg & RME32_RCR_LOCK) {
458 /* ADAT rate */
459 *is_adat = 1;
460 }
461 if (rme32->rcreg & RME32_RCR_ERF) {
462 return -1;
463 }
464
465 /* S/PDIF rate */
466 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
467 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
468 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
469
470 if (RME32_PRO_WITH_8414(rme32))
471 switch (n) { /* supporting the CS8414 */
472 case 0:
473 case 1:
474 case 2:
475 return -1;
476 case 3:
477 return 96000;
478 case 4:
479 return 88200;
480 case 5:
481 return 48000;
482 case 6:
483 return 44100;
484 case 7:
485 return 32000;
486 default:
487 return -1;
488 break;
489 }
490 else
491 switch (n) { /* supporting the CS8412 */
492 case 0:
493 return -1;
494 case 1:
495 return 48000;
496 case 2:
497 return 44100;
498 case 3:
499 return 32000;
500 case 4:
501 return 48000;
502 case 5:
503 return 44100;
504 case 6:
505 return 44056;
506 case 7:
507 return 32000;
508 default:
509 break;
510 }
511 return -1;
512 }
513
514 static int snd_rme32_playback_setrate(rme32_t * rme32, int rate)
515 {
516 int ds;
517
518 ds = rme32->wcreg & RME32_WCR_DS_BM;
519 switch (rate) {
520 case 32000:
521 rme32->wcreg &= ~RME32_WCR_DS_BM;
522 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
523 ~RME32_WCR_FREQ_1;
524 break;
525 case 44100:
526 rme32->wcreg &= ~RME32_WCR_DS_BM;
527 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
528 ~RME32_WCR_FREQ_0;
529 break;
530 case 48000:
531 rme32->wcreg &= ~RME32_WCR_DS_BM;
532 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
533 RME32_WCR_FREQ_1;
534 break;
535 case 64000:
536 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
537 return -EINVAL;
538 rme32->wcreg |= RME32_WCR_DS_BM;
539 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
540 ~RME32_WCR_FREQ_1;
541 break;
542 case 88200:
543 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
544 return -EINVAL;
545 rme32->wcreg |= RME32_WCR_DS_BM;
546 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
547 ~RME32_WCR_FREQ_0;
548 break;
549 case 96000:
550 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
551 return -EINVAL;
552 rme32->wcreg |= RME32_WCR_DS_BM;
553 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
554 RME32_WCR_FREQ_1;
555 break;
556 default:
557 return -EINVAL;
558 }
559 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
560 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
561 {
562 /* change to/from double-speed: reset the DAC (if available) */
563 snd_rme32_reset_dac(rme32);
564 } else {
565 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
566 }
567 return 0;
568 }
569
570 static int snd_rme32_setclockmode(rme32_t * rme32, int mode)
571 {
572 switch (mode) {
573 case RME32_CLOCKMODE_SLAVE:
574 /* AutoSync */
575 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
576 ~RME32_WCR_FREQ_1;
577 break;
578 case RME32_CLOCKMODE_MASTER_32:
579 /* Internal 32.0kHz */
580 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
581 ~RME32_WCR_FREQ_1;
582 break;
583 case RME32_CLOCKMODE_MASTER_44:
584 /* Internal 44.1kHz */
585 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
586 RME32_WCR_FREQ_1;
587 break;
588 case RME32_CLOCKMODE_MASTER_48:
589 /* Internal 48.0kHz */
590 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
591 RME32_WCR_FREQ_1;
592 break;
593 default:
594 return -EINVAL;
595 }
596 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
597 return 0;
598 }
599
600 static int snd_rme32_getclockmode(rme32_t * rme32)
601 {
602 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
603 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
604 }
605
606 static int snd_rme32_setinputtype(rme32_t * rme32, int type)
607 {
608 switch (type) {
609 case RME32_INPUT_OPTICAL:
610 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
611 ~RME32_WCR_INP_1;
612 break;
613 case RME32_INPUT_COAXIAL:
614 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
615 ~RME32_WCR_INP_1;
616 break;
617 case RME32_INPUT_INTERNAL:
618 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
619 RME32_WCR_INP_1;
620 break;
621 case RME32_INPUT_XLR:
622 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
623 RME32_WCR_INP_1;
624 break;
625 default:
626 return -EINVAL;
627 }
628 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
629 return 0;
630 }
631
632 static int snd_rme32_getinputtype(rme32_t * rme32)
633 {
634 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
635 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
636 }
637
638 static void
639 snd_rme32_setframelog(rme32_t * rme32, int n_channels, int is_playback)
640 {
641 int frlog;
642
643 if (n_channels == 2) {
644 frlog = 1;
645 } else {
646 /* assume 8 channels */
647 frlog = 3;
648 }
649 if (is_playback) {
650 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
651 rme32->playback_frlog = frlog;
652 } else {
653 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
654 rme32->capture_frlog = frlog;
655 }
656 }
657
658 static int snd_rme32_setformat(rme32_t * rme32, int format)
659 {
660 switch (format) {
661 case SNDRV_PCM_FORMAT_S16_LE:
662 rme32->wcreg &= ~RME32_WCR_MODE24;
663 break;
664 case SNDRV_PCM_FORMAT_S32_LE:
665 rme32->wcreg |= RME32_WCR_MODE24;
666 break;
667 default:
668 return -EINVAL;
669 }
670 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
671 return 0;
672 }
673
674 static int
675 snd_rme32_playback_hw_params(snd_pcm_substream_t * substream,
676 snd_pcm_hw_params_t * params)
677 {
678 int err, rate, dummy;
679 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
680
681 if ((err = snd_pcm_lib_malloc_pages(substream,
682 params_buffer_bytes(params))) < 0)
683 return err;
684 spin_lock_irq(&rme32->lock);
685 if ((rme32->rcreg & RME32_RCR_KMODE) &&
686 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
687 /* AutoSync */
688 if ((int)params_rate(params) != rate) {
689 spin_unlock_irq(&rme32->lock);
690 return -EIO;
691 }
692 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
693 spin_unlock_irq(&rme32->lock);
694 return err;
695 }
696 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
697 spin_unlock_irq(&rme32->lock);
698 return err;
699 }
700
701 snd_rme32_setframelog(rme32, params_channels(params), 1);
702 if (rme32->capture_periodsize != 0) {
703 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
704 spin_unlock_irq(&rme32->lock);
705 return -EBUSY;
706 }
707 }
708 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
709 /* S/PDIF setup */
710 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
711 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
712 writel(rme32->wcreg |=
713 rme32->wcreg_spdif_stream,
714 rme32->iobase + RME32_IO_CONTROL_REGISTER);
715 }
716 spin_unlock_irq(&rme32->lock);
717
718 return 0;
719 }
720
721 static int snd_rme32_playback_hw_free(snd_pcm_substream_t * substream)
722 {
723 snd_pcm_lib_free_pages(substream);
724 return 0;
725 }
726
727 static int
728 snd_rme32_capture_hw_params(snd_pcm_substream_t * substream,
729 snd_pcm_hw_params_t * params)
730 {
731 unsigned long flags;
732 int err, isadat, rate;
733 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
734 snd_pcm_runtime_t *runtime = substream->runtime;
735
736 if ((err = snd_pcm_lib_malloc_pages(substream,
737 params_buffer_bytes(params))) < 0)
738 return err;
739 spin_lock_irqsave(&rme32->lock, flags);
740 /* enable AutoSync for record-preparing */
741 rme32->wcreg |= RME32_WCR_AUTOSYNC;
742 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
743
744 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
745 spin_unlock_irqrestore(&rme32->lock, flags);
746 return err;
747 }
748 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
749 spin_unlock_irqrestore(&rme32->lock, flags);
750 return err;
751 }
752 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
753 if ((int)params_rate(params) != rate) {
754 spin_unlock_irqrestore(&rme32->lock, flags);
755 return -EIO;
756 }
757 if ((isadat && runtime->hw.channels_min == 2) ||
758 (!isadat && runtime->hw.channels_min == 8)) {
759 spin_unlock_irqrestore(&rme32->lock, flags);
760 return -EIO;
761 }
762 }
763 /* AutoSync off for recording */
764 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
765 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
766
767 snd_rme32_setframelog(rme32, params_channels(params), 0);
768 if (rme32->playback_periodsize != 0) {
769 if (params_period_size(params) << rme32->capture_frlog !=
770 rme32->playback_periodsize) {
771 spin_unlock_irqrestore(&rme32->lock, flags);
772 return -EBUSY;
773 }
774 }
775 rme32->capture_periodsize =
776 params_period_size(params) << rme32->capture_frlog;
777 spin_unlock_irqrestore(&rme32->lock, flags);
778
779 return 0;
780 }
781
782 static int snd_rme32_capture_hw_free(snd_pcm_substream_t * substream)
783 {
784 snd_pcm_lib_free_pages(substream);
785 return 0;
786 }
787
788 static void snd_rme32_playback_start(rme32_t * rme32, int from_pause)
789 {
790 if (!from_pause) {
791 writel(0, rme32->iobase + RME32_IO_RESET_POS);
792 rme32->playback_last_appl_ptr = 0;
793 rme32->playback_ptr = 0;
794 }
795
796 rme32->wcreg |= RME32_WCR_START;
797 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
798 }
799
800 static void snd_rme32_capture_start(rme32_t * rme32, int from_pause)
801 {
802 if (!from_pause) {
803 writel(0, rme32->iobase + RME32_IO_RESET_POS);
804 }
805
806 rme32->wcreg |= RME32_WCR_START;
807 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
808 }
809
810 static void snd_rme32_playback_stop(rme32_t * rme32)
811 {
812 /*
813 * Check if there is an unconfirmed IRQ, if so confirm it, or else
814 * the hardware will not stop generating interrupts
815 */
816 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
817 if (rme32->rcreg & RME32_RCR_IRQ) {
818 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
819 }
820 rme32->wcreg &= ~RME32_WCR_START;
821 if (rme32->wcreg & RME32_WCR_SEL)
822 rme32->wcreg |= RME32_WCR_MUTE;
823 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
824 }
825
826 static void snd_rme32_capture_stop(rme32_t * rme32)
827 {
828 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
829 if (rme32->rcreg & RME32_RCR_IRQ) {
830 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
831 }
832 rme32->wcreg &= ~RME32_WCR_START;
833 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
834 }
835
836 static irqreturn_t
837 snd_rme32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
838 {
839 rme32_t *rme32 = (rme32_t *) dev_id;
840
841 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
842 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
843 return IRQ_NONE;
844 } else {
845 if (rme32->capture_substream) {
846 snd_pcm_period_elapsed(rme32->capture_substream);
847 }
848 if (rme32->playback_substream) {
849 snd_pcm_period_elapsed(rme32->playback_substream);
850 }
851 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
852 }
853 return IRQ_HANDLED;
854 }
855
856 static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
857
858
859 #define PERIOD_BYTES sizeof(period_bytes) / sizeof(period_bytes[0])
860
861 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
862 .count = PERIOD_BYTES,
863 .list = period_bytes,
864 .mask = 0
865 };
866
867 static int snd_rme32_playback_spdif_open(snd_pcm_substream_t * substream)
868 {
869 unsigned long flags;
870 int rate, dummy;
871 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
872 snd_pcm_runtime_t *runtime = substream->runtime;
873
874 snd_pcm_set_sync(substream);
875
876 spin_lock_irqsave(&rme32->lock, flags);
877 if (rme32->playback_substream != NULL) {
878 spin_unlock_irqrestore(&rme32->lock, flags);
879 return -EBUSY;
880 }
881 rme32->wcreg &= ~RME32_WCR_ADAT;
882 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
883 rme32->playback_substream = substream;
884 rme32->playback_last_appl_ptr = 0;
885 rme32->playback_ptr = 0;
886 spin_unlock_irqrestore(&rme32->lock, flags);
887
888 runtime->hw = snd_rme32_playback_spdif_info;
889 if (rme32->pci->device == PCI_DEVICE_ID_DIGI32_PRO) {
890 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
891 runtime->hw.rate_max = 96000;
892 }
893 if ((rme32->rcreg & RME32_RCR_KMODE) &&
894 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
895 /* AutoSync */
896 runtime->hw.rates = snd_rme32_ratecode(rate);
897 runtime->hw.rate_min = rate;
898 runtime->hw.rate_max = rate;
899 }
900 snd_pcm_hw_constraint_minmax(runtime,
901 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
902 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
903 snd_pcm_hw_constraint_list(runtime, 0,
904 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
905 &hw_constraints_period_bytes);
906
907 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
908 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
909 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
910 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
911 return 0;
912 }
913
914 static int snd_rme32_capture_spdif_open(snd_pcm_substream_t * substream)
915 {
916 unsigned long flags;
917 int isadat, rate;
918 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
919 snd_pcm_runtime_t *runtime = substream->runtime;
920
921 snd_pcm_set_sync(substream);
922
923 spin_lock_irqsave(&rme32->lock, flags);
924 if (rme32->capture_substream != NULL) {
925 spin_unlock_irqrestore(&rme32->lock, flags);
926 return -EBUSY;
927 }
928 rme32->capture_substream = substream;
929 rme32->capture_ptr = 0;
930 spin_unlock_irqrestore(&rme32->lock, flags);
931
932 runtime->hw = snd_rme32_capture_spdif_info;
933 if (RME32_PRO_WITH_8414(rme32)) {
934 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
935 runtime->hw.rate_max = 96000;
936 }
937 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
938 if (isadat) {
939 return -EIO;
940 }
941 runtime->hw.rates = snd_rme32_ratecode(rate);
942 runtime->hw.rate_min = rate;
943 runtime->hw.rate_max = rate;
944 }
945
946 snd_pcm_hw_constraint_minmax(runtime,
947 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
948 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
949 snd_pcm_hw_constraint_list(runtime, 0,
950 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
951 &hw_constraints_period_bytes);
952
953 return 0;
954 }
955
956 static int
957 snd_rme32_playback_adat_open(snd_pcm_substream_t *substream)
958 {
959 unsigned long flags;
960 int rate, dummy;
961 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
962 snd_pcm_runtime_t *runtime = substream->runtime;
963
964 snd_pcm_set_sync(substream);
965
966 spin_lock_irqsave(&rme32->lock, flags);
967 if (rme32->playback_substream != NULL) {
968 spin_unlock_irqrestore(&rme32->lock, flags);
969 return -EBUSY;
970 }
971 rme32->wcreg |= RME32_WCR_ADAT;
972 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
973 rme32->playback_substream = substream;
974 rme32->playback_last_appl_ptr = 0;
975 rme32->playback_ptr = 0;
976 spin_unlock_irqrestore(&rme32->lock, flags);
977
978 runtime->hw = snd_rme32_playback_adat_info;
979 if ((rme32->rcreg & RME32_RCR_KMODE) &&
980 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
981 /* AutoSync */
982 runtime->hw.rates = snd_rme32_ratecode(rate);
983 runtime->hw.rate_min = rate;
984 runtime->hw.rate_max = rate;
985 }
986 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
987 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
988 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
989 &hw_constraints_period_bytes);
990 return 0;
991 }
992
993 static int
994 snd_rme32_capture_adat_open(snd_pcm_substream_t *substream)
995 {
996 unsigned long flags;
997 int isadat, rate;
998 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
999 snd_pcm_runtime_t *runtime = substream->runtime;
1000
1001 runtime->hw = snd_rme32_capture_adat_info;
1002 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
1003 if (!isadat) {
1004 return -EIO;
1005 }
1006 runtime->hw.rates = snd_rme32_ratecode(rate);
1007 runtime->hw.rate_min = rate;
1008 runtime->hw.rate_max = rate;
1009 }
1010
1011 snd_pcm_set_sync(substream);
1012
1013 spin_lock_irqsave(&rme32->lock, flags);
1014 if (rme32->capture_substream != NULL) {
1015 spin_unlock_irqrestore(&rme32->lock, flags);
1016 return -EBUSY;
1017 }
1018 rme32->capture_substream = substream;
1019 rme32->capture_ptr = 0;
1020 spin_unlock_irqrestore(&rme32->lock, flags);
1021
1022 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1023 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
1024 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1025 &hw_constraints_period_bytes);
1026 return 0;
1027 }
1028
1029 static int snd_rme32_playback_close(snd_pcm_substream_t * substream)
1030 {
1031 unsigned long flags;
1032 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1033 int spdif = 0;
1034
1035 spin_lock_irqsave(&rme32->lock, flags);
1036 rme32->playback_substream = NULL;
1037 rme32->playback_periodsize = 0;
1038 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1039 spin_unlock_irqrestore(&rme32->lock, flags);
1040 if (spdif) {
1041 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1042 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1043 SNDRV_CTL_EVENT_MASK_INFO,
1044 &rme32->spdif_ctl->id);
1045 }
1046 return 0;
1047 }
1048
1049 static int snd_rme32_capture_close(snd_pcm_substream_t * substream)
1050 {
1051 unsigned long flags;
1052 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1053
1054 spin_lock_irqsave(&rme32->lock, flags);
1055 rme32->capture_substream = NULL;
1056 rme32->capture_periodsize = 0;
1057 spin_unlock_irqrestore(&rme32->lock, flags);
1058 return 0;
1059 }
1060
1061 static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream)
1062 {
1063 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1064 unsigned long flags;
1065
1066 spin_lock_irqsave(&rme32->lock, flags);
1067 if (RME32_ISWORKING(rme32)) {
1068 snd_rme32_playback_stop(rme32);
1069 }
1070 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1071 if (rme32->wcreg & RME32_WCR_SEL)
1072 rme32->wcreg &= ~RME32_WCR_MUTE;
1073 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1074 spin_unlock_irqrestore(&rme32->lock, flags);
1075 return 0;
1076 }
1077
1078 static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream)
1079 {
1080 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1081 unsigned long flags;
1082
1083 spin_lock_irqsave(&rme32->lock, flags);
1084 if (RME32_ISWORKING(rme32)) {
1085 snd_rme32_capture_stop(rme32);
1086 }
1087 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1088 spin_unlock_irqrestore(&rme32->lock, flags);
1089 return 0;
1090 }
1091
1092 static int
1093 snd_rme32_playback_trigger(snd_pcm_substream_t * substream, int cmd)
1094 {
1095 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1096 switch (cmd) {
1097 case SNDRV_PCM_TRIGGER_START:
1098 if (!RME32_ISWORKING(rme32)) {
1099 if (substream != rme32->playback_substream) {
1100 return -EBUSY;
1101 }
1102 snd_rme32_playback_start(rme32, 0);
1103 }
1104 break;
1105
1106 case SNDRV_PCM_TRIGGER_STOP:
1107 if (RME32_ISWORKING(rme32)) {
1108 if (substream != rme32->playback_substream) {
1109 return -EBUSY;
1110 }
1111 snd_rme32_playback_stop(rme32);
1112 }
1113 break;
1114
1115 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1116 if (RME32_ISWORKING(rme32)) {
1117 snd_rme32_playback_stop(rme32);
1118 }
1119 break;
1120
1121 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1122 if (!RME32_ISWORKING(rme32)) {
1123 snd_rme32_playback_start(rme32, 1);
1124 }
1125 break;
1126
1127 default:
1128 return -EINVAL;
1129 }
1130 return 0;
1131 }
1132
1133 static int
1134 snd_rme32_capture_trigger(snd_pcm_substream_t * substream, int cmd)
1135 {
1136 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1137
1138 switch (cmd) {
1139 case SNDRV_PCM_TRIGGER_START:
1140 if (!RME32_ISWORKING(rme32)) {
1141 if (substream != rme32->capture_substream) {
1142 return -EBUSY;
1143 }
1144 snd_rme32_capture_start(rme32, 0);
1145 }
1146 break;
1147
1148 case SNDRV_PCM_TRIGGER_STOP:
1149 if (RME32_ISWORKING(rme32)) {
1150 if (substream != rme32->capture_substream) {
1151 return -EBUSY;
1152 }
1153 snd_rme32_capture_stop(rme32);
1154 }
1155 break;
1156
1157 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1158 if (RME32_ISWORKING(rme32)) {
1159 snd_rme32_capture_stop(rme32);
1160 }
1161 break;
1162
1163 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1164 if (!RME32_ISWORKING(rme32)) {
1165 snd_rme32_capture_start(rme32, 1);
1166 }
1167 break;
1168
1169 default:
1170 return -EINVAL;
1171 }
1172
1173 return 0;
1174 }
1175
1176 static snd_pcm_uframes_t
1177 snd_rme32_playback_pointer(snd_pcm_substream_t * substream)
1178 {
1179 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1180 snd_pcm_runtime_t *runtime = substream->runtime;
1181 snd_pcm_sframes_t diff;
1182 size_t bytes;
1183
1184
1185 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1186 diff = runtime->control->appl_ptr -
1187 rme32->playback_last_appl_ptr;
1188 rme32->playback_last_appl_ptr = runtime->control->appl_ptr;
1189 if (diff != 0 && diff < -(snd_pcm_sframes_t) (runtime->boundary >> 1)) {
1190 diff += runtime->boundary;
1191 }
1192 bytes = diff << rme32->playback_frlog;
1193 if (bytes > RME32_BUFFER_SIZE - rme32->playback_ptr) {
1194 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rme32->playback_ptr,
1195 runtime->dma_area + rme32->playback_ptr,
1196 RME32_BUFFER_SIZE - rme32->playback_ptr);
1197 bytes -= RME32_BUFFER_SIZE - rme32->playback_ptr;
1198 if (bytes > RME32_BUFFER_SIZE) {
1199 bytes = RME32_BUFFER_SIZE;
1200 }
1201 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER,
1202 runtime->dma_area, bytes);
1203 rme32->playback_ptr = bytes;
1204 } else if (bytes != 0) {
1205 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rme32->playback_ptr,
1206 runtime->dma_area + rme32->playback_ptr, bytes);
1207 rme32->playback_ptr += bytes;
1208 }
1209 }
1210 return snd_rme32_playback_ptr(rme32);
1211 }
1212
1213 static snd_pcm_uframes_t
1214 snd_rme32_capture_pointer(snd_pcm_substream_t * substream)
1215 {
1216 rme32_t *rme32 = _snd_pcm_substream_chip(substream);
1217 snd_pcm_runtime_t *runtime = substream->runtime;
1218 snd_pcm_uframes_t frameptr;
1219 size_t ptr;
1220
1221 frameptr = snd_rme32_capture_ptr(rme32);
1222 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1223 ptr = frameptr << rme32->capture_frlog;
1224 if (ptr > rme32->capture_ptr) {
1225 memcpy_fromio(runtime->dma_area + rme32->capture_ptr,
1226 rme32->iobase + RME32_IO_DATA_BUFFER +
1227 rme32->capture_ptr,
1228 ptr - rme32->capture_ptr);
1229 rme32->capture_ptr += ptr - rme32->capture_ptr;
1230 } else if (ptr < rme32->capture_ptr) {
1231 memcpy_fromio(runtime->dma_area + rme32->capture_ptr,
1232 rme32->iobase + RME32_IO_DATA_BUFFER +
1233 rme32->capture_ptr,
1234 RME32_BUFFER_SIZE - rme32->capture_ptr);
1235 memcpy_fromio(runtime->dma_area,
1236 rme32->iobase + RME32_IO_DATA_BUFFER,
1237 ptr);
1238 rme32->capture_ptr = ptr;
1239 }
1240 }
1241 return frameptr;
1242 }
1243
1244 static snd_pcm_ops_t snd_rme32_playback_spdif_ops = {
1245 .open = snd_rme32_playback_spdif_open,
1246 .close = snd_rme32_playback_close,
1247 .ioctl = snd_pcm_lib_ioctl,
1248 .hw_params = snd_rme32_playback_hw_params,
1249 .hw_free = snd_rme32_playback_hw_free,
1250 .prepare = snd_rme32_playback_prepare,
1251 .trigger = snd_rme32_playback_trigger,
1252 .pointer = snd_rme32_playback_pointer,
1253 .copy = snd_rme32_playback_copy,
1254 .silence = snd_rme32_playback_silence,
1255 };
1256
1257 static snd_pcm_ops_t snd_rme32_capture_spdif_ops = {
1258 .open = snd_rme32_capture_spdif_open,
1259 .close = snd_rme32_capture_close,
1260 .ioctl = snd_pcm_lib_ioctl,
1261 .hw_params = snd_rme32_capture_hw_params,
1262 .hw_free = snd_rme32_capture_hw_free,
1263 .prepare = snd_rme32_capture_prepare,
1264 .trigger = snd_rme32_capture_trigger,
1265 .pointer = snd_rme32_capture_pointer,
1266 .copy = snd_rme32_capture_copy,
1267 };
1268
1269 static snd_pcm_ops_t snd_rme32_playback_adat_ops = {
1270 .open = snd_rme32_playback_adat_open,
1271 .close = snd_rme32_playback_close,
1272 .ioctl = snd_pcm_lib_ioctl,
1273 .hw_params = snd_rme32_playback_hw_params,
1274 .hw_free = snd_rme32_playback_hw_free,
1275 .prepare = snd_rme32_playback_prepare,
1276 .trigger = snd_rme32_playback_trigger,
1277 .pointer = snd_rme32_playback_pointer,
1278 .copy = snd_rme32_playback_copy,
1279 .silence = snd_rme32_playback_silence,
1280 };
1281
1282 static snd_pcm_ops_t snd_rme32_capture_adat_ops = {
1283 .open = snd_rme32_capture_adat_open,
1284 .close = snd_rme32_capture_close,
1285 .ioctl = snd_pcm_lib_ioctl,
1286 .hw_params = snd_rme32_capture_hw_params,
1287 .hw_free = snd_rme32_capture_hw_free,
1288 .prepare = snd_rme32_capture_prepare,
1289 .trigger = snd_rme32_capture_trigger,
1290 .pointer = snd_rme32_capture_pointer,
1291 .copy = snd_rme32_capture_copy,
1292 };
1293
1294 static void snd_rme32_free(void *private_data)
1295 {
1296 rme32_t *rme32 = (rme32_t *) private_data;
1297
1298 if (rme32 == NULL) {
1299 return;
1300 }
1301 if (rme32->irq >= 0) {
1302 snd_rme32_playback_stop(rme32);
1303 snd_rme32_capture_stop(rme32);
1304 free_irq(rme32->irq, (void *) rme32);
1305 rme32->irq = -1;
1306 }
1307 if (rme32->iobase) {
1308 iounmap((void *) rme32->iobase);
1309 rme32->iobase = 0;
1310 }
1311 if (rme32->res_port != NULL) {
1312 release_resource(rme32->res_port);
1313 rme32->res_port = NULL;
1314 }
1315 }
1316
1317 static void snd_rme32_free_spdif_pcm(snd_pcm_t * pcm)
1318 {
1319 rme32_t *rme32 = (rme32_t *) pcm->private_data;
1320 rme32->spdif_pcm = NULL;
1321 snd_pcm_lib_preallocate_free_for_all(pcm);
1322 }
1323
1324 static void
1325 snd_rme32_free_adat_pcm(snd_pcm_t *pcm)
1326 {
1327 rme32_t *rme32 = (rme32_t *) pcm->private_data;
1328 rme32->adat_pcm = NULL;
1329 snd_pcm_lib_preallocate_free_for_all(pcm);
1330 }
1331
1332 static int __devinit snd_rme32_create(rme32_t * rme32)
1333 {
1334 struct pci_dev *pci = rme32->pci;
1335 int err;
1336
1337 rme32->irq = -1;
1338
1339 if ((err = pci_enable_device(pci)) < 0)
1340 return err;
1341
1342 rme32->port = pci_resource_start(rme32->pci, 0);
1343
1344 if ((rme32->res_port = request_mem_region(rme32->port, RME32_IO_SIZE, "RME32")) == NULL) {
1345 snd_printk("unable to grab memory region 0x%lx-0x%lx\n",
1346 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1347 return -EBUSY;
1348 }
1349
1350 if (request_irq(pci->irq, snd_rme32_interrupt, SA_INTERRUPT | SA_SHIRQ, "RME32", (void *) rme32)) {
1351 snd_printk("unable to grab IRQ %d\n", pci->irq);
1352 return -EBUSY;
1353 }
1354 rme32->irq = pci->irq;
1355
1356 spin_lock_init(&rme32->lock);
1357 if ((rme32->iobase = (unsigned long) ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
1358 snd_printk("unable to remap memory region 0x%lx-0x%lx\n",
1359 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1360 return -ENOMEM;
1361 }
1362
1363 /* read the card's revision number */
1364 pci_read_config_byte(pci, 8, &rme32->rev);
1365
1366 /* set up ALSA pcm device for S/PDIF */
1367 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1368 return err;
1369 }
1370 rme32->spdif_pcm->private_data = rme32;
1371 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1372 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1373 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1374 &snd_rme32_playback_spdif_ops);
1375 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1376 &snd_rme32_capture_spdif_ops);
1377
1378 rme32->spdif_pcm->info_flags = 0;
1379
1380 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm,
1381 RME32_BUFFER_SIZE,
1382 RME32_BUFFER_SIZE,
1383 GFP_KERNEL);
1384
1385 /* set up ALSA pcm device for ADAT */
1386 if ((pci->device == PCI_DEVICE_ID_DIGI32) ||
1387 (pci->device == PCI_DEVICE_ID_DIGI32_PRO)) {
1388 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1389 rme32->adat_pcm = NULL;
1390 }
1391 else {
1392 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1393 1, 1, &rme32->adat_pcm)) < 0)
1394 {
1395 return err;
1396 }
1397 rme32->adat_pcm->private_data = rme32;
1398 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1399 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1400 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1401 &snd_rme32_playback_adat_ops);
1402 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1403 &snd_rme32_capture_adat_ops);
1404
1405 rme32->adat_pcm->info_flags = 0;
1406
1407 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm,
1408 RME32_BUFFER_SIZE,
1409 RME32_BUFFER_SIZE,
1410 GFP_KERNEL);
1411 }
1412
1413
1414 rme32->playback_periodsize = 0;
1415 rme32->capture_periodsize = 0;
1416
1417 /* make sure playback/capture is stopped, if by some reason active */
1418 snd_rme32_playback_stop(rme32);
1419 snd_rme32_capture_stop(rme32);
1420
1421 /* reset DAC */
1422 snd_rme32_reset_dac(rme32);
1423
1424 /* reset buffer pointer */
1425 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1426
1427 /* set default values in registers */
1428 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1429 RME32_WCR_INP_0 | /* input select */
1430 RME32_WCR_MUTE; /* muting on */
1431 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1432
1433
1434 /* init switch interface */
1435 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1436 return err;
1437 }
1438
1439 /* init proc interface */
1440 snd_rme32_proc_init(rme32);
1441
1442 rme32->capture_substream = NULL;
1443 rme32->playback_substream = NULL;
1444
1445 return 0;
1446 }
1447
1448 /*
1449 * proc interface
1450 */
1451
1452 static void
1453 snd_rme32_proc_read(snd_info_entry_t * entry, snd_info_buffer_t * buffer)
1454 {
1455 int n;
1456 rme32_t *rme32 = (rme32_t *) entry->private_data;
1457
1458 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1459
1460 snd_iprintf(buffer, rme32->card->longname);
1461 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1462
1463 snd_iprintf(buffer, "\nGeneral settings\n");
1464 if (RME32_PRO_WITH_8414(rme32)) {
1465 snd_iprintf(buffer, " receiver: CS8414\n");
1466 } else {
1467 snd_iprintf(buffer, " receiver: CS8412\n");
1468 }
1469 if (rme32->wcreg & RME32_WCR_MODE24) {
1470 snd_iprintf(buffer, " format: 24 bit");
1471 } else {
1472 snd_iprintf(buffer, " format: 16 bit");
1473 }
1474 if (rme32->wcreg & RME32_WCR_MONO) {
1475 snd_iprintf(buffer, ", Mono\n");
1476 } else {
1477 snd_iprintf(buffer, ", Stereo\n");
1478 }
1479
1480 snd_iprintf(buffer, "\nInput settings\n");
1481 switch (snd_rme32_getinputtype(rme32)) {
1482 case RME32_INPUT_OPTICAL:
1483 snd_iprintf(buffer, " input: optical");
1484 break;
1485 case RME32_INPUT_COAXIAL:
1486 snd_iprintf(buffer, " input: coaxial");
1487 break;
1488 case RME32_INPUT_INTERNAL:
1489 snd_iprintf(buffer, " input: internal");
1490 break;
1491 case RME32_INPUT_XLR:
1492 snd_iprintf(buffer, " input: XLR");
1493 break;
1494 }
1495 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1496 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1497 } else {
1498 if (n) {
1499 snd_iprintf(buffer, " (8 channels)\n");
1500 } else {
1501 snd_iprintf(buffer, " (2 channels)\n");
1502 }
1503 snd_iprintf(buffer, " sample rate: %d Hz\n",
1504 snd_rme32_capture_getrate(rme32, &n));
1505 }
1506
1507 snd_iprintf(buffer, "\nOutput settings\n");
1508 if (rme32->wcreg & RME32_WCR_SEL) {
1509 snd_iprintf(buffer, " output signal: normal playback");
1510 } else {
1511 snd_iprintf(buffer, " output signal: same as input");
1512 }
1513 if (rme32->wcreg & RME32_WCR_MUTE) {
1514 snd_iprintf(buffer, " (muted)\n");
1515 } else {
1516 snd_iprintf(buffer, "\n");
1517 }
1518
1519 /* master output frequency */
1520 if (!
1521 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1522 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1523 snd_iprintf(buffer, " sample rate: %d Hz\n",
1524 snd_rme32_playback_getrate(rme32));
1525 }
1526 if (rme32->rcreg & RME32_RCR_KMODE) {
1527 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1528 } else {
1529 snd_iprintf(buffer, " sample clock source: Internal\n");
1530 }
1531 if (rme32->wcreg & RME32_WCR_PRO) {
1532 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1533 } else {
1534 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1535 }
1536 if (rme32->wcreg & RME32_WCR_EMP) {
1537 snd_iprintf(buffer, " emphasis: on\n");
1538 } else {
1539 snd_iprintf(buffer, " emphasis: off\n");
1540 }
1541 }
1542
1543 static void __devinit snd_rme32_proc_init(rme32_t * rme32)
1544 {
1545 snd_info_entry_t *entry;
1546
1547 if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1548 snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1549 }
1550
1551 /*
1552 * control interface
1553 */
1554
1555 static int
1556 snd_rme32_info_loopback_control(snd_kcontrol_t * kcontrol,
1557 snd_ctl_elem_info_t * uinfo)
1558 {
1559 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1560 uinfo->count = 1;
1561 uinfo->value.integer.min = 0;
1562 uinfo->value.integer.max = 1;
1563 return 0;
1564 }
1565 static int
1566 snd_rme32_get_loopback_control(snd_kcontrol_t * kcontrol,
1567 snd_ctl_elem_value_t * ucontrol)
1568 {
1569 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1570 unsigned long flags;
1571
1572 spin_lock_irqsave(&rme32->lock, flags);
1573 ucontrol->value.integer.value[0] =
1574 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1575 spin_unlock_irqrestore(&rme32->lock, flags);
1576 return 0;
1577 }
1578 static int
1579 snd_rme32_put_loopback_control(snd_kcontrol_t * kcontrol,
1580 snd_ctl_elem_value_t * ucontrol)
1581 {
1582 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1583 unsigned long flags;
1584 unsigned int val;
1585 int change;
1586
1587 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1588 spin_lock_irqsave(&rme32->lock, flags);
1589 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1590 change = val != rme32->wcreg;
1591 if (ucontrol->value.integer.value[0])
1592 val &= ~RME32_WCR_MUTE;
1593 else
1594 val |= RME32_WCR_MUTE;
1595 writel(rme32->wcreg =
1596 val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1597 spin_unlock_irqrestore(&rme32->lock, flags);
1598 return change;
1599 }
1600
1601 static int
1602 snd_rme32_info_inputtype_control(snd_kcontrol_t * kcontrol,
1603 snd_ctl_elem_info_t * uinfo)
1604 {
1605 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1606 static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1607
1608 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1609 uinfo->count = 1;
1610 switch (rme32->pci->device) {
1611 case PCI_DEVICE_ID_DIGI32:
1612 case PCI_DEVICE_ID_DIGI32_8:
1613 uinfo->value.enumerated.items = 3;
1614 break;
1615 case PCI_DEVICE_ID_DIGI32_PRO:
1616 uinfo->value.enumerated.items = 4;
1617 break;
1618 default:
1619 snd_BUG();
1620 break;
1621 }
1622 if (uinfo->value.enumerated.item >
1623 uinfo->value.enumerated.items - 1) {
1624 uinfo->value.enumerated.item =
1625 uinfo->value.enumerated.items - 1;
1626 }
1627 strcpy(uinfo->value.enumerated.name,
1628 texts[uinfo->value.enumerated.item]);
1629 return 0;
1630 }
1631 static int
1632 snd_rme32_get_inputtype_control(snd_kcontrol_t * kcontrol,
1633 snd_ctl_elem_value_t * ucontrol)
1634 {
1635 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1636 unsigned long flags;
1637 unsigned int items = 3;
1638
1639 spin_lock_irqsave(&rme32->lock, flags);
1640 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1641
1642 switch (rme32->pci->device) {
1643 case PCI_DEVICE_ID_DIGI32:
1644 case PCI_DEVICE_ID_DIGI32_8:
1645 items = 3;
1646 break;
1647 case PCI_DEVICE_ID_DIGI32_PRO:
1648 items = 4;
1649 break;
1650 default:
1651 snd_BUG();
1652 break;
1653 }
1654 if (ucontrol->value.enumerated.item[0] >= items) {
1655 ucontrol->value.enumerated.item[0] = items - 1;
1656 }
1657
1658 spin_unlock_irqrestore(&rme32->lock, flags);
1659 return 0;
1660 }
1661 static int
1662 snd_rme32_put_inputtype_control(snd_kcontrol_t * kcontrol,
1663 snd_ctl_elem_value_t * ucontrol)
1664 {
1665 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1666 unsigned long flags;
1667 unsigned int val;
1668 int change, items = 3;
1669
1670 switch (rme32->pci->device) {
1671 case PCI_DEVICE_ID_DIGI32:
1672 case PCI_DEVICE_ID_DIGI32_8:
1673 items = 3;
1674 break;
1675 case PCI_DEVICE_ID_DIGI32_PRO:
1676 items = 4;
1677 break;
1678 default:
1679 snd_BUG();
1680 break;
1681 }
1682 val = ucontrol->value.enumerated.item[0] % items;
1683
1684 spin_lock_irqsave(&rme32->lock, flags);
1685 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1686 snd_rme32_setinputtype(rme32, val);
1687 spin_unlock_irqrestore(&rme32->lock, flags);
1688 return change;
1689 }
1690
1691 static int
1692 snd_rme32_info_clockmode_control(snd_kcontrol_t * kcontrol,
1693 snd_ctl_elem_info_t * uinfo)
1694 {
1695 static char *texts[4] = { "AutoSync",
1696 "Internal 32.0kHz",
1697 "Internal 44.1kHz",
1698 "Internal 48.0kHz" };
1699
1700 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1701 uinfo->count = 1;
1702 uinfo->value.enumerated.items = 4;
1703 if (uinfo->value.enumerated.item > 3) {
1704 uinfo->value.enumerated.item = 3;
1705 }
1706 strcpy(uinfo->value.enumerated.name,
1707 texts[uinfo->value.enumerated.item]);
1708 return 0;
1709 }
1710 static int
1711 snd_rme32_get_clockmode_control(snd_kcontrol_t * kcontrol,
1712 snd_ctl_elem_value_t * ucontrol)
1713 {
1714 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1715 unsigned long flags;
1716
1717 spin_lock_irqsave(&rme32->lock, flags);
1718 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1719 spin_unlock_irqrestore(&rme32->lock, flags);
1720 return 0;
1721 }
1722 static int
1723 snd_rme32_put_clockmode_control(snd_kcontrol_t * kcontrol,
1724 snd_ctl_elem_value_t * ucontrol)
1725 {
1726 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1727 unsigned long flags;
1728 unsigned int val;
1729 int change;
1730
1731 val = ucontrol->value.enumerated.item[0] % 3;
1732 spin_lock_irqsave(&rme32->lock, flags);
1733 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1734 snd_rme32_setclockmode(rme32, val);
1735 spin_unlock_irqrestore(&rme32->lock, flags);
1736 return change;
1737 }
1738
1739 static u32 snd_rme32_convert_from_aes(snd_aes_iec958_t * aes)
1740 {
1741 u32 val = 0;
1742 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1743 if (val & RME32_WCR_PRO)
1744 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1745 else
1746 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1747 return val;
1748 }
1749
1750 static void snd_rme32_convert_to_aes(snd_aes_iec958_t * aes, u32 val)
1751 {
1752 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1753 if (val & RME32_WCR_PRO)
1754 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1755 else
1756 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1757 }
1758
1759 static int snd_rme32_control_spdif_info(snd_kcontrol_t * kcontrol,
1760 snd_ctl_elem_info_t * uinfo)
1761 {
1762 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1763 uinfo->count = 1;
1764 return 0;
1765 }
1766
1767 static int snd_rme32_control_spdif_get(snd_kcontrol_t * kcontrol,
1768 snd_ctl_elem_value_t * ucontrol)
1769 {
1770 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1771
1772 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1773 rme32->wcreg_spdif);
1774 return 0;
1775 }
1776
1777 static int snd_rme32_control_spdif_put(snd_kcontrol_t * kcontrol,
1778 snd_ctl_elem_value_t * ucontrol)
1779 {
1780 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1781 unsigned long flags;
1782 int change;
1783 u32 val;
1784
1785 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1786 spin_lock_irqsave(&rme32->lock, flags);
1787 change = val != rme32->wcreg_spdif;
1788 rme32->wcreg_spdif = val;
1789 spin_unlock_irqrestore(&rme32->lock, flags);
1790 return change;
1791 }
1792
1793 static int snd_rme32_control_spdif_stream_info(snd_kcontrol_t * kcontrol,
1794 snd_ctl_elem_info_t * uinfo)
1795 {
1796 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1797 uinfo->count = 1;
1798 return 0;
1799 }
1800
1801 static int snd_rme32_control_spdif_stream_get(snd_kcontrol_t * kcontrol,
1802 snd_ctl_elem_value_t *
1803 ucontrol)
1804 {
1805 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1806
1807 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1808 rme32->wcreg_spdif_stream);
1809 return 0;
1810 }
1811
1812 static int snd_rme32_control_spdif_stream_put(snd_kcontrol_t * kcontrol,
1813 snd_ctl_elem_value_t *
1814 ucontrol)
1815 {
1816 rme32_t *rme32 = _snd_kcontrol_chip(kcontrol);
1817 unsigned long flags;
1818 int change;
1819 u32 val;
1820
1821 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1822 spin_lock_irqsave(&rme32->lock, flags);
1823 change = val != rme32->wcreg_spdif_stream;
1824 rme32->wcreg_spdif_stream = val;
1825 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1826 writel(rme32->wcreg |= val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1827 spin_unlock_irqrestore(&rme32->lock, flags);
1828 return change;
1829 }
1830
1831 static int snd_rme32_control_spdif_mask_info(snd_kcontrol_t * kcontrol,
1832 snd_ctl_elem_info_t * uinfo)
1833 {
1834 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1835 uinfo->count = 1;
1836 return 0;
1837 }
1838
1839 static int snd_rme32_control_spdif_mask_get(snd_kcontrol_t * kcontrol,
1840 snd_ctl_elem_value_t *
1841 ucontrol)
1842 {
1843 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1844 return 0;
1845 }
1846
1847 static snd_kcontrol_new_t snd_rme32_controls[] = {
1848 {
1849 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1850 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1851 .info = snd_rme32_control_spdif_info,
1852 .get = snd_rme32_control_spdif_get,
1853 .put = snd_rme32_control_spdif_put
1854 },
1855 {
1856 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1857 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1858 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1859 .info = snd_rme32_control_spdif_stream_info,
1860 .get = snd_rme32_control_spdif_stream_get,
1861 .put = snd_rme32_control_spdif_stream_put
1862 },
1863 {
1864 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1865 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1866 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1867 .info = snd_rme32_control_spdif_mask_info,
1868 .get = snd_rme32_control_spdif_mask_get,
1869 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1870 },
1871 {
1872 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1873 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1874 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1875 .info = snd_rme32_control_spdif_mask_info,
1876 .get = snd_rme32_control_spdif_mask_get,
1877 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1878 },
1879 {
1880 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1881 .name = "Input Connector",
1882 .info = snd_rme32_info_inputtype_control,
1883 .get = snd_rme32_get_inputtype_control,
1884 .put = snd_rme32_put_inputtype_control
1885 },
1886 {
1887 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1888 .name = "Loopback Input",
1889 .info = snd_rme32_info_loopback_control,
1890 .get = snd_rme32_get_loopback_control,
1891 .put = snd_rme32_put_loopback_control
1892 },
1893 {
1894 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1895 .name = "Sample Clock Source",
1896 .info = snd_rme32_info_clockmode_control,
1897 .get = snd_rme32_get_clockmode_control,
1898 .put = snd_rme32_put_clockmode_control
1899 }
1900 };
1901
1902 static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32)
1903 {
1904 int idx, err;
1905 snd_kcontrol_t *kctl;
1906
1907 for (idx = 0; idx < 7; idx++) {
1908 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1909 return err;
1910 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1911 rme32->spdif_ctl = kctl;
1912 }
1913
1914 return 0;
1915 }
1916
1917 /*
1918 * Card initialisation
1919 */
1920
1921 static void snd_rme32_card_free(snd_card_t * card)
1922 {
1923 snd_rme32_free(card->private_data);
1924 }
1925
1926 static int __devinit
1927 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1928 {
1929 static int dev;
1930 rme32_t *rme32;
1931 snd_card_t *card;
1932 int err;
1933
1934 for (; dev < SNDRV_CARDS; dev++) {
1935 if (!enable[dev]) {
1936 dev++;
1937 return -ENOENT;
1938 }
1939 break;
1940 }
1941 if (dev >= SNDRV_CARDS) {
1942 return -ENODEV;
1943 }
1944 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
1945 sizeof(rme32_t))) == NULL)
1946 return -ENOMEM;
1947 card->private_free = snd_rme32_card_free;
1948 rme32 = (rme32_t *) card->private_data;
1949 rme32->card = card;
1950 rme32->pci = pci;
1951 if ((err = snd_rme32_create(rme32)) < 0) {
1952 snd_card_free(card);
1953 return err;
1954 }
1955
1956 strcpy(card->driver, "Digi32");
1957 switch (rme32->pci->device) {
1958 case PCI_DEVICE_ID_DIGI32:
1959 strcpy(card->shortname, "RME Digi32");
1960 break;
1961 case PCI_DEVICE_ID_DIGI32_8:
1962 strcpy(card->shortname, "RME Digi32/8");
1963 break;
1964 case PCI_DEVICE_ID_DIGI32_PRO:
1965 strcpy(card->shortname, "RME Digi32 PRO");
1966 break;
1967 }
1968 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1969 card->shortname, rme32->rev, rme32->port, rme32->irq);
1970
1971 if ((err = snd_card_register(card)) < 0) {
1972 snd_card_free(card);
1973 return err;
1974 }
1975 pci_set_drvdata(pci, card);
1976 dev++;
1977 return 0;
1978 }
1979
1980 static void __devexit snd_rme32_remove(struct pci_dev *pci)
1981 {
1982 snd_card_free(pci_get_drvdata(pci));
1983 pci_set_drvdata(pci, NULL);
1984 }
1985
1986 static struct pci_driver driver = {
1987 .name = "RME Digi32",
1988 .id_table = snd_rme32_ids,
1989 .probe = snd_rme32_probe,
1990 .remove = __devexit_p(snd_rme32_remove),
1991 };
1992
1993 static int __init alsa_card_rme32_init(void)
1994 {
1995 int err;
1996
1997 if ((err = pci_module_init(&driver)) < 0) {
1998 #ifdef MODULE
1999 snd_printk("No RME Digi32 cards found\n");
2000 #endif
2001 return err;
2002 }
2003 return 0;
2004 }
2005
2006 static void __exit alsa_card_rme32_exit(void)
2007 {
2008 pci_unregister_driver(&driver);
2009 }
2010
2011 module_init(alsa_card_rme32_init)
2012 module_exit(alsa_card_rme32_exit)
2013
2014 #ifndef MODULE
2015
2016 static int __init alsa_card_rme32_setup(char *str)
2017 {
2018 static unsigned __initdata nr_dev = 0;
2019
2020 if (nr_dev >= SNDRV_CARDS)
2021 return 0;
2022 (void) (get_option(&str, &enable[nr_dev]) == 2 &&
2023 get_option(&str, &index[nr_dev]) == 2 &&
2024 get_id(&str, &id[nr_dev]) == 2);
2025 nr_dev++;
2026 return 1;
2027 }
2028
2029 __setup("snd-rme32=", alsa_card_rme32_setup);
2030
2031 #endif /* ifndef MODULE */
Historical 2.5/2.6 development