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Merge bk://drm.bkbits.net/drm-fntbl
[linux-2.6/history.git] / drivers / net / r8169.c
blob0b3bb03d85019bd792f33f26c4a682c32194ec93
1 /*
2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 =========================================================================
10 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
11 Command: 'insmod r8169 media = SET_MEDIA'
12 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
13
14 SET_MEDIA can be:
15 _10_Half = 0x01
16 _10_Full = 0x02
17 _100_Half = 0x04
18 _100_Full = 0x08
19 _1000_Full = 0x10
20
21 2. Support TBI mode.
22 =========================================================================
23 VERSION 1.1 <2002/10/4>
24
25 The bit4:0 of MII register 4 is called "selector field", and have to be
26 00001b to indicate support of IEEE std 802.3 during NWay process of
27 exchanging Link Code Word (FLP).
28
29 VERSION 1.2 <2002/11/30>
30
31 - Large style cleanup
32 - Use ether_crc in stock kernel (linux/crc32.h)
33 - Copy mc_filter setup code from 8139cp
34 (includes an optimization, and avoids set_bit use)
35
36 */
37
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/crc32.h>
46 #include <linux/init.h>
47 #include <linux/dma-mapping.h>
48
49 #include <asm/io.h>
50
51 #define RTL8169_VERSION "1.2"
52 #define MODULENAME "r8169"
53 #define RTL8169_DRIVER_NAME MODULENAME " Gigabit Ethernet driver " RTL8169_VERSION
54 #define PFX MODULENAME ": "
55
56 #ifdef RTL8169_DEBUG
57 #define assert(expr) \
58 if(!(expr)) { \
59 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
60 #expr,__FILE__,__FUNCTION__,__LINE__); \
61 }
62 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args) } while (0)
63 #else
64 #define assert(expr) do {} while (0)
65 #define dprintk(fmt, args...) do {} while (0)
66 #endif /* RTL8169_DEBUG */
67
68 #ifdef CONFIG_R8169_NAPI
69 #define rtl8169_rx_skb netif_receive_skb
70 #define rtl8169_rx_quota(count, quota) min(count, quota)
71 #else
72 #define rtl8169_rx_skb netif_rx
73 #define rtl8169_rx_quota(count, quota) count
74 #endif
75
76 /* media options */
77 #define MAX_UNITS 8
78 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
79
80 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
81 static int max_interrupt_work = 20;
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static int multicast_filter_limit = 32;
86
87 /* MAC address length*/
88 #define MAC_ADDR_LEN 6
89
90 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
91 #define MAX_ETH_FRAME_SIZE 1536
92
93 #define TX_FIFO_THRESH 256 /* In bytes */
94
95 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
96 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
97 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
98 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
99 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
100 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
101
102 #define R8169_NAPI_WEIGHT 64
103 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
104 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
105 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
106 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
107 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
108
109 #define RTL_MIN_IO_SIZE 0x80
110 #define RTL8169_TX_TIMEOUT (6*HZ)
111 #define RTL8169_PHY_TIMEOUT (10*HZ)
112
113 /* write/read MMIO register */
114 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
115 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
116 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
117 #define RTL_R8(reg) readb (ioaddr + (reg))
118 #define RTL_R16(reg) readw (ioaddr + (reg))
119 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
120
121 enum mac_version {
122 RTL_GIGA_MAC_VER_B = 0x00,
123 /* RTL_GIGA_MAC_VER_C = 0x03, */
124 RTL_GIGA_MAC_VER_D = 0x01,
125 RTL_GIGA_MAC_VER_E = 0x02
126 };
127
128 enum phy_version {
129 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
130 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
131 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
132 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
133 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
134 };
135
136
137 #define _R(NAME,MAC,MASK) \
138 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
139
140 const static struct {
141 const char *name;
142 u8 mac_version;
143 u32 RxConfigMask; /* Clears the bits supported by this chip */
144 } rtl_chip_info[] = {
145 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
146 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
147 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880)
148 };
149 #undef _R
150
151 static struct pci_device_id rtl8169_pci_tbl[] = {
152 {0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {0,},
154 };
155
156 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
157
158 static int rx_copybreak = 200;
159
160 enum RTL8169_registers {
161 MAC0 = 0, /* Ethernet hardware address. */
162 MAR0 = 8, /* Multicast filter. */
163 TxDescStartAddrLow = 0x20,
164 TxDescStartAddrHigh = 0x24,
165 TxHDescStartAddrLow = 0x28,
166 TxHDescStartAddrHigh = 0x2c,
167 FLASH = 0x30,
168 ERSR = 0x36,
169 ChipCmd = 0x37,
170 TxPoll = 0x38,
171 IntrMask = 0x3C,
172 IntrStatus = 0x3E,
173 TxConfig = 0x40,
174 RxConfig = 0x44,
175 RxMissed = 0x4C,
176 Cfg9346 = 0x50,
177 Config0 = 0x51,
178 Config1 = 0x52,
179 Config2 = 0x53,
180 Config3 = 0x54,
181 Config4 = 0x55,
182 Config5 = 0x56,
183 MultiIntr = 0x5C,
184 PHYAR = 0x60,
185 TBICSR = 0x64,
186 TBI_ANAR = 0x68,
187 TBI_LPAR = 0x6A,
188 PHYstatus = 0x6C,
189 RxMaxSize = 0xDA,
190 CPlusCmd = 0xE0,
191 RxDescAddrLow = 0xE4,
192 RxDescAddrHigh = 0xE8,
193 EarlyTxThres = 0xEC,
194 FuncEvent = 0xF0,
195 FuncEventMask = 0xF4,
196 FuncPresetState = 0xF8,
197 FuncForceEvent = 0xFC,
198 };
199
200 enum RTL8169_register_content {
201 /*InterruptStatusBits */
202 SYSErr = 0x8000,
203 PCSTimeout = 0x4000,
204 SWInt = 0x0100,
205 TxDescUnavail = 0x80,
206 RxFIFOOver = 0x40,
207 LinkChg = 0x20,
208 RxOverflow = 0x10,
209 TxErr = 0x08,
210 TxOK = 0x04,
211 RxErr = 0x02,
212 RxOK = 0x01,
213
214 /*RxStatusDesc */
215 RxRES = 0x00200000,
216 RxCRC = 0x00080000,
217 RxRUNT = 0x00100000,
218 RxRWT = 0x00400000,
219
220 /*ChipCmdBits */
221 CmdReset = 0x10,
222 CmdRxEnb = 0x08,
223 CmdTxEnb = 0x04,
224 RxBufEmpty = 0x01,
225
226 /*Cfg9346Bits */
227 Cfg9346_Lock = 0x00,
228 Cfg9346_Unlock = 0xC0,
229
230 /*rx_mode_bits */
231 AcceptErr = 0x20,
232 AcceptRunt = 0x10,
233 AcceptBroadcast = 0x08,
234 AcceptMulticast = 0x04,
235 AcceptMyPhys = 0x02,
236 AcceptAllPhys = 0x01,
237
238 /*RxConfigBits */
239 RxCfgFIFOShift = 13,
240 RxCfgDMAShift = 8,
241
242 /*TxConfigBits */
243 TxInterFrameGapShift = 24,
244 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
245
246 /* TBICSR p.28 */
247 TBIReset = 0x80000000,
248 TBILoopback = 0x40000000,
249 TBINwEnable = 0x20000000,
250 TBINwRestart = 0x10000000,
251 TBILinkOk = 0x02000000,
252 TBINwComplete = 0x01000000,
253
254 /* CPlusCmd p.31 */
255 RxVlan = (1 << 6),
256 RxChkSum = (1 << 5),
257 PCIDAC = (1 << 4),
258 PCIMulRW = (1 << 3),
259
260 /*rtl8169_PHYstatus */
261 TBI_Enable = 0x80,
262 TxFlowCtrl = 0x40,
263 RxFlowCtrl = 0x20,
264 _1000bpsF = 0x10,
265 _100bps = 0x08,
266 _10bps = 0x04,
267 LinkStatus = 0x02,
268 FullDup = 0x01,
269
270 /*GIGABIT_PHY_registers */
271 PHY_CTRL_REG = 0,
272 PHY_STAT_REG = 1,
273 PHY_AUTO_NEGO_REG = 4,
274 PHY_1000_CTRL_REG = 9,
275
276 /*GIGABIT_PHY_REG_BIT */
277 PHY_Restart_Auto_Nego = 0x0200,
278 PHY_Enable_Auto_Nego = 0x1000,
279
280 //PHY_STAT_REG = 1;
281 PHY_Auto_Neco_Comp = 0x0020,
282
283 //PHY_AUTO_NEGO_REG = 4;
284 PHY_Cap_10_Half = 0x0020,
285 PHY_Cap_10_Full = 0x0040,
286 PHY_Cap_100_Half = 0x0080,
287 PHY_Cap_100_Full = 0x0100,
288
289 //PHY_1000_CTRL_REG = 9;
290 PHY_Cap_1000_Full = 0x0200,
291
292 PHY_Cap_Null = 0x0,
293
294 /*_MediaType*/
295 _10_Half = 0x01,
296 _10_Full = 0x02,
297 _100_Half = 0x04,
298 _100_Full = 0x08,
299 _1000_Full = 0x10,
300
301 /*_TBICSRBit*/
302 TBILinkOK = 0x02000000,
303 };
304
305 enum _DescStatusBit {
306 OWNbit = 0x80000000,
307 EORbit = 0x40000000,
308 FSbit = 0x20000000,
309 LSbit = 0x10000000,
310 };
311
312 #define RsvdMask 0x3fffc000
313
314 struct TxDesc {
315 u32 status;
316 u32 vlan_tag;
317 u64 addr;
318 };
319
320 struct RxDesc {
321 u32 status;
322 u32 vlan_tag;
323 u64 addr;
324 };
325
326 struct rtl8169_private {
327 void *mmio_addr; /* memory map physical address */
328 struct pci_dev *pci_dev; /* Index of PCI device */
329 struct net_device_stats stats; /* statistics of net device */
330 spinlock_t lock; /* spin lock flag */
331 int chipset;
332 int mac_version;
333 int phy_version;
334 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
335 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
336 u32 dirty_rx;
337 u32 dirty_tx;
338 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
339 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
340 dma_addr_t TxPhyAddr;
341 dma_addr_t RxPhyAddr;
342 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
343 struct sk_buff *Tx_skbuff[NUM_TX_DESC]; /* Tx data buffers */
344 struct timer_list timer;
345 u16 cp_cmd;
346 u16 intr_mask;
347 int phy_auto_nego_reg;
348 int phy_1000_ctrl_reg;
349
350 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
351 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
352 void (*phy_reset_enable)(void *);
353 unsigned int (*phy_reset_pending)(void *);
354 unsigned int (*link_ok)(void *);
355 };
356
357 MODULE_AUTHOR("Realtek");
358 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
359 MODULE_PARM(media, "1-" __MODULE_STRING(MAX_UNITS) "i");
360 MODULE_PARM(rx_copybreak, "i");
361 MODULE_LICENSE("GPL");
362
363 static int rtl8169_open(struct net_device *dev);
364 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
365 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
366 struct pt_regs *regs);
367 static int rtl8169_init_ring(struct net_device *dev);
368 static void rtl8169_hw_start(struct net_device *dev);
369 static int rtl8169_close(struct net_device *dev);
370 static void rtl8169_set_rx_mode(struct net_device *dev);
371 static void rtl8169_tx_timeout(struct net_device *dev);
372 static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
373 #ifdef CONFIG_R8169_NAPI
374 static int rtl8169_poll(struct net_device *dev, int *budget);
375 #endif
376
377 static const u16 rtl8169_intr_mask =
378 LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
379 static const u16 rtl8169_napi_event =
380 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
381 static const unsigned int rtl8169_rx_config =
382 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
383
384 #define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
385 #define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
386 #define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
387 #define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
388
389 static void mdio_write(void *ioaddr, int RegAddr, int value)
390 {
391 int i;
392
393 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
394 udelay(1000);
395
396 for (i = 2000; i > 0; i--) {
397 // Check if the RTL8169 has completed writing to the specified MII register
398 if (!(RTL_R32(PHYAR) & 0x80000000))
399 break;
400 udelay(100);
401 }
402 }
403
404 static int mdio_read(void *ioaddr, int RegAddr)
405 {
406 int i, value = -1;
407
408 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
409 udelay(1000);
410
411 for (i = 2000; i > 0; i--) {
412 // Check if the RTL8169 has completed retrieving data from the specified MII register
413 if (RTL_R32(PHYAR) & 0x80000000) {
414 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
415 break;
416 }
417 udelay(100);
418 }
419 return value;
420 }
421
422 static unsigned int rtl8169_tbi_reset_pending(void *ioaddr)
423 {
424 return RTL_R32(TBICSR) & TBIReset;
425 }
426
427 static unsigned int rtl8169_xmii_reset_pending(void *ioaddr)
428 {
429 return mdio_read(ioaddr, 0) & 0x8000;
430 }
431
432 static unsigned int rtl8169_tbi_link_ok(void *ioaddr)
433 {
434 return RTL_R32(TBICSR) & TBILinkOk;
435 }
436
437 static unsigned int rtl8169_xmii_link_ok(void *ioaddr)
438 {
439 return RTL_R8(PHYstatus) & LinkStatus;
440 }
441
442 static void rtl8169_tbi_reset_enable(void *ioaddr)
443 {
444 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
445 }
446
447 static void rtl8169_xmii_reset_enable(void *ioaddr)
448 {
449 unsigned int val;
450
451 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
452 mdio_write(ioaddr, PHY_CTRL_REG, val);
453 }
454
455 static void rtl8169_check_link_status(struct net_device *dev,
456 struct rtl8169_private *tp, void *ioaddr)
457 {
458 unsigned long flags;
459
460 spin_lock_irqsave(&tp->lock, flags);
461 if (tp->link_ok(ioaddr)) {
462 netif_carrier_on(dev);
463 printk(KERN_INFO PFX "%s: link up\n", dev->name);
464 } else
465 netif_carrier_off(dev);
466 spin_unlock_irqrestore(&tp->lock, flags);
467 }
468
469 static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
470 {
471 struct {
472 u16 speed;
473 u8 duplex;
474 u8 autoneg;
475 u8 media;
476 } link_settings[] = {
477 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
478 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
479 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
480 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
481 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
482 /* Make TBI happy */
483 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
484 }, *p;
485 unsigned char option;
486
487 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
488
489 if ((option != 0xff) && !idx)
490 printk(KERN_WARNING PFX "media option is deprecated.\n");
491
492 for (p = link_settings; p->media != 0xff; p++) {
493 if (p->media == option)
494 break;
495 }
496 *autoneg = p->autoneg;
497 *speed = p->speed;
498 *duplex = p->duplex;
499 }
500
501 static void rtl8169_get_drvinfo(struct net_device *dev,
502 struct ethtool_drvinfo *info)
503 {
504 struct rtl8169_private *tp = netdev_priv(dev);
505
506 strcpy(info->driver, RTL8169_DRIVER_NAME);
507 strcpy(info->version, RTL8169_VERSION );
508 strcpy(info->bus_info, pci_name(tp->pci_dev));
509 }
510
511 static int rtl8169_set_speed_tbi(struct net_device *dev,
512 u8 autoneg, u16 speed, u8 duplex)
513 {
514 struct rtl8169_private *tp = netdev_priv(dev);
515 void *ioaddr = tp->mmio_addr;
516 int ret = 0;
517 u32 reg;
518
519 reg = RTL_R32(TBICSR);
520 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
521 (duplex == DUPLEX_FULL)) {
522 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
523 } else if (autoneg == AUTONEG_ENABLE)
524 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
525 else {
526 printk(KERN_WARNING PFX
527 "%s: incorrect speed setting refused in TBI mode\n",
528 dev->name);
529 ret = -EOPNOTSUPP;
530 }
531
532 return ret;
533 }
534
535 static int rtl8169_set_speed_xmii(struct net_device *dev,
536 u8 autoneg, u16 speed, u8 duplex)
537 {
538 struct rtl8169_private *tp = netdev_priv(dev);
539 void *ioaddr = tp->mmio_addr;
540 int auto_nego, giga_ctrl;
541
542 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
543 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
544 PHY_Cap_100_Half | PHY_Cap_100_Full);
545 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
546 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
547
548 if (autoneg == AUTONEG_ENABLE) {
549 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
550 PHY_Cap_100_Half | PHY_Cap_100_Full);
551 giga_ctrl |= PHY_Cap_1000_Full;
552 } else {
553 if (speed == SPEED_10)
554 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
555 else if (speed == SPEED_100)
556 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
557 else if (speed == SPEED_1000)
558 giga_ctrl |= PHY_Cap_1000_Full;
559
560 if (duplex == DUPLEX_HALF)
561 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
562 }
563
564 tp->phy_auto_nego_reg = auto_nego;
565 tp->phy_1000_ctrl_reg = giga_ctrl;
566
567 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
568 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
569 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
570 PHY_Restart_Auto_Nego);
571 return 0;
572 }
573
574 static int rtl8169_set_speed(struct net_device *dev,
575 u8 autoneg, u16 speed, u8 duplex)
576 {
577 struct rtl8169_private *tp = netdev_priv(dev);
578 int ret;
579
580 ret = tp->set_speed(dev, autoneg, speed, duplex);
581
582 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
583 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
584
585 return ret;
586 }
587
588 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
589 {
590 struct rtl8169_private *tp = netdev_priv(dev);
591 unsigned long flags;
592 int ret;
593
594 spin_lock_irqsave(&tp->lock, flags);
595 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
596 spin_unlock_irqrestore(&tp->lock, flags);
597
598 return ret;
599 }
600
601 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
602 {
603 struct rtl8169_private *tp = netdev_priv(dev);
604 void *ioaddr = tp->mmio_addr;
605 u32 status;
606
607 cmd->supported =
608 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
609 cmd->port = PORT_FIBRE;
610 cmd->transceiver = XCVR_INTERNAL;
611
612 status = RTL_R32(TBICSR);
613 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
614 cmd->autoneg = !!(status & TBINwEnable);
615
616 cmd->speed = SPEED_1000;
617 cmd->duplex = DUPLEX_FULL; /* Always set */
618 }
619
620 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
621 {
622 struct rtl8169_private *tp = netdev_priv(dev);
623 void *ioaddr = tp->mmio_addr;
624 u8 status;
625
626 cmd->supported = SUPPORTED_10baseT_Half |
627 SUPPORTED_10baseT_Full |
628 SUPPORTED_100baseT_Half |
629 SUPPORTED_100baseT_Full |
630 SUPPORTED_1000baseT_Full |
631 SUPPORTED_Autoneg |
632 SUPPORTED_TP;
633
634 cmd->autoneg = 1;
635 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
636
637 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
638 cmd->advertising |= ADVERTISED_10baseT_Half;
639 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
640 cmd->advertising |= ADVERTISED_10baseT_Full;
641 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
642 cmd->advertising |= ADVERTISED_100baseT_Half;
643 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
644 cmd->advertising |= ADVERTISED_100baseT_Full;
645 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
646 cmd->advertising |= ADVERTISED_1000baseT_Full;
647
648 status = RTL_R8(PHYstatus);
649
650 if (status & _1000bpsF)
651 cmd->speed = SPEED_1000;
652 else if (status & _100bps)
653 cmd->speed = SPEED_100;
654 else if (status & _10bps)
655 cmd->speed = SPEED_10;
656
657 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
658 DUPLEX_FULL : DUPLEX_HALF;
659 }
660
661 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
662 {
663 struct rtl8169_private *tp = netdev_priv(dev);
664 unsigned long flags;
665
666 spin_lock_irqsave(&tp->lock, flags);
667
668 tp->get_settings(dev, cmd);
669
670 spin_unlock_irqrestore(&tp->lock, flags);
671 return 0;
672 }
673
674
675 static struct ethtool_ops rtl8169_ethtool_ops = {
676 .get_drvinfo = rtl8169_get_drvinfo,
677 .get_link = ethtool_op_get_link,
678 .get_settings = rtl8169_get_settings,
679 .set_settings = rtl8169_set_settings,
680 };
681
682 static void rtl8169_write_gmii_reg_bit(void *ioaddr, int reg, int bitnum,
683 int bitval)
684 {
685 int val;
686
687 val = mdio_read(ioaddr, reg);
688 val = (bitval == 1) ?
689 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
690 mdio_write(ioaddr, reg, val & 0xffff);
691 }
692
693 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void *ioaddr)
694 {
695 const struct {
696 u32 mask;
697 int mac_version;
698 } mac_info[] = {
699 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
700 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
701 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
702 }, *p = mac_info;
703 u32 reg;
704
705 reg = RTL_R32(TxConfig) & 0x7c800000;
706 while ((reg & p->mask) != p->mask)
707 p++;
708 tp->mac_version = p->mac_version;
709 }
710
711 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
712 {
713 struct {
714 int version;
715 char *msg;
716 } mac_print[] = {
717 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
718 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
719 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
720 { 0, NULL }
721 }, *p;
722
723 for (p = mac_print; p->msg; p++) {
724 if (tp->mac_version == p->version) {
725 dprintk("mac_version == %s (%04d)\n", p->msg,
726 p->version);
727 return;
728 }
729 }
730 dprintk("mac_version == Unknown\n");
731 }
732
733 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void *ioaddr)
734 {
735 const struct {
736 u16 mask;
737 u16 set;
738 int phy_version;
739 } phy_info[] = {
740 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
741 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
742 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
743 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
744 }, *p = phy_info;
745 u16 reg;
746
747 reg = mdio_read(ioaddr, 3) & 0xffff;
748 while ((reg & p->mask) != p->set)
749 p++;
750 tp->phy_version = p->phy_version;
751 }
752
753 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
754 {
755 struct {
756 int version;
757 char *msg;
758 u32 reg;
759 } phy_print[] = {
760 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
761 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
762 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
763 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
764 { 0, NULL, 0x0000 }
765 }, *p;
766
767 for (p = phy_print; p->msg; p++) {
768 if (tp->phy_version == p->version) {
769 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
770 return;
771 }
772 }
773 dprintk("phy_version == Unknown\n");
774 }
775
776 static void rtl8169_hw_phy_config(struct net_device *dev)
777 {
778 struct rtl8169_private *tp = netdev_priv(dev);
779 void *ioaddr = tp->mmio_addr;
780 struct {
781 u16 regs[5]; /* Beware of bit-sign propagation */
782 } phy_magic[5] = { {
783 { 0x0000, //w 4 15 12 0
784 0x00a1, //w 3 15 0 00a1
785 0x0008, //w 2 15 0 0008
786 0x1020, //w 1 15 0 1020
787 0x1000 } },{ //w 0 15 0 1000
788 { 0x7000, //w 4 15 12 7
789 0xff41, //w 3 15 0 ff41
790 0xde60, //w 2 15 0 de60
791 0x0140, //w 1 15 0 0140
792 0x0077 } },{ //w 0 15 0 0077
793 { 0xa000, //w 4 15 12 a
794 0xdf01, //w 3 15 0 df01
795 0xdf20, //w 2 15 0 df20
796 0xff95, //w 1 15 0 ff95
797 0xfa00 } },{ //w 0 15 0 fa00
798 { 0xb000, //w 4 15 12 b
799 0xff41, //w 3 15 0 ff41
800 0xde20, //w 2 15 0 de20
801 0x0140, //w 1 15 0 0140
802 0x00bb } },{ //w 0 15 0 00bb
803 { 0xf000, //w 4 15 12 f
804 0xdf01, //w 3 15 0 df01
805 0xdf20, //w 2 15 0 df20
806 0xff95, //w 1 15 0 ff95
807 0xbf00 } //w 0 15 0 bf00
808 }
809 }, *p = phy_magic;
810 int i;
811
812 rtl8169_print_mac_version(tp);
813 rtl8169_print_phy_version(tp);
814
815 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
816 return;
817 if (tp->phy_version >= RTL_GIGA_PHY_VER_F)
818 return;
819
820 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
821 dprintk("Do final_reg2.cfg\n");
822
823 /* Shazam ! */
824
825 // phy config for RTL8169s mac_version C chip
826 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
827 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
828 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
829 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
830
831 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
832 int val, pos = 4;
833
834 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
835 mdio_write(ioaddr, pos, val);
836 while (--pos >= 0)
837 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
838 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
839 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
840 }
841 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
842 }
843
844 static void rtl8169_phy_timer(unsigned long __opaque)
845 {
846 struct net_device *dev = (struct net_device *)__opaque;
847 struct rtl8169_private *tp = netdev_priv(dev);
848 struct timer_list *timer = &tp->timer;
849 void *ioaddr = tp->mmio_addr;
850 unsigned long timeout = RTL8169_PHY_TIMEOUT;
851
852 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
853 assert(tp->phy_version < RTL_GIGA_PHY_VER_G);
854
855 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
856 return;
857
858 spin_lock_irq(&tp->lock);
859
860 if (tp->phy_reset_pending(ioaddr)) {
861 /*
862 * A busy loop could burn quite a few cycles on nowadays CPU.
863 * Let's delay the execution of the timer for a few ticks.
864 */
865 timeout = HZ/10;
866 goto out_mod_timer;
867 }
868
869 if (tp->link_ok(ioaddr))
870 goto out_unlock;
871
872 printk(KERN_WARNING PFX "%s: PHY reset until link up\n", dev->name);
873
874 tp->phy_reset_enable(ioaddr);
875
876 out_mod_timer:
877 mod_timer(timer, jiffies + timeout);
878 out_unlock:
879 spin_unlock_irq(&tp->lock);
880 }
881
882 static inline void rtl8169_delete_timer(struct net_device *dev)
883 {
884 struct rtl8169_private *tp = netdev_priv(dev);
885 struct timer_list *timer = &tp->timer;
886
887 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
888 (tp->phy_version >= RTL_GIGA_PHY_VER_G))
889 return;
890
891 del_timer_sync(timer);
892 }
893
894 static inline void rtl8169_request_timer(struct net_device *dev)
895 {
896 struct rtl8169_private *tp = netdev_priv(dev);
897 struct timer_list *timer = &tp->timer;
898
899 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
900 (tp->phy_version >= RTL_GIGA_PHY_VER_G))
901 return;
902
903 init_timer(timer);
904 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
905 timer->data = (unsigned long)(dev);
906 timer->function = rtl8169_phy_timer;
907 add_timer(timer);
908 }
909
910 static int __devinit
911 rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
912 void **ioaddr_out)
913 {
914 void *ioaddr = NULL;
915 struct net_device *dev;
916 struct rtl8169_private *tp;
917 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
918 int rc, i, acpi_idle_state = 0, pm_cap;
919
920
921 assert(pdev != NULL);
922 assert(ioaddr_out != NULL);
923
924 *ioaddr_out = NULL;
925 *dev_out = NULL;
926
927 // dev zeroed in alloc_etherdev
928 dev = alloc_etherdev(sizeof (*tp));
929 if (dev == NULL) {
930 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
931 return -ENOMEM;
932 }
933
934 SET_MODULE_OWNER(dev);
935 SET_NETDEV_DEV(dev, &pdev->dev);
936 tp = dev->priv;
937
938 // enable device (incl. PCI PM wakeup and hotplug setup)
939 rc = pci_enable_device(pdev);
940 if (rc) {
941 printk(KERN_ERR PFX "%s: enable failure\n", pdev->slot_name);
942 goto err_out;
943 }
944
945 /* save power state before pci_enable_device overwrites it */
946 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
947 if (pm_cap) {
948 u16 pwr_command;
949
950 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
951 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
952 } else {
953 printk(KERN_ERR PFX
954 "Cannot find PowerManagement capability, aborting.\n");
955 goto err_out_free_res;
956 }
957
958 mmio_start = pci_resource_start(pdev, 1);
959 mmio_end = pci_resource_end(pdev, 1);
960 mmio_flags = pci_resource_flags(pdev, 1);
961 mmio_len = pci_resource_len(pdev, 1);
962
963 // make sure PCI base addr 1 is MMIO
964 if (!(mmio_flags & IORESOURCE_MEM)) {
965 printk(KERN_ERR PFX
966 "region #1 not an MMIO resource, aborting\n");
967 rc = -ENODEV;
968 goto err_out_disable;
969 }
970 // check for weird/broken PCI region reporting
971 if (mmio_len < RTL_MIN_IO_SIZE) {
972 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
973 rc = -ENODEV;
974 goto err_out_disable;
975 }
976
977 rc = pci_request_regions(pdev, MODULENAME);
978 if (rc) {
979 printk(KERN_ERR PFX "%s: could not request regions.\n",
980 pdev->slot_name);
981 goto err_out_disable;
982 }
983
984 tp->cp_cmd = PCIMulRW | RxChkSum;
985
986 if ((sizeof(dma_addr_t) > 32) &&
987 !pci_set_dma_mask(pdev, DMA_64BIT_MASK))
988 tp->cp_cmd |= PCIDAC;
989 else {
990 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
991 if (rc < 0) {
992 printk(KERN_ERR PFX "DMA configuration failed.\n");
993 goto err_out_free_res;
994 }
995 }
996
997
998 // enable PCI bus-mastering
999 pci_set_master(pdev);
1000
1001 // ioremap MMIO region
1002 ioaddr = ioremap(mmio_start, mmio_len);
1003 if (ioaddr == NULL) {
1004 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1005 rc = -EIO;
1006 goto err_out_free_res;
1007 }
1008
1009 // Soft reset the chip.
1010 RTL_W8(ChipCmd, CmdReset);
1011
1012 // Check that the chip has finished the reset.
1013 for (i = 1000; i > 0; i--) {
1014 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1015 break;
1016 udelay(10);
1017 }
1018
1019 // Identify chip attached to board
1020 rtl8169_get_mac_version(tp, ioaddr);
1021 rtl8169_get_phy_version(tp, ioaddr);
1022
1023 rtl8169_print_mac_version(tp);
1024 rtl8169_print_phy_version(tp);
1025
1026 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1027 if (tp->mac_version == rtl_chip_info[i].mac_version)
1028 break;
1029 }
1030 if (i < 0) {
1031 /* Unknown chip: assume array element #0, original RTL-8169 */
1032 printk(KERN_DEBUG PFX
1033 "PCI device %s: unknown chip version, assuming %s\n",
1034 pci_name(pdev), rtl_chip_info[0].name);
1035 i++;
1036 }
1037 tp->chipset = i;
1038
1039 *ioaddr_out = ioaddr;
1040 *dev_out = dev;
1041 return 0;
1042
1043 err_out_free_res:
1044 pci_release_regions(pdev);
1045
1046 err_out_disable:
1047 pci_disable_device(pdev);
1048
1049 err_out:
1050 free_netdev(dev);
1051 return rc;
1052 }
1053
1054 static int __devinit
1055 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1056 {
1057 struct net_device *dev = NULL;
1058 struct rtl8169_private *tp = NULL;
1059 void *ioaddr = NULL;
1060 static int board_idx = -1;
1061 static int printed_version = 0;
1062 u8 autoneg, duplex;
1063 u16 speed;
1064 int i, rc;
1065
1066 assert(pdev != NULL);
1067 assert(ent != NULL);
1068
1069 board_idx++;
1070
1071 if (!printed_version) {
1072 printk(KERN_INFO RTL8169_DRIVER_NAME " loaded\n");
1073 printed_version = 1;
1074 }
1075
1076 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1077 if (rc)
1078 return rc;
1079
1080 tp = dev->priv;
1081 assert(ioaddr != NULL);
1082 assert(dev != NULL);
1083 assert(tp != NULL);
1084
1085 if (RTL_R8(PHYstatus) & TBI_Enable) {
1086 tp->set_speed = rtl8169_set_speed_tbi;
1087 tp->get_settings = rtl8169_gset_tbi;
1088 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1089 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1090 tp->link_ok = rtl8169_tbi_link_ok;
1091
1092 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1093 } else {
1094 tp->set_speed = rtl8169_set_speed_xmii;
1095 tp->get_settings = rtl8169_gset_xmii;
1096 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1097 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1098 tp->link_ok = rtl8169_xmii_link_ok;
1099 }
1100
1101 // Get MAC address. FIXME: read EEPROM
1102 for (i = 0; i < MAC_ADDR_LEN; i++)
1103 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1104
1105 dev->open = rtl8169_open;
1106 dev->hard_start_xmit = rtl8169_start_xmit;
1107 dev->get_stats = rtl8169_get_stats;
1108 dev->ethtool_ops = &rtl8169_ethtool_ops;
1109 dev->stop = rtl8169_close;
1110 dev->tx_timeout = rtl8169_tx_timeout;
1111 dev->set_multicast_list = rtl8169_set_rx_mode;
1112 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1113 dev->irq = pdev->irq;
1114 dev->base_addr = (unsigned long) ioaddr;
1115 #ifdef CONFIG_R8169_NAPI
1116 dev->poll = rtl8169_poll;
1117 dev->weight = R8169_NAPI_WEIGHT;
1118 printk(KERN_INFO PFX "NAPI enabled\n");
1119 #endif
1120 tp->intr_mask = 0xffff;
1121 tp->pci_dev = pdev;
1122 tp->mmio_addr = ioaddr;
1123
1124 spin_lock_init(&tp->lock);
1125
1126 rc = register_netdev(dev);
1127 if (rc) {
1128 iounmap(ioaddr);
1129 pci_release_regions(pdev);
1130 pci_disable_device(pdev);
1131 free_netdev(dev);
1132 return rc;
1133 }
1134
1135 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
1136 rtl_chip_info[tp->chipset].name);
1137
1138 pci_set_drvdata(pdev, dev);
1139
1140 printk(KERN_INFO "%s: %s at 0x%lx, "
1141 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1142 "IRQ %d\n",
1143 dev->name,
1144 rtl_chip_info[ent->driver_data].name,
1145 dev->base_addr,
1146 dev->dev_addr[0], dev->dev_addr[1],
1147 dev->dev_addr[2], dev->dev_addr[3],
1148 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1149
1150 rtl8169_hw_phy_config(dev);
1151
1152 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1153 RTL_W8(0x82, 0x01);
1154
1155 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1156 dprintk("Set PCI Latency=0x40\n");
1157 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1158 }
1159
1160 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1161 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1162 RTL_W8(0x82, 0x01);
1163 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1164 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1165 }
1166
1167 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1168
1169 rtl8169_set_speed(dev, autoneg, speed, duplex);
1170
1171 if (RTL_R8(PHYstatus) & TBI_Enable)
1172 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1173
1174 return 0;
1175 }
1176
1177 static void __devexit
1178 rtl8169_remove_one(struct pci_dev *pdev)
1179 {
1180 struct net_device *dev = pci_get_drvdata(pdev);
1181 struct rtl8169_private *tp = netdev_priv(dev);
1182
1183 assert(dev != NULL);
1184 assert(tp != NULL);
1185
1186 unregister_netdev(dev);
1187 iounmap(tp->mmio_addr);
1188 pci_release_regions(pdev);
1189
1190 pci_disable_device(pdev);
1191 free_netdev(dev);
1192 pci_set_drvdata(pdev, NULL);
1193 }
1194
1195 #ifdef CONFIG_PM
1196
1197 static int rtl8169_suspend(struct pci_dev *pdev, u32 state)
1198 {
1199 struct net_device *dev = pci_get_drvdata(pdev);
1200 struct rtl8169_private *tp = netdev_priv(dev);
1201 void *ioaddr = tp->mmio_addr;
1202 unsigned long flags;
1203
1204 if (!netif_running(dev))
1205 return 0;
1206
1207 netif_device_detach(dev);
1208 netif_stop_queue(dev);
1209 spin_lock_irqsave(&tp->lock, flags);
1210
1211 /* Disable interrupts, stop Rx and Tx */
1212 RTL_W16(IntrMask, 0);
1213 RTL_W8(ChipCmd, 0);
1214
1215 /* Update the error counts. */
1216 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1217 RTL_W32(RxMissed, 0);
1218 spin_unlock_irqrestore(&tp->lock, flags);
1219
1220 return 0;
1221 }
1222
1223 static int rtl8169_resume(struct pci_dev *pdev)
1224 {
1225 struct net_device *dev = pci_get_drvdata(pdev);
1226
1227 if (!netif_running(dev))
1228 return 0;
1229
1230 netif_device_attach(dev);
1231 rtl8169_hw_start(dev);
1232
1233 return 0;
1234 }
1235
1236 #endif /* CONFIG_PM */
1237
1238 static int
1239 rtl8169_open(struct net_device *dev)
1240 {
1241 struct rtl8169_private *tp = netdev_priv(dev);
1242 struct pci_dev *pdev = tp->pci_dev;
1243 int retval;
1244
1245 retval =
1246 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1247 if (retval < 0)
1248 goto out;
1249
1250 retval = -ENOMEM;
1251
1252 /*
1253 * Rx and Tx desscriptors needs 256 bytes alignment.
1254 * pci_alloc_consistent provides more.
1255 */
1256 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1257 &tp->TxPhyAddr);
1258 if (!tp->TxDescArray)
1259 goto err_free_irq;
1260
1261 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1262 &tp->RxPhyAddr);
1263 if (!tp->RxDescArray)
1264 goto err_free_tx;
1265
1266 retval = rtl8169_init_ring(dev);
1267 if (retval < 0)
1268 goto err_free_rx;
1269
1270 rtl8169_hw_start(dev);
1271
1272 rtl8169_request_timer(dev);
1273
1274 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1275 out:
1276 return retval;
1277
1278 err_free_rx:
1279 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1280 tp->RxPhyAddr);
1281 err_free_tx:
1282 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1283 tp->TxPhyAddr);
1284 err_free_irq:
1285 free_irq(dev->irq, dev);
1286 goto out;
1287 }
1288
1289 static void
1290 rtl8169_hw_start(struct net_device *dev)
1291 {
1292 struct rtl8169_private *tp = netdev_priv(dev);
1293 void *ioaddr = tp->mmio_addr;
1294 u32 i;
1295
1296 /* Soft reset the chip. */
1297 RTL_W8(ChipCmd, CmdReset);
1298
1299 /* Check that the chip has finished the reset. */
1300 for (i = 1000; i > 0; i--) {
1301 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1302 break;
1303 udelay(10);
1304 }
1305
1306 RTL_W8(Cfg9346, Cfg9346_Unlock);
1307 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1308 RTL_W8(EarlyTxThres, EarlyTxThld);
1309
1310 // For gigabit rtl8169
1311 RTL_W16(RxMaxSize, RxPacketMaxSize);
1312
1313 // Set Rx Config register
1314 i = rtl8169_rx_config |
1315 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1316 RTL_W32(RxConfig, i);
1317
1318 /* Set DMA burst size and Interframe Gap Time */
1319 RTL_W32(TxConfig,
1320 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1321 TxInterFrameGapShift));
1322 tp->cp_cmd |= RTL_R16(CPlusCmd);
1323 RTL_W16(CPlusCmd, tp->cp_cmd);
1324
1325 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1326 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1327 "Bit-3 and bit-14 MUST be 1\n");
1328 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1329 RTL_W16(CPlusCmd, tp->cp_cmd);
1330 }
1331
1332 tp->cur_rx = 0;
1333
1334 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1335 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1336 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1337 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1338 RTL_W8(Cfg9346, Cfg9346_Lock);
1339 udelay(10);
1340
1341 RTL_W32(RxMissed, 0);
1342
1343 rtl8169_set_rx_mode(dev);
1344
1345 /* no early-rx interrupts */
1346 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1347
1348 /* Enable all known interrupts by setting the interrupt mask. */
1349 RTL_W16(IntrMask, rtl8169_intr_mask);
1350
1351 netif_start_queue(dev);
1352 }
1353
1354 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1355 {
1356 desc->addr = 0x0badbadbadbadbadull;
1357 desc->status &= ~cpu_to_le32(OWNbit | RsvdMask);
1358 }
1359
1360 static void rtl8169_free_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1361 struct RxDesc *desc)
1362 {
1363 pci_unmap_single(pdev, le64_to_cpu(desc->addr), RX_BUF_SIZE,
1364 PCI_DMA_FROMDEVICE);
1365 dev_kfree_skb(*sk_buff);
1366 *sk_buff = NULL;
1367 rtl8169_make_unusable_by_asic(desc);
1368 }
1369
1370 static inline void rtl8169_return_to_asic(struct RxDesc *desc)
1371 {
1372 desc->status |= cpu_to_le32(OWNbit + RX_BUF_SIZE);
1373 }
1374
1375 static inline void rtl8169_give_to_asic(struct RxDesc *desc, dma_addr_t mapping)
1376 {
1377 desc->addr = cpu_to_le64(mapping);
1378 desc->status |= cpu_to_le32(OWNbit + RX_BUF_SIZE);
1379 }
1380
1381 static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct net_device *dev,
1382 struct sk_buff **sk_buff, struct RxDesc *desc)
1383 {
1384 struct sk_buff *skb;
1385 dma_addr_t mapping;
1386 int ret = 0;
1387
1388 skb = dev_alloc_skb(RX_BUF_SIZE);
1389 if (!skb)
1390 goto err_out;
1391
1392 skb->dev = dev;
1393 skb_reserve(skb, 2);
1394 *sk_buff = skb;
1395
1396 mapping = pci_map_single(pdev, skb->tail, RX_BUF_SIZE,
1397 PCI_DMA_FROMDEVICE);
1398
1399 rtl8169_give_to_asic(desc, mapping);
1400
1401 out:
1402 return ret;
1403
1404 err_out:
1405 ret = -ENOMEM;
1406 rtl8169_make_unusable_by_asic(desc);
1407 goto out;
1408 }
1409
1410 static void rtl8169_rx_clear(struct rtl8169_private *tp)
1411 {
1412 int i;
1413
1414 for (i = 0; i < NUM_RX_DESC; i++) {
1415 if (tp->Rx_skbuff[i]) {
1416 rtl8169_free_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1417 tp->RxDescArray + i);
1418 }
1419 }
1420 }
1421
1422 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1423 u32 start, u32 end)
1424 {
1425 u32 cur;
1426
1427 for (cur = start; end - cur > 0; cur++) {
1428 int ret, i = cur % NUM_RX_DESC;
1429
1430 if (tp->Rx_skbuff[i])
1431 continue;
1432
1433 ret = rtl8169_alloc_rx_skb(tp->pci_dev, dev, tp->Rx_skbuff + i,
1434 tp->RxDescArray + i);
1435 if (ret < 0)
1436 break;
1437 }
1438 return cur - start;
1439 }
1440
1441 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1442 {
1443 desc->status |= cpu_to_le32(EORbit);
1444 }
1445
1446 static int rtl8169_init_ring(struct net_device *dev)
1447 {
1448 struct rtl8169_private *tp = netdev_priv(dev);
1449
1450 tp->cur_rx = tp->dirty_rx = 0;
1451 tp->cur_tx = tp->dirty_tx = 0;
1452 memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof (struct TxDesc));
1453 memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof (struct RxDesc));
1454
1455 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
1456 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1457
1458 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1459 goto err_out;
1460
1461 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1462
1463 return 0;
1464
1465 err_out:
1466 rtl8169_rx_clear(tp);
1467 return -ENOMEM;
1468 }
1469
1470 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1471 struct TxDesc *desc)
1472 {
1473 u32 len = sk_buff[0]->len;
1474
1475 pci_unmap_single(pdev, le64_to_cpu(desc->addr),
1476 len < ETH_ZLEN ? ETH_ZLEN : len, PCI_DMA_TODEVICE);
1477 desc->addr = 0x00;
1478 *sk_buff = NULL;
1479 }
1480
1481 static void
1482 rtl8169_tx_clear(struct rtl8169_private *tp)
1483 {
1484 int i;
1485
1486 tp->cur_tx = 0;
1487 for (i = 0; i < NUM_TX_DESC; i++) {
1488 struct sk_buff *skb = tp->Tx_skbuff[i];
1489
1490 if (skb) {
1491 rtl8169_unmap_tx_skb(tp->pci_dev, tp->Tx_skbuff + i,
1492 tp->TxDescArray + i);
1493 dev_kfree_skb(skb);
1494 tp->stats.tx_dropped++;
1495 }
1496 }
1497 }
1498
1499 static void
1500 rtl8169_tx_timeout(struct net_device *dev)
1501 {
1502 struct rtl8169_private *tp = netdev_priv(dev);
1503 void *ioaddr = tp->mmio_addr;
1504 u8 tmp8;
1505
1506 printk(KERN_INFO "%s: TX Timeout\n", dev->name);
1507 /* disable Tx, if not already */
1508 tmp8 = RTL_R8(ChipCmd);
1509 if (tmp8 & CmdTxEnb)
1510 RTL_W8(ChipCmd, tmp8 & ~CmdTxEnb);
1511
1512 /* Disable interrupts by clearing the interrupt mask. */
1513 RTL_W16(IntrMask, 0x0000);
1514
1515 /* Stop a shared interrupt from scavenging while we are. */
1516 spin_lock_irq(&tp->lock);
1517 rtl8169_tx_clear(tp);
1518 spin_unlock_irq(&tp->lock);
1519
1520 /* ...and finally, reset everything */
1521 rtl8169_hw_start(dev);
1522
1523 netif_wake_queue(dev);
1524 }
1525
1526 static int
1527 rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
1528 {
1529 struct rtl8169_private *tp = netdev_priv(dev);
1530 void *ioaddr = tp->mmio_addr;
1531 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1532 u32 len = skb->len;
1533
1534 if (unlikely(skb->len < ETH_ZLEN)) {
1535 skb = skb_padto(skb, ETH_ZLEN);
1536 if (!skb)
1537 goto err_update_stats;
1538 len = ETH_ZLEN;
1539 }
1540
1541 if (!(le32_to_cpu(tp->TxDescArray[entry].status) & OWNbit)) {
1542 dma_addr_t mapping;
1543 u32 status;
1544
1545 mapping = pci_map_single(tp->pci_dev, skb->data, len,
1546 PCI_DMA_TODEVICE);
1547
1548 tp->Tx_skbuff[entry] = skb;
1549 tp->TxDescArray[entry].addr = cpu_to_le64(mapping);
1550
1551 /* anti gcc 2.95.3 bugware */
1552 status = OWNbit | FSbit | LSbit | len |
1553 (EORbit * !((entry + 1) % NUM_TX_DESC));
1554 tp->TxDescArray[entry].status = cpu_to_le32(status);
1555
1556 RTL_W8(TxPoll, 0x40); //set polling bit
1557
1558 dev->trans_start = jiffies;
1559
1560 tp->cur_tx++;
1561 smp_wmb();
1562 } else
1563 goto err_drop;
1564
1565 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) {
1566 u32 dirty = tp->dirty_tx;
1567
1568 netif_stop_queue(dev);
1569 smp_rmb();
1570 if (dirty != tp->dirty_tx)
1571 netif_wake_queue(dev);
1572 }
1573
1574 out:
1575 return 0;
1576
1577 err_drop:
1578 dev_kfree_skb(skb);
1579 err_update_stats:
1580 tp->stats.tx_dropped++;
1581 goto out;
1582 }
1583
1584 static void
1585 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1586 void *ioaddr)
1587 {
1588 unsigned int dirty_tx, tx_left;
1589
1590 assert(dev != NULL);
1591 assert(tp != NULL);
1592 assert(ioaddr != NULL);
1593
1594 dirty_tx = tp->dirty_tx;
1595 smp_rmb();
1596 tx_left = tp->cur_tx - dirty_tx;
1597
1598 while (tx_left > 0) {
1599 unsigned int entry = dirty_tx % NUM_TX_DESC;
1600 struct sk_buff *skb = tp->Tx_skbuff[entry];
1601 u32 status;
1602
1603 rmb();
1604 status = le32_to_cpu(tp->TxDescArray[entry].status);
1605 if (status & OWNbit)
1606 break;
1607
1608 /* FIXME: is it really accurate for TxErr ? */
1609 tp->stats.tx_bytes += skb->len >= ETH_ZLEN ?
1610 skb->len : ETH_ZLEN;
1611 tp->stats.tx_packets++;
1612 rtl8169_unmap_tx_skb(tp->pci_dev, tp->Tx_skbuff + entry,
1613 tp->TxDescArray + entry);
1614 dev_kfree_skb_irq(skb);
1615 tp->Tx_skbuff[entry] = NULL;
1616 dirty_tx++;
1617 tx_left--;
1618 }
1619
1620 if (tp->dirty_tx != dirty_tx) {
1621 tp->dirty_tx = dirty_tx;
1622 smp_wmb();
1623 if (netif_queue_stopped(dev))
1624 netif_wake_queue(dev);
1625 }
1626 }
1627
1628 static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
1629 struct RxDesc *desc,
1630 struct net_device *dev)
1631 {
1632 int ret = -1;
1633
1634 if (pkt_size < rx_copybreak) {
1635 struct sk_buff *skb;
1636
1637 skb = dev_alloc_skb(pkt_size + 2);
1638 if (skb) {
1639 skb->dev = dev;
1640 skb_reserve(skb, 2);
1641 eth_copy_and_sum(skb, sk_buff[0]->tail, pkt_size, 0);
1642 *sk_buff = skb;
1643 rtl8169_return_to_asic(desc);
1644 ret = 0;
1645 }
1646 }
1647 return ret;
1648 }
1649
1650 static int
1651 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1652 void *ioaddr)
1653 {
1654 unsigned int cur_rx, rx_left, count;
1655 int delta;
1656
1657 assert(dev != NULL);
1658 assert(tp != NULL);
1659 assert(ioaddr != NULL);
1660
1661 cur_rx = tp->cur_rx;
1662 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
1663 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
1664
1665 while (rx_left > 0) {
1666 unsigned int entry = cur_rx % NUM_RX_DESC;
1667 u32 status;
1668
1669 rmb();
1670 status = le32_to_cpu(tp->RxDescArray[entry].status);
1671
1672 if (status & OWNbit)
1673 break;
1674 if (status & RxRES) {
1675 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
1676 tp->stats.rx_errors++;
1677 if (status & (RxRWT | RxRUNT))
1678 tp->stats.rx_length_errors++;
1679 if (status & RxCRC)
1680 tp->stats.rx_crc_errors++;
1681 } else {
1682 struct RxDesc *desc = tp->RxDescArray + entry;
1683 struct sk_buff *skb = tp->Rx_skbuff[entry];
1684 int pkt_size = (status & 0x00001FFF) - 4;
1685 void (*pci_action)(struct pci_dev *, dma_addr_t,
1686 size_t, int) = pci_dma_sync_single_for_device;
1687
1688
1689 pci_dma_sync_single_for_cpu(tp->pci_dev,
1690 le64_to_cpu(desc->addr), RX_BUF_SIZE,
1691 PCI_DMA_FROMDEVICE);
1692
1693 if (rtl8169_try_rx_copy(&skb, pkt_size, desc, dev)) {
1694 pci_action = pci_unmap_single;
1695 tp->Rx_skbuff[entry] = NULL;
1696 }
1697
1698 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
1699 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1700
1701 skb_put(skb, pkt_size);
1702 skb->protocol = eth_type_trans(skb, dev);
1703 rtl8169_rx_skb(skb);
1704
1705 dev->last_rx = jiffies;
1706 tp->stats.rx_bytes += pkt_size;
1707 tp->stats.rx_packets++;
1708 }
1709
1710 cur_rx++;
1711 rx_left--;
1712 }
1713
1714 count = cur_rx - tp->cur_rx;
1715 tp->cur_rx = cur_rx;
1716
1717 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
1718 if (delta < 0) {
1719 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
1720 delta = 0;
1721 }
1722 tp->dirty_rx += delta;
1723
1724 /*
1725 * FIXME: until there is periodic timer to try and refill the ring,
1726 * a temporary shortage may definitely kill the Rx process.
1727 * - disable the asic to try and avoid an overflow and kick it again
1728 * after refill ?
1729 * - how do others driver handle this condition (Uh oh...).
1730 */
1731 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
1732 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
1733
1734 return count;
1735 }
1736
1737 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
1738 static irqreturn_t
1739 rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1740 {
1741 struct net_device *dev = (struct net_device *) dev_instance;
1742 struct rtl8169_private *tp = netdev_priv(dev);
1743 int boguscnt = max_interrupt_work;
1744 void *ioaddr = tp->mmio_addr;
1745 int status = 0;
1746 int handled = 0;
1747
1748 do {
1749 status = RTL_R16(IntrStatus);
1750
1751 /* hotplug/major error/no more work/shared irq */
1752 if ((status == 0xFFFF) || !status)
1753 break;
1754
1755 handled = 1;
1756
1757 status &= tp->intr_mask;
1758 RTL_W16(IntrStatus,
1759 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1760
1761 if (!(status & rtl8169_intr_mask))
1762 break;
1763
1764 if (status & LinkChg)
1765 rtl8169_check_link_status(dev, tp, ioaddr);
1766
1767 #ifdef CONFIG_R8169_NAPI
1768 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
1769 tp->intr_mask = ~rtl8169_napi_event;
1770
1771 if (likely(netif_rx_schedule_prep(dev)))
1772 __netif_rx_schedule(dev);
1773 else {
1774 printk(KERN_INFO "%s: interrupt %x taken in poll\n",
1775 dev->name, status);
1776 }
1777 break;
1778 #else
1779 // Rx interrupt
1780 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
1781 rtl8169_rx_interrupt(dev, tp, ioaddr);
1782 }
1783 // Tx interrupt
1784 if (status & (TxOK | TxErr))
1785 rtl8169_tx_interrupt(dev, tp, ioaddr);
1786 #endif
1787
1788 boguscnt--;
1789 } while (boguscnt > 0);
1790
1791 if (boguscnt <= 0) {
1792 printk(KERN_WARNING "%s: Too much work at interrupt!\n",
1793 dev->name);
1794 /* Clear all interrupt sources. */
1795 RTL_W16(IntrStatus, 0xffff);
1796 }
1797 return IRQ_RETVAL(handled);
1798 }
1799
1800 #ifdef CONFIG_R8169_NAPI
1801 static int rtl8169_poll(struct net_device *dev, int *budget)
1802 {
1803 unsigned int work_done, work_to_do = min(*budget, dev->quota);
1804 struct rtl8169_private *tp = netdev_priv(dev);
1805 void *ioaddr = tp->mmio_addr;
1806
1807 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
1808 rtl8169_tx_interrupt(dev, tp, ioaddr);
1809
1810 *budget -= work_done;
1811 dev->quota -= work_done;
1812
1813 if ((work_done < work_to_do) || !netif_running(dev)) {
1814 netif_rx_complete(dev);
1815 tp->intr_mask = 0xffff;
1816 /*
1817 * 20040426: the barrier is not strictly required but the
1818 * behavior of the irq handler could be less predictable
1819 * without it. Btw, the lack of flush for the posted pci
1820 * write is safe - FR
1821 */
1822 smp_wmb();
1823 RTL_W16(IntrMask, rtl8169_intr_mask);
1824 }
1825
1826 return (work_done >= work_to_do);
1827 }
1828 #endif
1829
1830 static int
1831 rtl8169_close(struct net_device *dev)
1832 {
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834 struct pci_dev *pdev = tp->pci_dev;
1835 void *ioaddr = tp->mmio_addr;
1836
1837 netif_stop_queue(dev);
1838
1839 rtl8169_delete_timer(dev);
1840
1841 spin_lock_irq(&tp->lock);
1842
1843 /* Stop the chip's Tx and Rx DMA processes. */
1844 RTL_W8(ChipCmd, 0x00);
1845
1846 /* Disable interrupts by clearing the interrupt mask. */
1847 RTL_W16(IntrMask, 0x0000);
1848
1849 /* Update the error counts. */
1850 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1851 RTL_W32(RxMissed, 0);
1852
1853 spin_unlock_irq(&tp->lock);
1854
1855 synchronize_irq(dev->irq);
1856 free_irq(dev->irq, dev);
1857
1858 rtl8169_tx_clear(tp);
1859
1860 rtl8169_rx_clear(tp);
1861
1862 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1863 tp->RxPhyAddr);
1864 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1865 tp->TxPhyAddr);
1866 tp->TxDescArray = NULL;
1867 tp->RxDescArray = NULL;
1868
1869 return 0;
1870 }
1871
1872 static void
1873 rtl8169_set_rx_mode(struct net_device *dev)
1874 {
1875 struct rtl8169_private *tp = netdev_priv(dev);
1876 void *ioaddr = tp->mmio_addr;
1877 unsigned long flags;
1878 u32 mc_filter[2]; /* Multicast hash filter */
1879 int i, rx_mode;
1880 u32 tmp = 0;
1881
1882 if (dev->flags & IFF_PROMISC) {
1883 /* Unconditionally log net taps. */
1884 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1885 dev->name);
1886 rx_mode =
1887 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1888 AcceptAllPhys;
1889 mc_filter[1] = mc_filter[0] = 0xffffffff;
1890 } else if ((dev->mc_count > multicast_filter_limit)
1891 || (dev->flags & IFF_ALLMULTI)) {
1892 /* Too many to filter perfectly -- accept all multicasts. */
1893 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1894 mc_filter[1] = mc_filter[0] = 0xffffffff;
1895 } else {
1896 struct dev_mc_list *mclist;
1897 rx_mode = AcceptBroadcast | AcceptMyPhys;
1898 mc_filter[1] = mc_filter[0] = 0;
1899 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1900 i++, mclist = mclist->next) {
1901 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1902 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1903 rx_mode |= AcceptMulticast;
1904 }
1905 }
1906
1907 spin_lock_irqsave(&tp->lock, flags);
1908
1909 tmp = rtl8169_rx_config | rx_mode |
1910 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1911
1912 RTL_W32(RxConfig, tmp);
1913 RTL_W32(MAR0 + 0, mc_filter[0]);
1914 RTL_W32(MAR0 + 4, mc_filter[1]);
1915
1916 spin_unlock_irqrestore(&tp->lock, flags);
1917 }
1918
1919 /**
1920 * rtl8169_get_stats - Get rtl8169 read/write statistics
1921 * @dev: The Ethernet Device to get statistics for
1922 *
1923 * Get TX/RX statistics for rtl8169
1924 */
1925 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
1926 {
1927 struct rtl8169_private *tp = netdev_priv(dev);
1928 void *ioaddr = tp->mmio_addr;
1929 unsigned long flags;
1930
1931 if (netif_running(dev)) {
1932 spin_lock_irqsave(&tp->lock, flags);
1933 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1934 RTL_W32(RxMissed, 0);
1935 spin_unlock_irqrestore(&tp->lock, flags);
1936 }
1937
1938 return &tp->stats;
1939 }
1940
1941 static struct pci_driver rtl8169_pci_driver = {
1942 .name = MODULENAME,
1943 .id_table = rtl8169_pci_tbl,
1944 .probe = rtl8169_init_one,
1945 .remove = __devexit_p(rtl8169_remove_one),
1946 #ifdef CONFIG_PM
1947 .suspend = rtl8169_suspend,
1948 .resume = rtl8169_resume,
1949 #endif
1950 };
1951
1952 static int __init
1953 rtl8169_init_module(void)
1954 {
1955 return pci_module_init(&rtl8169_pci_driver);
1956 }
1957
1958 static void __exit
1959 rtl8169_cleanup_module(void)
1960 {
1961 pci_unregister_driver(&rtl8169_pci_driver);
1962 }
1963
1964 module_init(rtl8169_init_module);
1965 module_exit(rtl8169_cleanup_module);
Historical 2.5/2.6 development