include/asm-ia64/spinlock.h

   1 #ifndef _ASM_IA64_SPINLOCK_H
   2 #define _ASM_IA64_SPINLOCK_H
   3
   4 /*
   5  * Copyright (C) 1998-2003 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   8  *
   9  * This file is used for SMP configurations only.
  10  */
  11
  12 #include <linux/compiler.h>
  13 #include <linux/kernel.h>
  14
  15 #include <asm/atomic.h>
  16 #include <asm/bitops.h>
  17 #include <asm/intrinsics.h>
  18 #include <asm/system.h>
  19
  20 typedef struct {
  21         volatile unsigned int lock;
  22 } spinlock_t;
  23
  24 #define SPIN_LOCK_UNLOCKED                      (spinlock_t) { 0 }
  25 #define spin_lock_init(x)                       ((x)->lock = 0)
  26
  27 /*
  28  * Try to get the lock.  If we fail to get the lock, make a non-standard call to
  29  * ia64_spinlock_contention().  We do not use a normal call because that would force all
  30  * callers of spin_lock() to be non-leaf routines.  Instead, ia64_spinlock_contention() is
  31  * carefully coded to touch only those registers that spin_lock() marks "clobbered".
  32  */
  33
  34 #define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "r28", "r29", "r30", "b6", "memory"
  35
  36 static inline void
  37 _raw_spin_lock (spinlock_t *lock)
  38 {
  39         register volatile unsigned int *ptr asm ("r31") = &lock->lock;
  40
  41 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 4)
  42 # ifdef CONFIG_ITANIUM
  43         /* don't use brl on Itanium... */
  44         asm volatile ("{\n\t"
  45                       "  mov ar.ccv = r0\n\t"
  46                       "  mov r28 = ip\n\t"
  47                       "  mov r30 = 1;;\n\t"
  48                       "}\n\t"
  49                       "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
  50                       "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
  51                       "cmp4.ne p14, p0 = r30, r0\n\t"
  52                       "mov b6 = r29;;\n"
  53                       "(p14) br.cond.spnt.many b6"
  54                       : "=r"(ptr) : "r"(ptr) : IA64_SPINLOCK_CLOBBERS);
  55 # else
  56         asm volatile ("{\n\t"
  57                       "  mov ar.ccv = r0\n\t"
  58                       "  mov r28 = ip\n\t"
  59                       "  mov r30 = 1;;\n\t"
  60                       "}\n\t"
  61                       "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
  62                       "cmp4.ne p14, p0 = r30, r0\n"
  63                       "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4"
  64                       : "=r"(ptr) : "r"(ptr) : IA64_SPINLOCK_CLOBBERS);
  65 # endif /* CONFIG_MCKINLEY */
  66 #else
  67 # ifdef CONFIG_ITANIUM
  68         /* don't use brl on Itanium... */
  69         /* mis-declare, so we get the entry-point, not it's function descriptor: */
  70         asm volatile ("mov r30 = 1\n\t"
  71                       "mov ar.ccv = r0;;\n\t"
  72                       "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
  73                       "movl r29 = ia64_spinlock_contention;;\n\t"
  74                       "cmp4.ne p14, p0 = r30, r0\n\t"
  75                       "mov b6 = r29;;\n"
  76                       "(p14) br.call.spnt.many b6 = b6"
  77                       : "=r"(ptr) : "r"(ptr) : IA64_SPINLOCK_CLOBBERS);
  78 # else
  79         asm volatile ("mov r30 = 1\n\t"
  80                       "mov ar.ccv = r0;;\n\t"
  81                       "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
  82                       "cmp4.ne p14, p0 = r30, r0\n\t"
  83                       "(p14) brl.call.spnt.many b6=ia64_spinlock_contention"
  84                       : "=r"(ptr) : "r"(ptr) : IA64_SPINLOCK_CLOBBERS);
  85 # endif /* CONFIG_MCKINLEY */
  86 #endif
  87 }
  88
  89 #define spin_is_locked(x)       ((x)->lock != 0)
  90 #define _raw_spin_unlock(x)     do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
  91 #define _raw_spin_trylock(x)    (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
  92 #define spin_unlock_wait(x)     do { barrier(); } while ((x)->lock)
  93
  94 typedef struct {
  95         volatile int read_counter       : 31;
  96         volatile int write_lock         :  1;
  97 } rwlock_t;
  98 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
  99
 100 #define rwlock_init(x)          do { *(x) = RW_LOCK_UNLOCKED; } while(0)
 101 #define rwlock_is_locked(x)     (*(volatile int *) (x) != 0)
 102
 103 #define _raw_read_lock(rw)                                                              \
 104 do {                                                                                    \
 105         rwlock_t *__read_lock_ptr = (rw);                                               \
 106                                                                                         \
 107         while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) {          \
 108                 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);                        \
 109                 while (*(volatile int *)__read_lock_ptr < 0)                            \
 110                         cpu_relax();                                                    \
 111         }                                                                               \
 112 } while (0)
 113
 114 #define _raw_read_unlock(rw)                                    \
 115 do {                                                            \
 116         rwlock_t *__read_lock_ptr = (rw);                       \
 117         ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);        \
 118 } while (0)
 119
 120 #define _raw_write_lock(rw)                                                     \
 121 do {                                                                            \
 122         __asm__ __volatile__ (                                                  \
 123                 "mov ar.ccv = r0\n"                                             \
 124                 "dep r29 = -1, r0, 31, 1\n"                                     \
 125                 ";;\n"                                                          \
 126                 "1:\n"                                                          \
 127                 "ld4 r2 = [%0]\n"                                               \
 128                 ";;\n"                                                          \
 129                 "cmp4.eq p0,p7 = r0,r2\n"                                       \
 130                 "(p7) br.cond.spnt.few 1b \n"                                   \
 131                 "cmpxchg4.acq r2 = [%0], r29, ar.ccv\n"                         \
 132                 ";;\n"                                                          \
 133                 "cmp4.eq p0,p7 = r0, r2\n"                                      \
 134                 "(p7) br.cond.spnt.few 1b\n"                                    \
 135                 ";;\n"                                                          \
 136                 :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory");            \
 137 } while(0)
 138
 139 #define _raw_write_trylock(rw)                                                  \
 140 ({                                                                              \
 141         register long result;                                                   \
 142                                                                                 \
 143         __asm__ __volatile__ (                                                  \
 144                 "mov ar.ccv = r0\n"                                             \
 145                 "dep r29 = -1, r0, 31, 1\n"                                     \
 146                 ";;\n"                                                          \
 147                 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n"                         \
 148                 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory");          \
 149         (result == 0);                                                          \
 150 })
 151
 152 #define _raw_write_unlock(x)                                                            \
 153 ({                                                                                      \
 154         smp_mb__before_clear_bit();     /* need barrier before releasing lock... */     \
 155         clear_bit(31, (x));                                                             \
 156 })
 157
 158 #endif /*  _ASM_IA64_SPINLOCK_H */