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[PATCH] V4L: Update the saa7146 driver
[linux-2.6/history.git] / drivers / media / common / saa7146_hlp.c
blobbdae7fab33a49f29e32e7945947ae1ea9b872601
1 #include <linux/kernel.h>
2 #include <media/saa7146_vv.h>
3
4 static void calculate_output_format_register(struct saa7146_dev* saa, u32 palette, u32* clip_format)
5 {
6 /* clear out the necessary bits */
7 *clip_format &= 0x0000ffff;
8 /* set these bits new */
9 *clip_format |= (( ((palette&0xf00)>>8) << 30) | ((palette&0x00f) << 24) | (((palette&0x0f0)>>4) << 16));
10 }
11
12 static void calculate_bcs_ctrl_register(struct saa7146_dev *dev, int brightness, int contrast, int colour, u32 *bcs_ctrl)
13 {
14 *bcs_ctrl = ((brightness << 24) | (contrast << 16) | (colour << 0));
15 }
16
17 static void calculate_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync, u32* hps_ctrl)
18 {
19 *hps_ctrl &= ~(MASK_30 | MASK_31 | MASK_28);
20 *hps_ctrl |= (source << 30) | (sync << 28);
21 }
22
23 static void calculate_hxo_and_hyo(struct saa7146_vv *vv, u32* hps_h_scale, u32* hps_ctrl)
24 {
25 int hyo = 0, hxo = 0;
26
27 hyo = vv->standard->v_offset;
28 hxo = vv->standard->h_offset;
29
30 *hps_h_scale &= ~(MASK_B0 | 0xf00);
31 *hps_h_scale |= (hxo << 0);
32
33 *hps_ctrl &= ~(MASK_W0 | MASK_B2);
34 *hps_ctrl |= (hyo << 12);
35 }
36
37 /* helper functions for the calculation of the horizontal- and vertical
38 scaling registers, clip-format-register etc ...
39 these functions take pointers to the (most-likely read-out
40 original-values) and manipulate them according to the requested
41 changes.
42 */
43
44 /* hps_coeff used for CXY and CXUV; scale 1/1 -> scale 1/64 */
45 static struct {
46 u16 hps_coeff;
47 u16 weight_sum;
48 } hps_h_coeff_tab [] = {
49 {0x00, 2}, {0x02, 4}, {0x00, 4}, {0x06, 8}, {0x02, 8},
50 {0x08, 8}, {0x00, 8}, {0x1E, 16}, {0x0E, 8}, {0x26, 8},
51 {0x06, 8}, {0x42, 8}, {0x02, 8}, {0x80, 8}, {0x00, 8},
52 {0xFE, 16}, {0xFE, 8}, {0x7E, 8}, {0x7E, 8}, {0x3E, 8},
53 {0x3E, 8}, {0x1E, 8}, {0x1E, 8}, {0x0E, 8}, {0x0E, 8},
54 {0x06, 8}, {0x06, 8}, {0x02, 8}, {0x02, 8}, {0x00, 8},
55 {0x00, 8}, {0xFE, 16}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8},
56 {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8},
57 {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8},
58 {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0x7E, 8},
59 {0x7E, 8}, {0x3E, 8}, {0x3E, 8}, {0x1E, 8}, {0x1E, 8},
60 {0x0E, 8}, {0x0E, 8}, {0x06, 8}, {0x06, 8}, {0x02, 8},
61 {0x02, 8}, {0x00, 8}, {0x00, 8}, {0xFE, 16}
62 };
63
64 /* table of attenuation values for horizontal scaling */
65 u8 h_attenuation[] = { 1, 2, 4, 8, 2, 4, 8, 16, 0};
66
67 /* calculate horizontal scale registers */
68 static int calculate_h_scale_registers(struct saa7146_dev *dev,
69 int in_x, int out_x, int flip_lr,
70 u32* hps_ctrl, u32* hps_v_gain, u32* hps_h_prescale, u32* hps_h_scale)
71 {
72 /* horizontal prescaler */
73 u32 dcgx = 0, xpsc = 0, xacm = 0, cxy = 0, cxuv = 0;
74 /* horizontal scaler */
75 u32 xim = 0, xp = 0, xsci =0;
76 /* vertical scale & gain */
77 u32 pfuv = 0;
78
79 /* helper variables */
80 u32 h_atten = 0, i = 0;
81
82 if ( 0 == out_x ) {
83 return -EINVAL;
84 }
85
86 /* mask out vanity-bit */
87 *hps_ctrl &= ~MASK_29;
88
89 /* calculate prescale-(xspc)-value: [n .. 1/2) : 1
90 [1/2 .. 1/3) : 2
91 [1/3 .. 1/4) : 3
92 ... */
93 if (in_x > out_x) {
94 xpsc = in_x / out_x;
95 }
96 else {
97 /* zooming */
98 xpsc = 1;
99 }
100
101 /* if flip_lr-bit is set, number of pixels after
102 horizontal prescaling must be < 384 */
103 if ( 0 != flip_lr ) {
104
105 /* set vanity bit */
106 *hps_ctrl |= MASK_29;
107
108 while (in_x / xpsc >= 384 )
109 xpsc++;
110 }
111 /* if zooming is wanted, number of pixels after
112 horizontal prescaling must be < 768 */
113 else {
114 while ( in_x / xpsc >= 768 )
115 xpsc++;
116 }
117
118 /* maximum prescale is 64 (p.69) */
119 if ( xpsc > 64 )
120 xpsc = 64;
121
122 /* keep xacm clear*/
123 xacm = 0;
124
125 /* set horizontal filter parameters (CXY = CXUV) */
126 cxy = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].hps_coeff;
127 cxuv = cxy;
128
129 /* calculate and set horizontal fine scale (xsci) */
130
131 /* bypass the horizontal scaler ? */
132 if ( (in_x == out_x) && ( 1 == xpsc ) )
133 xsci = 0x400;
134 else
135 xsci = ( (1024 * in_x) / (out_x * xpsc) ) + xpsc;
136
137 /* set start phase for horizontal fine scale (xp) to 0 */
138 xp = 0;
139
140 /* set xim, if we bypass the horizontal scaler */
141 if ( 0x400 == xsci )
142 xim = 1;
143 else
144 xim = 0;
145
146 /* if the prescaler is bypassed, enable horizontal
147 accumulation mode (xacm) and clear dcgx */
148 if( 1 == xpsc ) {
149 xacm = 1;
150 dcgx = 0;
151 } else {
152 xacm = 0;
153 /* get best match in the table of attenuations
154 for horizontal scaling */
155 h_atten = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].weight_sum;
156
157 for (i = 0; h_attenuation[i] != 0; i++) {
158 if (h_attenuation[i] >= h_atten)
159 break;
160 }
161
162 dcgx = i;
163 }
164
165 /* the horizontal scaling increment controls the UV filter
166 to reduce the bandwith to improve the display quality,
167 so set it ... */
168 if ( xsci == 0x400)
169 pfuv = 0x00;
170 else if ( xsci < 0x600)
171 pfuv = 0x01;
172 else if ( xsci < 0x680)
173 pfuv = 0x11;
174 else if ( xsci < 0x700)
175 pfuv = 0x22;
176 else
177 pfuv = 0x33;
178
179
180 *hps_v_gain &= MASK_W0|MASK_B2;
181 *hps_v_gain |= (pfuv << 24);
182
183 *hps_h_scale &= ~(MASK_W1 | 0xf000);
184 *hps_h_scale |= (xim << 31) | (xp << 24) | (xsci << 12);
185
186 *hps_h_prescale |= (dcgx << 27) | ((xpsc-1) << 18) | (xacm << 17) | (cxy << 8) | (cxuv << 0);
187
188 return 0;
189 }
190
191 static struct {
192 u16 hps_coeff;
193 u16 weight_sum;
194 } hps_v_coeff_tab [] = {
195 {0x0100, 2}, {0x0102, 4}, {0x0300, 4}, {0x0106, 8}, {0x0502, 8},
196 {0x0708, 8}, {0x0F00, 8}, {0x011E, 16}, {0x110E, 16}, {0x1926, 16},
197 {0x3906, 16}, {0x3D42, 16}, {0x7D02, 16}, {0x7F80, 16}, {0xFF00, 16},
198 {0x01FE, 32}, {0x01FE, 32}, {0x817E, 32}, {0x817E, 32}, {0xC13E, 32},
199 {0xC13E, 32}, {0xE11E, 32}, {0xE11E, 32}, {0xF10E, 32}, {0xF10E, 32},
200 {0xF906, 32}, {0xF906, 32}, {0xFD02, 32}, {0xFD02, 32}, {0xFF00, 32},
201 {0xFF00, 32}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64},
202 {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64},
203 {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64},
204 {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x817E, 64},
205 {0x817E, 64}, {0xC13E, 64}, {0xC13E, 64}, {0xE11E, 64}, {0xE11E, 64},
206 {0xF10E, 64}, {0xF10E, 64}, {0xF906, 64}, {0xF906, 64}, {0xFD02, 64},
207 {0xFD02, 64}, {0xFF00, 64}, {0xFF00, 64}, {0x01FE, 128}
208 };
209
210 /* table of attenuation values for vertical scaling */
211 u16 v_attenuation[] = { 2, 4, 8, 16, 32, 64, 128, 256, 0};
212
213 /* calculate vertical scale registers */
214 static int calculate_v_scale_registers(struct saa7146_dev *dev, enum v4l2_field field,
215 int in_y, int out_y, u32* hps_v_scale, u32* hps_v_gain)
216 {
217 int lpi = 0;
218
219 /* vertical scaling */
220 u32 yacm = 0, ysci = 0, yacl = 0, ypo = 0, ype = 0;
221 /* vertical scale & gain */
222 u32 dcgy = 0, cya_cyb = 0;
223
224 /* helper variables */
225 u32 v_atten = 0, i = 0;
226
227 /* error, if vertical zooming */
228 if ( in_y < out_y ) {
229 return -EINVAL;
230 }
231
232 /* linear phase interpolation may be used
233 if scaling is between 1 and 1/2 (both fields used)
234 or scaling is between 1/2 and 1/4 (if only one field is used) */
235
236 if (V4L2_FIELD_HAS_BOTH(field)) {
237 if( 2*out_y >= in_y) {
238 lpi = 1;
239 }
240 } else if (field == V4L2_FIELD_TOP
241 || field == V4L2_FIELD_ALTERNATE
242 || field == V4L2_FIELD_BOTTOM) {
243 if( 4*out_y >= in_y ) {
244 lpi = 1;
245 }
246 out_y *= 2;
247 }
248 if( 0 != lpi ) {
249
250 yacm = 0;
251 yacl = 0;
252 cya_cyb = 0x00ff;
253
254 /* calculate scaling increment */
255 if ( in_y > out_y )
256 ysci = ((1024 * in_y) / (out_y + 1)) - 1024;
257 else
258 ysci = 0;
259
260 dcgy = 0;
261
262 /* calculate ype and ypo */
263 ype = ysci / 16;
264 ypo = ype + (ysci / 64);
265
266 } else {
267 yacm = 1;
268
269 /* calculate scaling increment */
270 ysci = (((10 * 1024 * (in_y - out_y - 1)) / in_y) + 9) / 10;
271
272 /* calculate ype and ypo */
273 ypo = ype = ((ysci + 15) / 16);
274
275 /* the sequence length interval (yacl) has to be set according
276 to the prescale value, e.g. [n .. 1/2) : 0
277 [1/2 .. 1/3) : 1
278 [1/3 .. 1/4) : 2
279 ... */
280 if ( ysci < 512) {
281 yacl = 0;
282 } else {
283 yacl = ( ysci / (1024 - ysci) );
284 }
285
286 /* get filter coefficients for cya, cyb from table hps_v_coeff_tab */
287 cya_cyb = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].hps_coeff;
288
289 /* get best match in the table of attenuations for vertical scaling */
290 v_atten = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].weight_sum;
291
292 for (i = 0; v_attenuation[i] != 0; i++) {
293 if (v_attenuation[i] >= v_atten)
294 break;
295 }
296
297 dcgy = i;
298 }
299
300 /* ypo and ype swapped in spec ? */
301 *hps_v_scale |= (yacm << 31) | (ysci << 21) | (yacl << 15) | (ypo << 8 ) | (ype << 1);
302
303 *hps_v_gain &= ~(MASK_W0|MASK_B2);
304 *hps_v_gain |= (dcgy << 16) | (cya_cyb << 0);
305
306 return 0;
307 }
308
309 /* simple bubble-sort algorithm with duplicate elimination */
310 static int sort_and_eliminate(u32* values, int* count)
311 {
312 int low = 0, high = 0, top = 0, temp = 0;
313 int cur = 0, next = 0;
314
315 /* sanity checks */
316 if( (0 > *count) || (NULL == values) ) {
317 return -EINVAL;
318 }
319
320 /* bubble sort the first ´count´ items of the array ´values´ */
321 for( top = *count; top > 0; top--) {
322 for( low = 0, high = 1; high < top; low++, high++) {
323 if( values[low] > values[high] ) {
324 temp = values[low];
325 values[low] = values[high];
326 values[high] = temp;
327 }
328 }
329 }
330
331 /* remove duplicate items */
332 for( cur = 0, next = 1; next < *count; next++) {
333 if( values[cur] != values[next])
334 values[++cur] = values[next];
335 }
336
337 *count = cur + 1;
338
339 return 0;
340 }
341
342 static void calculate_clipping_registers_rect(struct saa7146_dev *dev, struct saa7146_fh *fh,
343 struct saa7146_video_dma *vdma2, u32* clip_format, u32* arbtr_ctrl, enum v4l2_field field)
344 {
345 struct saa7146_vv *vv = dev->vv_data;
346 u32 *clipping = vv->d_clipping.cpu_addr;
347
348 int width = fh->ov.win.w.width;
349 int height = fh->ov.win.w.height;
350 int clipcount = fh->ov.nclips;
351
352 u32 line_list[32];
353 u32 pixel_list[32];
354 int numdwords = 0;
355
356 int i = 0, j = 0;
357 int cnt_line = 0, cnt_pixel = 0;
358
359 int x[32], y[32], w[32], h[32];
360
361 /* clear out memory */
362 memset(&line_list[0], 0x00, sizeof(u32)*32);
363 memset(&pixel_list[0], 0x00, sizeof(u32)*32);
364 memset(clipping, 0x00, SAA7146_CLIPPING_MEM);
365
366 /* fill the line and pixel-lists */
367 for(i = 0; i < clipcount; i++) {
368 int l = 0, r = 0, t = 0, b = 0;
369
370 x[i] = fh->ov.clips[i].c.left;
371 y[i] = fh->ov.clips[i].c.top;
372 w[i] = fh->ov.clips[i].c.width;
373 h[i] = fh->ov.clips[i].c.height;
374
375 if( w[i] < 0) {
376 x[i] += w[i]; w[i] = -w[i];
377 }
378 if( h[i] < 0) {
379 y[i] += h[i]; h[i] = -h[i];
380 }
381 if( x[i] < 0) {
382 w[i] += x[i]; x[i] = 0;
383 }
384 if( y[i] < 0) {
385 h[i] += y[i]; y[i] = 0;
386 }
387 if( 0 != vv->vflip ) {
388 y[i] = height - y[i] - h[i];
389 }
390
391 l = x[i];
392 r = x[i]+w[i];
393 t = y[i];
394 b = y[i]+h[i];
395
396 /* insert left/right coordinates */
397 pixel_list[ 2*i ] = min_t(int, l, width);
398 pixel_list[(2*i)+1] = min_t(int, r, width);
399 /* insert top/bottom coordinates */
400 line_list[ 2*i ] = min_t(int, t, height);
401 line_list[(2*i)+1] = min_t(int, b, height);
402 }
403
404 /* sort and eliminate lists */
405 cnt_line = cnt_pixel = 2*clipcount;
406 sort_and_eliminate( &pixel_list[0], &cnt_pixel );
407 sort_and_eliminate( &line_list[0], &cnt_line );
408
409 /* calculate the number of used u32s */
410 numdwords = max_t(int, (cnt_line+1), (cnt_pixel+1))*2;
411 numdwords = max_t(int, 4, numdwords);
412 numdwords = min_t(int, 64, numdwords);
413
414 /* fill up cliptable */
415 for(i = 0; i < cnt_pixel; i++) {
416 clipping[2*i] |= (pixel_list[i] << 16);
417 }
418 for(i = 0; i < cnt_line; i++) {
419 clipping[(2*i)+1] |= (line_list[i] << 16);
420 }
421
422 /* fill up cliptable with the display infos */
423 for(j = 0; j < clipcount; j++) {
424
425 for(i = 0; i < cnt_pixel; i++) {
426
427 if( x[j] < 0)
428 x[j] = 0;
429
430 if( pixel_list[i] < (x[j] + w[j])) {
431
432 if ( pixel_list[i] >= x[j] ) {
433 clipping[2*i] |= (1 << j);
434 }
435 }
436 }
437 for(i = 0; i < cnt_line; i++) {
438
439 if( y[j] < 0)
440 y[j] = 0;
441
442 if( line_list[i] < (y[j] + h[j]) ) {
443
444 if( line_list[i] >= y[j] ) {
445 clipping[(2*i)+1] |= (1 << j);
446 }
447 }
448 }
449 }
450
451 /* adjust arbitration control register */
452 *arbtr_ctrl &= 0xffff00ff;
453 *arbtr_ctrl |= 0x00001c00;
454
455 vdma2->base_even = vv->d_clipping.dma_handle;
456 vdma2->base_odd = vv->d_clipping.dma_handle;
457 vdma2->prot_addr = vv->d_clipping.dma_handle+((sizeof(u32))*(numdwords));
458 vdma2->base_page = 0x04;
459 vdma2->pitch = 0x00;
460 vdma2->num_line_byte = (0 << 16 | (sizeof(u32))*(numdwords-1) );
461
462 /* set clipping-mode. this depends on the field(s) used */
463 *clip_format &= 0xfffffff7;
464 if (V4L2_FIELD_HAS_BOTH(field)) {
465 *clip_format |= 0x00000008;
466 } else {
467 *clip_format |= 0x00000000;
468 }
469 }
470
471 /* disable clipping */
472 static void saa7146_disable_clipping(struct saa7146_dev *dev)
473 {
474 u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
475
476 /* mask out relevant bits (=lower word)*/
477 clip_format &= MASK_W1;
478
479 /* upload clipping-registers*/
480 saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
481 saa7146_write(dev, MC2, (MASK_05 | MASK_21));
482
483 /* disable video dma2 */
484 saa7146_write(dev, MC1, MASK_21);
485 }
486
487 static void saa7146_set_clipping_rect(struct saa7146_fh *fh)
488 {
489 struct saa7146_dev *dev = fh->dev;
490 enum v4l2_field field = fh->ov.win.field;
491 struct saa7146_video_dma vdma2;
492 u32 clip_format;
493 u32 arbtr_ctrl;
494
495 /* check clipcount, disable clipping if clipcount == 0*/
496 if( fh->ov.nclips == 0 ) {
497 saa7146_disable_clipping(dev);
498 return;
499 }
500
501 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
502 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
503
504 calculate_clipping_registers_rect(dev, fh, &vdma2, &clip_format, &arbtr_ctrl, field);
505
506 /* set clipping format */
507 clip_format &= 0xffff0008;
508 clip_format |= (SAA7146_CLIPPING_RECT << 4);
509
510 /* prepare video dma2 */
511 saa7146_write(dev, BASE_EVEN2, vdma2.base_even);
512 saa7146_write(dev, BASE_ODD2, vdma2.base_odd);
513 saa7146_write(dev, PROT_ADDR2, vdma2.prot_addr);
514 saa7146_write(dev, BASE_PAGE2, vdma2.base_page);
515 saa7146_write(dev, PITCH2, vdma2.pitch);
516 saa7146_write(dev, NUM_LINE_BYTE2, vdma2.num_line_byte);
517
518 /* prepare the rest */
519 saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
520 saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
521
522 /* upload clip_control-register, clipping-registers, enable video dma2 */
523 saa7146_write(dev, MC2, (MASK_05 | MASK_21 | MASK_03 | MASK_19));
524 saa7146_write(dev, MC1, (MASK_05 | MASK_21));
525 }
526
527 static void saa7146_set_window(struct saa7146_dev *dev, int width, int height, enum v4l2_field field)
528 {
529 struct saa7146_vv *vv = dev->vv_data;
530
531 int source = vv->current_hps_source;
532 int sync = vv->current_hps_sync;
533
534 u32 hps_v_scale = 0, hps_v_gain = 0, hps_ctrl = 0, hps_h_prescale = 0, hps_h_scale = 0;
535
536 /* set vertical scale */
537 hps_v_scale = 0; /* all bits get set by the function-call */
538 hps_v_gain = 0; /* fixme: saa7146_read(dev, HPS_V_GAIN);*/
539 calculate_v_scale_registers(dev, field, vv->standard->v_field*2, height, &hps_v_scale, &hps_v_gain);
540
541 /* set horizontal scale */
542 hps_ctrl = 0;
543 hps_h_prescale = 0; /* all bits get set in the function */
544 hps_h_scale = 0;
545 calculate_h_scale_registers(dev, vv->standard->h_pixels, width, vv->hflip, &hps_ctrl, &hps_v_gain, &hps_h_prescale, &hps_h_scale);
546
547 /* set hyo and hxo */
548 calculate_hxo_and_hyo(vv, &hps_h_scale, &hps_ctrl);
549 calculate_hps_source_and_sync(dev, source, sync, &hps_ctrl);
550
551 /* write out new register contents */
552 saa7146_write(dev, HPS_V_SCALE, hps_v_scale);
553 saa7146_write(dev, HPS_V_GAIN, hps_v_gain);
554 saa7146_write(dev, HPS_CTRL, hps_ctrl);
555 saa7146_write(dev, HPS_H_PRESCALE,hps_h_prescale);
556 saa7146_write(dev, HPS_H_SCALE, hps_h_scale);
557
558 /* upload shadow-ram registers */
559 saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) );
560 }
561
562 /* calculate the new memory offsets for a desired position */
563 static void saa7146_set_position(struct saa7146_dev *dev, int w_x, int w_y, int w_height, enum v4l2_field field)
564 {
565 struct saa7146_vv *vv = dev->vv_data;
566
567 int b_depth = vv->ov_fmt->depth;
568 int b_bpl = vv->ov_fb.fmt.bytesperline;
569 u32 base = (u32)vv->ov_fb.base;
570
571 struct saa7146_video_dma vdma1;
572
573 /* calculate memory offsets for picture, look if we shall top-down-flip */
574 vdma1.pitch = 2*b_bpl;
575 if ( 0 == vv->vflip ) {
576 vdma1.base_even = (u32)base + (w_y * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
577 vdma1.base_odd = vdma1.base_even + (vdma1.pitch / 2);
578 vdma1.prot_addr = vdma1.base_even + (w_height * (vdma1.pitch / 2));
579 }
580 else {
581 vdma1.base_even = (u32)base + ((w_y+w_height) * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
582 vdma1.base_odd = vdma1.base_even - (vdma1.pitch / 2);
583 vdma1.prot_addr = vdma1.base_odd - (w_height * (vdma1.pitch / 2));
584 }
585
586 if (V4L2_FIELD_HAS_BOTH(field)) {
587 } else if (field == V4L2_FIELD_ALTERNATE) {
588 /* fixme */
589 vdma1.base_odd = vdma1.prot_addr;
590 vdma1.pitch /= 2;
591 } else if (field == V4L2_FIELD_TOP) {
592 vdma1.base_odd = vdma1.prot_addr;
593 vdma1.pitch /= 2;
594 } else if (field == V4L2_FIELD_BOTTOM) {
595 vdma1.base_odd = vdma1.base_even;
596 vdma1.base_even = vdma1.prot_addr;
597 vdma1.pitch /= 2;
598 }
599
600 if ( 0 != vv->vflip ) {
601 vdma1.pitch *= -1;
602 }
603
604 vdma1.base_page = 0;
605 vdma1.num_line_byte = (vv->standard->v_field<<16)+vv->standard->h_pixels;
606
607 saa7146_write_out_dma(dev, 1, &vdma1);
608 }
609
610 static void saa7146_set_output_format(struct saa7146_dev *dev, unsigned long palette)
611 {
612 u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
613
614 /* call helper function */
615 calculate_output_format_register(dev,palette,&clip_format);
616
617 /* update the hps registers */
618 saa7146_write(dev, CLIP_FORMAT_CTRL, clip_format);
619 saa7146_write(dev, MC2, (MASK_05 | MASK_21));
620 }
621
622 void saa7146_set_picture_prop(struct saa7146_dev *dev, int brightness, int contrast, int colour)
623 {
624 u32 bcs_ctrl = 0;
625
626 calculate_bcs_ctrl_register(dev, brightness, contrast, colour, &bcs_ctrl);
627 saa7146_write(dev, BCS_CTRL, bcs_ctrl);
628
629 /* update the bcs register */
630 saa7146_write(dev, MC2, (MASK_06 | MASK_22));
631 }
632
633
634 /* select input-source */
635 void saa7146_set_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync)
636 {
637 struct saa7146_vv *vv = dev->vv_data;
638 u32 hps_ctrl = 0;
639
640 /* read old state */
641 hps_ctrl = saa7146_read(dev, HPS_CTRL);
642
643 hps_ctrl &= ~( MASK_31 | MASK_30 | MASK_28 );
644 hps_ctrl |= (source << 30) | (sync << 28);
645
646 /* write back & upload register */
647 saa7146_write(dev, HPS_CTRL, hps_ctrl);
648 saa7146_write(dev, MC2, (MASK_05 | MASK_21));
649
650 vv->current_hps_source = source;
651 vv->current_hps_sync = sync;
652 }
653
654 int saa7146_enable_overlay(struct saa7146_fh *fh)
655 {
656 struct saa7146_dev *dev = fh->dev;
657 struct saa7146_vv *vv = dev->vv_data;
658
659 saa7146_set_window(dev, fh->ov.win.w.width, fh->ov.win.w.height, fh->ov.win.field);
660 saa7146_set_position(dev, fh->ov.win.w.left, fh->ov.win.w.top, fh->ov.win.w.height, fh->ov.win.field);
661 saa7146_set_output_format(dev, vv->ov_fmt->trans);
662 saa7146_set_clipping_rect(fh);
663
664 /* enable video dma1 */
665 saa7146_write(dev, MC1, (MASK_06 | MASK_22));
666 return 0;
667 }
668
669 void saa7146_disable_overlay(struct saa7146_fh *fh)
670 {
671 struct saa7146_dev *dev = fh->dev;
672
673 /* disable clipping + video dma1 */
674 saa7146_disable_clipping(dev);
675 saa7146_write(dev, MC1, MASK_22);
676 }
677
678 void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma)
679 {
680 int where = 0;
681
682 if( which < 1 || which > 3) {
683 return;
684 }
685
686 /* calculate starting address */
687 where = (which-1)*0x18;
688
689 saa7146_write(dev, where, vdma->base_odd);
690 saa7146_write(dev, where+0x04, vdma->base_even);
691 saa7146_write(dev, where+0x08, vdma->prot_addr);
692 saa7146_write(dev, where+0x0c, vdma->pitch);
693 saa7146_write(dev, where+0x10, vdma->base_page);
694 saa7146_write(dev, where+0x14, vdma->num_line_byte);
695
696 /* upload */
697 saa7146_write(dev, MC2, (MASK_02<<(which-1))|(MASK_18<<(which-1)));
698 /*
699 printk("vdma%d.base_even: 0x%08x\n", which,vdma->base_even);
700 printk("vdma%d.base_odd: 0x%08x\n", which,vdma->base_odd);
701 printk("vdma%d.prot_addr: 0x%08x\n", which,vdma->prot_addr);
702 printk("vdma%d.base_page: 0x%08x\n", which,vdma->base_page);
703 printk("vdma%d.pitch: 0x%08x\n", which,vdma->pitch);
704 printk("vdma%d.num_line_byte: 0x%08x\n", which,vdma->num_line_byte);
705 */
706 }
707 static int calculate_video_dma_grab_packed(struct saa7146_dev* dev, struct saa7146_buf *buf)
708 {
709 struct saa7146_vv *vv = dev->vv_data;
710 struct saa7146_video_dma vdma1;
711
712 struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
713
714 int width = buf->fmt->width;
715 int height = buf->fmt->height;
716 int bytesperline = buf->fmt->bytesperline;
717 enum v4l2_field field = buf->fmt->field;
718
719 int depth = sfmt->depth;
720
721 DEB_CAP(("[size=%dx%d,fields=%s]\n",
722 width,height,v4l2_field_names[field]));
723
724 if( bytesperline != 0) {
725 vdma1.pitch = bytesperline*2;
726 } else {
727 vdma1.pitch = (width*depth*2)/8;
728 }
729 vdma1.num_line_byte = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
730 vdma1.base_page = buf->pt[0].dma | ME1;
731
732 if( 0 != vv->vflip ) {
733 vdma1.prot_addr = buf->pt[0].offset;
734 vdma1.base_even = buf->pt[0].offset+(vdma1.pitch/2)*height;
735 vdma1.base_odd = vdma1.base_even - (vdma1.pitch/2);
736 } else {
737 vdma1.base_even = buf->pt[0].offset;
738 vdma1.base_odd = vdma1.base_even + (vdma1.pitch/2);
739 vdma1.prot_addr = buf->pt[0].offset+(vdma1.pitch/2)*height;
740 }
741
742 if (V4L2_FIELD_HAS_BOTH(field)) {
743 } else if (field == V4L2_FIELD_ALTERNATE) {
744 /* fixme */
745 if ( vv->last_field == V4L2_FIELD_TOP ) {
746 vdma1.base_odd = vdma1.prot_addr;
747 vdma1.pitch /= 2;
748 } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
749 vdma1.base_odd = vdma1.base_even;
750 vdma1.base_even = vdma1.prot_addr;
751 vdma1.pitch /= 2;
752 }
753 } else if (field == V4L2_FIELD_TOP) {
754 vdma1.base_odd = vdma1.prot_addr;
755 vdma1.pitch /= 2;
756 } else if (field == V4L2_FIELD_BOTTOM) {
757 vdma1.base_odd = vdma1.base_even;
758 vdma1.base_even = vdma1.prot_addr;
759 vdma1.pitch /= 2;
760 }
761
762 if( 0 != vv->vflip ) {
763 vdma1.pitch *= -1;
764 }
765
766 saa7146_write_out_dma(dev, 1, &vdma1);
767 return 0;
768 }
769
770 static int calc_planar_422(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
771 {
772 int height = buf->fmt->height;
773 int width = buf->fmt->width;
774
775 vdma2->pitch = width;
776 vdma3->pitch = width;
777
778 /* fixme: look at bytesperline! */
779
780 if( 0 != vv->vflip ) {
781 vdma2->prot_addr = buf->pt[1].offset;
782 vdma2->base_even = ((vdma2->pitch/2)*height)+buf->pt[1].offset;
783 vdma2->base_odd = vdma2->base_even - (vdma2->pitch/2);
784
785 vdma3->prot_addr = buf->pt[2].offset;
786 vdma3->base_even = ((vdma3->pitch/2)*height)+buf->pt[2].offset;
787 vdma3->base_odd = vdma3->base_even - (vdma3->pitch/2);
788
789 } else {
790 vdma3->base_even = buf->pt[2].offset;
791 vdma3->base_odd = vdma3->base_even + (vdma3->pitch/2);
792 vdma3->prot_addr = (vdma3->pitch/2)*height+buf->pt[2].offset;
793
794 vdma2->base_even = buf->pt[1].offset;
795 vdma2->base_odd = vdma2->base_even + (vdma2->pitch/2);
796 vdma2->prot_addr = (vdma2->pitch/2)*height+buf->pt[1].offset;
797 }
798
799 return 0;
800 }
801
802 static int calc_planar_420(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
803 {
804 int height = buf->fmt->height;
805 int width = buf->fmt->width;
806
807 vdma2->pitch = width/2;
808 vdma3->pitch = width/2;
809
810 if( 0 != vv->vflip ) {
811 vdma2->prot_addr = buf->pt[2].offset;
812 vdma2->base_even = ((vdma2->pitch/2)*height)+buf->pt[2].offset;
813 vdma2->base_odd = vdma2->base_even - (vdma2->pitch/2);
814
815 vdma3->prot_addr = buf->pt[1].offset;
816 vdma3->base_even = ((vdma3->pitch/2)*height)+buf->pt[1].offset;
817 vdma3->base_odd = vdma3->base_even - (vdma3->pitch/2);
818
819 } else {
820 vdma3->base_even = buf->pt[2].offset;
821 vdma3->base_odd = vdma3->base_even + (vdma3->pitch);
822 vdma3->prot_addr = (vdma3->pitch/2)*height+buf->pt[2].offset;
823
824 vdma2->base_even = buf->pt[1].offset;
825 vdma2->base_odd = vdma2->base_even + (vdma2->pitch);
826 vdma2->prot_addr = (vdma2->pitch/2)*height+buf->pt[1].offset;
827 }
828 return 0;
829 }
830
831
832 static int calculate_video_dma_grab_planar(struct saa7146_dev* dev, struct saa7146_buf *buf)
833 {
834 struct saa7146_vv *vv = dev->vv_data;
835 struct saa7146_video_dma vdma1;
836 struct saa7146_video_dma vdma2;
837 struct saa7146_video_dma vdma3;
838
839 struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
840
841 int width = buf->fmt->width;
842 int height = buf->fmt->height;
843 enum v4l2_field field = buf->fmt->field;
844
845 BUG_ON(0 == buf->pt[0].dma);
846 BUG_ON(0 == buf->pt[1].dma);
847 BUG_ON(0 == buf->pt[2].dma);
848
849 DEB_CAP(("[size=%dx%d,fields=%s]\n",
850 width,height,v4l2_field_names[field]));
851
852 /* fixme: look at bytesperline! */
853
854 /* fixme: what happens for user space buffers here?. The offsets are
855 most likely wrong, this version here only works for page-aligned
856 buffers, modifications to the pagetable-functions are necessary...*/
857
858 vdma1.pitch = width*2;
859 vdma1.num_line_byte = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
860 vdma1.base_page = buf->pt[0].dma | ME1;
861
862 if( 0 != vv->vflip ) {
863 vdma1.prot_addr = buf->pt[0].offset;
864 vdma1.base_even = ((vdma1.pitch/2)*height)+buf->pt[0].offset;
865 vdma1.base_odd = vdma1.base_even - (vdma1.pitch/2);
866 } else {
867 vdma1.base_even = buf->pt[0].offset;
868 vdma1.base_odd = vdma1.base_even + (vdma1.pitch/2);
869 vdma1.prot_addr = (vdma1.pitch/2)*height+buf->pt[0].offset;
870 }
871
872 vdma2.num_line_byte = 0; /* unused */
873 vdma2.base_page = buf->pt[1].dma | ME1;
874
875 vdma3.num_line_byte = 0; /* unused */
876 vdma3.base_page = buf->pt[2].dma | ME1;
877
878 switch( sfmt->depth ) {
879 case 12: {
880 calc_planar_420(vv,buf,&vdma2,&vdma3);
881 break;
882 }
883 case 16: {
884 calc_planar_422(vv,buf,&vdma2,&vdma3);
885 break;
886 }
887 default: {
888 return -1;
889 }
890 }
891
892 if (V4L2_FIELD_HAS_BOTH(field)) {
893 } else if (field == V4L2_FIELD_ALTERNATE) {
894 /* fixme */
895 vdma1.base_odd = vdma1.prot_addr;
896 vdma1.pitch /= 2;
897 vdma2.base_odd = vdma2.prot_addr;
898 vdma2.pitch /= 2;
899 vdma3.base_odd = vdma3.prot_addr;
900 vdma3.pitch /= 2;
901 } else if (field == V4L2_FIELD_TOP) {
902 vdma1.base_odd = vdma1.prot_addr;
903 vdma1.pitch /= 2;
904 vdma2.base_odd = vdma2.prot_addr;
905 vdma2.pitch /= 2;
906 vdma3.base_odd = vdma3.prot_addr;
907 vdma3.pitch /= 2;
908 } else if (field == V4L2_FIELD_BOTTOM) {
909 vdma1.base_odd = vdma1.base_even;
910 vdma1.base_even = vdma1.prot_addr;
911 vdma1.pitch /= 2;
912 vdma2.base_odd = vdma2.base_even;
913 vdma2.base_even = vdma2.prot_addr;
914 vdma2.pitch /= 2;
915 vdma3.base_odd = vdma3.base_even;
916 vdma3.base_even = vdma3.prot_addr;
917 vdma3.pitch /= 2;
918 }
919
920 if( 0 != vv->vflip ) {
921 vdma1.pitch *= -1;
922 vdma2.pitch *= -1;
923 vdma3.pitch *= -1;
924 }
925
926 saa7146_write_out_dma(dev, 1, &vdma1);
927 if( (sfmt->flags & FORMAT_BYTE_SWAP) != 0 ) {
928 saa7146_write_out_dma(dev, 3, &vdma2);
929 saa7146_write_out_dma(dev, 2, &vdma3);
930 } else {
931 saa7146_write_out_dma(dev, 2, &vdma2);
932 saa7146_write_out_dma(dev, 3, &vdma3);
933 }
934 return 0;
935 }
936
937 static void program_capture_engine(struct saa7146_dev *dev, int planar)
938 {
939 struct saa7146_vv *vv = dev->vv_data;
940 int count = 0;
941
942 unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
943 unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
944
945 /* wait for o_fid_a/b / e_fid_a/b toggle only if rps register 0 is not set*/
946 WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | o_wait);
947 WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | e_wait);
948
949 /* set rps register 0 */
950 WRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4));
951 WRITE_RPS0(MASK_27 | MASK_11);
952
953 /* turn on video-dma1 */
954 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
955 WRITE_RPS0(MASK_06 | MASK_22); /* => mask */
956 WRITE_RPS0(MASK_06 | MASK_22); /* => values */
957 if( 0 != planar ) {
958 /* turn on video-dma2 */
959 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
960 WRITE_RPS0(MASK_05 | MASK_21); /* => mask */
961 WRITE_RPS0(MASK_05 | MASK_21); /* => values */
962
963 /* turn on video-dma3 */
964 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
965 WRITE_RPS0(MASK_04 | MASK_20); /* => mask */
966 WRITE_RPS0(MASK_04 | MASK_20); /* => values */
967 }
968
969 /* wait for o_fid_a/b / e_fid_a/b toggle */
970 if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
971 WRITE_RPS0(CMD_PAUSE | o_wait);
972 WRITE_RPS0(CMD_PAUSE | e_wait);
973 } else if ( vv->last_field == V4L2_FIELD_TOP ) {
974 WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
975 WRITE_RPS0(CMD_PAUSE | o_wait);
976 } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
977 WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
978 WRITE_RPS0(CMD_PAUSE | e_wait);
979 }
980
981 /* turn off video-dma1 */
982 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
983 WRITE_RPS0(MASK_22 | MASK_06); /* => mask */
984 WRITE_RPS0(MASK_22); /* => values */
985 if( 0 != planar ) {
986 /* turn off video-dma2 */
987 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
988 WRITE_RPS0(MASK_05 | MASK_21); /* => mask */
989 WRITE_RPS0(MASK_21); /* => values */
990
991 /* turn off video-dma3 */
992 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
993 WRITE_RPS0(MASK_04 | MASK_20); /* => mask */
994 WRITE_RPS0(MASK_20); /* => values */
995 }
996
997 /* generate interrupt */
998 WRITE_RPS0(CMD_INTERRUPT);
999
1000 /* stop */
1001 WRITE_RPS0(CMD_STOP);
1002 }
1003
1004 void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
1005 {
1006 struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
1007 struct saa7146_vv *vv = dev->vv_data;
1008 u32 vdma1_prot_addr;
1009
1010 DEB_CAP(("buf:%p, next:%p\n",buf,next));
1011
1012 vdma1_prot_addr = saa7146_read(dev, PROT_ADDR1);
1013 if( 0 == vdma1_prot_addr ) {
1014 /* clear out beginning of streaming bit (rps register 0)*/
1015 DEB_CAP(("forcing sync to new frame\n"));
1016 saa7146_write(dev, MC2, MASK_27 );
1017 }
1018
1019 saa7146_set_window(dev, buf->fmt->width, buf->fmt->height, buf->fmt->field);
1020 saa7146_set_output_format(dev, sfmt->trans);
1021 saa7146_disable_clipping(dev);
1022
1023 if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
1024 } else if ( vv->last_field == V4L2_FIELD_TOP ) {
1025 vv->last_field = V4L2_FIELD_BOTTOM;
1026 } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
1027 vv->last_field = V4L2_FIELD_TOP;
1028 }
1029
1030 if( 0 != IS_PLANAR(sfmt->trans)) {
1031 calculate_video_dma_grab_planar(dev, buf);
1032 program_capture_engine(dev,1);
1033 } else {
1034 calculate_video_dma_grab_packed(dev, buf);
1035 program_capture_engine(dev,0);
1036 }
1037
1038 /*
1039 printk("vdma%d.base_even: 0x%08x\n", 1,saa7146_read(dev,BASE_EVEN1));
1040 printk("vdma%d.base_odd: 0x%08x\n", 1,saa7146_read(dev,BASE_ODD1));
1041 printk("vdma%d.prot_addr: 0x%08x\n", 1,saa7146_read(dev,PROT_ADDR1));
1042 printk("vdma%d.base_page: 0x%08x\n", 1,saa7146_read(dev,BASE_PAGE1));
1043 printk("vdma%d.pitch: 0x%08x\n", 1,saa7146_read(dev,PITCH1));
1044 printk("vdma%d.num_line_byte: 0x%08x\n", 1,saa7146_read(dev,NUM_LINE_BYTE1));
1045 printk("vdma%d => vptr : 0x%08x\n", 1,saa7146_read(dev,PCI_VDP1));
1046 */
1047
1048 /* write the address of the rps-program */
1049 saa7146_write(dev, RPS_ADDR0, dev->d_rps0.dma_handle);
1050
1051 /* turn on rps */
1052 saa7146_write(dev, MC1, (MASK_12 | MASK_28));
1053 }
1054
Historical 2.5/2.6 development