2 * Driver for HFC PCI based cards
4 * Author Kai Germaschewski
5 * Copyright 2002 by Kai Germaschewski <kai.germaschewski@gmx.de>
6 * 2000 by Karsten Keil <keil@isdn4linux.de>
7 * 2000 by Werner Cornelius <werner@isdn4linux.de>
9 * based upon Werner Cornelius's original hfc_pci.c driver
11 * This software may be used and distributed according to the terms
12 * of the GNU General Public License, incorporated herein by reference.
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/kmod.h>
23 #include <linux/slab.h>
24 #include <linux/skbuff.h>
25 #include <linux/netdevice.h>
26 #include <asm/delay.h>
27 #include "hisax_hfcpci.h"
30 #define __debug_variable debug
31 #include "hisax_debug.h"
33 #ifdef CONFIG_HISAX_DEBUG
35 MODULE_PARM(debug
, "i");
38 MODULE_AUTHOR("Kai Germaschewski <kai.germaschewski@gmx.de>/Werner Cornelius <werner@isdn4linux.de>");
39 MODULE_DESCRIPTION("HFC PCI ISDN driver");
41 #define ID(ven, dev, name) \
42 { .vendor = PCI_VENDOR_ID_##ven, \
43 .device = PCI_DEVICE_ID_##dev, \
44 .subvendor = PCI_ANY_ID, \
45 .subdevice = PCI_ANY_ID, \
48 .driver_data = (unsigned long) name }
50 static struct pci_device_id hfcpci_ids
[] = {
51 ID(CCD
, CCD_2BD0
, "CCD/Billion/Asuscom 2BD0"),
52 ID(CCD
, CCD_B000
, "Billion B000"),
53 ID(CCD
, CCD_B006
, "Billion B006"),
54 ID(CCD
, CCD_B007
, "Billion B007"),
55 ID(CCD
, CCD_B008
, "Billion B008"),
56 ID(CCD
, CCD_B009
, "Billion B009"),
57 ID(CCD
, CCD_B00A
, "Billion B00A"),
58 ID(CCD
, CCD_B00B
, "Billion B00B"),
59 ID(CCD
, CCD_B00C
, "Billion B00C"),
60 ID(CCD
, CCD_B100
, "Seyeon"),
61 ID(ABOCOM
, ABOCOM_2BD1
, "Abocom/Magitek"),
62 ID(ASUSTEK
, ASUSTEK_0675
, "Asuscom/Askey"),
63 ID(BERKOM
, BERKOM_T_CONCEPT
, "German Telekom T-Concept"),
64 ID(BERKOM
, BERKOM_A1T
, "German Telekom A1T"),
65 ID(ANIGMA
, ANIGMA_MC145575
, "Motorola MC145575"),
66 ID(ZOLTRIX
, ZOLTRIX_2BD0
, "Zoltrix 2BD0"),
67 ID(DIGI
, DIGI_DF_M_IOM2_E
, "Digi DataFire Micro V IOM2 (Europe)"),
68 ID(DIGI
, DIGI_DF_M_E
, "Digi DataFire Micro V (Europe)"),
69 ID(DIGI
, DIGI_DF_M_IOM2_A
, "Digi DataFire Micro V IOM2 (America)"),
70 ID(DIGI
, DIGI_DF_M_A
, "Digi DataFire Micro V (America)"),
73 MODULE_DEVICE_TABLE(pci
, hfcpci_ids
);
77 static int protocol
= 2; /* EURO-ISDN Default */
78 MODULE_PARM(protocol
, "i");
80 // ----------------------------------------------------------------------
83 #define DBG_WARN 0x0001
84 #define DBG_INFO 0x0002
85 #define DBG_IRQ 0x0010
86 #define DBG_L1M 0x0020
88 #define DBG_D_XMIT 0x0100
89 #define DBG_D_RECV 0x0200
90 #define DBG_B_XMIT 0x1000
91 #define DBG_B_RECV 0x2000
93 /* memory window base address offset (in config space) */
95 #define HFCPCI_MWBA 0x80
97 /* GCI/IOM bus monitor registers */
99 #define HCFPCI_C_I 0x08
100 #define HFCPCI_TRxR 0x0C
101 #define HFCPCI_MON1_D 0x28
102 #define HFCPCI_MON2_D 0x2C
105 /* GCI/IOM bus timeslot registers */
107 #define HFCPCI_B1_SSL 0x80
108 #define HFCPCI_B2_SSL 0x84
109 #define HFCPCI_AUX1_SSL 0x88
110 #define HFCPCI_AUX2_SSL 0x8C
111 #define HFCPCI_B1_RSL 0x90
112 #define HFCPCI_B2_RSL 0x94
113 #define HFCPCI_AUX1_RSL 0x98
114 #define HFCPCI_AUX2_RSL 0x9C
116 /* GCI/IOM bus data registers */
118 #define HFCPCI_B1_D 0xA0
119 #define HFCPCI_B2_D 0xA4
120 #define HFCPCI_AUX1_D 0xA8
121 #define HFCPCI_AUX2_D 0xAC
123 /* GCI/IOM bus configuration registers */
125 #define HFCPCI_MST_EMOD 0xB4
126 #define HFCPCI_MST_MODE 0xB8
127 #define HFCPCI_CONNECT 0xBC
130 /* Interrupt and status registers */
132 #define HFCPCI_FIFO_EN 0x44
133 #define HFCPCI_TRM 0x48
134 #define HFCPCI_B_MODE 0x4C
135 #define HFCPCI_CHIP_ID 0x58
136 #define HFCPCI_CIRM 0x60
137 #define HFCPCI_CTMT 0x64
138 #define HFCPCI_INT_M1 0x68
139 #define HFCPCI_INT_M2 0x6C
140 #define HFCPCI_INT_S1 0x78
141 #define HFCPCI_INT_S2 0x7C
142 #define HFCPCI_STATUS 0x70
144 /* S/T section registers */
146 #define HFCPCI_STATES 0xC0
147 #define HFCPCI_SCTRL 0xC4
148 #define HFCPCI_SCTRL_E 0xC8
149 #define HFCPCI_SCTRL_R 0xCC
150 #define HFCPCI_SQ 0xD0
151 #define HFCPCI_CLKDEL 0xDC
152 #define HFCPCI_B1_REC 0xF0
153 #define HFCPCI_B1_SEND 0xF0
154 #define HFCPCI_B2_REC 0xF4
155 #define HFCPCI_B2_SEND 0xF4
156 #define HFCPCI_D_REC 0xF8
157 #define HFCPCI_D_SEND 0xF8
158 #define HFCPCI_E_REC 0xFC
161 /* bits in status register (READ) */
162 #define HFCPCI_PCI_PROC 0x02
163 #define HFCPCI_NBUSY 0x04
164 #define HFCPCI_TIMER_ELAP 0x10
165 #define HFCPCI_STATINT 0x20
166 #define HFCPCI_FRAMEINT 0x40
167 #define HFCPCI_ANYINT 0x80
169 /* bits in CTMT (Write) */
170 #define HFCPCI_CLTIMER 0x80
171 #define HFCPCI_TIM3_125 0x04
172 #define HFCPCI_TIM25 0x10
173 #define HFCPCI_TIM50 0x14
174 #define HFCPCI_TIM400 0x18
175 #define HFCPCI_TIM800 0x1C
176 #define HFCPCI_AUTO_TIMER 0x20
177 #define HFCPCI_TRANSB2 0x02
178 #define HFCPCI_TRANSB1 0x01
180 /* bits in CIRM (Write) */
181 #define HFCPCI_AUX_MSK 0x07
182 #define HFCPCI_RESET 0x08
183 #define HFCPCI_B1_REV 0x40
184 #define HFCPCI_B2_REV 0x80
186 /* bits in INT_M1 and INT_S1 */
187 #define HFCPCI_INTS_B1TRANS 0x01
188 #define HFCPCI_INTS_B2TRANS 0x02
189 #define HFCPCI_INTS_DTRANS 0x04
190 #define HFCPCI_INTS_B1REC 0x08
191 #define HFCPCI_INTS_B2REC 0x10
192 #define HFCPCI_INTS_DREC 0x20
193 #define HFCPCI_INTS_L1STATE 0x40
194 #define HFCPCI_INTS_TIMER 0x80
197 #define HFCPCI_PROC_TRANS 0x01
198 #define HFCPCI_GCI_I_CHG 0x02
199 #define HFCPCI_GCI_MON_REC 0x04
200 #define HFCPCI_IRQ_ENABLE 0x08
201 #define HFCPCI_PMESEL 0x80
204 #define HFCPCI_STATE_MSK 0x0F
205 #define HFCPCI_LOAD_STATE 0x10
206 #define HFCPCI_ACTIVATE 0x20
207 #define HFCPCI_DO_ACTION 0x40
208 #define HFCPCI_NT_G2_G3 0x80
210 /* bits in HFCD_MST_MODE */
211 #define HFCPCI_MASTER 0x01
212 #define HFCPCI_SLAVE 0x00
213 /* remaining bits are for codecs control */
215 /* bits in HFCD_SCTRL */
216 #define SCTRL_B1_ENA 0x01
217 #define SCTRL_B2_ENA 0x02
218 #define SCTRL_MODE_TE 0x00
219 #define SCTRL_MODE_NT 0x04
220 #define SCTRL_LOW_PRIO 0x08
221 #define SCTRL_SQ_ENA 0x10
222 #define SCTRL_TEST 0x20
223 #define SCTRL_NONE_CAP 0x40
224 #define SCTRL_PWR_DOWN 0x80
226 /* bits in SCTRL_E */
227 #define HFCPCI_AUTO_AWAKE 0x01
228 #define HFCPCI_DBIT_1 0x04
229 #define HFCPCI_IGNORE_COL 0x08
230 #define HFCPCI_CHG_B1_B2 0x80
232 /* bits in FIFO_EN register */
233 #define HFCPCI_FIFOEN_B1 0x03
234 #define HFCPCI_FIFOEN_B2 0x0C
235 #define HFCPCI_FIFOEN_DTX 0x10
236 #define HFCPCI_FIFOEN_DRX 0x20
237 #define HFCPCI_FIFOEN_B1TX 0x01
238 #define HFCPCI_FIFOEN_B1RX 0x02
239 #define HFCPCI_FIFOEN_B2TX 0x04
240 #define HFCPCI_FIFOEN_B2RX 0x08
243 * thresholds for transparent B-channel mode
244 * change mask and threshold simultaneously
246 #define HFCPCI_BTRANS_THRESHOLD 128
247 #define HFCPCI_BTRANS_THRESMASK 0x00
249 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
250 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
252 #define MAX_D_FRAMES 0x10
253 #define MAX_B_FRAMES 0x20
254 #define B_FIFO_START 0x0200
255 #define B_FIFO_END 0x2000
256 #define B_FIFO_SIZE (B_FIFO_END - B_FIFO_START)
257 #define D_FIFO_START 0x0000
258 #define D_FIFO_END 0x0200
259 #define D_FIFO_SIZE (D_FIFO_END - D_FIFO_START)
261 // ----------------------------------------------------------------------
262 // push messages to the upper layers
264 static inline void D_L1L2(struct hfcpci_adapter
*adapter
, int pr
, void *arg
)
266 struct hisax_if
*ifc
= (struct hisax_if
*) &adapter
->d_if
;
268 DBG(DBG_PR
, "pr %#x", pr
);
269 ifc
->l1l2(ifc
, pr
, arg
);
272 static inline void B_L1L2(struct hfcpci_bcs
*bcs
, int pr
, void *arg
)
274 struct hisax_if
*ifc
= (struct hisax_if
*) &bcs
->b_if
;
276 DBG(DBG_PR
, "pr %#x", pr
);
277 ifc
->l1l2(ifc
, pr
, arg
);
280 // ----------------------------------------------------------------------
284 hfcpci_writeb(struct hfcpci_adapter
*adapter
, u8 b
, unsigned char offset
)
286 writeb(b
, adapter
->mmio
+ offset
);
290 hfcpci_readb(struct hfcpci_adapter
*adapter
, unsigned char offset
)
292 return readb(adapter
->mmio
+ offset
);
295 // ----------------------------------------------------------------------
296 // magic to define the various F/Z counter accesses
298 #define DECL_B_F(r, f) \
300 get_b_##r##_##f (struct hfcpci_bcs *bcs) \
302 u16 off = bcs->channel ? OFF_B2_##r##_##f : OFF_B1_##r##_##f; \
304 return *(bcs->adapter->fifo + off); \
308 set_b_##r##_##f (struct hfcpci_bcs *bcs, u8 f) \
310 u16 off = bcs->channel ? OFF_B2_##r##_##f : OFF_B1_##r##_##f; \
312 *(bcs->adapter->fifo + off) = f; \
315 #define OFF_B1_rx_f1 0x6080
316 #define OFF_B2_rx_f1 0x6180
317 #define OFF_B1_rx_f2 0x6081
318 #define OFF_B2_rx_f2 0x6181
320 #define OFF_B1_tx_f1 0x2080
321 #define OFF_B2_tx_f1 0x2180
322 #define OFF_B1_tx_f2 0x2081
323 #define OFF_B2_tx_f2 0x2181
332 #define DECL_B_Z(r, z) \
334 get_b_##r##_##z (struct hfcpci_bcs *bcs, u8 f) \
336 u16 off = bcs->channel ? OFF_B2_##r##_##z : OFF_B1_##r##_##z; \
338 return le16_to_cpu(*((u16 *) (bcs->adapter->fifo + off + f * 4))); \
342 set_b_##r##_##z(struct hfcpci_bcs *bcs, u8 f, u16 z) \
344 u16 off = bcs->channel ? OFF_B2_##r##_##z : OFF_B1_##r##_##z; \
346 *((u16 *) (bcs->adapter->fifo + off + f * 4)) = cpu_to_le16(z); \
349 #define OFF_B1_rx_z1 0x6000
350 #define OFF_B2_rx_z1 0x6100
351 #define OFF_B1_rx_z2 0x6002
352 #define OFF_B2_rx_z2 0x6102
354 #define OFF_B1_tx_z1 0x2000
355 #define OFF_B2_tx_z1 0x2100
356 #define OFF_B1_tx_z2 0x2002
357 #define OFF_B2_tx_z2 0x2102
366 #define DECL_D_F(r, f) \
368 get_d_##r##_##f (struct hfcpci_adapter *adapter) \
370 u16 off = OFF_D_##r##_##f; \
372 return *(adapter->fifo + off) & 0xf; \
376 set_d_##r##_##f (struct hfcpci_adapter *adapter, u8 f) \
378 u16 off = OFF_D_##r##_##f; \
380 *(adapter->fifo + off) = f | 0x10; \
383 #define OFF_D_rx_f1 0x60a0
384 #define OFF_D_rx_f2 0x60a1
386 #define OFF_D_tx_f1 0x20a0
387 #define OFF_D_tx_f2 0x20a1
396 #define DECL_D_Z(r, z) \
398 get_d_##r##_##z (struct hfcpci_adapter *adapter, u8 f) \
400 u16 off = OFF_D_##r##_##z; \
402 return le16_to_cpu(*((u16 *) (adapter->fifo + off + (f | 0x10) * 4)));\
406 set_d_##r##_##z(struct hfcpci_adapter *adapter, u8 f, u16 z) \
408 u16 off = OFF_D_##r##_##z; \
410 *((u16 *) (adapter->fifo + off + (f | 0x10) * 4)) = cpu_to_le16(z); \
413 #define OFF_D_rx_z1 0x6080
414 #define OFF_D_rx_z2 0x6082
416 #define OFF_D_tx_z1 0x2080
417 #define OFF_D_tx_z2 0x2082
426 // ----------------------------------------------------------------------
430 hfcpci_fill_d_fifo(struct hfcpci_adapter
*adapter
)
435 char *fifo_adr
= adapter
->fifo
;
436 struct sk_buff
*tx_skb
= adapter
->tx_skb
;
438 f1
= get_d_tx_f1(adapter
);
439 f2
= get_d_tx_f2(adapter
);
440 DBG(DBG_D_XMIT
, "f1 %#x f2 %#x", f1
, f2
);
444 fcnt
+= MAX_D_FRAMES
;
451 z1
= get_d_tx_z1(adapter
, f1
);
452 z2
= get_d_tx_z2(adapter
, f1
); //XXX
453 DBG(DBG_D_XMIT
, "z1 %#x z2 %#x", z1
, z2
);
459 if (tx_skb
->len
> cnt
) {
465 if (z1
+ cnt
<= D_FIFO_END
) {
466 memcpy(fifo_adr
+ z1
, tx_skb
->data
, cnt
);
468 memcpy(fifo_adr
+ z1
, tx_skb
->data
, D_FIFO_END
- z1
);
469 memcpy(fifo_adr
+ D_FIFO_START
,
470 tx_skb
->data
+ (D_FIFO_END
- z1
),
471 cnt
- (D_FIFO_END
- z1
));
474 if (z1
>= D_FIFO_END
)
477 f1
= (f1
+ 1) & (MAX_D_FRAMES
- 1);
479 set_d_tx_z1(adapter
, f1
, z1
);
481 set_d_tx_f1(adapter
, f1
);
485 hfcpci_fill_b_fifo_hdlc(struct hfcpci_bcs
*bcs
)
490 char *fifo_adr
= bcs
->adapter
->fifo
+ (bcs
->channel
? 0x2000 : 0x0000);
491 struct sk_buff
*tx_skb
= bcs
->tx_skb
;
493 f1
= get_b_tx_f1(bcs
);
494 f2
= get_b_tx_f2(bcs
);
495 DBG(DBG_B_XMIT
, "f1 %#x f2 %#x", f1
, f2
);
499 fcnt
+= MAX_B_FRAMES
;
506 z1
= get_b_tx_z1(bcs
, f1
);
507 z2
= get_b_tx_z2(bcs
, f1
); //XXX
508 DBG(DBG_B_XMIT
, "z1 %#x z2 %#x", z1
, z2
);
514 if (tx_skb
->len
> cnt
) {
520 if (z1
+ cnt
<= B_FIFO_END
) {
521 memcpy(fifo_adr
+ z1
, tx_skb
->data
, cnt
);
523 memcpy(fifo_adr
+ z1
, tx_skb
->data
, B_FIFO_END
- z1
);
524 memcpy(fifo_adr
+ B_FIFO_START
,
525 tx_skb
->data
+ (B_FIFO_END
- z1
),
526 cnt
- (B_FIFO_END
- z1
));
529 if (z1
>= B_FIFO_END
)
532 f1
= (f1
+ 1) & (MAX_B_FRAMES
- 1);
534 set_b_tx_z1(bcs
, f1
, z1
);
536 set_b_tx_f1(bcs
, f1
);
540 hfcpci_fill_b_fifo_trans(struct hfcpci_bcs
*bcs
)
543 char *fifo_adr
= bcs
->adapter
->fifo
+ (bcs
->channel
? 0x2000 : 0x0000);
544 struct sk_buff
*tx_skb
= bcs
->tx_skb
;
548 f1
= get_b_tx_f1(bcs
);
549 f2
= get_b_tx_f2(bcs
);
554 z1
= get_b_tx_z1(bcs
, f1
);
555 z2
= get_b_tx_z2(bcs
, f1
);
561 if (tx_skb
->len
> cnt
)
564 if (z1
+ cnt
<= B_FIFO_END
) {
565 memcpy(fifo_adr
+ z1
, tx_skb
->data
, cnt
);
567 memcpy(fifo_adr
+ z1
, tx_skb
->data
, B_FIFO_END
- z1
);
568 memcpy(fifo_adr
+ B_FIFO_START
,
569 tx_skb
->data
+ (B_FIFO_END
- z1
),
570 cnt
- (B_FIFO_END
- z1
));
573 if (z1
>= B_FIFO_END
)
577 set_b_tx_z1(bcs
, f1
, z1
);
581 hfcpci_fill_b_fifo(struct hfcpci_bcs
*bcs
)
590 hfcpci_fill_b_fifo_trans(bcs
);
593 hfcpci_fill_b_fifo_hdlc(bcs
);
600 static void hfcpci_clear_b_rx_fifo(struct hfcpci_bcs
*bcs
);
601 static void hfcpci_clear_b_tx_fifo(struct hfcpci_bcs
*bcs
);
604 hfcpci_b_mode(struct hfcpci_bcs
*bcs
, int mode
)
606 struct hfcpci_adapter
*adapter
= bcs
->adapter
;
608 DBG(DBG_B_XMIT
, "B%d mode %d --> %d",
609 bcs
->channel
+ 1, bcs
->mode
, mode
);
611 if (bcs
->mode
== mode
)
616 if (bcs
->channel
== 0) {
617 adapter
->sctrl
&= ~SCTRL_B1_ENA
;
618 adapter
->sctrl_r
&= ~SCTRL_B1_ENA
;
619 adapter
->fifo_en
&= ~HFCPCI_FIFOEN_B1
;
620 adapter
->int_m1
&= ~(HFCPCI_INTS_B1TRANS
+ HFCPCI_INTS_B1REC
);
622 adapter
->sctrl
&= ~SCTRL_B2_ENA
;
623 adapter
->sctrl_r
&= ~SCTRL_B2_ENA
;
624 adapter
->fifo_en
&= ~HFCPCI_FIFOEN_B2
;
625 adapter
->int_m1
&= ~(HFCPCI_INTS_B2TRANS
+ HFCPCI_INTS_B2REC
);
630 hfcpci_clear_b_rx_fifo(bcs
);
631 hfcpci_clear_b_tx_fifo(bcs
);
632 if (bcs
->channel
== 0) {
633 adapter
->sctrl
|= SCTRL_B1_ENA
;
634 adapter
->sctrl_r
|= SCTRL_B1_ENA
;
635 adapter
->fifo_en
|= HFCPCI_FIFOEN_B1
;
636 adapter
->int_m1
|= (HFCPCI_INTS_B1TRANS
+ HFCPCI_INTS_B1REC
);
638 if (mode
== L1_MODE_TRANS
)
644 adapter
->sctrl
|= SCTRL_B2_ENA
;
645 adapter
->sctrl_r
|= SCTRL_B2_ENA
;
646 adapter
->fifo_en
|= HFCPCI_FIFOEN_B2
;
647 adapter
->int_m1
|= (HFCPCI_INTS_B2TRANS
+ HFCPCI_INTS_B2REC
);
649 if (mode
== L1_MODE_TRANS
)
657 hfcpci_writeb(adapter
, adapter
->int_m1
, HFCPCI_INT_M1
);
658 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
659 hfcpci_writeb(adapter
, adapter
->sctrl
, HFCPCI_SCTRL
);
660 hfcpci_writeb(adapter
, adapter
->sctrl_r
, HFCPCI_SCTRL_R
);
661 hfcpci_writeb(adapter
, adapter
->ctmt
, HFCPCI_CTMT
);
662 hfcpci_writeb(adapter
, adapter
->conn
, HFCPCI_CONNECT
);
667 // ----------------------------------------------------------------------
668 // Layer 1 state machine
670 static struct Fsm l1fsm
;
683 #define L1_STATE_COUNT (ST_L1_F8+1)
685 static char *strL1State
[] =
708 EV_PH_DEACTIVATE_REQ
,
712 #define L1_EVENT_COUNT (EV_TIMER3 + 1)
714 static char *strL1Event
[] =
725 "EV_PH_ACTIVATE_REQ",
726 "EV_PH_DEACTIVATE_REQ",
730 static void l1_ignore(struct FsmInst
*fi
, int event
, void *arg
)
734 static void l1_go_f3(struct FsmInst
*fi
, int event
, void *arg
)
736 FsmChangeState(fi
, ST_L1_F3
);
739 static void l1_go_f3_deact_ind(struct FsmInst
*fi
, int event
, void *arg
)
741 struct hfcpci_adapter
*adapter
= fi
->userdata
;
743 FsmChangeState(fi
, ST_L1_F3
);
744 D_L1L2(adapter
, PH_DEACTIVATE
| INDICATION
, NULL
);
747 static void l1_go_f4(struct FsmInst
*fi
, int event
, void *arg
)
749 FsmChangeState(fi
, ST_L1_F3
);
752 static void l1_go_f5(struct FsmInst
*fi
, int event
, void *arg
)
754 FsmChangeState(fi
, ST_L1_F3
);
757 static void l1_go_f6(struct FsmInst
*fi
, int event
, void *arg
)
759 FsmChangeState(fi
, ST_L1_F6
);
762 static void l1_go_f6_deact_ind(struct FsmInst
*fi
, int event
, void *arg
)
764 struct hfcpci_adapter
*adapter
= fi
->userdata
;
766 FsmChangeState(fi
, ST_L1_F6
);
767 D_L1L2(adapter
, PH_DEACTIVATE
| INDICATION
, NULL
);
770 static void l1_go_f7(struct FsmInst
*fi
, int event
, void *arg
)
772 FsmChangeState(fi
, ST_L1_F7
);
775 static void l1_go_f7_act_ind(struct FsmInst
*fi
, int event
, void *arg
)
777 struct hfcpci_adapter
*adapter
= fi
->userdata
;
779 FsmChangeState(fi
, ST_L1_F7
);
780 D_L1L2(adapter
, PH_ACTIVATE
| INDICATION
, NULL
);
783 static void l1_go_f8(struct FsmInst
*fi
, int event
, void *arg
)
785 FsmChangeState(fi
, ST_L1_F8
);
788 static void l1_go_f8_deact_ind(struct FsmInst
*fi
, int event
, void *arg
)
790 struct hfcpci_adapter
*adapter
= fi
->userdata
;
792 FsmChangeState(fi
, ST_L1_F8
);
793 D_L1L2(adapter
, PH_DEACTIVATE
| INDICATION
, NULL
);
796 static void l1_act_req(struct FsmInst
*fi
, int event
, void *arg
)
798 struct hfcpci_adapter
*adapter
= fi
->userdata
;
800 hfcpci_writeb(adapter
, HFCPCI_ACTIVATE
| HFCPCI_DO_ACTION
, HFCPCI_STATES
);
803 static struct FsmNode L1FnList
[] __initdata
=
805 {ST_L1_F2
, EV_PH_F3
, l1_go_f3
},
806 {ST_L1_F2
, EV_PH_F6
, l1_go_f6
},
807 {ST_L1_F2
, EV_PH_F7
, l1_go_f7_act_ind
},
809 {ST_L1_F3
, EV_PH_F3
, l1_ignore
},
810 {ST_L1_F3
, EV_PH_F4
, l1_go_f4
},
811 {ST_L1_F3
, EV_PH_F5
, l1_go_f5
},
812 {ST_L1_F3
, EV_PH_F6
, l1_go_f6
},
813 {ST_L1_F3
, EV_PH_F7
, l1_go_f7_act_ind
},
814 {ST_L1_F3
, EV_PH_ACTIVATE_REQ
, l1_act_req
},
816 {ST_L1_F4
, EV_PH_F7
, l1_ignore
},
817 {ST_L1_F4
, EV_PH_F3
, l1_go_f3
},
818 {ST_L1_F4
, EV_PH_F5
, l1_go_f5
},
819 {ST_L1_F4
, EV_PH_F6
, l1_go_f6
},
820 {ST_L1_F4
, EV_PH_F7
, l1_go_f7
},
822 {ST_L1_F5
, EV_PH_F7
, l1_ignore
},
823 {ST_L1_F5
, EV_PH_F3
, l1_go_f3
},
824 {ST_L1_F5
, EV_PH_F6
, l1_go_f6
},
825 {ST_L1_F5
, EV_PH_F7
, l1_go_f7
},
827 {ST_L1_F6
, EV_PH_F7
, l1_ignore
},
828 {ST_L1_F6
, EV_PH_F3
, l1_go_f3
},
829 {ST_L1_F6
, EV_PH_F7
, l1_go_f7_act_ind
},
830 {ST_L1_F6
, EV_PH_F8
, l1_go_f8
},
832 {ST_L1_F7
, EV_PH_F7
, l1_ignore
},
833 {ST_L1_F7
, EV_PH_F3
, l1_go_f3_deact_ind
},
834 {ST_L1_F7
, EV_PH_F6
, l1_go_f6_deact_ind
},
835 {ST_L1_F7
, EV_PH_F8
, l1_go_f8_deact_ind
},
837 {ST_L1_F8
, EV_PH_F7
, l1_ignore
},
838 {ST_L1_F8
, EV_PH_F3
, l1_go_f3
},
839 {ST_L1_F8
, EV_PH_F6
, l1_go_f6
},
840 {ST_L1_F8
, EV_PH_F7
, l1_go_f7_act_ind
},
844 static void l1m_debug(struct FsmInst
*fi
, char *fmt
, ...)
850 vsprintf(buf
, fmt
, args
);
851 DBG(DBG_L1M
, "%s", buf
);
855 // ----------------------------------------------------------------------
859 hfcpci_clear_d_rx_fifo(struct hfcpci_adapter
*adapter
)
865 fifo_state
= adapter
->fifo_en
& HFCPCI_FIFOEN_DRX
;
867 if (fifo_state
) { // enabled
869 adapter
->fifo_en
&= ~fifo_state
;
870 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
873 adapter
->last_fcnt
= 0;
875 set_d_rx_z1(adapter
, MAX_D_FRAMES
- 1, D_FIFO_END
- 1);
876 set_d_rx_z2(adapter
, MAX_D_FRAMES
- 1, D_FIFO_END
- 1);
878 set_d_rx_f1(adapter
, MAX_D_FRAMES
- 1);
879 set_d_rx_f2(adapter
, MAX_D_FRAMES
- 1);
883 adapter
->fifo_en
|= fifo_state
;
884 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
889 hfcpci_clear_b_rx_fifo(struct hfcpci_bcs
*bcs
)
891 struct hfcpci_adapter
*adapter
= bcs
->adapter
;
892 int nr
= bcs
->channel
;
897 fifo_state
= adapter
->fifo_en
&
898 (nr
? HFCPCI_FIFOEN_B2RX
: HFCPCI_FIFOEN_B1RX
);
900 if (fifo_state
) { // enabled
901 adapter
->fifo_en
&= ~fifo_state
;
902 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
907 set_b_rx_z1(bcs
, MAX_B_FRAMES
- 1, B_FIFO_END
- 1);
908 set_b_rx_z2(bcs
, MAX_B_FRAMES
- 1, B_FIFO_END
- 1);
910 set_b_rx_f1(bcs
, MAX_B_FRAMES
- 1);
911 set_b_rx_f2(bcs
, MAX_B_FRAMES
- 1);
915 adapter
->fifo_en
|= fifo_state
;
916 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
920 // XXX clear d_tx_fifo?
923 hfcpci_clear_b_tx_fifo(struct hfcpci_bcs
*bcs
)
925 struct hfcpci_adapter
*adapter
= bcs
->adapter
;
926 int nr
= bcs
->channel
;
929 fifo_state
= adapter
->fifo_en
&
930 (nr
? HFCPCI_FIFOEN_B2TX
: HFCPCI_FIFOEN_B1TX
);
932 if (fifo_state
) { // enabled
933 adapter
->fifo_en
&= ~fifo_state
;
934 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
939 set_b_rx_z1(bcs
, MAX_B_FRAMES
- 1, B_FIFO_END
- 1);
940 set_b_rx_z2(bcs
, MAX_B_FRAMES
- 1, B_FIFO_END
- 1);
942 set_b_rx_f1(bcs
, MAX_B_FRAMES
- 1);
943 set_b_rx_f2(bcs
, MAX_B_FRAMES
- 1);
947 adapter
->fifo_en
|= fifo_state
;
948 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
952 // ----------------------------------------------------------------------
953 // receive messages from upper layers
956 hfcpci_d_l2l1(struct hisax_if
*ifc
, int pr
, void *arg
)
958 struct hfcpci_adapter
*adapter
= ifc
->priv
;
959 struct sk_buff
*skb
= arg
;
961 DBG(DBG_PR
, "pr %#x", pr
);
964 case PH_ACTIVATE
| REQUEST
:
965 FsmEvent(&adapter
->l1m
, EV_PH_ACTIVATE_REQ
, NULL
);
967 case PH_DEACTIVATE
| REQUEST
:
968 FsmEvent(&adapter
->l1m
, EV_PH_DEACTIVATE_REQ
, NULL
);
970 case PH_DATA
| REQUEST
:
971 DBG(DBG_PR
, "PH_DATA REQUEST len %d", skb
->len
);
972 DBG_SKB(DBG_D_XMIT
, skb
);
973 if (adapter
->l1m
.state
!= ST_L1_F7
) {
974 DBG(DBG_WARN
, "L1 wrong state %d", adapter
->l1m
.state
);
980 adapter
->tx_skb
= skb
;
981 hfcpci_fill_d_fifo(adapter
);
987 hfcpci_b_l2l1(struct hisax_if
*ifc
, int pr
, void *arg
)
989 struct hfcpci_bcs
*bcs
= ifc
->priv
;
990 struct sk_buff
*skb
= arg
;
993 DBG(DBG_PR
, "pr %#x", pr
);
996 case PH_DATA
| REQUEST
:
1001 DBG_SKB(DBG_B_XMIT
, skb
);
1002 hfcpci_fill_b_fifo(bcs
);
1004 case PH_ACTIVATE
| REQUEST
:
1006 DBG(DBG_PR
,"B%d,PH_ACTIVATE_REQUEST %d", bcs
->channel
+ 1, mode
);
1007 hfcpci_b_mode(bcs
, mode
);
1008 B_L1L2(bcs
, PH_ACTIVATE
| INDICATION
, NULL
);
1010 case PH_DEACTIVATE
| REQUEST
:
1011 DBG(DBG_PR
,"B%d,PH_DEACTIVATE_REQUEST", bcs
->channel
+ 1);
1012 hfcpci_b_mode(bcs
, L1_MODE_NULL
);
1013 B_L1L2(bcs
, PH_DEACTIVATE
| INDICATION
, NULL
);
1018 // ----------------------------------------------------------------------
1022 hfcpci_d_recv_irq(struct hfcpci_adapter
*adapter
)
1024 struct sk_buff
*skb
;
1025 char *fifo_adr
= adapter
->fifo
+ 0x4000;
1032 while (loop
-- > 0) {
1033 f1
= get_d_rx_f1(adapter
);
1034 f2
= get_d_rx_f2(adapter
);
1035 DBG(DBG_D_RECV
, "f1 %#x f2 %#x", f1
, f2
);
1044 if (fcnt
< adapter
->last_fcnt
)
1046 hfcpci_clear_d_rx_fifo(adapter
);
1047 // XXX init last_fcnt
1049 z1
= get_d_rx_z1(adapter
, f2
);
1050 z2
= get_d_rx_z2(adapter
, f2
);
1051 DBG(DBG_D_RECV
, "z1 %#x z2 %#x", z1
, z2
);
1059 DBG(DBG_WARN
, "frame too short");
1062 if (fifo_adr
[z1
] != 0) {
1063 DBG(DBG_WARN
, "CRC error");
1067 skb
= dev_alloc_skb(cnt
);
1069 DBG(DBG_WARN
, "no mem");
1072 p
= skb_put(skb
, cnt
);
1073 if (z2
+ cnt
<= D_FIFO_END
) {
1074 memcpy(p
, fifo_adr
+ z2
, cnt
);
1076 memcpy(p
, fifo_adr
+ z2
, D_FIFO_END
- z2
);
1077 memcpy(p
+ (D_FIFO_END
- z2
), fifo_adr
+ D_FIFO_START
,
1078 cnt
- (D_FIFO_END
- z2
));
1081 DBG_SKB(DBG_D_RECV
, skb
);
1082 D_L1L2(adapter
, PH_DATA
| INDICATION
, skb
);
1085 if (++z1
>= D_FIFO_END
)
1088 f2
= (f2
+ 1) & (MAX_D_FRAMES
- 1);
1090 set_d_rx_z2(adapter
, f2
, z1
);
1092 set_d_rx_f2(adapter
, f2
);
1094 adapter
->last_fcnt
= fcnt
- 1;
1099 hfcpci_b_recv_hdlc_irq(struct hfcpci_adapter
*adapter
, int nr
)
1101 struct hfcpci_bcs
*bcs
= &adapter
->bcs
[nr
];
1102 struct sk_buff
*skb
;
1103 char *fifo_adr
= adapter
->fifo
+ (nr
? 0x6000 : 0x4000);
1110 while (loop
-- > 0) {
1111 f1
= get_b_rx_f1(bcs
);
1112 f2
= get_b_rx_f2(bcs
);
1113 DBG(DBG_B_RECV
, "f1 %d f2 %d", f1
, f2
);
1122 if (fcnt
< bcs
->last_fcnt
)
1124 hfcpci_clear_b_rx_fifo(bcs
);
1125 // XXX init last_fcnt
1127 z1
= get_b_rx_z1(bcs
, f2
);
1128 z2
= get_b_rx_z2(bcs
, f2
);
1129 DBG(DBG_B_RECV
, "z1 %d z2 %d", z1
, z2
);
1137 DBG(DBG_WARN
, "frame too short");
1140 if (fifo_adr
[z1
] != 0) {
1141 DBG(DBG_WARN
, "CRC error");
1145 skb
= dev_alloc_skb(cnt
);
1147 DBG(DBG_WARN
, "no mem");
1150 p
= skb_put(skb
, cnt
);
1151 if (z2
+ cnt
<= B_FIFO_END
) {
1152 memcpy(p
, fifo_adr
+ z2
, cnt
);
1154 memcpy(p
, fifo_adr
+ z2
, B_FIFO_END
- z2
);
1155 memcpy(p
+ (B_FIFO_END
- z2
), fifo_adr
+ B_FIFO_START
,
1156 cnt
- (B_FIFO_END
- z2
));
1159 DBG_SKB(DBG_B_RECV
, skb
);
1160 B_L1L2(bcs
, PH_DATA
| INDICATION
, skb
);
1163 if (++z1
>= B_FIFO_END
)
1166 f2
= (f2
+ 1) & (MAX_B_FRAMES
- 1);
1168 set_b_rx_z2(bcs
, f2
, z1
);
1170 set_b_rx_f2(bcs
, f2
);
1172 bcs
->last_fcnt
= fcnt
- 1;
1177 hfcpci_b_recv_trans_irq(struct hfcpci_adapter
*adapter
, int nr
)
1179 struct hfcpci_bcs
*bcs
= &adapter
->bcs
[nr
];
1180 struct sk_buff
*skb
;
1181 char *fifo_adr
= adapter
->fifo
+ (nr
? 0x6000 : 0x4000);
1188 f1
= get_b_rx_f1(bcs
);
1189 f2
= get_b_rx_f2(bcs
);
1194 while (loop
-- > 0) {
1195 z1
= get_b_rx_z1(bcs
, f2
);
1196 z2
= get_b_rx_z2(bcs
, f2
);
1200 /* no data available */
1206 if (cnt
> HFCPCI_BTRANS_THRESHOLD
)
1207 cnt
= HFCPCI_BTRANS_THRESHOLD
;
1209 skb
= dev_alloc_skb(cnt
);
1211 DBG(DBG_WARN
, "no mem");
1215 p
= skb_put(skb
, cnt
);
1216 if (z2
+ cnt
<= 0x2000) {
1217 memcpy(p
, fifo_adr
+ z2
, cnt
);
1219 memcpy(p
, fifo_adr
+ z2
, 0x2000 - z2
);
1221 memcpy(p
, fifo_adr
+ 0x200, cnt
- (0x2000 - z2
));
1224 DBG_SKB(DBG_B_RECV
, skb
);
1225 B_L1L2(bcs
, PH_DATA
| INDICATION
, skb
);
1233 set_b_rx_z2(bcs
, f2
, z2
);
1234 // XXX always receive buffers of a given size
1239 hfcpci_b_recv_irq(struct hfcpci_adapter
*adapter
, int nr
)
1241 DBG(DBG_B_RECV
, "");
1243 switch (adapter
->bcs
[nr
].mode
) {
1249 hfcpci_b_recv_hdlc_irq(adapter
, nr
);
1253 hfcpci_b_recv_trans_irq(adapter
, nr
);
1258 // ----------------------------------------------------------------------
1261 // XXX make xmit FIFO deeper than 1
1264 hfcpci_d_xmit_irq(struct hfcpci_adapter
*adapter
)
1266 struct sk_buff
*skb
;
1268 DBG(DBG_D_XMIT
, "");
1270 skb
= adapter
->tx_skb
;
1276 adapter
->tx_skb
= NULL
;
1277 D_L1L2(adapter
, PH_DATA
| CONFIRM
, (void *) skb
->truesize
);
1278 dev_kfree_skb_irq(skb
);
1282 hfcpci_b_xmit_irq(struct hfcpci_adapter
*adapter
, int nr
)
1284 struct hfcpci_bcs
*bcs
= &adapter
->bcs
[nr
];
1285 struct sk_buff
*skb
;
1287 DBG(DBG_B_XMIT
, "");
1296 B_L1L2(bcs
, PH_DATA
| CONFIRM
, skb
);
1299 // ----------------------------------------------------------------------
1300 // Layer 1 state change IRQ
1303 hfcpci_state_irq(struct hfcpci_adapter
*adapter
)
1307 val
= hfcpci_readb(adapter
, HFCPCI_STATES
);
1308 DBG(DBG_L1M
, "STATES %#x", val
);
1309 FsmEvent(&adapter
->l1m
, val
& 0xf, NULL
);
1312 // ----------------------------------------------------------------------
1316 hfcpci_timer_irq(struct hfcpci_adapter
*adapter
)
1318 hfcpci_writeb(adapter
, adapter
->ctmt
| HFCPCI_CLTIMER
, HFCPCI_CTMT
);
1321 // ----------------------------------------------------------------------
1325 hfcpci_irq(int intno
, void *dev
, struct pt_regs
*regs
)
1327 struct hfcpci_adapter
*adapter
= dev
;
1331 if (!(adapter
->int_m2
& 0x08))
1332 return IRQ_NONE
; /* not initialised */ // XX
1334 stat
= hfcpci_readb(adapter
, HFCPCI_STATUS
);
1335 if (!(stat
& HFCPCI_ANYINT
))
1338 spin_lock(&adapter
->hw_lock
);
1339 while (loop
-- > 0) {
1340 val
= hfcpci_readb(adapter
, HFCPCI_INT_S1
);
1341 DBG(DBG_IRQ
, "stat %02x s1 %02x", stat
, val
);
1342 val
&= adapter
->int_m1
;
1348 hfcpci_b_recv_irq(adapter
, 0);
1351 hfcpci_b_recv_irq(adapter
, 1);
1354 hfcpci_b_xmit_irq(adapter
, 0);
1357 hfcpci_b_xmit_irq(adapter
, 1);
1360 hfcpci_d_recv_irq(adapter
);
1363 hfcpci_d_xmit_irq(adapter
);
1366 hfcpci_state_irq(adapter
);
1369 hfcpci_timer_irq(adapter
);
1371 spin_unlock(&adapter
->hw_lock
);
1375 // ----------------------------------------------------------------------
1379 hfcpci_reset(struct hfcpci_adapter
*adapter
)
1381 /* disable all interrupts */
1382 adapter
->int_m1
= 0;
1383 adapter
->int_m2
= 0;
1384 hfcpci_writeb(adapter
, adapter
->int_m1
, HFCPCI_INT_M1
);
1385 hfcpci_writeb(adapter
, adapter
->int_m2
, HFCPCI_INT_M2
);
1388 hfcpci_writeb(adapter
, HFCPCI_RESET
, HFCPCI_CIRM
);
1389 set_current_state(TASK_UNINTERRUPTIBLE
);
1390 schedule_timeout((30 * HZ
) / 1000);
1391 hfcpci_writeb(adapter
, 0, HFCPCI_CIRM
);
1392 set_current_state(TASK_UNINTERRUPTIBLE
);
1393 schedule_timeout((20 * HZ
) / 1000);
1394 if (hfcpci_readb(adapter
, HFCPCI_STATUS
) & 2) // XX
1395 printk(KERN_WARNING
"HFC-PCI init bit busy\n");
1398 // ----------------------------------------------------------------------
1402 hfcpci_hw_init(struct hfcpci_adapter
*adapter
)
1404 adapter
->fifo_en
= 0x30; /* only D fifos enabled */ // XX
1405 hfcpci_writeb(adapter
, adapter
->fifo_en
, HFCPCI_FIFO_EN
);
1407 /* no echo connect , threshold */
1408 adapter
->trm
= HFCPCI_BTRANS_THRESMASK
;
1409 hfcpci_writeb(adapter
, adapter
->trm
, HFCPCI_TRM
);
1411 /* ST-Bit delay for TE-Mode */
1412 hfcpci_writeb(adapter
, CLKDEL_TE
, HFCPCI_CLKDEL
);
1414 /* S/T Auto awake */
1415 adapter
->sctrl_e
= HFCPCI_AUTO_AWAKE
;
1416 hfcpci_writeb(adapter
, adapter
->sctrl_e
, HFCPCI_SCTRL_E
);
1419 adapter
->bswapped
= 0;
1420 /* we are in TE mode */
1421 adapter
->nt_mode
= 0;
1423 adapter
->ctmt
= HFCPCI_TIM3_125
| HFCPCI_AUTO_TIMER
;
1424 hfcpci_writeb(adapter
, adapter
->ctmt
, HFCPCI_CTMT
);
1426 adapter
->int_m1
= HFCPCI_INTS_DTRANS
| HFCPCI_INTS_DREC
|
1427 HFCPCI_INTS_L1STATE
;
1428 hfcpci_writeb(adapter
, adapter
->int_m1
, HFCPCI_INT_M1
);
1430 /* clear already pending ints */
1431 hfcpci_readb(adapter
, HFCPCI_INT_S1
);
1433 adapter
->l1m
.state
= 2;
1434 hfcpci_writeb(adapter
, HFCPCI_LOAD_STATE
| 2, HFCPCI_STATES
); // XX /* HFC ST 2 */
1436 hfcpci_writeb(adapter
, 2, HFCPCI_STATES
); /* HFC ST 2 */
1438 /* HFC Master Mode */
1439 adapter
->mst_m
= HFCPCI_MASTER
;
1440 hfcpci_writeb(adapter
, adapter
->mst_m
, HFCPCI_MST_MODE
);
1442 /* set tx_lo mode, error in datasheet ! */
1443 adapter
->sctrl
= 0x40;
1444 hfcpci_writeb(adapter
, adapter
->sctrl
, HFCPCI_SCTRL
);
1446 adapter
->sctrl_r
= 0;
1447 hfcpci_writeb(adapter
, adapter
->sctrl_r
, HFCPCI_SCTRL_R
);
1450 /* Init GCI/IOM2 in master mode */
1451 /* Slots 0 and 1 are set for B-chan 1 and 2 */
1452 /* D- and monitor/CI channel are not enabled */
1453 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
1454 /* STIO2 is used as data input, B1+B2 from IOM->ST */
1455 /* ST B-channel send disabled -> continous 1s */
1456 /* The IOM slots are always enabled */
1457 adapter
->conn
= 0; /* set data flow directions */
1458 hfcpci_writeb(adapter
, adapter
->conn
, HFCPCI_CONNECT
);
1459 hfcpci_writeb(adapter
, 0x80, HFCPCI_B1_SSL
); /* B1-Slot 0 STIO1 out enabled */
1460 hfcpci_writeb(adapter
, 0x81, HFCPCI_B2_SSL
); /* B2-Slot 1 STIO1 out enabled */
1461 hfcpci_writeb(adapter
, 0x80, HFCPCI_B1_RSL
); /* B1-Slot 0 STIO2 in enabled */
1462 hfcpci_writeb(adapter
, 0x81, HFCPCI_B2_RSL
); /* B2-Slot 1 STIO2 in enabled */
1464 /* Finally enable IRQ output */
1465 adapter
->int_m2
= HFCPCI_IRQ_ENABLE
;
1466 hfcpci_writeb(adapter
, adapter
->int_m2
, HFCPCI_INT_M2
);
1468 hfcpci_readb(adapter
, HFCPCI_INT_S2
);
1471 // ----------------------------------------------------------------------
1474 static struct hfcpci_adapter
* __devinit
1475 new_adapter(struct pci_dev
*pdev
)
1477 struct hfcpci_adapter
*adapter
;
1478 struct hisax_b_if
*b_if
[2];
1481 adapter
= kmalloc(sizeof(struct hfcpci_adapter
), GFP_KERNEL
);
1485 memset(adapter
, 0, sizeof(struct hfcpci_adapter
));
1487 adapter
->d_if
.owner
= THIS_MODULE
;
1488 adapter
->d_if
.ifc
.priv
= adapter
;
1489 adapter
->d_if
.ifc
.l2l1
= hfcpci_d_l2l1
;
1491 for (i
= 0; i
< 2; i
++) {
1492 adapter
->bcs
[i
].adapter
= adapter
;
1493 adapter
->bcs
[i
].channel
= i
;
1494 adapter
->bcs
[i
].b_if
.ifc
.priv
= &adapter
->bcs
[i
];
1495 adapter
->bcs
[i
].b_if
.ifc
.l2l1
= hfcpci_b_l2l1
;
1498 pci_set_drvdata(pdev
, adapter
);
1500 for (i
= 0; i
< 2; i
++)
1501 b_if
[i
] = &adapter
->bcs
[i
].b_if
;
1503 hisax_register(&adapter
->d_if
, b_if
, "hfcpci", protocol
);
1508 static void delete_adapter(struct hfcpci_adapter
*adapter
)
1510 hisax_unregister(&adapter
->d_if
);
1514 static int __devinit
hfcpci_probe(struct pci_dev
*pdev
,
1515 const struct pci_device_id
*ent
)
1517 struct hfcpci_adapter
*adapter
;
1522 adapter
= new_adapter(pdev
);
1526 retval
= pci_enable_device(pdev
);
1530 adapter
->irq
= pdev
->irq
;
1531 retval
= request_irq(adapter
->irq
, hfcpci_irq
, SA_SHIRQ
,
1537 if (!request_mem_region(pci_resource_start(pdev
, 1), 256, "hfcpci"))
1540 adapter
->mmio
= ioremap(pci_resource_start(pdev
, 1), 256); // XX pci_io
1542 goto err_release_region
;
1544 /* Allocate 32K for FIFOs */
1545 if (pci_set_dma_mask(pdev
, 0xffffffff))
1548 adapter
->fifo
= pci_alloc_consistent(pdev
, 32768, &adapter
->fifo_dma
);
1552 pci_write_config_dword(pdev
, HFCPCI_MWBA
, (u32
) adapter
->fifo_dma
);
1553 pci_set_master(pdev
);
1555 adapter
->l1m
.fsm
= &l1fsm
;
1556 adapter
->l1m
.state
= ST_L1_F0
;
1557 #ifdef CONFIG_HISAX_DEBUG
1558 adapter
->l1m
.debug
= 1;
1560 adapter
->l1m
.debug
= 0;
1562 adapter
->l1m
.userdata
= adapter
;
1563 adapter
->l1m
.printdebug
= l1m_debug
;
1564 FsmInitTimer(&adapter
->l1m
, &adapter
->timer
);
1566 hfcpci_reset(adapter
);
1567 hfcpci_hw_init(adapter
);
1569 printk(KERN_INFO
"hisax_hfcpci: found adapter %s at %s\n",
1570 (char *) ent
->driver_data
, pci_name(pdev
));
1575 iounmap(adapter
->mmio
);
1577 release_mem_region(pci_resource_start(pdev
, 1), 256);
1579 free_irq(adapter
->irq
, adapter
);
1581 delete_adapter(adapter
);
1586 static void __devexit
hfcpci_remove(struct pci_dev
*pdev
)
1588 struct hfcpci_adapter
*adapter
= pci_get_drvdata(pdev
);
1590 hfcpci_reset(adapter
);
1592 // del_timer(&cs->hw.hfcpci.timer); XX
1595 pci_disable_device(pdev
);
1596 pci_write_config_dword(pdev
, HFCPCI_MWBA
, 0);
1597 pci_free_consistent(pdev
, 32768, adapter
->fifo
, adapter
->fifo_dma
);
1599 iounmap(adapter
->mmio
);
1600 release_mem_region(pci_resource_start(pdev
, 1), 256);
1601 free_irq(adapter
->irq
, adapter
);
1602 delete_adapter(adapter
);
1605 static struct pci_driver hfcpci_driver
= {
1607 .probe
= hfcpci_probe
,
1608 .remove
= __devexit_p(hfcpci_remove
),
1609 .id_table
= hfcpci_ids
,
1612 static int __init
hisax_hfcpci_init(void)
1616 printk(KERN_INFO
"hisax_hfcpcipnp: HFC PCI ISDN driver v0.0.1\n");
1618 l1fsm
.state_count
= L1_STATE_COUNT
;
1619 l1fsm
.event_count
= L1_EVENT_COUNT
;
1620 l1fsm
.strState
= strL1State
;
1621 l1fsm
.strEvent
= strL1Event
;
1622 retval
= FsmNew(&l1fsm
, L1FnList
, ARRAY_SIZE(L1FnList
));
1626 retval
= pci_module_init(&hfcpci_driver
);
1638 static void __exit
hisax_hfcpci_exit(void)
1641 pci_unregister_driver(&hfcpci_driver
);
1644 module_init(hisax_hfcpci_init
);
1645 module_exit(hisax_hfcpci_exit
);