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[PATCH] update copyright and licensing
[linux-2.6/history.git] / drivers / video / sa1100fb.c
blob926b302f00d9da9f3370a60adc2ffb3ca16efbb5
1 /*
2 * linux/drivers/video/sa1100fb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas
5 * Based on acornfb.c Copyright (C) Russell King.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * StrongARM 1100 LCD Controller Frame Buffer Driver
12 *
13 * Please direct your questions and comments on this driver to the following
14 * email address:
15 *
16 * linux-arm-kernel@lists.arm.linux.org.uk
17 *
18 * Clean patches should be sent to the ARM Linux Patch System. Please see the
19 * following web page for more information:
20 *
21 * http://www.arm.linux.org.uk/developer/patches/info.shtml
22 *
23 * Thank you.
24 *
25 * Known problems:
26 * - With the Neponset plugged into an Assabet, LCD powerdown
27 * doesn't work (LCD stays powered up). Therefore we shouldn't
28 * blank the screen.
29 * - We don't limit the CPU clock rate nor the mode selection
30 * according to the available SDRAM bandwidth.
31 *
32 * Other notes:
33 * - Linear grayscale palettes and the kernel.
34 * Such code does not belong in the kernel. The kernel frame buffer
35 * drivers do not expect a linear colourmap, but a colourmap based on
36 * the VT100 standard mapping.
37 *
38 * If your _userspace_ requires a linear colourmap, then the setup of
39 * such a colourmap belongs _in userspace_, not in the kernel. Code
40 * to set the colourmap correctly from user space has been sent to
41 * David Neuer. It's around 8 lines of C code, plus another 4 to
42 * detect if we are using grayscale.
43 *
44 * - The following must never be specified in a panel definition:
45 * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
46 *
47 * - The following should be specified:
48 * either LCCR0_Color or LCCR0_Mono
49 * either LCCR0_Sngl or LCCR0_Dual
50 * either LCCR0_Act or LCCR0_Pas
51 * either LCCR3_OutEnH or LCCD3_OutEnL
52 * either LCCR3_PixRsEdg or LCCR3_PixFlEdg
53 * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
54 *
55 * Code Status:
56 * 1999/04/01:
57 * - Driver appears to be working for Brutus 320x200x8bpp mode. Other
58 * resolutions are working, but only the 8bpp mode is supported.
59 * Changes need to be made to the palette encode and decode routines
60 * to support 4 and 16 bpp modes.
61 * Driver is not designed to be a module. The FrameBuffer is statically
62 * allocated since dynamic allocation of a 300k buffer cannot be
63 * guaranteed.
64 *
65 * 1999/06/17:
66 * - FrameBuffer memory is now allocated at run-time when the
67 * driver is initialized.
68 *
69 * 2000/04/10: Nicolas Pitre <nico@cam.org>
70 * - Big cleanup for dynamic selection of machine type at run time.
71 *
72 * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
73 * - Support for Bitsy aka Compaq iPAQ H3600 added.
74 *
75 * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
76 * Jeff Sutherland <jsutherland@accelent.com>
77 * - Resolved an issue caused by a change made to the Assabet's PLD
78 * earlier this year which broke the framebuffer driver for newer
79 * Phase 4 Assabets. Some other parameters were changed to optimize
80 * for the Sharp display.
81 *
82 * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
83 * - XP860 support added
84 *
85 * 2000/08/19: Mark Huang <mhuang@livetoy.com>
86 * - Allows standard options to be passed on the kernel command line
87 * for most common passive displays.
88 *
89 * 2000/08/29:
90 * - s/save_flags_cli/local_irq_save/
91 * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
92 *
93 * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
94 * - Updated LART stuff. Fixed some minor bugs.
95 *
96 * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
97 * - Pangolin support added
98 *
99 * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
100 * - Huw Webpanel support added
101 *
102 * 2000/11/23: Eric Peng <ericpeng@coventive.com>
103 * - Freebird add
104 *
105 * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com>
106 * Cliff Brake <cbrake@accelent.com>
107 * - Added PM callback
108 *
109 * 2001/05/26: <rmk@arm.linux.org.uk>
110 * - Fix 16bpp so that (a) we use the right colours rather than some
111 * totally random colour depending on what was in page 0, and (b)
112 * we don't de-reference a NULL pointer.
113 * - remove duplicated implementation of consistent_alloc()
114 * - convert dma address types to dma_addr_t
115 * - remove unused 'montype' stuff
116 * - remove redundant zero inits of init_var after the initial
117 * memzero.
118 * - remove allow_modeset (acornfb idea does not belong here)
119 *
120 * 2001/05/28: <rmk@arm.linux.org.uk>
121 * - massive cleanup - move machine dependent data into structures
122 * - I've left various #warnings in - if you see one, and know
123 * the hardware concerned, please get in contact with me.
124 *
125 * 2001/05/31: <rmk@arm.linux.org.uk>
126 * - Fix LCCR1 HSW value, fix all machine type specifications to
127 * keep values in line. (Please check your machine type specs)
128 *
129 * 2001/06/10: <rmk@arm.linux.org.uk>
130 * - Fiddle with the LCD controller from task context only; mainly
131 * so that we can run with interrupts on, and sleep.
132 * - Convert #warnings into #errors. No pain, no gain. ;)
133 *
134 * 2001/06/14: <rmk@arm.linux.org.uk>
135 * - Make the palette BPS value for 12bpp come out correctly.
136 * - Take notice of "greyscale" on any colour depth.
137 * - Make truecolor visuals use the RGB channel encoding information.
138 *
139 * 2001/07/02: <rmk@arm.linux.org.uk>
140 * - Fix colourmap problems.
141 *
142 * 2001/07/13: <abraham@2d3d.co.za>
143 * - Added support for the ICP LCD-Kit01 on LART. This LCD is
144 * manufactured by Prime View, model no V16C6448AB
145 *
146 * 2001/07/23: <rmk@arm.linux.org.uk>
147 * - Hand merge version from handhelds.org CVS tree. See patch
148 * notes for 595/1 for more information.
149 * - Drop 12bpp (it's 16bpp with different colour register mappings).
150 * - This hardware can not do direct colour. Therefore we don't
151 * support it.
152 *
153 * 2001/07/27: <rmk@arm.linux.org.uk>
154 * - Halve YRES on dual scan LCDs.
155 *
156 * 2001/08/22: <rmk@arm.linux.org.uk>
157 * - Add b/w iPAQ pixclock value.
158 *
159 * 2001/10/12: <rmk@arm.linux.org.uk>
160 * - Add patch 681/1 and clean up stork definitions.
161 */
162
163 #include <linux/config.h>
164 #include <linux/module.h>
165 #include <linux/kernel.h>
166 #include <linux/sched.h>
167 #include <linux/errno.h>
168 #include <linux/string.h>
169 #include <linux/interrupt.h>
170 #include <linux/slab.h>
171 #include <linux/fb.h>
172 #include <linux/delay.h>
173 #include <linux/init.h>
174 #include <linux/ioport.h>
175 #include <linux/cpufreq.h>
176 #include <linux/device.h>
177 #include <linux/dma-mapping.h>
178
179 #include <asm/hardware.h>
180 #include <asm/io.h>
181 #include <asm/irq.h>
182 #include <asm/mach-types.h>
183 #include <asm/uaccess.h>
184 #include <asm/arch/assabet.h>
185 #include <asm/arch/shannon.h>
186
187 /*
188 * debugging?
189 */
190 #define DEBUG 0
191 /*
192 * Complain if VAR is out of range.
193 */
194 #define DEBUG_VAR 1
195
196 #undef ASSABET_PAL_VIDEO
197
198 #include "sa1100fb.h"
199
200 extern void (*sa1100fb_backlight_power)(int on);
201 extern void (*sa1100fb_lcd_power)(int on);
202
203 /*
204 * IMHO this looks wrong. In 8BPP, length should be 8.
205 */
206 static struct sa1100fb_rgb rgb_8 = {
207 .red = { .offset = 0, .length = 4, },
208 .green = { .offset = 0, .length = 4, },
209 .blue = { .offset = 0, .length = 4, },
210 .transp = { .offset = 0, .length = 0, },
211 };
212
213 static struct sa1100fb_rgb def_rgb_16 = {
214 .red = { .offset = 11, .length = 5, },
215 .green = { .offset = 5, .length = 6, },
216 .blue = { .offset = 0, .length = 5, },
217 .transp = { .offset = 0, .length = 0, },
218 };
219
220 #ifdef CONFIG_SA1100_ASSABET
221 #ifndef ASSABET_PAL_VIDEO
222 /*
223 * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
224 * takes an RGB666 signal, but we provide it with an RGB565 signal
225 * instead (def_rgb_16).
226 */
227 static struct sa1100fb_mach_info lq039q2ds54_info __initdata = {
228 .pixclock = 171521, .bpp = 16,
229 .xres = 320, .yres = 240,
230
231 .hsync_len = 5, .vsync_len = 1,
232 .left_margin = 61, .upper_margin = 3,
233 .right_margin = 9, .lower_margin = 0,
234
235 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
236
237 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
238 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
239 };
240 #else
241 static struct sa1100fb_mach_info pal_info __initdata = {
242 .pixclock = 67797, .bpp = 16,
243 .xres = 640, .yres = 512,
244
245 .hsync_len = 64, .vsync_len = 6,
246 .left_margin = 125, .upper_margin = 70,
247 .right_margin = 115, .lower_margin = 36,
248
249 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
250 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
251 };
252 #endif
253 #endif
254
255 #ifdef CONFIG_SA1100_H3800
256 static struct sa1100fb_mach_info h3800_info __initdata = {
257 .pixclock = 174757, .bpp = 16,
258 .xres = 320, .yres = 240,
259
260 .hsync_len = 3, .vsync_len = 3,
261 .left_margin = 12, .upper_margin = 10,
262 .right_margin = 17, .lower_margin = 1,
263
264 .cmap_static = 1,
265
266 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
267 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
268 };
269 #endif
270
271 #ifdef CONFIG_SA1100_H3600
272 static struct sa1100fb_mach_info h3600_info __initdata = {
273 .pixclock = 174757, .bpp = 16,
274 .xres = 320, .yres = 240,
275
276 .hsync_len = 3, .vsync_len = 3,
277 .left_margin = 12, .upper_margin = 10,
278 .right_margin = 17, .lower_margin = 1,
279
280 .cmap_static = 1,
281
282 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
283 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
284 };
285
286 static struct sa1100fb_rgb h3600_rgb_16 = {
287 .red = { .offset = 12, .length = 4, },
288 .green = { .offset = 7, .length = 4, },
289 .blue = { .offset = 1, .length = 4, },
290 .transp = { .offset = 0, .length = 0, },
291 };
292 #endif
293
294 #ifdef CONFIG_SA1100_H3100
295 static struct sa1100fb_mach_info h3100_info __initdata = {
296 .pixclock = 406977, .bpp = 4,
297 .xres = 320, .yres = 240,
298
299 .hsync_len = 26, .vsync_len = 41,
300 .left_margin = 4, .upper_margin = 0,
301 .right_margin = 4, .lower_margin = 0,
302
303 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
304 .cmap_greyscale = 1,
305 .cmap_inverse = 1,
306
307 .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
308 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
309 };
310 #endif
311
312 #ifdef CONFIG_SA1100_BRUTUS
313 static struct sa1100fb_mach_info brutus_info __initdata = {
314 .pixclock = 0, .bpp = 8,
315 .xres = 320, .yres = 240,
316
317 .hsync_len = 3, .vsync_len = 1,
318 .left_margin = 41, .upper_margin = 0,
319 .right_margin = 101, .lower_margin = 0,
320
321 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
322
323 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
324 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
325 LCCR3_PixClkDiv(44),
326 };
327 #endif
328
329 #ifdef CONFIG_SA1100_CERF
330 static struct sa1100fb_mach_info cerf_info __initdata = {
331 #if defined(CONFIG_CERF_LCD_72_A)
332 .pixclock = 171521, .bpp = 8,
333 .xres = 640, .yres = 480,
334 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
335 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
336 LCCR3_PixClkDiv(38),
337 #elif defined(CONFIG_CERF_LCD_57_A)
338 .pixclock = 171521, .bpp = 8,
339 .xres = 320, .yres = 240,
340 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
341 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
342 LCCR3_PixClkDiv(38),
343 #elif defined(CONFIG_CERF_LCD_38_A)
344 .pixclock = 171521, .bpp = 8,
345 .xres = 240, .yres = 320,
346 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
347 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(56) |
348 LCCR3_PixClkDiv(38),
349 #elif defined(CONFIG_CERF_LCD_38_B)
350 .pixclock = 171521, .bpp = 4,
351 .xres = 320, .yres = 240,
352 .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
353 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(56) |
354 LCCR3_PixClkDiv(38),
355 #else
356 #error "Must have a CerfBoard LCD form factor selected"
357 #endif
358
359 .hsync_len = 5, .vsync_len = 1,
360 .left_margin = 61, .upper_margin = 3,
361 .right_margin = 9, .lower_margin = 0,
362
363 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
364
365 };
366
367 #if 0
368 static struct sa1100fb_rgb cerf_rgb_16 = {
369 .red = { .offset = 8, .length = 4, },
370 .green = { .offset = 4, .length = 4, },
371 .blue = { .offset = 0, .length = 4, },
372 .transp = { .offset = 0, .length = 0, },
373 };
374 #endif
375 #endif
376
377 #ifdef CONFIG_SA1100_FREEBIRD
378 #warning Please check this carefully
379 static struct sa1100fb_mach_info freebird_info __initdata = {
380 .pixclock = 171521, .bpp = 16,
381 .xres = 240, .yres = 320,
382
383 .hsync_len = 3, .vsync_len = 2,
384 .left_margin = 2, .upper_margin = 0,
385 .right_margin = 2, .lower_margin = 0,
386
387 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
388
389 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
390 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(2),
391 };
392
393 static struct sa1100fb_rgb freebird_rgb_16 = {
394 .red = { .offset = 8, .length = 4, },
395 .green = { .offset = 4, .length = 4, },
396 .blue = { .offset = 0, .length = 4, },
397 .transp = { .offset = 12, .length = 4, },
398 };
399 #endif
400
401 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
402 static struct sa1100fb_mach_info graphicsclient_info __initdata = {
403 .pixclock = 53500, .bpp = 8,
404 .xres = 640, .yres = 480,
405
406 .hsync_len = 9, .vsync_len = 9,
407 .left_margin = 54, .upper_margin = 24,
408 .right_margin = 54, .lower_margin = 32,
409
410 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
411 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
412 };
413 #endif
414
415 #ifdef CONFIG_SA1100_HUW_WEBPANEL
416 static struct sa1100fb_mach_info huw_webpanel_info __initdata = {
417 .pixclock = 0, .bpp = 8,
418 .xres = 640, .yres = 480,
419
420 .hsync_len = 3, .vsync_len = 1,
421 .left_margin = 41, .upper_margin = 0,
422 .right_margin = 101, .lower_margin = 0,
423
424 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
425
426 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
427 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) | 8,
428 #error FIXME
429 /*
430 * FIXME: please get rid of the '| 8' in preference to an
431 * LCCR3_PixClkDiv() version. --rmk
432 */
433 };
434 #endif
435
436 #ifdef LART_GREY_LCD
437 static struct sa1100fb_mach_info lart_grey_info __initdata = {
438 .pixclock = 150000, .bpp = 4,
439 .xres = 320, .yres = 240,
440
441 .hsync_len = 1, .vsync_len = 1,
442 .left_margin = 4, .upper_margin = 0,
443 .right_margin = 2, .lower_margin = 0,
444
445 .cmap_greyscale = 1,
446 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
447
448 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
449 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
450 };
451 #endif
452 #ifdef LART_COLOR_LCD
453 static struct sa1100fb_mach_info lart_color_info __initdata = {
454 .pixclock = 150000, .bpp = 16,
455 .xres = 320, .yres = 240,
456
457 .hsync_len = 2, .vsync_len = 3,
458 .left_margin = 69, .upper_margin = 14,
459 .right_margin = 8, .lower_margin = 4,
460
461 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
462 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
463 };
464 #endif
465 #ifdef LART_VIDEO_OUT
466 static struct sa1100fb_mach_info lart_video_info __initdata = {
467 .pixclock = 39721, .bpp = 16,
468 .xres = 640, .yres = 480,
469
470 .hsync_len = 95, .vsync_len = 2,
471 .left_margin = 40, .upper_margin = 32,
472 .right_margin = 24, .lower_margin = 11,
473
474 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
475
476 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
477 .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
478 };
479 #endif
480
481 #ifdef LART_KIT01_LCD
482 static struct sa1100fb_mach_info lart_kit01_info __initdata = {
483 .pixclock = 63291, .bpp = 16,
484 .xres = 640, .yres = 480,
485
486 .hsync_len = 64, .vsync_len = 3,
487 .left_margin = 122, .upper_margin = 45,
488 .right_margin = 10, .lower_margin = 10,
489
490 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
491 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
492 };
493 #endif
494
495 #ifdef CONFIG_SA1100_SHANNON
496 static struct sa1100fb_mach_info shannon_info __initdata = {
497 .pixclock = 152500, .bpp = 8,
498 .xres = 640, .yres = 480,
499
500 .hsync_len = 4, .vsync_len = 3,
501 .left_margin = 2, .upper_margin = 0,
502 .right_margin = 1, .lower_margin = 0,
503
504 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
505
506 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
507 .lccr3 = LCCR3_ACBsDiv(512),
508 };
509 #endif
510
511 #ifdef CONFIG_SA1100_OMNIMETER
512 static struct sa1100fb_mach_info omnimeter_info __initdata = {
513 .pixclock = 0, .bpp = 4,
514 .xres = 480, .yres = 320,
515
516 .hsync_len = 1, .vsync_len = 1,
517 .left_margin = 10, .upper_margin = 0,
518 .right_margin = 10, .lower_margin = 0,
519
520 .cmap_greyscale = 1,
521 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
522
523 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_8PixMono,
524 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(255) |
525 LCCR3_PixClkDiv(44),
526 #error FIXME: fix pixclock, ACBsDiv
527 /*
528 * FIXME: I think ACBsDiv is wrong above - should it be 512 (disabled)?
529 * - rmk
530 */
531 };
532 #endif
533
534 #ifdef CONFIG_SA1100_PANGOLIN
535 static struct sa1100fb_mach_info pangolin_info __initdata = {
536 .pixclock = 341521, .bpp = 16,
537 .xres = 800, .yres = 600,
538
539 .hsync_len = 64, .vsync_len = 7,
540 .left_margin = 160, .upper_margin = 7,
541 .right_margin = 24, .lower_margin = 1,
542
543 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
544
545 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
546 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsCntOff,
547 };
548 #endif
549
550 #ifdef CONFIG_SA1100_STORK
551 #if STORK_TFT /* ie the NEC TFT */
552 /*
553 * pixclock is ps per clock. say 72Hz, 800x600 clocks => (1/72)/(800*600)
554 * = 28935 and a bit
555 * NB likely to be increased to ease bus timings wrt pcmcia interface
556 */
557 static struct sa1100fb_mach_info stork_tft_info __initdata = {
558 .pixclock = 28935, .bpp = 16,
559 .xres = 640, .yres = 480,
560
561 .hsync_len = 64, .vsync_len = 2,
562 .left_margin = 48, .upper_margin = 12,
563 .right_margin = 48, .lower_margin = 31,
564
565 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
566 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsCntOff,
567 };
568
569 static struct sa1100fb_rgb stork_tft_rgb_16 = {
570 .red = { .offset = 11, .length = 5, },
571 .green = { .offset = 5, .length = 6, },
572 .blue = { .offset = 0, .length = 5, },
573 .transp = { .offset = 0, .length = 0, },
574 };
575
576 #else /* Kyocera DSTN */
577
578 static struct sa1100fb_mach_info stork_dstn_info __initdata = {
579 .pixclock = 0, .bpp = 16,
580 .xres = 640, .yres = 480,
581
582 .hsync_len = 2, .vsync_len = 2,
583 .left_margin = 2, .upper_margin = 0,
584 .right_margin = 2, .lower_margin = 0,
585
586 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT ,
587
588 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
589 #error Fixme
590 .lccr3 = 0xff00 |
591 0x18 /* ought to be 0x14 but DMA isn't up to that as yet */
592 };
593
594 static struct sa1100fb_rgb stork_dstn_rgb_16 = {
595 .red = { .offset = 8, .length = 4, },
596 .green = { .offset = 4, .length = 4, },
597 .blue = { .offset = 0, .length = 4, },
598 .transp = { .offset = 0, .length = 0, },
599 };
600 #endif
601 #endif
602
603 #ifdef CONFIG_SA1100_PT_SYSTEM3
604 /*
605 * 648 x 480 x 8bpp x 75Hz Dual Panel Color STN Display
606 *
607 * pixclock = 1/( 640*3/8*240 ), [pixclock]=1e-12s=ps
608 * 3 due to r,g,b lines
609 * 8 due to 8 bit data bus
610 * 640 due to 640 pixels per line
611 * 240 = 480/2 due to dual panel display
612 * =>4.32Mhz => 231481E-12s
613 */
614 static struct sa1100fb_mach_info system3_info __initdata = {
615 .pixclock = 231481, .bpp = 8,
616 .xres = 640, .yres = 480,
617
618 .hsync_len = 2, .vsync_len = 2,
619 .left_margin = 2, .upper_margin = 0,
620 .right_margin = 2, .lower_margin = 0,
621
622 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
623
624 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
625 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
626 };
627 #endif
628
629 #ifdef CONFIG_SA1100_XP860
630 static struct sa1100fb_mach_info xp860_info __initdata = {
631 .pixclock = 0, .bpp = 8,
632 .xres = 1024, .yres = 768,
633
634 .hsync_len = 3, .vsync_len = 3,
635 .left_margin = 3, .upper_margin = 2,
636 .right_margin = 2, .lower_margin = 1,
637
638 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
639 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_PixClkDiv(6),
640 };
641 #endif
642
643
644
645 static struct sa1100fb_mach_info * __init
646 sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
647 {
648 struct sa1100fb_mach_info *inf = NULL;
649
650 /*
651 * R G B T
652 * default {11,5}, { 5,6}, { 0,5}, { 0,0}
653 * h3600 {12,4}, { 7,4}, { 1,4}, { 0,0}
654 * freebird { 8,4}, { 4,4}, { 0,4}, {12,4}
655 */
656 #ifdef CONFIG_SA1100_ASSABET
657 if (machine_is_assabet()) {
658 #ifndef ASSABET_PAL_VIDEO
659 inf = &lq039q2ds54_info;
660 #else
661 inf = &pal_info;
662 #endif
663 }
664 #endif
665 #ifdef CONFIG_SA1100_H3100
666 if (machine_is_h3100()) {
667 inf = &h3100_info;
668 }
669 #endif
670 #ifdef CONFIG_SA1100_H3600
671 if (machine_is_h3600()) {
672 inf = &h3600_info;
673 fbi->rgb[RGB_16] = &h3600_rgb_16;
674 }
675 #endif
676 #ifdef CONFIG_SA1100_H3800
677 if (machine_is_h3800()) {
678 inf = &h3800_info;
679 }
680 #endif
681 #ifdef CONFIG_SA1100_BRUTUS
682 if (machine_is_brutus()) {
683 inf = &brutus_info;
684 }
685 #endif
686 #ifdef CONFIG_SA1100_CERF
687 if (machine_is_cerf()) {
688 inf = &cerf_info;
689 }
690 #endif
691 #ifdef CONFIG_SA1100_FREEBIRD
692 if (machine_is_freebird()) {
693 inf = &freebird_info;
694 fbi->rgb[RGB_16] = &freebird_rgb16;
695 }
696 #endif
697 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
698 if (machine_is_graphicsclient()) {
699 inf = &graphicsclient_info;
700 }
701 #endif
702 #ifdef CONFIG_SA1100_HUW_WEBPANEL
703 if (machine_is_huw_webpanel()) {
704 inf = &huw_webpanel_info;
705 }
706 #endif
707 #ifdef CONFIG_SA1100_LART
708 if (machine_is_lart()) {
709 #ifdef LART_GREY_LCD
710 inf = &lart_grey_info;
711 #endif
712 #ifdef LART_COLOR_LCD
713 inf = &lart_color_info;
714 #endif
715 #ifdef LART_VIDEO_OUT
716 inf = &lart_video_info;
717 #endif
718 #ifdef LART_KIT01_LCD
719 inf = &lart_kit01_info;
720 #endif
721 }
722 #endif
723 #ifdef CONFIG_SA1100_OMNIMETER
724 if (machine_is_omnimeter()) {
725 inf = &omnimeter_info;
726 }
727 #endif
728 #ifdef CONFIG_SA1100_PANGOLIN
729 if (machine_is_pangolin()) {
730 inf = &pangolin_info;
731 }
732 #endif
733 #ifdef CONFIG_SA1100_PT_SYSTEM3
734 if (machine_is_pt_system3()) {
735 inf = &system3_info;
736 }
737 #endif
738 #ifdef CONFIG_SA1100_SHANNON
739 if (machine_is_shannon()) {
740 inf = &shannon_info;
741 }
742 #endif
743 #ifdef CONFIG_SA1100_STORK
744 if (machine_is_stork()) {
745 #if STORK_TFT
746 inf = &stork_tft_info;
747 fbi->rgb[RGB_16] = &stork_tft_rgb_16;
748 #else
749 inf = &stork_dstn_info;
750 fbi->rgb[RGB_16] = &stork_dstn_rgb_16;
751 #endif
752 }
753 #endif
754 #ifdef CONFIG_SA1100_XP860
755 if (machine_is_xp860()) {
756 inf = &xp860_info;
757 }
758 #endif
759 return inf;
760 }
761
762 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
763 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
764
765 static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
766 {
767 unsigned long flags;
768
769 local_irq_save(flags);
770 /*
771 * We need to handle two requests being made at the same time.
772 * There are two important cases:
773 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
774 * We must perform the unblanking, which will do our REENABLE for us.
775 * 2. When we are blanking, but immediately unblank before we have
776 * blanked. We do the "REENABLE" thing here as well, just to be sure.
777 */
778 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
779 state = (u_int) -1;
780 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
781 state = C_REENABLE;
782
783 if (state != (u_int)-1) {
784 fbi->task_state = state;
785 schedule_work(&fbi->task);
786 }
787 local_irq_restore(flags);
788 }
789
790 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
791 {
792 chan &= 0xffff;
793 chan >>= 16 - bf->length;
794 return chan << bf->offset;
795 }
796
797 /*
798 * Convert bits-per-pixel to a hardware palette PBS value.
799 */
800 static inline u_int palette_pbs(struct fb_var_screeninfo *var)
801 {
802 int ret = 0;
803 switch (var->bits_per_pixel) {
804 case 4: ret = 0 << 12; break;
805 case 8: ret = 1 << 12; break;
806 case 16: ret = 2 << 12; break;
807 }
808 return ret;
809 }
810
811 static int
812 sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
813 u_int trans, struct fb_info *info)
814 {
815 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
816 u_int val, ret = 1;
817
818 if (regno < fbi->palette_size) {
819 val = ((red >> 4) & 0xf00);
820 val |= ((green >> 8) & 0x0f0);
821 val |= ((blue >> 12) & 0x00f);
822
823 if (regno == 0)
824 val |= palette_pbs(&fbi->fb.var);
825
826 fbi->palette_cpu[regno] = val;
827 ret = 0;
828 }
829 return ret;
830 }
831
832 static int
833 sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
834 u_int trans, struct fb_info *info)
835 {
836 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
837 unsigned int val;
838 int ret = 1;
839
840 /*
841 * If inverse mode was selected, invert all the colours
842 * rather than the register number. The register number
843 * is what you poke into the framebuffer to produce the
844 * colour you requested.
845 */
846 if (fbi->cmap_inverse) {
847 red = 0xffff - red;
848 green = 0xffff - green;
849 blue = 0xffff - blue;
850 }
851
852 /*
853 * If greyscale is true, then we convert the RGB value
854 * to greyscale no mater what visual we are using.
855 */
856 if (fbi->fb.var.grayscale)
857 red = green = blue = (19595 * red + 38470 * green +
858 7471 * blue) >> 16;
859
860 switch (fbi->fb.fix.visual) {
861 case FB_VISUAL_TRUECOLOR:
862 /*
863 * 12 or 16-bit True Colour. We encode the RGB value
864 * according to the RGB bitfield information.
865 */
866 if (regno < 16) {
867 u32 *pal = fbi->fb.pseudo_palette;
868
869 val = chan_to_field(red, &fbi->fb.var.red);
870 val |= chan_to_field(green, &fbi->fb.var.green);
871 val |= chan_to_field(blue, &fbi->fb.var.blue);
872
873 pal[regno] = val;
874 ret = 0;
875 }
876 break;
877
878 case FB_VISUAL_STATIC_PSEUDOCOLOR:
879 case FB_VISUAL_PSEUDOCOLOR:
880 ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
881 break;
882 }
883
884 return ret;
885 }
886
887 /*
888 * sa1100fb_display_dma_period()
889 * Calculate the minimum period (in picoseconds) between two DMA
890 * requests for the LCD controller. If we hit this, it means we're
891 * doing nothing but LCD DMA.
892 */
893 static unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
894 {
895 /*
896 * Period = pixclock * bits_per_byte * bytes_per_transfer
897 * / memory_bits_per_pixel;
898 */
899 return var->pixclock * 8 * 16 / var->bits_per_pixel;
900 }
901
902 /*
903 * sa1100fb_check_var():
904 * Round up in the following order: bits_per_pixel, xres,
905 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
906 * bitfields, horizontal timing, vertical timing.
907 */
908 static int
909 sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
910 {
911 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
912 int rgbidx;
913
914 if (var->xres < MIN_XRES)
915 var->xres = MIN_XRES;
916 if (var->yres < MIN_YRES)
917 var->yres = MIN_YRES;
918 if (var->xres > fbi->max_xres)
919 var->xres = fbi->max_xres;
920 if (var->yres > fbi->max_yres)
921 var->yres = fbi->max_yres;
922 var->xres_virtual = max(var->xres_virtual, var->xres);
923 var->yres_virtual = max(var->yres_virtual, var->yres);
924
925 DPRINTK("var->bits_per_pixel=%d\n", var->bits_per_pixel);
926 switch (var->bits_per_pixel) {
927 case 4:
928 rgbidx = RGB_8;
929 break;
930 case 8:
931 rgbidx = RGB_8;
932 break;
933 case 16:
934 rgbidx = RGB_16;
935 break;
936 default:
937 return -EINVAL;
938 }
939
940 /*
941 * Copy the RGB parameters for this display
942 * from the machine specific parameters.
943 */
944 var->red = fbi->rgb[rgbidx]->red;
945 var->green = fbi->rgb[rgbidx]->green;
946 var->blue = fbi->rgb[rgbidx]->blue;
947 var->transp = fbi->rgb[rgbidx]->transp;
948
949 DPRINTK("RGBT length = %d:%d:%d:%d\n",
950 var->red.length, var->green.length, var->blue.length,
951 var->transp.length);
952
953 DPRINTK("RGBT offset = %d:%d:%d:%d\n",
954 var->red.offset, var->green.offset, var->blue.offset,
955 var->transp.offset);
956
957 #ifdef CONFIG_CPU_FREQ
958 printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz\n",
959 sa1100fb_display_dma_period(var),
960 cpufreq_get(smp_processor_id()));
961 #endif
962
963 return 0;
964 }
965
966 static inline void sa1100fb_set_truecolor(u_int is_true_color)
967 {
968 if (machine_is_assabet()) {
969 #if 1 // phase 4 or newer Assabet's
970 if (is_true_color)
971 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
972 else
973 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
974 #else
975 // older Assabet's
976 if (is_true_color)
977 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
978 else
979 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
980 #endif
981 }
982 }
983
984 /*
985 * sa1100fb_set_par():
986 * Set the user defined part of the display for the specified console
987 */
988 static int sa1100fb_set_par(struct fb_info *info)
989 {
990 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
991 struct fb_var_screeninfo *var = &info->var;
992 unsigned long palette_mem_size;
993
994 DPRINTK("set_par\n");
995
996 if (var->bits_per_pixel == 16)
997 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
998 else if (!fbi->cmap_static)
999 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
1000 else {
1001 /*
1002 * Some people have weird ideas about wanting static
1003 * pseudocolor maps. I suspect their user space
1004 * applications are broken.
1005 */
1006 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
1007 }
1008
1009 fbi->fb.fix.line_length = var->xres_virtual *
1010 var->bits_per_pixel / 8;
1011 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
1012
1013 palette_mem_size = fbi->palette_size * sizeof(u16);
1014
1015 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
1016
1017 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1018 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1019
1020 /*
1021 * Set (any) board control register to handle new color depth
1022 */
1023 sa1100fb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
1024
1025 #ifdef CONFIG_SA1100_OMNIMETER
1026 #error Do we have to do this here? We already do it at init time.
1027 if (machine_is_omnimeter())
1028 SetLCDContrast(DefaultLCDContrast);
1029 #endif
1030
1031 sa1100fb_activate_var(var, fbi);
1032
1033 return 0;
1034 }
1035
1036 #if 0
1037 static int
1038 sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
1039 struct fb_info *info)
1040 {
1041 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
1042
1043 /*
1044 * Make sure the user isn't doing something stupid.
1045 */
1046 if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->cmap_static))
1047 return -EINVAL;
1048
1049 return gen_set_cmap(cmap, kspc, con, info);
1050 }
1051 #endif
1052
1053 /*
1054 * Formal definition of the VESA spec:
1055 * On
1056 * This refers to the state of the display when it is in full operation
1057 * Stand-By
1058 * This defines an optional operating state of minimal power reduction with
1059 * the shortest recovery time
1060 * Suspend
1061 * This refers to a level of power management in which substantial power
1062 * reduction is achieved by the display. The display can have a longer
1063 * recovery time from this state than from the Stand-by state
1064 * Off
1065 * This indicates that the display is consuming the lowest level of power
1066 * and is non-operational. Recovery from this state may optionally require
1067 * the user to manually power on the monitor
1068 *
1069 * Now, the fbdev driver adds an additional state, (blank), where they
1070 * turn off the video (maybe by colormap tricks), but don't mess with the
1071 * video itself: think of it semantically between on and Stand-By.
1072 *
1073 * So here's what we should do in our fbdev blank routine:
1074 *
1075 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
1076 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
1077 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
1078 * VESA_POWERDOWN (mode 3) Video off, front/back light off
1079 *
1080 * This will match the matrox implementation.
1081 */
1082 /*
1083 * sa1100fb_blank():
1084 * Blank the display by setting all palette values to zero. Note, the
1085 * 12 and 16 bpp modes don't really use the palette, so this will not
1086 * blank the display in all modes.
1087 */
1088 static int sa1100fb_blank(int blank, struct fb_info *info)
1089 {
1090 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
1091 int i;
1092
1093 DPRINTK("sa1100fb_blank: blank=%d\n", blank);
1094
1095 switch (blank) {
1096 case VESA_POWERDOWN:
1097 case VESA_VSYNC_SUSPEND:
1098 case VESA_HSYNC_SUSPEND:
1099 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
1100 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
1101 for (i = 0; i < fbi->palette_size; i++)
1102 sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
1103 sa1100fb_schedule_work(fbi, C_DISABLE);
1104 break;
1105
1106 case VESA_NO_BLANKING:
1107 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
1108 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
1109 fb_set_cmap(&fbi->fb.cmap, 1, info);
1110 sa1100fb_schedule_work(fbi, C_ENABLE);
1111 }
1112 return 0;
1113 }
1114
1115 static struct fb_ops sa1100fb_ops = {
1116 .owner = THIS_MODULE,
1117 .fb_check_var = sa1100fb_check_var,
1118 .fb_set_par = sa1100fb_set_par,
1119 // .fb_set_cmap = sa1100fb_set_cmap,
1120 .fb_setcolreg = sa1100fb_setcolreg,
1121 .fb_fillrect = cfb_fillrect,
1122 .fb_copyarea = cfb_copyarea,
1123 .fb_imageblit = cfb_imageblit,
1124 .fb_blank = sa1100fb_blank,
1125 .fb_cursor = soft_cursor,
1126 };
1127
1128 /*
1129 * Calculate the PCD value from the clock rate (in picoseconds).
1130 * We take account of the PPCR clock setting.
1131 */
1132 static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock)
1133 {
1134 unsigned int pcd = cpuclock / 100;
1135
1136 pcd *= pixclock;
1137 pcd /= 10000000;
1138
1139 return pcd + 1; /* make up for integer math truncations */
1140 }
1141
1142 /*
1143 * sa1100fb_activate_var():
1144 * Configures LCD Controller based on entries in var parameter. Settings are
1145 * only written to the controller if changes were made.
1146 */
1147 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
1148 {
1149 struct sa1100fb_lcd_reg new_regs;
1150 u_int half_screen_size, yres, pcd;
1151 u_long flags;
1152
1153 DPRINTK("Configuring SA1100 LCD\n");
1154
1155 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
1156 var->xres, var->hsync_len,
1157 var->left_margin, var->right_margin);
1158 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
1159 var->yres, var->vsync_len,
1160 var->upper_margin, var->lower_margin);
1161
1162 #if DEBUG_VAR
1163 if (var->xres < 16 || var->xres > 1024)
1164 printk(KERN_ERR "%s: invalid xres %d\n",
1165 fbi->fb.fix.id, var->xres);
1166 if (var->hsync_len < 1 || var->hsync_len > 64)
1167 printk(KERN_ERR "%s: invalid hsync_len %d\n",
1168 fbi->fb.fix.id, var->hsync_len);
1169 if (var->left_margin < 1 || var->left_margin > 255)
1170 printk(KERN_ERR "%s: invalid left_margin %d\n",
1171 fbi->fb.fix.id, var->left_margin);
1172 if (var->right_margin < 1 || var->right_margin > 255)
1173 printk(KERN_ERR "%s: invalid right_margin %d\n",
1174 fbi->fb.fix.id, var->right_margin);
1175 if (var->yres < 1 || var->yres > 1024)
1176 printk(KERN_ERR "%s: invalid yres %d\n",
1177 fbi->fb.fix.id, var->yres);
1178 if (var->vsync_len < 1 || var->vsync_len > 64)
1179 printk(KERN_ERR "%s: invalid vsync_len %d\n",
1180 fbi->fb.fix.id, var->vsync_len);
1181 if (var->upper_margin < 0 || var->upper_margin > 255)
1182 printk(KERN_ERR "%s: invalid upper_margin %d\n",
1183 fbi->fb.fix.id, var->upper_margin);
1184 if (var->lower_margin < 0 || var->lower_margin > 255)
1185 printk(KERN_ERR "%s: invalid lower_margin %d\n",
1186 fbi->fb.fix.id, var->lower_margin);
1187 #endif
1188
1189 new_regs.lccr0 = fbi->lccr0 |
1190 LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
1191 LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
1192
1193 new_regs.lccr1 =
1194 LCCR1_DisWdth(var->xres) +
1195 LCCR1_HorSnchWdth(var->hsync_len) +
1196 LCCR1_BegLnDel(var->left_margin) +
1197 LCCR1_EndLnDel(var->right_margin);
1198
1199 /*
1200 * If we have a dual scan LCD, then we need to halve
1201 * the YRES parameter.
1202 */
1203 yres = var->yres;
1204 if (fbi->lccr0 & LCCR0_Dual)
1205 yres /= 2;
1206
1207 new_regs.lccr2 =
1208 LCCR2_DisHght(yres) +
1209 LCCR2_VrtSnchWdth(var->vsync_len) +
1210 LCCR2_BegFrmDel(var->upper_margin) +
1211 LCCR2_EndFrmDel(var->lower_margin);
1212
1213 pcd = get_pcd(var->pixclock, cpufreq_get(0));
1214 new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->lccr3 |
1215 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
1216 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1217
1218 DPRINTK("nlccr0 = 0x%08lx\n", new_regs.lccr0);
1219 DPRINTK("nlccr1 = 0x%08lx\n", new_regs.lccr1);
1220 DPRINTK("nlccr2 = 0x%08lx\n", new_regs.lccr2);
1221 DPRINTK("nlccr3 = 0x%08lx\n", new_regs.lccr3);
1222
1223 half_screen_size = var->bits_per_pixel;
1224 half_screen_size = half_screen_size * var->xres * var->yres / 16;
1225
1226 /* Update shadow copy atomically */
1227 local_irq_save(flags);
1228 fbi->dbar1 = fbi->palette_dma;
1229 fbi->dbar2 = fbi->screen_dma + half_screen_size;
1230
1231 fbi->reg_lccr0 = new_regs.lccr0;
1232 fbi->reg_lccr1 = new_regs.lccr1;
1233 fbi->reg_lccr2 = new_regs.lccr2;
1234 fbi->reg_lccr3 = new_regs.lccr3;
1235 local_irq_restore(flags);
1236
1237 /*
1238 * Only update the registers if the controller is enabled
1239 * and something has changed.
1240 */
1241 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
1242 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
1243 (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
1244 sa1100fb_schedule_work(fbi, C_REENABLE);
1245
1246 return 0;
1247 }
1248
1249 /*
1250 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1251 * Do not call them directly; set_ctrlr_state does the correct serialisation
1252 * to ensure that things happen in the right way 100% of time time.
1253 * -- rmk
1254 */
1255 static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
1256 {
1257 DPRINTK("backlight o%s\n", on ? "n" : "ff");
1258
1259 if (sa1100fb_backlight_power)
1260 sa1100fb_backlight_power(on);
1261 }
1262
1263 static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
1264 {
1265 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
1266
1267 if (sa1100fb_lcd_power)
1268 sa1100fb_lcd_power(on);
1269 }
1270
1271 static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
1272 {
1273 u_int mask = 0;
1274
1275 /*
1276 * Enable GPIO<9:2> for LCD use if:
1277 * 1. Active display, or
1278 * 2. Color Dual Passive display
1279 *
1280 * see table 11.8 on page 11-27 in the SA1100 manual
1281 * -- Erik.
1282 *
1283 * SA1110 spec update nr. 25 says we can and should
1284 * clear LDD15 to 12 for 4 or 8bpp modes with active
1285 * panels.
1286 */
1287 if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
1288 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
1289 mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
1290
1291 if (fbi->fb.var.bits_per_pixel > 8 ||
1292 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
1293 mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
1294
1295 }
1296
1297 /* GPIO15 is used as a bypass for 3.8" displays */
1298 if (machine_is_cerf())
1299 mask |= GPIO_GPIO15;
1300
1301 if (mask) {
1302 GPDR |= mask;
1303 GAFR |= mask;
1304 }
1305 }
1306
1307 static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
1308 {
1309 DPRINTK("Enabling LCD controller\n");
1310
1311 /*
1312 * Make sure the mode bits are present in the first palette entry
1313 */
1314 fbi->palette_cpu[0] &= 0xcfff;
1315 fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
1316
1317 /* Sequence from 11.7.10 */
1318 LCCR3 = fbi->reg_lccr3;
1319 LCCR2 = fbi->reg_lccr2;
1320 LCCR1 = fbi->reg_lccr1;
1321 LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
1322 DBAR1 = fbi->dbar1;
1323 DBAR2 = fbi->dbar2;
1324 LCCR0 |= LCCR0_LEN;
1325
1326 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
1327 #error Where is GPIO24 set as an output? Can we fit this in somewhere else?
1328 if (machine_is_graphicsclient()) {
1329 // From ADS doc again...same as disable
1330 set_current_state(TASK_UNINTERRUPTIBLE);
1331 schedule_timeout(20 * HZ / 1000);
1332 GPSR |= GPIO_GPIO24;
1333 }
1334 #endif
1335
1336 if (machine_is_shannon()) {
1337 GPDR |= SHANNON_GPIO_DISP_EN;
1338 GPSR |= SHANNON_GPIO_DISP_EN;
1339 }
1340
1341 DPRINTK("DBAR1 = 0x%08x\n", DBAR1);
1342 DPRINTK("DBAR2 = 0x%08x\n", DBAR2);
1343 DPRINTK("LCCR0 = 0x%08x\n", LCCR0);
1344 DPRINTK("LCCR1 = 0x%08x\n", LCCR1);
1345 DPRINTK("LCCR2 = 0x%08x\n", LCCR2);
1346 DPRINTK("LCCR3 = 0x%08x\n", LCCR3);
1347 }
1348
1349 static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
1350 {
1351 DECLARE_WAITQUEUE(wait, current);
1352
1353 DPRINTK("Disabling LCD controller\n");
1354
1355 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
1356 #error Where is GPIO24 set as an output? Can we fit this in somewhere else?
1357 if (machine_is_graphicsclient()) {
1358 /*
1359 * From ADS internal document:
1360 * GPIO24 should be LOW at least 10msec prior to disabling
1361 * the LCD interface.
1362 *
1363 * We'll wait 20msec.
1364 */
1365 GPCR |= GPIO_GPIO24;
1366 set_current_state(TASK_UNINTERRUPTIBLE);
1367 schedule_timeout(20 * HZ / 1000);
1368 }
1369 #endif
1370 #ifdef CONFIG_SA1100_HUW_WEBPANEL
1371 #error Move me into __sa1100fb_lcd_power and/or __sa1100fb_backlight_power
1372 if (machine_is_huw_webpanel()) {
1373 // don't forget to set the control lines to zero (?)
1374 DPRINTK("ShutDown HuW LCD controller\n");
1375 BCR_clear(BCR_TFT_ENA + BCR_CCFL_POW + BCR_PWM_BACKLIGHT);
1376 }
1377 #endif
1378
1379 if (machine_is_shannon()) {
1380 GPCR |= SHANNON_GPIO_DISP_EN;
1381 }
1382
1383 add_wait_queue(&fbi->ctrlr_wait, &wait);
1384 set_current_state(TASK_UNINTERRUPTIBLE);
1385
1386 LCSR = 0xffffffff; /* Clear LCD Status Register */
1387 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
1388 LCCR0 &= ~LCCR0_LEN; /* Disable LCD Controller */
1389
1390 schedule_timeout(20 * HZ / 1000);
1391 remove_wait_queue(&fbi->ctrlr_wait, &wait);
1392 }
1393
1394 /*
1395 * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
1396 */
1397 static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
1398 {
1399 struct sa1100fb_info *fbi = dev_id;
1400 unsigned int lcsr = LCSR;
1401
1402 if (lcsr & LCSR_LDD) {
1403 LCCR0 |= LCCR0_LDM;
1404 wake_up(&fbi->ctrlr_wait);
1405 }
1406
1407 LCSR = lcsr;
1408 return IRQ_HANDLED;
1409 }
1410
1411 /*
1412 * This function must be called from task context only, since it will
1413 * sleep when disabling the LCD controller, or if we get two contending
1414 * processes trying to alter state.
1415 */
1416 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
1417 {
1418 u_int old_state;
1419
1420 down(&fbi->ctrlr_sem);
1421
1422 old_state = fbi->state;
1423
1424 /*
1425 * Hack around fbcon initialisation.
1426 */
1427 if (old_state == C_STARTUP && state == C_REENABLE)
1428 state = C_ENABLE;
1429
1430 switch (state) {
1431 case C_DISABLE_CLKCHANGE:
1432 /*
1433 * Disable controller for clock change. If the
1434 * controller is already disabled, then do nothing.
1435 */
1436 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1437 fbi->state = state;
1438 sa1100fb_disable_controller(fbi);
1439 }
1440 break;
1441
1442 case C_DISABLE_PM:
1443 case C_DISABLE:
1444 /*
1445 * Disable controller
1446 */
1447 if (old_state != C_DISABLE) {
1448 fbi->state = state;
1449
1450 __sa1100fb_backlight_power(fbi, 0);
1451 if (old_state != C_DISABLE_CLKCHANGE)
1452 sa1100fb_disable_controller(fbi);
1453 __sa1100fb_lcd_power(fbi, 0);
1454 }
1455 break;
1456
1457 case C_ENABLE_CLKCHANGE:
1458 /*
1459 * Enable the controller after clock change. Only
1460 * do this if we were disabled for the clock change.
1461 */
1462 if (old_state == C_DISABLE_CLKCHANGE) {
1463 fbi->state = C_ENABLE;
1464 sa1100fb_enable_controller(fbi);
1465 }
1466 break;
1467
1468 case C_REENABLE:
1469 /*
1470 * Re-enable the controller only if it was already
1471 * enabled. This is so we reprogram the control
1472 * registers.
1473 */
1474 if (old_state == C_ENABLE) {
1475 sa1100fb_disable_controller(fbi);
1476 sa1100fb_setup_gpio(fbi);
1477 sa1100fb_enable_controller(fbi);
1478 }
1479 break;
1480
1481 case C_ENABLE_PM:
1482 /*
1483 * Re-enable the controller after PM. This is not
1484 * perfect - think about the case where we were doing
1485 * a clock change, and we suspended half-way through.
1486 */
1487 if (old_state != C_DISABLE_PM)
1488 break;
1489 /* fall through */
1490
1491 case C_ENABLE:
1492 /*
1493 * Power up the LCD screen, enable controller, and
1494 * turn on the backlight.
1495 */
1496 if (old_state != C_ENABLE) {
1497 fbi->state = C_ENABLE;
1498 sa1100fb_setup_gpio(fbi);
1499 __sa1100fb_lcd_power(fbi, 1);
1500 sa1100fb_enable_controller(fbi);
1501 __sa1100fb_backlight_power(fbi, 1);
1502 }
1503 break;
1504 }
1505 up(&fbi->ctrlr_sem);
1506 }
1507
1508 /*
1509 * Our LCD controller task (which is called when we blank or unblank)
1510 * via keventd.
1511 */
1512 static void sa1100fb_task(void *dummy)
1513 {
1514 struct sa1100fb_info *fbi = dummy;
1515 u_int state = xchg(&fbi->task_state, -1);
1516
1517 set_ctrlr_state(fbi, state);
1518 }
1519
1520 #ifdef CONFIG_CPU_FREQ
1521 /*
1522 * Calculate the minimum DMA period over all displays that we own.
1523 * This, together with the SDRAM bandwidth defines the slowest CPU
1524 * frequency that can be selected.
1525 */
1526 static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi)
1527 {
1528 #if 0
1529 unsigned int min_period = (unsigned int)-1;
1530 int i;
1531
1532 for (i = 0; i < MAX_NR_CONSOLES; i++) {
1533 struct display *disp = &fb_display[i];
1534 unsigned int period;
1535
1536 /*
1537 * Do we own this display?
1538 */
1539 if (disp->fb_info != &fbi->fb)
1540 continue;
1541
1542 /*
1543 * Ok, calculate its DMA period
1544 */
1545 period = sa1100fb_display_dma_period(&disp->var);
1546 if (period < min_period)
1547 min_period = period;
1548 }
1549
1550 return min_period;
1551 #else
1552 /*
1553 * FIXME: we need to verify _all_ consoles.
1554 */
1555 return sa1100fb_display_dma_period(&fbi->fb.var);
1556 #endif
1557 }
1558
1559 /*
1560 * CPU clock speed change handler. We need to adjust the LCD timing
1561 * parameters when the CPU clock is adjusted by the power management
1562 * subsystem.
1563 */
1564 static int
1565 sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
1566 void *data)
1567 {
1568 struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
1569 struct cpufreq_freqs *f = data;
1570 u_int pcd;
1571
1572 switch (val) {
1573 case CPUFREQ_PRECHANGE:
1574 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1575 break;
1576
1577 case CPUFREQ_POSTCHANGE:
1578 pcd = get_pcd(fbi->fb.var.pixclock, f->new);
1579 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1580 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1581 break;
1582 }
1583 return 0;
1584 }
1585
1586 static int
1587 sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val,
1588 void *data)
1589 {
1590 struct sa1100fb_info *fbi = TO_INF(nb, freq_policy);
1591 struct cpufreq_policy *policy = data;
1592
1593 switch (val) {
1594 case CPUFREQ_ADJUST:
1595 case CPUFREQ_INCOMPATIBLE:
1596 printk(KERN_DEBUG "min dma period: %d ps, "
1597 "new clock %d kHz\n", sa1100fb_min_dma_period(fbi),
1598 policy->max);
1599 /* todo: fill in min/max values */
1600 break;
1601 case CPUFREQ_NOTIFY:
1602 do {} while(0);
1603 /* todo: panic if min/max values aren't fulfilled
1604 * [can't really happen unless there's a bug in the
1605 * CPU policy verififcation process *
1606 */
1607 break;
1608 }
1609 return 0;
1610 }
1611 #endif
1612
1613 #ifdef CONFIG_PM
1614 /*
1615 * Power management hooks. Note that we won't be called from IRQ context,
1616 * unlike the blank functions above, so we may sleep.
1617 */
1618 static int sa1100fb_suspend(struct device *dev, u32 state, u32 level)
1619 {
1620 struct sa1100fb_info *fbi = dev_get_drvdata(dev);
1621
1622 if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
1623 set_ctrlr_state(fbi, C_DISABLE_PM);
1624 return 0;
1625 }
1626
1627 static int sa1100fb_resume(struct device *dev, u32 level)
1628 {
1629 struct sa1100fb_info *fbi = dev_get_drvdata(dev);
1630
1631 if (level == RESUME_ENABLE)
1632 set_ctrlr_state(fbi, C_ENABLE_PM);
1633 return 0;
1634 }
1635 #else
1636 #define sa1100fb_suspend NULL
1637 #define sa1100fb_resume NULL
1638 #endif
1639
1640 /*
1641 * sa1100fb_map_video_memory():
1642 * Allocates the DRAM memory for the frame buffer. This buffer is
1643 * remapped into a non-cached, non-buffered, memory region to
1644 * allow palette and pixel writes to occur without flushing the
1645 * cache. Once this area is remapped, all virtual memory
1646 * access to the video memory should occur at the new region.
1647 */
1648 static int __init sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
1649 {
1650 /*
1651 * We reserve one page for the palette, plus the size
1652 * of the framebuffer.
1653 */
1654 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1655 fbi->map_cpu = consistent_alloc(GFP_KERNEL, fbi->map_size,
1656 &fbi->map_dma, PTE_BUFFERABLE);
1657
1658 if (fbi->map_cpu) {
1659 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1660 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1661 fbi->fb.fix.smem_start = fbi->screen_dma;
1662 }
1663
1664 return fbi->map_cpu ? 0 : -ENOMEM;
1665 }
1666
1667 /* Fake monspecs to fill in fbinfo structure */
1668 static struct fb_monspecs monspecs __initdata = {
1669 30000, 70000, 50, 65, 0 /* Generic */
1670 };
1671
1672
1673 static struct sa1100fb_info * __init sa1100fb_init_fbinfo(void)
1674 {
1675 struct sa1100fb_mach_info *inf;
1676 struct sa1100fb_info *fbi;
1677
1678 fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16,
1679 GFP_KERNEL);
1680 if (!fbi)
1681 return NULL;
1682
1683 memset(fbi, 0, sizeof(struct sa1100fb_info));
1684
1685 strcpy(fbi->fb.fix.id, SA1100_NAME);
1686
1687 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1688 fbi->fb.fix.type_aux = 0;
1689 fbi->fb.fix.xpanstep = 0;
1690 fbi->fb.fix.ypanstep = 0;
1691 fbi->fb.fix.ywrapstep = 0;
1692 fbi->fb.fix.accel = FB_ACCEL_NONE;
1693
1694 fbi->fb.var.nonstd = 0;
1695 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1696 fbi->fb.var.height = -1;
1697 fbi->fb.var.width = -1;
1698 fbi->fb.var.accel_flags = 0;
1699 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1700
1701 fbi->fb.fbops = &sa1100fb_ops;
1702 fbi->fb.flags = FBINFO_FLAG_DEFAULT;
1703 fbi->fb.monspecs = monspecs;
1704 fbi->fb.currcon = -1;
1705 fbi->fb.pseudo_palette = (fbi + 1);
1706
1707 fbi->rgb[RGB_8] = &rgb_8;
1708 fbi->rgb[RGB_16] = &def_rgb_16;
1709
1710 inf = sa1100fb_get_machine_info(fbi);
1711
1712 /*
1713 * People just don't seem to get this. We don't support
1714 * anything but correct entries now, so panic if someone
1715 * does something stupid.
1716 */
1717 if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
1718 inf->pixclock == 0)
1719 panic("sa1100fb error: invalid LCCR3 fields set or zero "
1720 "pixclock.");
1721
1722 fbi->max_xres = inf->xres;
1723 fbi->fb.var.xres = inf->xres;
1724 fbi->fb.var.xres_virtual = inf->xres;
1725 fbi->max_yres = inf->yres;
1726 fbi->fb.var.yres = inf->yres;
1727 fbi->fb.var.yres_virtual = inf->yres;
1728 fbi->max_bpp = inf->bpp;
1729 fbi->fb.var.bits_per_pixel = inf->bpp;
1730 fbi->fb.var.pixclock = inf->pixclock;
1731 fbi->fb.var.hsync_len = inf->hsync_len;
1732 fbi->fb.var.left_margin = inf->left_margin;
1733 fbi->fb.var.right_margin = inf->right_margin;
1734 fbi->fb.var.vsync_len = inf->vsync_len;
1735 fbi->fb.var.upper_margin = inf->upper_margin;
1736 fbi->fb.var.lower_margin = inf->lower_margin;
1737 fbi->fb.var.sync = inf->sync;
1738 fbi->fb.var.grayscale = inf->cmap_greyscale;
1739 fbi->cmap_inverse = inf->cmap_inverse;
1740 fbi->cmap_static = inf->cmap_static;
1741 fbi->lccr0 = inf->lccr0;
1742 fbi->lccr3 = inf->lccr3;
1743 fbi->state = C_STARTUP;
1744 fbi->task_state = (u_char)-1;
1745 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1746 fbi->max_bpp / 8;
1747
1748 init_waitqueue_head(&fbi->ctrlr_wait);
1749 INIT_WORK(&fbi->task, sa1100fb_task, fbi);
1750 init_MUTEX(&fbi->ctrlr_sem);
1751
1752 return fbi;
1753 }
1754
1755 static int __init sa1100fb_probe(struct device *dev)
1756 {
1757 struct sa1100fb_info *fbi;
1758 int ret;
1759
1760 if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
1761 return -EBUSY;
1762
1763 fbi = sa1100fb_init_fbinfo();
1764 ret = -ENOMEM;
1765 if (!fbi)
1766 goto failed;
1767
1768 /* Initialize video memory */
1769 ret = sa1100fb_map_video_memory(fbi);
1770 if (ret)
1771 goto failed;
1772
1773 ret = request_irq(IRQ_LCD, sa1100fb_handle_irq, SA_INTERRUPT,
1774 "LCD", fbi);
1775 if (ret) {
1776 printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
1777 goto failed;
1778 }
1779
1780 #ifdef ASSABET_PAL_VIDEO
1781 if (machine_is_assabet())
1782 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
1783 #endif
1784
1785 #ifdef CONFIG_SA1100_FREEBIRD
1786 #error Please move this into __sa1100fb_lcd_power
1787 if (machine_is_freebird()) {
1788 BCR_set(BCR_FREEBIRD_LCD_DISP);
1789 mdelay(20);
1790 BCR_set(BCR_FREEBIRD_LCD_PWR);
1791 mdelay(20);
1792 }
1793 #endif
1794
1795 /*
1796 * This makes sure that our colour bitfield
1797 * descriptors are correctly initialised.
1798 */
1799 sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
1800
1801 dev_set_drvdata(dev, fbi);
1802
1803 ret = register_framebuffer(&fbi->fb);
1804 if (ret < 0)
1805 goto failed;
1806
1807 #ifdef CONFIG_CPU_FREQ
1808 fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
1809 fbi->freq_policy.notifier_call = sa1100fb_freq_policy;
1810 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1811 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1812 #endif
1813
1814 /* This driver cannot be unloaded at the moment */
1815 MOD_INC_USE_COUNT;
1816
1817 return 0;
1818
1819 failed:
1820 dev_set_drvdata(dev, NULL);
1821 if (fbi)
1822 kfree(fbi);
1823 release_mem_region(0xb0100000, 0x10000);
1824 return ret;
1825 }
1826
1827 static struct device_driver sa1100fb_driver = {
1828 .name = "sa11x0-fb",
1829 .bus = &platform_bus_type,
1830 .probe = sa1100fb_probe,
1831 .suspend = sa1100fb_suspend,
1832 .resume = sa1100fb_resume,
1833 };
1834
1835 int __init sa1100fb_init(void)
1836 {
1837 return driver_register(&sa1100fb_driver);
1838 }
1839
1840 int __init sa1100fb_setup(char *options)
1841 {
1842 #if 0
1843 char *this_opt;
1844
1845 if (!options || !*options)
1846 return 0;
1847
1848 while ((this_opt = strsep(&options, ",")) != NULL) {
1849
1850 if (!strncmp(this_opt, "bpp:", 4))
1851 current_par.max_bpp =
1852 simple_strtoul(this_opt + 4, NULL, 0);
1853
1854 if (!strncmp(this_opt, "lccr0:", 6))
1855 lcd_shadow.lccr0 =
1856 simple_strtoul(this_opt + 6, NULL, 0);
1857 if (!strncmp(this_opt, "lccr1:", 6)) {
1858 lcd_shadow.lccr1 =
1859 simple_strtoul(this_opt + 6, NULL, 0);
1860 current_par.max_xres =
1861 (lcd_shadow.lccr1 & 0x3ff) + 16;
1862 }
1863 if (!strncmp(this_opt, "lccr2:", 6)) {
1864 lcd_shadow.lccr2 =
1865 simple_strtoul(this_opt + 6, NULL, 0);
1866 current_par.max_yres =
1867 (lcd_shadow.
1868 lccr0 & LCCR0_SDS) ? ((lcd_shadow.
1869 lccr2 & 0x3ff) +
1870 1) *
1871 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
1872 }
1873 if (!strncmp(this_opt, "lccr3:", 6))
1874 lcd_shadow.lccr3 =
1875 simple_strtoul(this_opt + 6, NULL, 0);
1876 }
1877 #endif
1878 return 0;
1879 }
1880
1881 MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
1882 MODULE_LICENSE("GPL");
Historical 2.5/2.6 development