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[linux-2.6/history.git] / drivers / parport / parport_pc.c
blobb25d216de6256230c3b34dbfe28b137038fccd78
1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <Philip.Blundell@pobox.com>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 */
17
18 /* This driver should work with any hardware that is broadly compatible
19 * with that in the IBM PC. This applies to the majority of integrated
20 * I/O chipsets that are commonly available. The expected register
21 * layout is:
22 *
23 * base+0 data
24 * base+1 status
25 * base+2 control
26 *
27 * In addition, there are some optional registers:
28 *
29 * base+3 EPP address
30 * base+4 EPP data
31 * base+0x400 ECP config A
32 * base+0x401 ECP config B
33 * base+0x402 ECP control
34 *
35 * All registers are 8 bits wide and read/write. If your hardware differs
36 * only in register addresses (eg because your registers are on 32-bit
37 * word boundaries) then you can alter the constants in parport_pc.h to
38 * accommodate this.
39 *
40 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
41 * but rather will start at port->base_hi.
42 */
43
44 #include <linux/config.h>
45 #include <linux/module.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/ioport.h>
52 #include <linux/kernel.h>
53 #include <linux/slab.h>
54 #include <linux/pci.h>
55 #include <linux/pnp.h>
56 #include <linux/sysctl.h>
57
58 #include <asm/io.h>
59 #include <asm/dma.h>
60 #include <asm/uaccess.h>
61
62 #include <linux/parport.h>
63 #include <linux/parport_pc.h>
64 #include <asm/parport.h>
65
66 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
67
68 /* ECR modes */
69 #define ECR_SPP 00
70 #define ECR_PS2 01
71 #define ECR_PPF 02
72 #define ECR_ECP 03
73 #define ECR_EPP 04
74 #define ECR_VND 05
75 #define ECR_TST 06
76 #define ECR_CNF 07
77 #define ECR_MODE_MASK 0xe0
78 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
79
80 #undef DEBUG
81
82 #ifdef DEBUG
83 #define DPRINTK printk
84 #else
85 #define DPRINTK(stuff...)
86 #endif
87
88
89 #define NR_SUPERIOS 3
90 static struct superio_struct { /* For Super-IO chips autodetection */
91 int io;
92 int irq;
93 int dma;
94 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
95
96 static int user_specified;
97 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
98 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
99 static int verbose_probing;
100 #endif
101 static int registered_parport;
102
103 /* frob_control, but for ECR */
104 static void frob_econtrol (struct parport *pb, unsigned char m,
105 unsigned char v)
106 {
107 unsigned char ectr = 0;
108
109 if (m != 0xff)
110 ectr = inb (ECONTROL (pb));
111
112 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
113 m, v, ectr, (ectr & ~m) ^ v);
114
115 outb ((ectr & ~m) ^ v, ECONTROL (pb));
116 }
117
118 static __inline__ void frob_set_mode (struct parport *p, int mode)
119 {
120 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
121 }
122
123 #ifdef CONFIG_PARPORT_PC_FIFO
124 /* Safely change the mode bits in the ECR
125 Returns:
126 0 : Success
127 -EBUSY: Could not drain FIFO in some finite amount of time,
128 mode not changed!
129 */
130 static int change_mode(struct parport *p, int m)
131 {
132 const struct parport_pc_private *priv = p->physport->private_data;
133 unsigned char oecr;
134 int mode;
135
136 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
137
138 if (!priv->ecr) {
139 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
140 return 0;
141 }
142
143 /* Bits <7:5> contain the mode. */
144 oecr = inb (ECONTROL (p));
145 mode = (oecr >> 5) & 0x7;
146 if (mode == m) return 0;
147
148 if (mode >= 2 && !(priv->ctr & 0x20)) {
149 /* This mode resets the FIFO, so we may
150 * have to wait for it to drain first. */
151 unsigned long expire = jiffies + p->physport->cad->timeout;
152 int counter;
153 switch (mode) {
154 case ECR_PPF: /* Parallel Port FIFO mode */
155 case ECR_ECP: /* ECP Parallel Port mode */
156 /* Busy wait for 200us */
157 for (counter = 0; counter < 40; counter++) {
158 if (inb (ECONTROL (p)) & 0x01)
159 break;
160 if (signal_pending (current)) break;
161 udelay (5);
162 }
163
164 /* Poll slowly. */
165 while (!(inb (ECONTROL (p)) & 0x01)) {
166 if (time_after_eq (jiffies, expire))
167 /* The FIFO is stuck. */
168 return -EBUSY;
169 __set_current_state (TASK_INTERRUPTIBLE);
170 schedule_timeout ((HZ + 99) / 100);
171 if (signal_pending (current))
172 break;
173 }
174 }
175 }
176
177 if (mode >= 2 && m >= 2) {
178 /* We have to go through mode 001 */
179 oecr &= ~(7 << 5);
180 oecr |= ECR_PS2 << 5;
181 ECR_WRITE (p, oecr);
182 }
183
184 /* Set the mode. */
185 oecr &= ~(7 << 5);
186 oecr |= m << 5;
187 ECR_WRITE (p, oecr);
188 return 0;
189 }
190
191 #ifdef CONFIG_PARPORT_1284
192 /* Find FIFO lossage; FIFO is reset */
193 static int get_fifo_residue (struct parport *p)
194 {
195 int residue;
196 int cnfga;
197 const struct parport_pc_private *priv = p->physport->private_data;
198
199 /* Adjust for the contents of the FIFO. */
200 for (residue = priv->fifo_depth; ; residue--) {
201 if (inb (ECONTROL (p)) & 0x2)
202 /* Full up. */
203 break;
204
205 outb (0, FIFO (p));
206 }
207
208 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
209 residue);
210
211 /* Reset the FIFO. */
212 frob_set_mode (p, ECR_PS2);
213
214 /* Now change to config mode and clean up. FIXME */
215 frob_set_mode (p, ECR_CNF);
216 cnfga = inb (CONFIGA (p));
217 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
218
219 if (!(cnfga & (1<<2))) {
220 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
221 residue++;
222 }
223
224 /* Don't care about partial PWords until support is added for
225 * PWord != 1 byte. */
226
227 /* Back to PS2 mode. */
228 frob_set_mode (p, ECR_PS2);
229
230 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
231 return residue;
232 }
233 #endif /* IEEE 1284 support */
234 #endif /* FIFO support */
235
236 /*
237 * Clear TIMEOUT BIT in EPP MODE
238 *
239 * This is also used in SPP detection.
240 */
241 static int clear_epp_timeout(struct parport *pb)
242 {
243 unsigned char r;
244
245 if (!(parport_pc_read_status(pb) & 0x01))
246 return 1;
247
248 /* To clear timeout some chips require double read */
249 parport_pc_read_status(pb);
250 r = parport_pc_read_status(pb);
251 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
252 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
253 r = parport_pc_read_status(pb);
254
255 return !(r & 0x01);
256 }
257
258 /*
259 * Access functions.
260 *
261 * Most of these aren't static because they may be used by the
262 * parport_xxx_yyy macros. extern __inline__ versions of several
263 * of these are in parport_pc.h.
264 */
265
266 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
267 {
268 parport_generic_irq(irq, (struct parport *) dev_id, regs);
269 /* FIXME! Was it really ours? */
270 return IRQ_HANDLED;
271 }
272
273 void parport_pc_write_data(struct parport *p, unsigned char d)
274 {
275 outb (d, DATA (p));
276 }
277
278 unsigned char parport_pc_read_data(struct parport *p)
279 {
280 return inb (DATA (p));
281 }
282
283 void parport_pc_write_control(struct parport *p, unsigned char d)
284 {
285 const unsigned char wm = (PARPORT_CONTROL_STROBE |
286 PARPORT_CONTROL_AUTOFD |
287 PARPORT_CONTROL_INIT |
288 PARPORT_CONTROL_SELECT);
289
290 /* Take this out when drivers have adapted to the newer interface. */
291 if (d & 0x20) {
292 printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
293 p->name, p->cad->name);
294 parport_pc_data_reverse (p);
295 }
296
297 __parport_pc_frob_control (p, wm, d & wm);
298 }
299
300 unsigned char parport_pc_read_control(struct parport *p)
301 {
302 const unsigned char wm = (PARPORT_CONTROL_STROBE |
303 PARPORT_CONTROL_AUTOFD |
304 PARPORT_CONTROL_INIT |
305 PARPORT_CONTROL_SELECT);
306 const struct parport_pc_private *priv = p->physport->private_data;
307 return priv->ctr & wm; /* Use soft copy */
308 }
309
310 unsigned char parport_pc_frob_control (struct parport *p, unsigned char mask,
311 unsigned char val)
312 {
313 const unsigned char wm = (PARPORT_CONTROL_STROBE |
314 PARPORT_CONTROL_AUTOFD |
315 PARPORT_CONTROL_INIT |
316 PARPORT_CONTROL_SELECT);
317
318 /* Take this out when drivers have adapted to the newer interface. */
319 if (mask & 0x20) {
320 printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
321 p->name, p->cad->name,
322 (val & 0x20) ? "reverse" : "forward");
323 if (val & 0x20)
324 parport_pc_data_reverse (p);
325 else
326 parport_pc_data_forward (p);
327 }
328
329 /* Restrict mask and val to control lines. */
330 mask &= wm;
331 val &= wm;
332
333 return __parport_pc_frob_control (p, mask, val);
334 }
335
336 unsigned char parport_pc_read_status(struct parport *p)
337 {
338 return inb (STATUS (p));
339 }
340
341 void parport_pc_disable_irq(struct parport *p)
342 {
343 __parport_pc_frob_control (p, 0x10, 0);
344 }
345
346 void parport_pc_enable_irq(struct parport *p)
347 {
348 if (p->irq != PARPORT_IRQ_NONE)
349 __parport_pc_frob_control (p, 0x10, 0x10);
350 }
351
352 void parport_pc_data_forward (struct parport *p)
353 {
354 __parport_pc_frob_control (p, 0x20, 0);
355 }
356
357 void parport_pc_data_reverse (struct parport *p)
358 {
359 __parport_pc_frob_control (p, 0x20, 0x20);
360 }
361
362 void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
363 {
364 s->u.pc.ctr = 0xc;
365 if (dev->irq_func &&
366 dev->port->irq != PARPORT_IRQ_NONE)
367 /* Set ackIntEn */
368 s->u.pc.ctr |= 0x10;
369
370 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
371 * D.Gruszka VScom */
372 }
373
374 void parport_pc_save_state(struct parport *p, struct parport_state *s)
375 {
376 const struct parport_pc_private *priv = p->physport->private_data;
377 s->u.pc.ctr = priv->ctr;
378 if (priv->ecr)
379 s->u.pc.ecr = inb (ECONTROL (p));
380 }
381
382 void parport_pc_restore_state(struct parport *p, struct parport_state *s)
383 {
384 struct parport_pc_private *priv = p->physport->private_data;
385 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
386 outb (c, CONTROL (p));
387 priv->ctr = c;
388 if (priv->ecr)
389 ECR_WRITE (p, s->u.pc.ecr);
390 }
391
392 #ifdef CONFIG_PARPORT_1284
393 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
394 size_t length, int flags)
395 {
396 size_t got = 0;
397
398 if (flags & PARPORT_W91284PIC) {
399 unsigned char status;
400 size_t left = length;
401
402 /* use knowledge about data lines..:
403 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
404 * pError is 1 if there are 16 bytes in the Warp's FIFO
405 */
406 status = inb (STATUS (port));
407
408 while (!(status & 0x08) && (got < length)) {
409 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
410 /* can grab 16 bytes from warp fifo */
411 if (!((long)buf & 0x03)) {
412 insl (EPPDATA (port), buf, 4);
413 } else {
414 insb (EPPDATA (port), buf, 16);
415 }
416 buf += 16;
417 got += 16;
418 left -= 16;
419 } else {
420 /* grab single byte from the warp fifo */
421 *((char *)buf)++ = inb (EPPDATA (port));
422 got++;
423 left--;
424 }
425 status = inb (STATUS (port));
426 if (status & 0x01) {
427 /* EPP timeout should never occur... */
428 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
429 "w91284pic (should not have done)\n", port->name);
430 clear_epp_timeout (port);
431 }
432 }
433 return got;
434 }
435 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
436 if (!(((long)buf | length) & 0x03)) {
437 insl (EPPDATA (port), buf, (length >> 2));
438 } else {
439 insb (EPPDATA (port), buf, length);
440 }
441 if (inb (STATUS (port)) & 0x01) {
442 clear_epp_timeout (port);
443 return -EIO;
444 }
445 return length;
446 }
447 for (; got < length; got++) {
448 *((char*)buf)++ = inb (EPPDATA(port));
449 if (inb (STATUS (port)) & 0x01) {
450 /* EPP timeout */
451 clear_epp_timeout (port);
452 break;
453 }
454 }
455
456 return got;
457 }
458
459 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
460 size_t length, int flags)
461 {
462 size_t written = 0;
463
464 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
465 if (!(((long)buf | length) & 0x03)) {
466 outsl (EPPDATA (port), buf, (length >> 2));
467 } else {
468 outsb (EPPDATA (port), buf, length);
469 }
470 if (inb (STATUS (port)) & 0x01) {
471 clear_epp_timeout (port);
472 return -EIO;
473 }
474 return length;
475 }
476 for (; written < length; written++) {
477 outb (*((char*)buf)++, EPPDATA(port));
478 if (inb (STATUS(port)) & 0x01) {
479 clear_epp_timeout (port);
480 break;
481 }
482 }
483
484 return written;
485 }
486
487 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
488 size_t length, int flags)
489 {
490 size_t got = 0;
491
492 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
493 insb (EPPADDR (port), buf, length);
494 if (inb (STATUS (port)) & 0x01) {
495 clear_epp_timeout (port);
496 return -EIO;
497 }
498 return length;
499 }
500 for (; got < length; got++) {
501 *((char*)buf)++ = inb (EPPADDR (port));
502 if (inb (STATUS (port)) & 0x01) {
503 clear_epp_timeout (port);
504 break;
505 }
506 }
507
508 return got;
509 }
510
511 static size_t parport_pc_epp_write_addr (struct parport *port,
512 const void *buf, size_t length,
513 int flags)
514 {
515 size_t written = 0;
516
517 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
518 outsb (EPPADDR (port), buf, length);
519 if (inb (STATUS (port)) & 0x01) {
520 clear_epp_timeout (port);
521 return -EIO;
522 }
523 return length;
524 }
525 for (; written < length; written++) {
526 outb (*((char*)buf)++, EPPADDR (port));
527 if (inb (STATUS (port)) & 0x01) {
528 clear_epp_timeout (port);
529 break;
530 }
531 }
532
533 return written;
534 }
535
536 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
537 size_t length, int flags)
538 {
539 size_t got;
540
541 frob_set_mode (port, ECR_EPP);
542 parport_pc_data_reverse (port);
543 parport_pc_write_control (port, 0x4);
544 got = parport_pc_epp_read_data (port, buf, length, flags);
545 frob_set_mode (port, ECR_PS2);
546
547 return got;
548 }
549
550 static size_t parport_pc_ecpepp_write_data (struct parport *port,
551 const void *buf, size_t length,
552 int flags)
553 {
554 size_t written;
555
556 frob_set_mode (port, ECR_EPP);
557 parport_pc_write_control (port, 0x4);
558 parport_pc_data_forward (port);
559 written = parport_pc_epp_write_data (port, buf, length, flags);
560 frob_set_mode (port, ECR_PS2);
561
562 return written;
563 }
564
565 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
566 size_t length, int flags)
567 {
568 size_t got;
569
570 frob_set_mode (port, ECR_EPP);
571 parport_pc_data_reverse (port);
572 parport_pc_write_control (port, 0x4);
573 got = parport_pc_epp_read_addr (port, buf, length, flags);
574 frob_set_mode (port, ECR_PS2);
575
576 return got;
577 }
578
579 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
580 const void *buf, size_t length,
581 int flags)
582 {
583 size_t written;
584
585 frob_set_mode (port, ECR_EPP);
586 parport_pc_write_control (port, 0x4);
587 parport_pc_data_forward (port);
588 written = parport_pc_epp_write_addr (port, buf, length, flags);
589 frob_set_mode (port, ECR_PS2);
590
591 return written;
592 }
593 #endif /* IEEE 1284 support */
594
595 #ifdef CONFIG_PARPORT_PC_FIFO
596 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
597 const void *buf, size_t length)
598 {
599 int ret = 0;
600 const unsigned char *bufp = buf;
601 size_t left = length;
602 unsigned long expire = jiffies + port->physport->cad->timeout;
603 const int fifo = FIFO (port);
604 int poll_for = 8; /* 80 usecs */
605 const struct parport_pc_private *priv = port->physport->private_data;
606 const int fifo_depth = priv->fifo_depth;
607
608 port = port->physport;
609
610 /* We don't want to be interrupted every character. */
611 parport_pc_disable_irq (port);
612 /* set nErrIntrEn and serviceIntr */
613 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
614
615 /* Forward mode. */
616 parport_pc_data_forward (port); /* Must be in PS2 mode */
617
618 while (left) {
619 unsigned char byte;
620 unsigned char ecrval = inb (ECONTROL (port));
621 int i = 0;
622
623 if (need_resched() && time_before (jiffies, expire))
624 /* Can't yield the port. */
625 schedule ();
626
627 /* Anyone else waiting for the port? */
628 if (port->waithead) {
629 printk (KERN_DEBUG "Somebody wants the port\n");
630 break;
631 }
632
633 if (ecrval & 0x02) {
634 /* FIFO is full. Wait for interrupt. */
635
636 /* Clear serviceIntr */
637 ECR_WRITE (port, ecrval & ~(1<<2));
638 false_alarm:
639 ret = parport_wait_event (port, HZ);
640 if (ret < 0) break;
641 ret = 0;
642 if (!time_before (jiffies, expire)) {
643 /* Timed out. */
644 printk (KERN_DEBUG "FIFO write timed out\n");
645 break;
646 }
647 ecrval = inb (ECONTROL (port));
648 if (!(ecrval & (1<<2))) {
649 if (need_resched() &&
650 time_before (jiffies, expire))
651 schedule ();
652
653 goto false_alarm;
654 }
655
656 continue;
657 }
658
659 /* Can't fail now. */
660 expire = jiffies + port->cad->timeout;
661
662 poll:
663 if (signal_pending (current))
664 break;
665
666 if (ecrval & 0x01) {
667 /* FIFO is empty. Blast it full. */
668 const int n = left < fifo_depth ? left : fifo_depth;
669 outsb (fifo, bufp, n);
670 bufp += n;
671 left -= n;
672
673 /* Adjust the poll time. */
674 if (i < (poll_for - 2)) poll_for--;
675 continue;
676 } else if (i++ < poll_for) {
677 udelay (10);
678 ecrval = inb (ECONTROL (port));
679 goto poll;
680 }
681
682 /* Half-full (call me an optimist) */
683 byte = *bufp++;
684 outb (byte, fifo);
685 left--;
686 }
687
688 dump_parport_state ("leave fifo_write_block_pio", port);
689 return length - left;
690 }
691
692 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
693 const void *buf, size_t length)
694 {
695 int ret = 0;
696 unsigned long dmaflag;
697 size_t left = length;
698 const struct parport_pc_private *priv = port->physport->private_data;
699 dma_addr_t dma_addr, dma_handle;
700 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
701 unsigned long start = (unsigned long) buf;
702 unsigned long end = (unsigned long) buf + length - 1;
703
704 dump_parport_state ("enter fifo_write_block_dma", port);
705 if (end < MAX_DMA_ADDRESS) {
706 /* If it would cross a 64k boundary, cap it at the end. */
707 if ((start ^ end) & ~0xffffUL)
708 maxlen = 0x10000 - (start & 0xffff);
709
710 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
711 PCI_DMA_TODEVICE);
712 } else {
713 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
714 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
715 dma_addr = priv->dma_handle;
716 dma_handle = 0;
717 }
718
719 port = port->physport;
720
721 /* We don't want to be interrupted every character. */
722 parport_pc_disable_irq (port);
723 /* set nErrIntrEn and serviceIntr */
724 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
725
726 /* Forward mode. */
727 parport_pc_data_forward (port); /* Must be in PS2 mode */
728
729 while (left) {
730 unsigned long expire = jiffies + port->physport->cad->timeout;
731
732 size_t count = left;
733
734 if (count > maxlen)
735 count = maxlen;
736
737 if (!dma_handle) /* bounce buffer ! */
738 memcpy(priv->dma_buf, buf, count);
739
740 dmaflag = claim_dma_lock();
741 disable_dma(port->dma);
742 clear_dma_ff(port->dma);
743 set_dma_mode(port->dma, DMA_MODE_WRITE);
744 set_dma_addr(port->dma, dma_addr);
745 set_dma_count(port->dma, count);
746
747 /* Set DMA mode */
748 frob_econtrol (port, 1<<3, 1<<3);
749
750 /* Clear serviceIntr */
751 frob_econtrol (port, 1<<2, 0);
752
753 enable_dma(port->dma);
754 release_dma_lock(dmaflag);
755
756 /* assume DMA will be successful */
757 left -= count;
758 buf += count;
759 if (dma_handle) dma_addr += count;
760
761 /* Wait for interrupt. */
762 false_alarm:
763 ret = parport_wait_event (port, HZ);
764 if (ret < 0) break;
765 ret = 0;
766 if (!time_before (jiffies, expire)) {
767 /* Timed out. */
768 printk (KERN_DEBUG "DMA write timed out\n");
769 break;
770 }
771 /* Is serviceIntr set? */
772 if (!(inb (ECONTROL (port)) & (1<<2))) {
773 cond_resched();
774
775 goto false_alarm;
776 }
777
778 dmaflag = claim_dma_lock();
779 disable_dma(port->dma);
780 clear_dma_ff(port->dma);
781 count = get_dma_residue(port->dma);
782 release_dma_lock(dmaflag);
783
784 cond_resched(); /* Can't yield the port. */
785
786 /* Anyone else waiting for the port? */
787 if (port->waithead) {
788 printk (KERN_DEBUG "Somebody wants the port\n");
789 break;
790 }
791
792 /* update for possible DMA residue ! */
793 buf -= count;
794 left += count;
795 if (dma_handle) dma_addr -= count;
796 }
797
798 /* Maybe got here through break, so adjust for DMA residue! */
799 dmaflag = claim_dma_lock();
800 disable_dma(port->dma);
801 clear_dma_ff(port->dma);
802 left += get_dma_residue(port->dma);
803 release_dma_lock(dmaflag);
804
805 /* Turn off DMA mode */
806 frob_econtrol (port, 1<<3, 0);
807
808 if (dma_handle)
809 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
810
811 dump_parport_state ("leave fifo_write_block_dma", port);
812 return length - left;
813 }
814
815 /* Parallel Port FIFO mode (ECP chipsets) */
816 size_t parport_pc_compat_write_block_pio (struct parport *port,
817 const void *buf, size_t length,
818 int flags)
819 {
820 size_t written;
821 int r;
822 unsigned long expire;
823 const struct parport_pc_private *priv = port->physport->private_data;
824
825 /* Special case: a timeout of zero means we cannot call schedule().
826 * Also if O_NONBLOCK is set then use the default implementation. */
827 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
828 return parport_ieee1284_write_compat (port, buf,
829 length, flags);
830
831 /* Set up parallel port FIFO mode.*/
832 parport_pc_data_forward (port); /* Must be in PS2 mode */
833 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
834 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
835 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
836
837 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
838
839 /* Write the data to the FIFO. */
840 if (port->dma != PARPORT_DMA_NONE)
841 written = parport_pc_fifo_write_block_dma (port, buf, length);
842 else
843 written = parport_pc_fifo_write_block_pio (port, buf, length);
844
845 /* Finish up. */
846 /* For some hardware we don't want to touch the mode until
847 * the FIFO is empty, so allow 4 seconds for each position
848 * in the fifo.
849 */
850 expire = jiffies + (priv->fifo_depth * HZ * 4);
851 do {
852 /* Wait for the FIFO to empty */
853 r = change_mode (port, ECR_PS2);
854 if (r != -EBUSY) {
855 break;
856 }
857 } while (time_before (jiffies, expire));
858 if (r == -EBUSY) {
859
860 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
861
862 /* Prevent further data transfer. */
863 frob_set_mode (port, ECR_TST);
864
865 /* Adjust for the contents of the FIFO. */
866 for (written -= priv->fifo_depth; ; written++) {
867 if (inb (ECONTROL (port)) & 0x2) {
868 /* Full up. */
869 break;
870 }
871 outb (0, FIFO (port));
872 }
873
874 /* Reset the FIFO and return to PS2 mode. */
875 frob_set_mode (port, ECR_PS2);
876 }
877
878 r = parport_wait_peripheral (port,
879 PARPORT_STATUS_BUSY,
880 PARPORT_STATUS_BUSY);
881 if (r)
882 printk (KERN_DEBUG
883 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
884 port->name, r);
885
886 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
887
888 return written;
889 }
890
891 /* ECP */
892 #ifdef CONFIG_PARPORT_1284
893 size_t parport_pc_ecp_write_block_pio (struct parport *port,
894 const void *buf, size_t length,
895 int flags)
896 {
897 size_t written;
898 int r;
899 unsigned long expire;
900 const struct parport_pc_private *priv = port->physport->private_data;
901
902 /* Special case: a timeout of zero means we cannot call schedule().
903 * Also if O_NONBLOCK is set then use the default implementation. */
904 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
905 return parport_ieee1284_ecp_write_data (port, buf,
906 length, flags);
907
908 /* Switch to forward mode if necessary. */
909 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
910 /* Event 47: Set nInit high. */
911 parport_frob_control (port,
912 PARPORT_CONTROL_INIT
913 | PARPORT_CONTROL_AUTOFD,
914 PARPORT_CONTROL_INIT
915 | PARPORT_CONTROL_AUTOFD);
916
917 /* Event 49: PError goes high. */
918 r = parport_wait_peripheral (port,
919 PARPORT_STATUS_PAPEROUT,
920 PARPORT_STATUS_PAPEROUT);
921 if (r) {
922 printk (KERN_DEBUG "%s: PError timeout (%d) "
923 "in ecp_write_block_pio\n", port->name, r);
924 }
925 }
926
927 /* Set up ECP parallel port mode.*/
928 parport_pc_data_forward (port); /* Must be in PS2 mode */
929 parport_pc_frob_control (port,
930 PARPORT_CONTROL_STROBE |
931 PARPORT_CONTROL_AUTOFD,
932 0);
933 r = change_mode (port, ECR_ECP); /* ECP FIFO */
934 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
935 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
936
937 /* Write the data to the FIFO. */
938 if (port->dma != PARPORT_DMA_NONE)
939 written = parport_pc_fifo_write_block_dma (port, buf, length);
940 else
941 written = parport_pc_fifo_write_block_pio (port, buf, length);
942
943 /* Finish up. */
944 /* For some hardware we don't want to touch the mode until
945 * the FIFO is empty, so allow 4 seconds for each position
946 * in the fifo.
947 */
948 expire = jiffies + (priv->fifo_depth * (HZ * 4));
949 do {
950 /* Wait for the FIFO to empty */
951 r = change_mode (port, ECR_PS2);
952 if (r != -EBUSY) {
953 break;
954 }
955 } while (time_before (jiffies, expire));
956 if (r == -EBUSY) {
957
958 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
959
960 /* Prevent further data transfer. */
961 frob_set_mode (port, ECR_TST);
962
963 /* Adjust for the contents of the FIFO. */
964 for (written -= priv->fifo_depth; ; written++) {
965 if (inb (ECONTROL (port)) & 0x2) {
966 /* Full up. */
967 break;
968 }
969 outb (0, FIFO (port));
970 }
971
972 /* Reset the FIFO and return to PS2 mode. */
973 frob_set_mode (port, ECR_PS2);
974
975 /* Host transfer recovery. */
976 parport_pc_data_reverse (port); /* Must be in PS2 mode */
977 udelay (5);
978 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
979 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
980 if (r)
981 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
982 "in ecp_write_block_pio\n", port->name, r);
983
984 parport_frob_control (port,
985 PARPORT_CONTROL_INIT,
986 PARPORT_CONTROL_INIT);
987 r = parport_wait_peripheral (port,
988 PARPORT_STATUS_PAPEROUT,
989 PARPORT_STATUS_PAPEROUT);
990 if (r)
991 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
992 "in ecp_write_block_pio\n", port->name, r);
993 }
994
995 r = parport_wait_peripheral (port,
996 PARPORT_STATUS_BUSY,
997 PARPORT_STATUS_BUSY);
998 if(r)
999 printk (KERN_DEBUG
1000 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
1001 port->name, r);
1002
1003 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1004
1005 return written;
1006 }
1007
1008 size_t parport_pc_ecp_read_block_pio (struct parport *port,
1009 void *buf, size_t length, int flags)
1010 {
1011 size_t left = length;
1012 size_t fifofull;
1013 int r;
1014 const int fifo = FIFO(port);
1015 const struct parport_pc_private *priv = port->physport->private_data;
1016 const int fifo_depth = priv->fifo_depth;
1017 char *bufp = buf;
1018
1019 port = port->physport;
1020 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
1021 dump_parport_state ("enter fcn", port);
1022
1023 /* Special case: a timeout of zero means we cannot call schedule().
1024 * Also if O_NONBLOCK is set then use the default implementation. */
1025 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1026 return parport_ieee1284_ecp_read_data (port, buf,
1027 length, flags);
1028
1029 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
1030 /* If the peripheral is allowed to send RLE compressed
1031 * data, it is possible for a byte to expand to 128
1032 * bytes in the FIFO. */
1033 fifofull = 128;
1034 } else {
1035 fifofull = fifo_depth;
1036 }
1037
1038 /* If the caller wants less than a full FIFO's worth of data,
1039 * go through software emulation. Otherwise we may have to throw
1040 * away data. */
1041 if (length < fifofull)
1042 return parport_ieee1284_ecp_read_data (port, buf,
1043 length, flags);
1044
1045 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
1046 /* change to reverse-idle phase (must be in forward-idle) */
1047
1048 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
1049 parport_frob_control (port,
1050 PARPORT_CONTROL_AUTOFD
1051 | PARPORT_CONTROL_STROBE,
1052 PARPORT_CONTROL_AUTOFD);
1053 parport_pc_data_reverse (port); /* Must be in PS2 mode */
1054 udelay (5);
1055 /* Event 39: Set nInit low to initiate bus reversal */
1056 parport_frob_control (port,
1057 PARPORT_CONTROL_INIT,
1058 0);
1059 /* Event 40: Wait for nAckReverse (PError) to go low */
1060 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
1061 if (r) {
1062 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
1063 "in ecp_read_block_pio\n", port->name, r);
1064 return 0;
1065 }
1066 }
1067
1068 /* Set up ECP FIFO mode.*/
1069 /* parport_pc_frob_control (port,
1070 PARPORT_CONTROL_STROBE |
1071 PARPORT_CONTROL_AUTOFD,
1072 PARPORT_CONTROL_AUTOFD); */
1073 r = change_mode (port, ECR_ECP); /* ECP FIFO */
1074 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
1075
1076 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1077
1078 /* the first byte must be collected manually */
1079 dump_parport_state ("pre 43", port);
1080 /* Event 43: Wait for nAck to go low */
1081 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1082 if (r) {
1083 /* timed out while reading -- no data */
1084 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1085 goto out_no_data;
1086 }
1087 /* read byte */
1088 *bufp++ = inb (DATA (port));
1089 left--;
1090 dump_parport_state ("43-44", port);
1091 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1092 parport_pc_frob_control (port,
1093 PARPORT_CONTROL_AUTOFD,
1094 0);
1095 dump_parport_state ("pre 45", port);
1096 /* Event 45: Wait for nAck to go high */
1097 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1098 dump_parport_state ("post 45", port);
1099 r = 0;
1100 if (r) {
1101 /* timed out while waiting for peripheral to respond to ack */
1102 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1103
1104 /* keep hold of the byte we've got already */
1105 goto out_no_data;
1106 }
1107 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1108 parport_pc_frob_control (port,
1109 PARPORT_CONTROL_AUTOFD,
1110 PARPORT_CONTROL_AUTOFD);
1111
1112
1113 dump_parport_state ("rev idle", port);
1114 /* Do the transfer. */
1115 while (left > fifofull) {
1116 int ret;
1117 unsigned long expire = jiffies + port->cad->timeout;
1118 unsigned char ecrval = inb (ECONTROL (port));
1119
1120 if (need_resched() && time_before (jiffies, expire))
1121 /* Can't yield the port. */
1122 schedule ();
1123
1124 /* At this point, the FIFO may already be full. In
1125 * that case ECP is already holding back the
1126 * peripheral (assuming proper design) with a delayed
1127 * handshake. Work fast to avoid a peripheral
1128 * timeout. */
1129
1130 if (ecrval & 0x01) {
1131 /* FIFO is empty. Wait for interrupt. */
1132 dump_parport_state ("FIFO empty", port);
1133
1134 /* Anyone else waiting for the port? */
1135 if (port->waithead) {
1136 printk (KERN_DEBUG "Somebody wants the port\n");
1137 break;
1138 }
1139
1140 /* Clear serviceIntr */
1141 ECR_WRITE (port, ecrval & ~(1<<2));
1142 false_alarm:
1143 dump_parport_state ("waiting", port);
1144 ret = parport_wait_event (port, HZ);
1145 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1146 if (ret < 0)
1147 break;
1148 ret = 0;
1149 if (!time_before (jiffies, expire)) {
1150 /* Timed out. */
1151 dump_parport_state ("timeout", port);
1152 printk (KERN_DEBUG "PIO read timed out\n");
1153 break;
1154 }
1155 ecrval = inb (ECONTROL (port));
1156 if (!(ecrval & (1<<2))) {
1157 if (need_resched() &&
1158 time_before (jiffies, expire)) {
1159 schedule ();
1160 }
1161 goto false_alarm;
1162 }
1163
1164 /* Depending on how the FIFO threshold was
1165 * set, how long interrupt service took, and
1166 * how fast the peripheral is, we might be
1167 * lucky and have a just filled FIFO. */
1168 continue;
1169 }
1170
1171 if (ecrval & 0x02) {
1172 /* FIFO is full. */
1173 dump_parport_state ("FIFO full", port);
1174 insb (fifo, bufp, fifo_depth);
1175 bufp += fifo_depth;
1176 left -= fifo_depth;
1177 continue;
1178 }
1179
1180 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1181
1182 /* FIFO not filled. We will cycle this loop for a while
1183 * and either the peripheral will fill it faster,
1184 * tripping a fast empty with insb, or we empty it. */
1185 *bufp++ = inb (fifo);
1186 left--;
1187 }
1188
1189 /* scoop up anything left in the FIFO */
1190 while (left && !(inb (ECONTROL (port) & 0x01))) {
1191 *bufp++ = inb (fifo);
1192 left--;
1193 }
1194
1195 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1196 dump_parport_state ("rev idle2", port);
1197
1198 out_no_data:
1199
1200 /* Go to forward idle mode to shut the peripheral up (event 47). */
1201 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1202
1203 /* event 49: PError goes high */
1204 r = parport_wait_peripheral (port,
1205 PARPORT_STATUS_PAPEROUT,
1206 PARPORT_STATUS_PAPEROUT);
1207 if (r) {
1208 printk (KERN_DEBUG
1209 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1210 port->name, r);
1211 }
1212
1213 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1214
1215 /* Finish up. */
1216 {
1217 int lost = get_fifo_residue (port);
1218 if (lost)
1219 /* Shouldn't happen with compliant peripherals. */
1220 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1221 port->name, lost);
1222 }
1223
1224 dump_parport_state ("fwd idle", port);
1225 return length - left;
1226 }
1227
1228 #endif /* IEEE 1284 support */
1229 #endif /* Allowed to use FIFO/DMA */
1230
1231
1232 /*
1233 * ******************************************
1234 * INITIALISATION AND MODULE STUFF BELOW HERE
1235 * ******************************************
1236 */
1237
1238 struct parport_operations parport_pc_ops =
1239 {
1240 .write_data = parport_pc_write_data,
1241 .read_data = parport_pc_read_data,
1242
1243 .write_control = parport_pc_write_control,
1244 .read_control = parport_pc_read_control,
1245 .frob_control = parport_pc_frob_control,
1246
1247 .read_status = parport_pc_read_status,
1248
1249 .enable_irq = parport_pc_enable_irq,
1250 .disable_irq = parport_pc_disable_irq,
1251
1252 .data_forward = parport_pc_data_forward,
1253 .data_reverse = parport_pc_data_reverse,
1254
1255 .init_state = parport_pc_init_state,
1256 .save_state = parport_pc_save_state,
1257 .restore_state = parport_pc_restore_state,
1258
1259 .epp_write_data = parport_ieee1284_epp_write_data,
1260 .epp_read_data = parport_ieee1284_epp_read_data,
1261 .epp_write_addr = parport_ieee1284_epp_write_addr,
1262 .epp_read_addr = parport_ieee1284_epp_read_addr,
1263
1264 .ecp_write_data = parport_ieee1284_ecp_write_data,
1265 .ecp_read_data = parport_ieee1284_ecp_read_data,
1266 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1267
1268 .compat_write_data = parport_ieee1284_write_compat,
1269 .nibble_read_data = parport_ieee1284_read_nibble,
1270 .byte_read_data = parport_ieee1284_read_byte,
1271
1272 .owner = THIS_MODULE,
1273 };
1274
1275 #ifdef CONFIG_PARPORT_PC_SUPERIO
1276 /* Super-IO chipset detection, Winbond, SMSC */
1277 static void __devinit show_parconfig_smsc37c669(int io, int key)
1278 {
1279 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1280 static const char *modes[]={ "SPP and Bidirectional (PS/2)",
1281 "EPP and SPP",
1282 "ECP",
1283 "ECP and EPP" };
1284
1285 outb(key,io);
1286 outb(key,io);
1287 outb(1,io);
1288 cr1=inb(io+1);
1289 outb(4,io);
1290 cr4=inb(io+1);
1291 outb(0x0a,io);
1292 cra=inb(io+1);
1293 outb(0x23,io);
1294 cr23=inb(io+1);
1295 outb(0x26,io);
1296 cr26=inb(io+1);
1297 outb(0x27,io);
1298 cr27=inb(io+1);
1299 outb(0xaa,io);
1300
1301 if (verbose_probing) {
1302 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1303 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1304 cr1,cr4,cra,cr23,cr26,cr27);
1305
1306 /* The documentation calls DMA and IRQ-Lines by letters, so
1307 the board maker can/will wire them
1308 appropriately/randomly... G=reserved H=IDE-irq, */
1309 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1310 "fifo threshold=%d\n", cr23*4,
1311 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1312 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1313 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1314 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1315 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1316 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1317 (cr4 & 0x40) ? "1.7" : "1.9");
1318 }
1319
1320 /* Heuristics ! BIOS setup for this mainboard device limits
1321 the choices to standard settings, i.e. io-address and IRQ
1322 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1323 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1324 if(cr23*4 >=0x100) { /* if active */
1325 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1326 i++;
1327 if(i==NR_SUPERIOS)
1328 printk(KERN_INFO "Super-IO: too many chips!\n");
1329 else {
1330 int d;
1331 switch (cr23*4) {
1332 case 0x3bc:
1333 superios[i].io = 0x3bc;
1334 superios[i].irq = 7;
1335 break;
1336 case 0x378:
1337 superios[i].io = 0x378;
1338 superios[i].irq = 7;
1339 break;
1340 case 0x278:
1341 superios[i].io = 0x278;
1342 superios[i].irq = 5;
1343 }
1344 d=(cr26 &0x0f);
1345 if((d==1) || (d==3))
1346 superios[i].dma= d;
1347 else
1348 superios[i].dma= PARPORT_DMA_NONE;
1349 }
1350 }
1351 }
1352
1353
1354 static void __devinit show_parconfig_winbond(int io, int key)
1355 {
1356 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1357 static const char *modes[] = {
1358 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1359 "EPP-1.9 and SPP",
1360 "ECP",
1361 "ECP and EPP-1.9",
1362 "Standard (SPP)",
1363 "EPP-1.7 and SPP", /* 5 */
1364 "undefined!",
1365 "ECP and EPP-1.7" };
1366 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" };
1367
1368 /* The registers are called compatible-PnP because the
1369 register layout is modelled after ISA-PnP, the access
1370 method is just another ... */
1371 outb(key,io);
1372 outb(key,io);
1373 outb(0x07,io); /* Register 7: Select Logical Device */
1374 outb(0x01,io+1); /* LD1 is Parallel Port */
1375 outb(0x30,io);
1376 cr30=inb(io+1);
1377 outb(0x60,io);
1378 cr60=inb(io+1);
1379 outb(0x61,io);
1380 cr61=inb(io+1);
1381 outb(0x70,io);
1382 cr70=inb(io+1);
1383 outb(0x74,io);
1384 cr74=inb(io+1);
1385 outb(0xf0,io);
1386 crf0=inb(io+1);
1387 outb(0xaa,io);
1388
1389 if (verbose_probing) {
1390 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1391 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1392 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1393 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1394 if ((cr74 & 0x07) > 3)
1395 printk("dma=none\n");
1396 else
1397 printk("dma=%d\n",cr74 & 0x07);
1398 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1399 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1400 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1401 }
1402
1403 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1404 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1405 i++;
1406 if(i==NR_SUPERIOS)
1407 printk(KERN_INFO "Super-IO: too many chips!\n");
1408 else {
1409 superios[i].io = (cr60<<8)|cr61;
1410 superios[i].irq = cr70&0x0f;
1411 superios[i].dma = (((cr74 & 0x07) > 3) ?
1412 PARPORT_DMA_NONE : (cr74 & 0x07));
1413 }
1414 }
1415 }
1416
1417 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1418 {
1419 const char *type = "unknown";
1420 int id,progif=2;
1421
1422 if (devid == devrev)
1423 /* simple heuristics, we happened to read some
1424 non-winbond register */
1425 return;
1426
1427 id=(devid<<8) | devrev;
1428
1429 /* Values are from public data sheets pdf files, I can just
1430 confirm 83977TF is correct :-) */
1431 if (id == 0x9771) type="83977F/AF";
1432 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1433 else if (id == 0x9774) type="83977ATF";
1434 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1435 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1436 else if ((id & ~0x0f) == 0x5210) type="83627";
1437 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1438 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1439 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1440 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1441 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1442 else progif=0;
1443
1444 if (verbose_probing)
1445 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1446 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1447 efer, key, devid, devrev, oldid, type);
1448
1449 if (progif == 2)
1450 show_parconfig_winbond(efer,key);
1451 }
1452
1453 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1454 {
1455 const char *type = "unknown";
1456 void (*func)(int io, int key);
1457 int id;
1458
1459 if (devid == devrev)
1460 /* simple heuristics, we happened to read some
1461 non-smsc register */
1462 return;
1463
1464 func=NULL;
1465 id=(devid<<8) | devrev;
1466
1467 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1468 else if (id==0x6582) type="37c665IR";
1469 else if (devid==0x65) type="37c665GT";
1470 else if (devid==0x66) type="37c666GT";
1471
1472 if (verbose_probing)
1473 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1474 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1475 efer, key, devid, devrev, type);
1476
1477 if (func)
1478 func(efer,key);
1479 }
1480
1481
1482 static void __devinit winbond_check(int io, int key)
1483 {
1484 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1485
1486 /* First probe without key */
1487 outb(0x20,io);
1488 x_devid=inb(io+1);
1489 outb(0x21,io);
1490 x_devrev=inb(io+1);
1491 outb(0x09,io);
1492 x_oldid=inb(io+1);
1493
1494 outb(key,io);
1495 outb(key,io); /* Write Magic Sequence to EFER, extended
1496 funtion enable register */
1497 outb(0x20,io); /* Write EFIR, extended function index register */
1498 devid=inb(io+1); /* Read EFDR, extended function data register */
1499 outb(0x21,io);
1500 devrev=inb(io+1);
1501 outb(0x09,io);
1502 oldid=inb(io+1);
1503 outb(0xaa,io); /* Magic Seal */
1504
1505 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1506 return; /* protection against false positives */
1507
1508 decode_winbond(io,key,devid,devrev,oldid);
1509 }
1510
1511 static void __devinit winbond_check2(int io,int key)
1512 {
1513 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1514
1515 /* First probe without the key */
1516 outb(0x20,io+2);
1517 x_devid=inb(io+2);
1518 outb(0x21,io+1);
1519 x_devrev=inb(io+2);
1520 outb(0x09,io+1);
1521 x_oldid=inb(io+2);
1522
1523 outb(key,io); /* Write Magic Byte to EFER, extended
1524 funtion enable register */
1525 outb(0x20,io+2); /* Write EFIR, extended function index register */
1526 devid=inb(io+2); /* Read EFDR, extended function data register */
1527 outb(0x21,io+1);
1528 devrev=inb(io+2);
1529 outb(0x09,io+1);
1530 oldid=inb(io+2);
1531 outb(0xaa,io); /* Magic Seal */
1532
1533 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1534 return; /* protection against false positives */
1535
1536 decode_winbond(io,key,devid,devrev,oldid);
1537 }
1538
1539 static void __devinit smsc_check(int io, int key)
1540 {
1541 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1542
1543 /* First probe without the key */
1544 outb(0x0d,io);
1545 x_oldid=inb(io+1);
1546 outb(0x0e,io);
1547 x_oldrev=inb(io+1);
1548 outb(0x20,io);
1549 x_id=inb(io+1);
1550 outb(0x21,io);
1551 x_rev=inb(io+1);
1552
1553 outb(key,io);
1554 outb(key,io); /* Write Magic Sequence to EFER, extended
1555 funtion enable register */
1556 outb(0x0d,io); /* Write EFIR, extended function index register */
1557 oldid=inb(io+1); /* Read EFDR, extended function data register */
1558 outb(0x0e,io);
1559 oldrev=inb(io+1);
1560 outb(0x20,io);
1561 id=inb(io+1);
1562 outb(0x21,io);
1563 rev=inb(io+1);
1564 outb(0xaa,io); /* Magic Seal */
1565
1566 if ((x_id == id) && (x_oldrev == oldrev) &&
1567 (x_oldid == oldid) && (x_rev == rev))
1568 return; /* protection against false positives */
1569
1570 decode_smsc(io,key,oldid,oldrev);
1571 }
1572
1573
1574 static void __devinit detect_and_report_winbond (void)
1575 {
1576 if (verbose_probing)
1577 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1578 winbond_check(0x3f0,0x87);
1579 winbond_check(0x370,0x87);
1580 winbond_check(0x2e ,0x87);
1581 winbond_check(0x4e ,0x87);
1582 winbond_check(0x3f0,0x86);
1583 winbond_check2(0x250,0x88);
1584 winbond_check2(0x250,0x89);
1585 }
1586
1587 static void __devinit detect_and_report_smsc (void)
1588 {
1589 if (verbose_probing)
1590 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1591 smsc_check(0x3f0,0x55);
1592 smsc_check(0x370,0x55);
1593 smsc_check(0x3f0,0x44);
1594 smsc_check(0x370,0x44);
1595 }
1596 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1597
1598 static int __devinit get_superio_dma (struct parport *p)
1599 {
1600 int i=0;
1601 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1602 i++;
1603 if (i!=NR_SUPERIOS)
1604 return superios[i].dma;
1605 return PARPORT_DMA_NONE;
1606 }
1607
1608 static int __devinit get_superio_irq (struct parport *p)
1609 {
1610 int i=0;
1611 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1612 i++;
1613 if (i!=NR_SUPERIOS)
1614 return superios[i].irq;
1615 return PARPORT_IRQ_NONE;
1616 }
1617
1618
1619 /* --- Mode detection ------------------------------------- */
1620
1621 /*
1622 * Checks for port existence, all ports support SPP MODE
1623 * Returns:
1624 * 0 : No parallel port at this address
1625 * PARPORT_MODE_PCSPP : SPP port detected
1626 * (if the user specified an ioport himself,
1627 * this shall always be the case!)
1628 *
1629 */
1630 static int __devinit parport_SPP_supported(struct parport *pb)
1631 {
1632 unsigned char r, w;
1633
1634 /*
1635 * first clear an eventually pending EPP timeout
1636 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1637 * that does not even respond to SPP cycles if an EPP
1638 * timeout is pending
1639 */
1640 clear_epp_timeout(pb);
1641
1642 /* Do a simple read-write test to make sure the port exists. */
1643 w = 0xc;
1644 outb (w, CONTROL (pb));
1645
1646 /* Is there a control register that we can read from? Some
1647 * ports don't allow reads, so read_control just returns a
1648 * software copy. Some ports _do_ allow reads, so bypass the
1649 * software copy here. In addition, some bits aren't
1650 * writable. */
1651 r = inb (CONTROL (pb));
1652 if ((r & 0xf) == w) {
1653 w = 0xe;
1654 outb (w, CONTROL (pb));
1655 r = inb (CONTROL (pb));
1656 outb (0xc, CONTROL (pb));
1657 if ((r & 0xf) == w)
1658 return PARPORT_MODE_PCSPP;
1659 }
1660
1661 if (user_specified)
1662 /* That didn't work, but the user thinks there's a
1663 * port here. */
1664 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1665 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1666
1667 /* Try the data register. The data lines aren't tri-stated at
1668 * this stage, so we expect back what we wrote. */
1669 w = 0xaa;
1670 parport_pc_write_data (pb, w);
1671 r = parport_pc_read_data (pb);
1672 if (r == w) {
1673 w = 0x55;
1674 parport_pc_write_data (pb, w);
1675 r = parport_pc_read_data (pb);
1676 if (r == w)
1677 return PARPORT_MODE_PCSPP;
1678 }
1679
1680 if (user_specified) {
1681 /* Didn't work, but the user is convinced this is the
1682 * place. */
1683 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1684 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1685 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1686 "but there is probably no parallel port there!\n",
1687 pb->base);
1688 }
1689
1690 /* It's possible that we can't read the control register or
1691 * the data register. In that case just believe the user. */
1692 if (user_specified)
1693 return PARPORT_MODE_PCSPP;
1694
1695 return 0;
1696 }
1697
1698 /* Check for ECR
1699 *
1700 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1701 * on these cards actually accesses the CTR.
1702 *
1703 * Modern cards don't do this but reading from ECR will return 0xff
1704 * regardless of what is written here if the card does NOT support
1705 * ECP.
1706 *
1707 * We first check to see if ECR is the same as CTR. If not, the low
1708 * two bits of ECR aren't writable, so we check by writing ECR and
1709 * reading it back to see if it's what we expect.
1710 */
1711 static int __devinit parport_ECR_present(struct parport *pb)
1712 {
1713 struct parport_pc_private *priv = pb->private_data;
1714 unsigned char r = 0xc;
1715
1716 outb (r, CONTROL (pb));
1717 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1718 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1719
1720 r = inb (CONTROL (pb));
1721 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1722 goto no_reg; /* Sure that no ECR register exists */
1723 }
1724
1725 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1726 goto no_reg;
1727
1728 ECR_WRITE (pb, 0x34);
1729 if (inb (ECONTROL (pb)) != 0x35)
1730 goto no_reg;
1731
1732 priv->ecr = 1;
1733 outb (0xc, CONTROL (pb));
1734
1735 /* Go to mode 000 */
1736 frob_set_mode (pb, ECR_SPP);
1737
1738 return 1;
1739
1740 no_reg:
1741 outb (0xc, CONTROL (pb));
1742 return 0;
1743 }
1744
1745 #ifdef CONFIG_PARPORT_1284
1746 /* Detect PS/2 support.
1747 *
1748 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1749 * allows us to read data from the data lines. In theory we would get back
1750 * 0xff but any peripheral attached to the port may drag some or all of the
1751 * lines down to zero. So if we get back anything that isn't the contents
1752 * of the data register we deem PS/2 support to be present.
1753 *
1754 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1755 * drivers, but an external peripheral with sufficiently beefy drivers of
1756 * its own can overpower them and assert its own levels onto the bus, from
1757 * where they can then be read back as normal. Ports with this property
1758 * and the right type of device attached are likely to fail the SPP test,
1759 * (as they will appear to have stuck bits) and so the fact that they might
1760 * be misdetected here is rather academic.
1761 */
1762
1763 static int __devinit parport_PS2_supported(struct parport *pb)
1764 {
1765 int ok = 0;
1766
1767 clear_epp_timeout(pb);
1768
1769 /* try to tri-state the buffer */
1770 parport_pc_data_reverse (pb);
1771
1772 parport_pc_write_data(pb, 0x55);
1773 if (parport_pc_read_data(pb) != 0x55) ok++;
1774
1775 parport_pc_write_data(pb, 0xaa);
1776 if (parport_pc_read_data(pb) != 0xaa) ok++;
1777
1778 /* cancel input mode */
1779 parport_pc_data_forward (pb);
1780
1781 if (ok) {
1782 pb->modes |= PARPORT_MODE_TRISTATE;
1783 } else {
1784 struct parport_pc_private *priv = pb->private_data;
1785 priv->ctr_writable &= ~0x20;
1786 }
1787
1788 return ok;
1789 }
1790
1791 #ifdef CONFIG_PARPORT_PC_FIFO
1792 static int __devinit parport_ECP_supported(struct parport *pb)
1793 {
1794 int i;
1795 int config, configb;
1796 int pword;
1797 struct parport_pc_private *priv = pb->private_data;
1798 /* Translate ECP intrLine to ISA irq value */
1799 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1800
1801 /* If there is no ECR, we have no hope of supporting ECP. */
1802 if (!priv->ecr)
1803 return 0;
1804
1805 /* Find out FIFO depth */
1806 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1807 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1808 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1809 outb (0xaa, FIFO (pb));
1810
1811 /*
1812 * Using LGS chipset it uses ECR register, but
1813 * it doesn't support ECP or FIFO MODE
1814 */
1815 if (i == 1024) {
1816 ECR_WRITE (pb, ECR_SPP << 5);
1817 return 0;
1818 }
1819
1820 priv->fifo_depth = i;
1821 if (verbose_probing)
1822 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1823
1824 /* Find out writeIntrThreshold */
1825 frob_econtrol (pb, 1<<2, 1<<2);
1826 frob_econtrol (pb, 1<<2, 0);
1827 for (i = 1; i <= priv->fifo_depth; i++) {
1828 inb (FIFO (pb));
1829 udelay (50);
1830 if (inb (ECONTROL (pb)) & (1<<2))
1831 break;
1832 }
1833
1834 if (i <= priv->fifo_depth) {
1835 if (verbose_probing)
1836 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1837 pb->base, i);
1838 } else
1839 /* Number of bytes we know we can write if we get an
1840 interrupt. */
1841 i = 0;
1842
1843 priv->writeIntrThreshold = i;
1844
1845 /* Find out readIntrThreshold */
1846 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1847 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1848 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1849 frob_econtrol (pb, 1<<2, 1<<2);
1850 frob_econtrol (pb, 1<<2, 0);
1851 for (i = 1; i <= priv->fifo_depth; i++) {
1852 outb (0xaa, FIFO (pb));
1853 if (inb (ECONTROL (pb)) & (1<<2))
1854 break;
1855 }
1856
1857 if (i <= priv->fifo_depth) {
1858 if (verbose_probing)
1859 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1860 pb->base, i);
1861 } else
1862 /* Number of bytes we can read if we get an interrupt. */
1863 i = 0;
1864
1865 priv->readIntrThreshold = i;
1866
1867 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1868 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1869 config = inb (CONFIGA (pb));
1870 pword = (config >> 4) & 0x7;
1871 switch (pword) {
1872 case 0:
1873 pword = 2;
1874 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1875 pb->base);
1876 break;
1877 case 2:
1878 pword = 4;
1879 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1880 pb->base);
1881 break;
1882 default:
1883 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1884 pb->base);
1885 /* Assume 1 */
1886 case 1:
1887 pword = 1;
1888 }
1889 priv->pword = pword;
1890
1891 if (verbose_probing) {
1892 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1893
1894 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1895 config & 0x80 ? "Level" : "Pulses");
1896
1897 configb = inb (CONFIGB (pb));
1898 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1899 pb->base, config, configb);
1900 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1901 if ((configb >>3) & 0x07)
1902 printk("%d",intrline[(configb >>3) & 0x07]);
1903 else
1904 printk("<none or set by other means>");
1905 printk (" dma=");
1906 if( (configb & 0x03 ) == 0x00)
1907 printk("<none or set by other means>\n");
1908 else
1909 printk("%d\n",configb & 0x07);
1910 }
1911
1912 /* Go back to mode 000 */
1913 frob_set_mode (pb, ECR_SPP);
1914
1915 return 1;
1916 }
1917 #endif
1918
1919 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1920 {
1921 const struct parport_pc_private *priv = pb->private_data;
1922 int result;
1923 unsigned char oecr;
1924
1925 if (!priv->ecr)
1926 return 0;
1927
1928 oecr = inb (ECONTROL (pb));
1929 ECR_WRITE (pb, ECR_PS2 << 5);
1930 result = parport_PS2_supported(pb);
1931 ECR_WRITE (pb, oecr);
1932 return result;
1933 }
1934
1935 /* EPP mode detection */
1936
1937 static int __devinit parport_EPP_supported(struct parport *pb)
1938 {
1939 const struct parport_pc_private *priv = pb->private_data;
1940
1941 /*
1942 * Theory:
1943 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1944 * when EPP is possible and is set high when an EPP timeout
1945 * occurs (EPP uses the HALT line to stop the CPU while it does
1946 * the byte transfer, an EPP timeout occurs if the attached
1947 * device fails to respond after 10 micro seconds).
1948 *
1949 * This bit is cleared by either reading it (National Semi)
1950 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1951 * This bit is always high in non EPP modes.
1952 */
1953
1954 /* If EPP timeout bit clear then EPP available */
1955 if (!clear_epp_timeout(pb)) {
1956 return 0; /* No way to clear timeout */
1957 }
1958
1959 /* Check for Intel bug. */
1960 if (priv->ecr) {
1961 unsigned char i;
1962 for (i = 0x00; i < 0x80; i += 0x20) {
1963 ECR_WRITE (pb, i);
1964 if (clear_epp_timeout (pb)) {
1965 /* Phony EPP in ECP. */
1966 return 0;
1967 }
1968 }
1969 }
1970
1971 pb->modes |= PARPORT_MODE_EPP;
1972
1973 /* Set up access functions to use EPP hardware. */
1974 pb->ops->epp_read_data = parport_pc_epp_read_data;
1975 pb->ops->epp_write_data = parport_pc_epp_write_data;
1976 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1977 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1978
1979 return 1;
1980 }
1981
1982 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1983 {
1984 struct parport_pc_private *priv = pb->private_data;
1985 int result;
1986 unsigned char oecr;
1987
1988 if (!priv->ecr) {
1989 return 0;
1990 }
1991
1992 oecr = inb (ECONTROL (pb));
1993 /* Search for SMC style EPP+ECP mode */
1994 ECR_WRITE (pb, 0x80);
1995 outb (0x04, CONTROL (pb));
1996 result = parport_EPP_supported(pb);
1997
1998 ECR_WRITE (pb, oecr);
1999
2000 if (result) {
2001 /* Set up access functions to use ECP+EPP hardware. */
2002 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
2003 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
2004 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
2005 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
2006 }
2007
2008 return result;
2009 }
2010
2011 #else /* No IEEE 1284 support */
2012
2013 /* Don't bother probing for modes we know we won't use. */
2014 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
2015 #ifdef CONFIG_PARPORT_PC_FIFO
2016 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
2017 #endif
2018 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
2019 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
2020 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
2021
2022 #endif /* No IEEE 1284 support */
2023
2024 /* --- IRQ detection -------------------------------------- */
2025
2026 /* Only if supports ECP mode */
2027 static int __devinit programmable_irq_support(struct parport *pb)
2028 {
2029 int irq, intrLine;
2030 unsigned char oecr = inb (ECONTROL (pb));
2031 static const int lookup[8] = {
2032 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
2033 };
2034
2035 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
2036
2037 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
2038 irq = lookup[intrLine];
2039
2040 ECR_WRITE (pb, oecr);
2041 return irq;
2042 }
2043
2044 static int __devinit irq_probe_ECP(struct parport *pb)
2045 {
2046 int i;
2047 unsigned long irqs;
2048
2049 irqs = probe_irq_on();
2050
2051 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
2052 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
2053 ECR_WRITE (pb, ECR_TST << 5);
2054
2055 /* If Full FIFO sure that writeIntrThreshold is generated */
2056 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
2057 outb (0xaa, FIFO (pb));
2058
2059 pb->irq = probe_irq_off(irqs);
2060 ECR_WRITE (pb, ECR_SPP << 5);
2061
2062 if (pb->irq <= 0)
2063 pb->irq = PARPORT_IRQ_NONE;
2064
2065 return pb->irq;
2066 }
2067
2068 /*
2069 * This detection seems that only works in National Semiconductors
2070 * This doesn't work in SMC, LGS, and Winbond
2071 */
2072 static int __devinit irq_probe_EPP(struct parport *pb)
2073 {
2074 #ifndef ADVANCED_DETECT
2075 return PARPORT_IRQ_NONE;
2076 #else
2077 int irqs;
2078 unsigned char oecr;
2079
2080 if (pb->modes & PARPORT_MODE_PCECR)
2081 oecr = inb (ECONTROL (pb));
2082
2083 irqs = probe_irq_on();
2084
2085 if (pb->modes & PARPORT_MODE_PCECR)
2086 frob_econtrol (pb, 0x10, 0x10);
2087
2088 clear_epp_timeout(pb);
2089 parport_pc_frob_control (pb, 0x20, 0x20);
2090 parport_pc_frob_control (pb, 0x10, 0x10);
2091 clear_epp_timeout(pb);
2092
2093 /* Device isn't expecting an EPP read
2094 * and generates an IRQ.
2095 */
2096 parport_pc_read_epp(pb);
2097 udelay(20);
2098
2099 pb->irq = probe_irq_off (irqs);
2100 if (pb->modes & PARPORT_MODE_PCECR)
2101 ECR_WRITE (pb, oecr);
2102 parport_pc_write_control(pb, 0xc);
2103
2104 if (pb->irq <= 0)
2105 pb->irq = PARPORT_IRQ_NONE;
2106
2107 return pb->irq;
2108 #endif /* Advanced detection */
2109 }
2110
2111 static int __devinit irq_probe_SPP(struct parport *pb)
2112 {
2113 /* Don't even try to do this. */
2114 return PARPORT_IRQ_NONE;
2115 }
2116
2117 /* We will attempt to share interrupt requests since other devices
2118 * such as sound cards and network cards seem to like using the
2119 * printer IRQs.
2120 *
2121 * When ECP is available we can autoprobe for IRQs.
2122 * NOTE: If we can autoprobe it, we can register the IRQ.
2123 */
2124 static int __devinit parport_irq_probe(struct parport *pb)
2125 {
2126 struct parport_pc_private *priv = pb->private_data;
2127
2128 if (priv->ecr) {
2129 pb->irq = programmable_irq_support(pb);
2130
2131 if (pb->irq == PARPORT_IRQ_NONE)
2132 pb->irq = irq_probe_ECP(pb);
2133 }
2134
2135 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2136 (pb->modes & PARPORT_MODE_EPP))
2137 pb->irq = irq_probe_EPP(pb);
2138
2139 clear_epp_timeout(pb);
2140
2141 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2142 pb->irq = irq_probe_EPP(pb);
2143
2144 clear_epp_timeout(pb);
2145
2146 if (pb->irq == PARPORT_IRQ_NONE)
2147 pb->irq = irq_probe_SPP(pb);
2148
2149 if (pb->irq == PARPORT_IRQ_NONE)
2150 pb->irq = get_superio_irq(pb);
2151
2152 return pb->irq;
2153 }
2154
2155 /* --- DMA detection -------------------------------------- */
2156
2157 /* Only if chipset conforms to ECP ISA Interface Standard */
2158 static int __devinit programmable_dma_support (struct parport *p)
2159 {
2160 unsigned char oecr = inb (ECONTROL (p));
2161 int dma;
2162
2163 frob_set_mode (p, ECR_CNF);
2164
2165 dma = inb (CONFIGB(p)) & 0x07;
2166 /* 000: Indicates jumpered 8-bit DMA if read-only.
2167 100: Indicates jumpered 16-bit DMA if read-only. */
2168 if ((dma & 0x03) == 0)
2169 dma = PARPORT_DMA_NONE;
2170
2171 ECR_WRITE (p, oecr);
2172 return dma;
2173 }
2174
2175 static int __devinit parport_dma_probe (struct parport *p)
2176 {
2177 const struct parport_pc_private *priv = p->private_data;
2178 if (priv->ecr)
2179 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2180 if (p->dma == PARPORT_DMA_NONE) {
2181 /* ask known Super-IO chips proper, although these
2182 claim ECP compatible, some don't report their DMA
2183 conforming to ECP standards */
2184 p->dma = get_superio_dma(p);
2185 }
2186
2187 return p->dma;
2188 }
2189
2190 /* --- Initialisation code -------------------------------- */
2191
2192 struct parport *parport_pc_probe_port (unsigned long int base,
2193 unsigned long int base_hi,
2194 int irq, int dma,
2195 struct pci_dev *dev)
2196 {
2197 struct parport_pc_private *priv;
2198 struct parport_operations *ops;
2199 struct parport tmp;
2200 struct parport *p = &tmp;
2201 int probedirq = PARPORT_IRQ_NONE;
2202 struct resource *base_res;
2203 struct resource *ECR_res = NULL;
2204 struct resource *EPP_res = NULL;
2205 char *fake_name = "parport probe";
2206
2207 /*
2208 * Chicken and Egg problem. request_region() wants the name of
2209 * the owner, but this instance will not know that name until
2210 * after the parport_register_port() call. Give request_region()
2211 * a fake name until after parport_register_port(), then use
2212 * rename_region() to set correct name.
2213 */
2214 base_res = request_region(base, 3, fake_name);
2215 if (base_res == NULL)
2216 return NULL;
2217 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2218 if (!priv) {
2219 printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
2220 release_region(base, 3);
2221 return NULL;
2222 }
2223 ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
2224 if (!ops) {
2225 printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
2226 base);
2227 release_region(base, 3);
2228 kfree (priv);
2229 return NULL;
2230 }
2231 memcpy (ops, &parport_pc_ops, sizeof (struct parport_operations));
2232 priv->ctr = 0xc;
2233 priv->ctr_writable = ~0x10;
2234 priv->ecr = 0;
2235 priv->fifo_depth = 0;
2236 priv->dma_buf = 0;
2237 priv->dma_handle = 0;
2238 priv->dev = dev;
2239 p->base = base;
2240 p->base_hi = base_hi;
2241 p->irq = irq;
2242 p->dma = dma;
2243 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2244 p->ops = ops;
2245 p->private_data = priv;
2246 p->physport = p;
2247
2248 if (base_hi) {
2249 ECR_res = request_region(base_hi, 3, fake_name);
2250 if (ECR_res)
2251 parport_ECR_present(p);
2252 }
2253
2254 if (base != 0x3bc) {
2255 EPP_res = request_region(base+0x3, 5, fake_name);
2256 if (EPP_res)
2257 if (!parport_EPP_supported(p))
2258 parport_ECPEPP_supported(p);
2259 }
2260 if (!parport_SPP_supported (p))
2261 /* No port. */
2262 goto errout;
2263 if (priv->ecr)
2264 parport_ECPPS2_supported(p);
2265 else
2266 parport_PS2_supported (p);
2267
2268 if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
2269 PARPORT_DMA_NONE, ops)))
2270 goto errout;
2271
2272 /*
2273 * Now the real name is known... Replace the fake name
2274 * in the resources with the correct one.
2275 */
2276 rename_region(base_res, p->name);
2277 if (ECR_res)
2278 rename_region(ECR_res, p->name);
2279 if (EPP_res)
2280 rename_region(EPP_res, p->name);
2281
2282 p->base_hi = base_hi;
2283 p->modes = tmp.modes;
2284 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2285 p->private_data = priv;
2286
2287 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2288 if (p->base_hi && priv->ecr)
2289 printk(" (0x%lx)", p->base_hi);
2290 p->irq = irq;
2291 p->dma = dma;
2292 if (p->irq == PARPORT_IRQ_AUTO) {
2293 p->irq = PARPORT_IRQ_NONE;
2294 parport_irq_probe(p);
2295 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2296 p->irq = PARPORT_IRQ_NONE;
2297 parport_irq_probe(p);
2298 probedirq = p->irq;
2299 p->irq = PARPORT_IRQ_NONE;
2300 }
2301 if (p->irq != PARPORT_IRQ_NONE) {
2302 printk(", irq %d", p->irq);
2303 priv->ctr_writable |= 0x10;
2304
2305 if (p->dma == PARPORT_DMA_AUTO) {
2306 p->dma = PARPORT_DMA_NONE;
2307 parport_dma_probe(p);
2308 }
2309 }
2310 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2311 is mandatory (see above) */
2312 p->dma = PARPORT_DMA_NONE;
2313
2314 #ifdef CONFIG_PARPORT_PC_FIFO
2315 if (parport_ECP_supported(p) &&
2316 p->dma != PARPORT_DMA_NOFIFO &&
2317 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2318 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2319 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2320 #ifdef CONFIG_PARPORT_1284
2321 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2322 /* currently broken, but working on it.. (FB) */
2323 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2324 #endif /* IEEE 1284 support */
2325 if (p->dma != PARPORT_DMA_NONE) {
2326 printk(", dma %d", p->dma);
2327 p->modes |= PARPORT_MODE_DMA;
2328 }
2329 else printk(", using FIFO");
2330 }
2331 else
2332 /* We can't use the DMA channel after all. */
2333 p->dma = PARPORT_DMA_NONE;
2334 #endif /* Allowed to use FIFO/DMA */
2335
2336 printk(" [");
2337 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2338 {
2339 int f = 0;
2340 printmode(PCSPP);
2341 printmode(TRISTATE);
2342 printmode(COMPAT)
2343 printmode(EPP);
2344 printmode(ECP);
2345 printmode(DMA);
2346 }
2347 #undef printmode
2348 #ifndef CONFIG_PARPORT_1284
2349 printk ("(,...)");
2350 #endif /* CONFIG_PARPORT_1284 */
2351 printk("]\n");
2352 if (probedirq != PARPORT_IRQ_NONE)
2353 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2354 parport_proc_register(p);
2355
2356 /* If No ECP release the ports grabbed above. */
2357 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2358 release_region(base_hi, 3);
2359 ECR_res = NULL;
2360 }
2361
2362 if (p->irq != PARPORT_IRQ_NONE) {
2363 if (request_irq (p->irq, parport_pc_interrupt,
2364 0, p->name, p)) {
2365 printk (KERN_WARNING "%s: irq %d in use, "
2366 "resorting to polled operation\n",
2367 p->name, p->irq);
2368 p->irq = PARPORT_IRQ_NONE;
2369 p->dma = PARPORT_DMA_NONE;
2370 }
2371
2372 #ifdef CONFIG_PARPORT_PC_FIFO
2373 if (p->dma != PARPORT_DMA_NONE) {
2374 if (request_dma (p->dma, p->name)) {
2375 printk (KERN_WARNING "%s: dma %d in use, "
2376 "resorting to PIO operation\n",
2377 p->name, p->dma);
2378 p->dma = PARPORT_DMA_NONE;
2379 } else {
2380 priv->dma_buf =
2381 pci_alloc_consistent(priv->dev,
2382 PAGE_SIZE,
2383 &priv->dma_handle);
2384 if (! priv->dma_buf) {
2385 printk (KERN_WARNING "%s: "
2386 "cannot get buffer for DMA, "
2387 "resorting to PIO operation\n",
2388 p->name);
2389 free_dma(p->dma);
2390 p->dma = PARPORT_DMA_NONE;
2391 }
2392 }
2393 }
2394 #endif /* CONFIG_PARPORT_PC_FIFO */
2395 }
2396
2397 /* Done probing. Now put the port into a sensible start-up state. */
2398 if (priv->ecr)
2399 /*
2400 * Put the ECP detected port in PS2 mode.
2401 * Do this also for ports that have ECR but don't do ECP.
2402 */
2403 ECR_WRITE (p, 0x34);
2404
2405 parport_pc_write_data(p, 0);
2406 parport_pc_data_forward (p);
2407
2408 /* Now that we've told the sharing engine about the port, and
2409 found out its characteristics, let the high-level drivers
2410 know about it. */
2411 parport_announce_port (p);
2412
2413 return p;
2414
2415 errout:
2416 release_region(p->base, 3);
2417 if (ECR_res)
2418 release_region(base_hi, 3);
2419 if (EPP_res)
2420 release_region(base+0x3, 5);
2421
2422 kfree (priv);
2423 kfree (ops);
2424 return NULL;
2425 }
2426
2427 void parport_pc_unregister_port (struct parport *p)
2428 {
2429 #ifdef CONFIG_PARPORT_PC_FIFO
2430 struct parport_pc_private *priv = p->private_data;
2431 #endif /* CONFIG_PARPORT_PC_FIFO */
2432 struct parport_operations *ops = p->ops;
2433 if (p->dma != PARPORT_DMA_NONE)
2434 free_dma(p->dma);
2435 if (p->irq != PARPORT_IRQ_NONE)
2436 free_irq(p->irq, p);
2437 release_region(p->base, 3);
2438 if (p->size > 3)
2439 release_region(p->base + 3, p->size - 3);
2440 if (p->modes & PARPORT_MODE_ECP)
2441 release_region(p->base_hi, 3);
2442 parport_proc_unregister(p);
2443 #ifdef CONFIG_PARPORT_PC_FIFO
2444 if (priv->dma_buf)
2445 pci_free_consistent(priv->dev, PAGE_SIZE,
2446 priv->dma_buf,
2447 priv->dma_handle);
2448 #endif /* CONFIG_PARPORT_PC_FIFO */
2449 kfree (p->private_data);
2450 parport_unregister_port(p);
2451 kfree (ops); /* hope no-one cached it */
2452 }
2453
2454 #ifdef CONFIG_PCI
2455
2456 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2457 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2458 int autodma)
2459 {
2460 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2461 struct resource *base_res;
2462 u32 ite8872set;
2463 u32 ite8872_lpt, ite8872_lpthi;
2464 u8 ite8872_irq, type;
2465 char *fake_name = "parport probe";
2466 int irq;
2467 int i;
2468
2469 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2470
2471 // make sure which one chip
2472 for(i = 0; i < 5; i++) {
2473 base_res = request_region(inta_addr[i], 0x8, fake_name);
2474 if (base_res) {
2475 int test;
2476 pci_write_config_dword (pdev, 0x60,
2477 0xe7000000 | inta_addr[i]);
2478 pci_write_config_dword (pdev, 0x78,
2479 0x00000000 | inta_addr[i]);
2480 test = inb (inta_addr[i]);
2481 if (test != 0xff) break;
2482 release_region(inta_addr[i], 0x8);
2483 }
2484 }
2485 if(i >= 5) {
2486 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2487 return 0;
2488 }
2489
2490 type = inb (inta_addr[i] + 0x18);
2491 type &= 0x0f;
2492
2493 switch (type) {
2494 case 0x2:
2495 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2496 ite8872set = 0x64200000;
2497 break;
2498 case 0xa:
2499 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2500 ite8872set = 0x64200000;
2501 break;
2502 case 0xe:
2503 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2504 ite8872set = 0x64e00000;
2505 break;
2506 case 0x6:
2507 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2508 return 0;
2509 case 0x8:
2510 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2511 return 0;
2512 default:
2513 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2514 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2515 "output to Rich.Liu@ite.com.tw\n");
2516 return 0;
2517 }
2518
2519 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2520 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2521 ite8872_lpt &= 0x0000ff00;
2522 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2523 ite8872_lpthi &= 0x0000ff00;
2524 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2525 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2526 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2527 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2528 // SET Parallel IRQ
2529 pci_write_config_dword (pdev, 0x9c,
2530 ite8872set | (ite8872_irq * 0x11111));
2531
2532 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2533 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2534 ite8872_lpt);
2535 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2536 ite8872_lpthi);
2537
2538 /* Let the user (or defaults) steer us away from interrupts */
2539 irq = ite8872_irq;
2540 if (autoirq != PARPORT_IRQ_AUTO)
2541 irq = PARPORT_IRQ_NONE;
2542
2543 /*
2544 * Release the resource so that parport_pc_probe_port can get it.
2545 */
2546 release_resource(base_res);
2547 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2548 irq, PARPORT_DMA_NONE, NULL)) {
2549 printk (KERN_INFO
2550 "parport_pc: ITE 8872 parallel port: io=0x%X",
2551 ite8872_lpt);
2552 if (irq != PARPORT_IRQ_NONE)
2553 printk (", irq=%d", irq);
2554 printk ("\n");
2555 return 1;
2556 }
2557
2558 return 0;
2559 }
2560
2561 /* Via support maintained by Jeff Garzik <jgarzik@pobox.com> */
2562 static int __devinit sio_via_686a_probe (struct pci_dev *pdev, int autoirq,
2563 int autodma)
2564 {
2565 u8 tmp;
2566 int dma, irq;
2567 unsigned port1, port2, have_eppecp;
2568
2569 /*
2570 * unlock super i/o configuration, set 0x85_1
2571 */
2572 pci_read_config_byte (pdev, 0x85, &tmp);
2573 tmp |= (1 << 1);
2574 pci_write_config_byte (pdev, 0x85, tmp);
2575
2576 /*
2577 * Super I/O configuration, index port == 3f0h, data port == 3f1h
2578 */
2579
2580 /* 0xE2_1-0: Parallel Port Mode / Enable */
2581 outb (0xE2, 0x3F0);
2582 tmp = inb (0x3F1);
2583
2584 if ((tmp & 0x03) == 0x03) {
2585 printk (KERN_INFO "parport_pc: Via 686A parallel port disabled in BIOS\n");
2586 return 0;
2587 }
2588
2589 /* 0xE6: Parallel Port I/O Base Address, bits 9-2 */
2590 outb (0xE6, 0x3F0);
2591 port1 = inb (0x3F1) << 2;
2592
2593 switch (port1) {
2594 case 0x3bc: port2 = 0x7bc; break;
2595 case 0x378: port2 = 0x778; break;
2596 case 0x278: port2 = 0x678; break;
2597 default:
2598 printk (KERN_INFO "parport_pc: Weird Via 686A parport base 0x%X, ignoring\n",
2599 port1);
2600 return 0;
2601 }
2602
2603 /* 0xF0_5: EPP+ECP enable */
2604 outb (0xF0, 0x3F0);
2605 have_eppecp = (inb (0x3F1) & (1 << 5));
2606
2607 /*
2608 * lock super i/o configuration, clear 0x85_1
2609 */
2610 pci_read_config_byte (pdev, 0x85, &tmp);
2611 tmp &= ~(1 << 1);
2612 pci_write_config_byte (pdev, 0x85, tmp);
2613
2614 /*
2615 * Get DMA and IRQ from PCI->ISA bridge PCI config registers
2616 */
2617
2618 /* 0x50_3-2: PnP Routing for Parallel Port DRQ */
2619 pci_read_config_byte (pdev, 0x50, &tmp);
2620 dma = ((tmp >> 2) & 0x03);
2621
2622 /* 0x51_7-4: PnP Routing for Parallel Port IRQ */
2623 pci_read_config_byte (pdev, 0x51, &tmp);
2624 irq = ((tmp >> 4) & 0x0F);
2625
2626 /* filter bogus IRQs */
2627 switch (irq) {
2628 case 0:
2629 case 2:
2630 case 8:
2631 case 13:
2632 irq = PARPORT_IRQ_NONE;
2633 break;
2634
2635 default: /* do nothing */
2636 break;
2637 }
2638
2639 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2640 if (!have_eppecp)
2641 dma = PARPORT_DMA_NONE;
2642
2643 /* Let the user (or defaults) steer us away from interrupts and DMA */
2644 if (autoirq != PARPORT_IRQ_AUTO) {
2645 irq = PARPORT_IRQ_NONE;
2646 dma = PARPORT_DMA_NONE;
2647 }
2648 if (autodma != PARPORT_DMA_AUTO)
2649 dma = PARPORT_DMA_NONE;
2650
2651 /* finally, do the probe with values obtained */
2652 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2653 printk (KERN_INFO
2654 "parport_pc: Via 686A parallel port: io=0x%X", port1);
2655 if (irq != PARPORT_IRQ_NONE)
2656 printk (", irq=%d", irq);
2657 if (dma != PARPORT_DMA_NONE)
2658 printk (", dma=%d", dma);
2659 printk ("\n");
2660 return 1;
2661 }
2662
2663 printk (KERN_WARNING "parport_pc: Strange, can't probe Via 686A parallel port: io=0x%X, irq=%d, dma=%d\n",
2664 port1, irq, dma);
2665 return 0;
2666 }
2667
2668
2669 enum parport_pc_sio_types {
2670 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2671 sio_ite_8872,
2672 last_sio
2673 };
2674
2675 /* each element directly indexed from enum list, above */
2676 static struct parport_pc_superio {
2677 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma);
2678 } parport_pc_superio_info[] __devinitdata = {
2679 { sio_via_686a_probe, },
2680 { sio_ite_8872_probe, },
2681 };
2682
2683
2684 enum parport_pc_pci_cards {
2685 siig_1s1p_10x_550 = last_sio,
2686 siig_1s1p_10x_650,
2687 siig_1s1p_10x_850,
2688 siig_1p_10x,
2689 siig_2p_10x,
2690 siig_2s1p_10x_550,
2691 siig_2s1p_10x_650,
2692 siig_2s1p_10x_850,
2693 siig_1p_20x,
2694 siig_2p_20x,
2695 siig_2p1s_20x_550,
2696 siig_2p1s_20x_650,
2697 siig_2p1s_20x_850,
2698 siig_1s1p_20x_550,
2699 siig_1s1p_20x_650,
2700 siig_1s1p_20x_850,
2701 siig_2s1p_20x_550,
2702 siig_2s1p_20x_650,
2703 siig_2s1p_20x_850,
2704 lava_parallel,
2705 lava_parallel_dual_a,
2706 lava_parallel_dual_b,
2707 boca_ioppar,
2708 plx_9050,
2709 timedia_4078a,
2710 timedia_4079h,
2711 timedia_4085h,
2712 timedia_4088a,
2713 timedia_4089a,
2714 timedia_4095a,
2715 timedia_4096a,
2716 timedia_4078u,
2717 timedia_4079a,
2718 timedia_4085u,
2719 timedia_4079r,
2720 timedia_4079s,
2721 timedia_4079d,
2722 timedia_4079e,
2723 timedia_4079f,
2724 timedia_9079a,
2725 timedia_9079b,
2726 timedia_9079c,
2727 timedia_4006a,
2728 timedia_4014,
2729 timedia_4008a,
2730 timedia_4018,
2731 timedia_9018a,
2732 syba_2p_epp,
2733 syba_1p_ecp,
2734 titan_010l,
2735 titan_1284p2,
2736 avlab_1p,
2737 avlab_2p,
2738 oxsemi_954,
2739 oxsemi_840,
2740 aks_0100,
2741 mobility_pp,
2742 };
2743
2744
2745 /* each element directly indexed from enum list, above
2746 * (but offset by last_sio) */
2747 static struct parport_pc_pci {
2748 int numports;
2749 struct { /* BAR (base address registers) numbers in the config
2750 space header */
2751 int lo;
2752 int hi; /* -1 if not there, >6 for offset-method (max
2753 BAR is 6) */
2754 } addr[4];
2755
2756 /* If set, this is called immediately after pci_enable_device.
2757 * If it returns non-zero, no probing will take place and the
2758 * ports will not be used. */
2759 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2760
2761 /* If set, this is called after probing for ports. If 'failed'
2762 * is non-zero we couldn't use any of the ports. */
2763 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2764 } cards[] __devinitdata = {
2765 /* siig_1s1p_10x_550 */ { 1, { { 3, 4 }, } },
2766 /* siig_1s1p_10x_650 */ { 1, { { 3, 4 }, } },
2767 /* siig_1s1p_10x_850 */ { 1, { { 3, 4 }, } },
2768 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2769 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2770 /* siig_2s1p_10x_550 */ { 1, { { 4, 5 }, } },
2771 /* siig_2s1p_10x_650 */ { 1, { { 4, 5 }, } },
2772 /* siig_2s1p_10x_850 */ { 1, { { 4, 5 }, } },
2773 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2774 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2775 /* siig_2p1s_20x_550 */ { 2, { { 1, 2 }, { 3, 4 }, } },
2776 /* siig_2p1s_20x_650 */ { 2, { { 1, 2 }, { 3, 4 }, } },
2777 /* siig_2p1s_20x_850 */ { 2, { { 1, 2 }, { 3, 4 }, } },
2778 /* siig_1s1p_20x_550 */ { 1, { { 1, 2 }, } },
2779 /* siig_1s1p_20x_650 */ { 1, { { 1, 2 }, } },
2780 /* siig_1s1p_20x_850 */ { 1, { { 1, 2 }, } },
2781 /* siig_2s1p_20x_550 */ { 1, { { 2, 3 }, } },
2782 /* siig_2s1p_20x_650 */ { 1, { { 2, 3 }, } },
2783 /* siig_2s1p_20x_850 */ { 1, { { 2, 3 }, } },
2784 /* lava_parallel */ { 1, { { 0, -1 }, } },
2785 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2786 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2787 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2788 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2789 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2790 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2791 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2792 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2793 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2794 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2795 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2796 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2797 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2798 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2799 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2800 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2801 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2802 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2803 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2804 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2805 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2806 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2807 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2808 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2809 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2810 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2811 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2812 /* SYBA uses fixed offsets in
2813 a 1K io window */
2814 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2815 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2816 /* titan_010l */ { 1, { { 3, -1 }, } },
2817 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2818 /* avlab_1p */ { 1, { { 0, 1}, } },
2819 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2820 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2821 * and 840 locks up if you write 1 to bit 2! */
2822 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2823 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2824 /* aks_0100 */ { 1, { { 0, 1 }, } },
2825 /* mobility_pp */ { 1, { { 0, 1 }, } },
2826 };
2827
2828 static struct pci_device_id parport_pc_pci_tbl[] = {
2829 /* Super-IO onboard chips */
2830 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2831 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2832 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2833
2834 /* PCI cards */
2835 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x_550 },
2837 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
2838 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x_650 },
2839 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
2840 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x_850 },
2841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2843 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2844 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2845 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
2846 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x_550 },
2847 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
2848 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x_650 },
2849 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
2850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x_850 },
2851 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2852 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2853 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2854 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2855 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
2856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x_550 },
2857 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
2858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x_650 },
2859 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
2860 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x_850 },
2861 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
2862 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_550 },
2863 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
2864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x_650 },
2865 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
2866 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x_850 },
2867 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
2868 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_550 },
2869 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
2870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_650 },
2871 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
2872 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_850 },
2873 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2874 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2875 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2876 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2877 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2878 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2879 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2880 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2881 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2882 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2883 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2884 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2885 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2886 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2887 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2888 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2889 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2890 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2891 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2892 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2893 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2894 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2895 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2896 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2897 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2898 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2899 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2900 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2901 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2902 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2903 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2904 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2905 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2906 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2907 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2908 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2910 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2911 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2912 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2913 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2914 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2915 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2916 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2917 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2918 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2919 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2920 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2921 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2922 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2923 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2924 { 0, } /* terminate list */
2925 };
2926 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2927
2928 static int __devinit parport_pc_pci_probe (struct pci_dev *dev,
2929 const struct pci_device_id *id)
2930 {
2931 int err, count, n, i = id->driver_data;
2932 if (i < last_sio)
2933 /* This is an onboard Super-IO and has already been probed */
2934 return 0;
2935
2936 /* This is a PCI card */
2937 i -= last_sio;
2938 count = 0;
2939 if ((err = pci_enable_device (dev)) != 0)
2940 return err;
2941
2942 if (cards[i].preinit_hook &&
2943 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
2944 return -ENODEV;
2945
2946 for (n = 0; n < cards[i].numports; n++) {
2947 int lo = cards[i].addr[n].lo;
2948 int hi = cards[i].addr[n].hi;
2949 unsigned long io_lo, io_hi;
2950 io_lo = pci_resource_start (dev, lo);
2951 io_hi = 0;
2952 if ((hi >= 0) && (hi <= 6))
2953 io_hi = pci_resource_start (dev, hi);
2954 else if (hi > 6)
2955 io_lo += hi; /* Reinterpret the meaning of
2956 "hi" as an offset (see SYBA
2957 def.) */
2958 /* TODO: test if sharing interrupts works */
2959 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2960 "I/O at %#lx(%#lx)\n",
2961 parport_pc_pci_tbl[i + last_sio].vendor,
2962 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2963 if (parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2964 PARPORT_DMA_NONE, dev))
2965 count++;
2966 }
2967
2968 if (cards[i].postinit_hook)
2969 cards[i].postinit_hook (dev, count == 0);
2970
2971 return count == 0 ? -ENODEV : 0;
2972 }
2973
2974 static struct pci_driver parport_pc_pci_driver = {
2975 .name = "parport_pc",
2976 .id_table = parport_pc_pci_tbl,
2977 .probe = parport_pc_pci_probe,
2978 };
2979
2980 static int __init parport_pc_init_superio (int autoirq, int autodma)
2981 {
2982 const struct pci_device_id *id;
2983 struct pci_dev *pdev = NULL;
2984 int ret = 0;
2985
2986 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
2987 id = pci_match_device (parport_pc_pci_tbl, pdev);
2988 if (id == NULL || id->driver_data >= last_sio)
2989 continue;
2990
2991 if (parport_pc_superio_info[id->driver_data].probe
2992 (pdev, autoirq, autodma)) {
2993 ret++;
2994 }
2995 }
2996
2997 return ret; /* number of devices found */
2998 }
2999 #else
3000 static struct pci_driver parport_pc_pci_driver;
3001 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
3002 #endif /* CONFIG_PCI */
3003
3004 #ifdef CONFIG_PNP
3005 static const struct pnp_device_id pnp_dev_table[] = {
3006 /* Standard LPT Printer Port */
3007 {.id = "PNP0400", .driver_data = 0},
3008 /* ECP Printer Port */
3009 {.id = "PNP0401", .driver_data = 0},
3010 {.id = ""}
3011 };
3012
3013 /* we only need the pnp layer to activate the device, at least for now */
3014 static struct pnp_driver parport_pc_pnp_driver = {
3015 .name = "parport_pc",
3016 .id_table = pnp_dev_table,
3017 };
3018 #else
3019 static struct pnp_driver parport_pc_pnp_driver;
3020 #endif
3021
3022 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3023 static int __init __attribute__((unused))
3024 parport_pc_find_isa_ports (int autoirq, int autodma)
3025 {
3026 int count = 0;
3027
3028 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
3029 count++;
3030 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
3031 count++;
3032 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
3033 count++;
3034
3035 return count;
3036 }
3037
3038 /* This function is called by parport_pc_init if the user didn't
3039 * specify any ports to probe. Its job is to find some ports. Order
3040 * is important here -- we want ISA ports to be registered first,
3041 * followed by PCI cards (for least surprise), but before that we want
3042 * to do chipset-specific tests for some onboard ports that we know
3043 * about.
3044 *
3045 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3046 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3047 */
3048 static int __init parport_pc_find_ports (int autoirq, int autodma)
3049 {
3050 int count = 0, r;
3051
3052 #ifdef CONFIG_PARPORT_PC_SUPERIO
3053 detect_and_report_winbond ();
3054 detect_and_report_smsc ();
3055 #endif
3056
3057 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3058 count += parport_pc_init_superio (autoirq, autodma);
3059
3060 /* ISA ports and whatever (see asm/parport.h). */
3061 count += parport_pc_find_nonpci_ports (autoirq, autodma);
3062
3063 r = pci_register_driver (&parport_pc_pci_driver);
3064 if (r >= 0) {
3065 registered_parport = 1;
3066 count += r;
3067 }
3068
3069 return count;
3070 }
3071
3072 int __init parport_pc_init (int *io, int *io_hi, int *irq, int *dma)
3073 {
3074 int count = 0, i = 0;
3075 /* try to activate any PnP parports first */
3076 pnp_register_driver(&parport_pc_pnp_driver);
3077
3078 if (io && *io) {
3079 /* Only probe the ports we were given. */
3080 user_specified = 1;
3081 do {
3082 if ((*io_hi) == PARPORT_IOHI_AUTO)
3083 *io_hi = 0x400 + *io;
3084 if (parport_pc_probe_port(*(io++), *(io_hi++),
3085 *(irq++), *(dma++), NULL))
3086 count++;
3087 } while (*io && (++i < PARPORT_PC_MAX_PORTS));
3088 } else {
3089 count += parport_pc_find_ports (irq[0], dma[0]);
3090 }
3091
3092 return count;
3093 }
3094
3095 /* Exported symbols. */
3096 EXPORT_SYMBOL (parport_pc_probe_port);
3097 EXPORT_SYMBOL (parport_pc_unregister_port);
3098
3099 #ifdef MODULE
3100 static int io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
3101 static int io_hi[PARPORT_PC_MAX_PORTS+1] =
3102 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
3103 static int dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
3104 static int irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
3105 static const char *irq[PARPORT_PC_MAX_PORTS] = { NULL, };
3106 static const char *dma[PARPORT_PC_MAX_PORTS] = { NULL, };
3107
3108 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3109 MODULE_DESCRIPTION("PC-style parallel port driver");
3110 MODULE_LICENSE("GPL");
3111
3112 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3113 MODULE_PARM(io, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3114 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3115 MODULE_PARM(io_hi, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3116 MODULE_PARM_DESC(irq, "IRQ line");
3117 MODULE_PARM(irq, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3118 MODULE_PARM_DESC(dma, "DMA channel");
3119 MODULE_PARM(dma, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3120 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3121 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3122 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3123 MODULE_PARM(verbose_probing, "i");
3124 #endif
3125
3126 int init_module(void)
3127 {
3128 /* Work out how many ports we have, then get parport_share to parse
3129 the irq values. */
3130 unsigned int i;
3131 int ret;
3132 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++);
3133 if (i) {
3134 if (parport_parse_irqs(i, irq, irqval)) return 1;
3135 if (parport_parse_dmas(i, dma, dmaval)) return 1;
3136 }
3137 else {
3138 /* The user can make us use any IRQs or DMAs we find. */
3139 int val;
3140
3141 if (irq[0] && !parport_parse_irqs (1, irq, &val))
3142 switch (val) {
3143 case PARPORT_IRQ_NONE:
3144 case PARPORT_IRQ_AUTO:
3145 irqval[0] = val;
3146 break;
3147 default:
3148 printk (KERN_WARNING
3149 "parport_pc: irq specified "
3150 "without base address. Use 'io=' "
3151 "to specify one\n");
3152 }
3153
3154 if (dma[0] && !parport_parse_dmas (1, dma, &val))
3155 switch (val) {
3156 case PARPORT_DMA_NONE:
3157 case PARPORT_DMA_AUTO:
3158 dmaval[0] = val;
3159 break;
3160 default:
3161 printk (KERN_WARNING
3162 "parport_pc: dma specified "
3163 "without base address. Use 'io=' "
3164 "to specify one\n");
3165 }
3166 }
3167
3168 ret = !parport_pc_init (io, io_hi, irqval, dmaval);
3169 if (ret && registered_parport)
3170 pci_unregister_driver (&parport_pc_pci_driver);
3171
3172 return ret;
3173 }
3174
3175 void cleanup_module(void)
3176 {
3177 /* We ought to keep track of which ports are actually ours. */
3178 struct parport *p = parport_enumerate(), *tmp;
3179
3180 if (!user_specified)
3181 pci_unregister_driver (&parport_pc_pci_driver);
3182
3183 while (p) {
3184 tmp = p->next;
3185 if (p->modes & PARPORT_MODE_PCSPP)
3186 parport_pc_unregister_port (p);
3187
3188 p = tmp;
3189 }
3190 pnp_unregister_driver (&parport_pc_pnp_driver);
3191 }
3192 #endif
Historical 2.5/2.6 development