1 /******************************************************************************
4 * Project: Gigabit Ethernet Adapters, Common Modules
5 * Version: $Revision: 1.93 $
6 * Date: $Date: 2003/05/28 15:44:43 $
7 * Purpose: Contains functions to initialize the adapter
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2002 SysKonnect.
14 * (C)Copyright 2002-2003 Marvell.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * The information in this file is provided "AS IS" without warranty.
23 ******************************************************************************/
25 /******************************************************************************
29 * $Log: skgeinit.c,v $
30 * Revision 1.93 2003/05/28 15:44:43 rschmidt
31 * Added check for chip Id on WOL WA for chip Rev. A.
32 * Added setting of GILevel in SkGeDeInit().
33 * Minor changes to avoid LINT warnings.
36 * Revision 1.92 2003/05/13 17:42:26 mkarl
37 * Added SK_FAR for PXE.
38 * Separated code pathes not used for SLIM driver to reduce code size.
39 * Removed calls to I2C for SLIM driver.
40 * Removed currently unused function SkGeLoadLnkSyncCnt.
43 * Revision 1.91 2003/05/06 12:21:48 rschmidt
44 * Added use of pAC->GIni.GIYukon for selection of YUKON branches.
45 * Added defines around GENESIS resp. YUKON branches to reduce
49 * Revision 1.90 2003/04/28 09:12:20 rschmidt
50 * Added init for GIValIrqMask (common IRQ mask).
51 * Disabled HW Error IRQ on Yukon if sensor IRQ is set in SkGeInit1()
52 * by changing the common mask stored in GIValIrqMask.
55 * Revision 1.89 2003/04/10 14:33:10 rschmidt
56 * Fixed alignement error of patchable configuration parameter
57 * in struct OemConfig caused by length of recognition string.
59 * Revision 1.88 2003/04/09 12:59:45 rschmidt
60 * Added define around initialization of patchable OEM specific
61 * configuration parameter.
63 * Revision 1.87 2003/04/08 16:46:13 rschmidt
64 * Added configuration variable for OEMs and initialization for
65 * GILedBlinkCtrl (LED Blink Control).
66 * Improved detection for YUKON-Lite Rev. A1.
69 * Revision 1.86 2003/03/31 06:53:13 mkarl
70 * Corrected Copyright.
73 * Revision 1.85 2003/02/05 15:30:33 rschmidt
74 * Corrected setting of GIHstClkFact (Host Clock Factor) and
75 * GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON.
78 * Revision 1.84 2003/01/28 09:57:25 rschmidt
79 * Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite).
80 * Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0.
81 * Added support for CLK_RUN (YUKON-Lite).
82 * Added additional check of PME from D3cold for setting GIVauxAvail.
85 * Revision 1.83 2002/12/17 16:15:41 rschmidt
86 * Added default setting of PhyType (Copper) for YUKON.
87 * Added define around check for HW self test results.
90 * Revision 1.82 2002/12/05 13:40:21 rschmidt
91 * Added setting of Rx GMAC FIFO Flush Mask register.
92 * Corrected PhyType with new define SK_PHY_MARV_FIBER when
93 * YUKON Fiber board was found.
96 * Revision 1.81 2002/11/15 12:48:35 rschmidt
97 * Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error
99 * Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch.
102 * Revision 1.80 2002/11/12 17:28:30 rschmidt
103 * Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1().
104 * Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu().
107 * Revision 1.79 2002/10/21 09:31:02 mkarl
108 * Changed SkGeInitAssignRamToQueues(), removed call to
109 * SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in
112 * Revision 1.78 2002/10/16 15:55:07 mkarl
113 * Fixed a bug in SkGeInitAssignRamToQueues.
115 * Revision 1.77 2002/10/14 15:07:22 rschmidt
116 * Corrected timeout handling for Rx queue in SkGeStopPort() (#10748)
119 * Revision 1.76 2002/10/11 09:24:38 mkarl
120 * Added check for HW self test results.
122 * Revision 1.75 2002/10/09 16:56:44 mkarl
123 * Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign
124 * the adapter memory to the queues. This default assignment is not suitable
127 * Revision 1.74 2002/09/12 08:45:06 rwahl
128 * Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY.
130 * Revision 1.73 2002/08/16 15:19:45 rschmidt
131 * Corrected check for Tx queues in SkGeCheckQSize().
132 * Added init for new entry GIGenesis and GICopperType
133 * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
134 * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros.
136 * Revision 1.72 2002/08/12 13:38:55 rschmidt
137 * Added check if VAUX is available (stored in GIVauxAvail)
138 * Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS
141 * Revision 1.71 2002/08/08 16:32:58 rschmidt
142 * Added check for Tx queues in SkGeCheckQSize().
143 * Added start of Time Stamp Timer (YUKON) in SkGeInit2().
146 * Revision 1.70 2002/07/23 16:04:26 rschmidt
147 * Added init for GIWolOffs (HW-Bug in YUKON 1st rev.)
150 * Revision 1.69 2002/07/17 17:07:08 rwahl
151 * - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc
153 * - Editorial changes.
155 * Revision 1.68 2002/07/15 18:38:31 rwahl
156 * Added initialization for MAC type dependent function table.
158 * Revision 1.67 2002/07/15 15:45:39 rschmidt
159 * Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB)
160 * Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER
163 * Revision 1.66 2002/06/10 09:35:08 rschmidt
164 * Replaced C++ comments (//)
167 * Revision 1.65 2002/06/05 08:33:37 rschmidt
168 * Changed GIRamSize and Reset sequence for YUKON.
169 * SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac()
171 * Revision 1.64 2002/04/25 13:03:20 rschmidt
172 * Changes for handling YUKON.
173 * Removed reference to xmac_ii.h (not necessary).
174 * Moved all defines into header file.
175 * Replaced all SkXm...() functions with SkMac...() to handle also
177 * Added handling for GMAC FIFO in SkGeInitMacFifo(), SkGeStopPort().
178 * Removed 'goto'-directive from SkGeCfgSync(), SkGeCheckQSize().
179 * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(),
180 * SkMacFlushTxFifo().
181 * Optimized timeout handling in SkGeStopPort().
182 * Initialized PLinkSpeed in Port struct with SK_LSPEED_AUTO.
183 * Release of GMAC Link Control reset in SkGeInit1().
184 * Initialized GIChipId and GIChipRev in GE Init structure.
185 * Added GIRamSize and PhyType values for YUKON.
186 * Removed use of PRxCmd to setup XMAC.
187 * Moved setting of XM_RX_DIS_CEXT to SkXmInitMac().
188 * Use of SkGeXmitLED() only for GENESIS.
189 * Changes for V-CPU support.
192 * Revision 1.63 2001/04/05 11:02:09 rassmann
193 * Stop Port check of the STOP bit did not take 2/18 sec as wanted.
195 * Revision 1.62 2001/02/07 07:54:21 rassmann
196 * Corrected copyright.
198 * Revision 1.61 2001/01/31 15:31:40 gklug
199 * fix: problem with autosensing an SR8800 switch
201 * Revision 1.60 2000/10/18 12:22:21 cgoos
202 * Added workaround for half duplex hangup.
204 * Revision 1.59 2000/10/10 11:22:06 gklug
205 * add: in manual half duplex mode ignore carrier extension errors
207 * Revision 1.58 2000/10/02 14:10:27 rassmann
208 * Reading BCOM PHY after releasing reset until it returns a valid value.
210 * Revision 1.57 2000/08/03 14:55:28 rassmann
211 * Waiting for I2C to be ready before de-initializing adapter
212 * (prevents sensors from hanging up).
214 * Revision 1.56 2000/07/27 12:16:48 gklug
215 * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted
217 * Revision 1.55 1999/11/22 13:32:26 cgoos
218 * Changed license header to GPL.
220 * Revision 1.54 1999/10/26 07:32:54 malthoff
221 * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics.
223 * Revision 1.53 1999/08/12 19:13:50 malthoff
224 * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when
225 * disabling receiver and transmitter. Other bits
228 * Revision 1.52 1999/07/01 09:29:54 gklug
229 * fix: DoInitRamQueue needs pAC
231 * Revision 1.51 1999/07/01 08:42:21 gklug
232 * chg: use Store & forward for RAM buffer when Jumbos are used
234 * Revision 1.50 1999/05/27 13:19:38 cgoos
235 * Added Tx PCI watermark initialization.
236 * Removed Tx RAM queue Store & Forward setting.
238 * Revision 1.49 1999/05/20 14:32:45 malthoff
239 * SkGeLinkLED() is completly removed now.
241 * Revision 1.48 1999/05/19 07:28:24 cgoos
242 * SkGeLinkLED no more available for drivers.
243 * Changes for 1000Base-T.
245 * Revision 1.47 1999/04/08 13:57:45 gklug
246 * add: Init of new port struct fiels PLinkResCt
247 * chg: StopPort Timer check
249 * Revision 1.46 1999/03/25 07:42:15 malthoff
250 * SkGeStopPort(): Add workaround for cache incoherency.
251 * Create error log entry, disable port, and
252 * exit loop if it does not terminate.
253 * Add XM_RX_LENERR_OK to the default value for the
254 * XMAC receive command register.
256 * Revision 1.45 1999/03/12 16:24:47 malthoff
257 * Remove PPollRxD and PPollTxD.
258 * Add check for GIPollTimerVal.
260 * Revision 1.44 1999/03/12 13:40:23 malthoff
261 * Fix: SkGeXmitLED(), SK_LED_TST mode does not work.
262 * Add: Jumbo frame support.
263 * Chg: Resolution of parameter IntTime in SkGeCfgSync().
265 * Revision 1.43 1999/02/09 10:29:46 malthoff
266 * Bugfix: The previous modification again also for the second location.
268 * Revision 1.42 1999/02/09 09:35:16 malthoff
269 * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while
270 * clearing the error bits in the PCI status register.
272 * Revision 1.41 1999/01/18 13:07:02 malthoff
273 * Bugfix: Do not use CFG cycles after during Init- or Runtime, because
274 * they may not be available after Boottime.
276 * Revision 1.40 1999/01/11 12:40:49 malthoff
277 * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit.
279 * Revision 1.39 1998/12/11 15:17:33 gklug
280 * chg: Init LipaAutoNeg with Unknown
282 * Revision 1.38 1998/12/10 11:02:57 malthoff
283 * Disable Error Log Message when calling SkGeInit(level 2)
286 * Revision 1.37 1998/12/07 12:18:25 gklug
287 * add: refinement of autosense mode: take into account the autoneg cap of LiPa
289 * Revision 1.36 1998/12/07 07:10:39 gklug
290 * fix: init values of LinkBroken/ Capabilities for management
292 * Revision 1.35 1998/12/02 10:56:20 gklug
293 * fix: do NOT init LoinkSync Counter.
295 * Revision 1.34 1998/12/01 10:53:21 gklug
296 * add: init of additional Counters for workaround
298 * Revision 1.33 1998/12/01 10:00:49 gklug
299 * add: init PIsave var in Port struct
301 * Revision 1.32 1998/11/26 14:50:40 gklug
302 * chg: Default is autosensing with AUTOFULL mode
304 * Revision 1.31 1998/11/25 15:36:16 gklug
305 * fix: do NOT stop LED Timer when port should be stopped
307 * Revision 1.30 1998/11/24 13:15:28 gklug
308 * add: Init PCkeckPar struct member
310 * Revision 1.29 1998/11/18 13:19:27 malthoff
311 * Disable packet arbiter timeouts on receive side.
312 * Use maximum timeout value for packet arbiter
314 * Add TestStopBit() function to handle stop RX/TX
315 * problem with active descriptor poll timers.
316 * Bug Fix: Descriptor Poll Timer not started, because
317 * GIPollTimerVal was initialized with 0.
319 * Revision 1.28 1998/11/13 14:24:26 malthoff
320 * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout
321 * is pending or occurs while waiting for TX_STOP and RX_STOP.
322 * The PA timeout is cleared now while waiting for TX- or RX_STOP.
324 * Revision 1.27 1998/11/02 11:04:36 malthoff
327 * Revision 1.26 1998/11/02 10:37:03 malthoff
328 * Fix: SkGePollTxD() enables always the synchronounous poll timer.
330 * Revision 1.25 1998/10/28 07:12:43 cgoos
331 * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit.
332 * Removed: Reset of RAM Interface in SkGeStopPort.
334 * Revision 1.24 1998/10/27 08:13:12 malthoff
335 * Remove temporary code.
337 * Revision 1.23 1998/10/26 07:45:03 malthoff
338 * Add Address Calculation Workaround: If the EPROM byte
339 * Id is 3, the address offset is 512 kB.
340 * Initialize default values for PLinkMode and PFlowCtrlMode.
342 * Revision 1.22 1998/10/22 09:46:47 gklug
343 * fix SysKonnectFileId typo
345 * Revision 1.21 1998/10/20 12:11:56 malthoff
346 * Don't dendy the Queue config if the size of the unused
349 * Revision 1.20 1998/10/19 07:27:58 malthoff
350 * SkGeInitRamIface() is public to be called by diagnostics.
352 * Revision 1.19 1998/10/16 13:33:45 malthoff
353 * Fix: enabling descriptor polling is not allowed until
354 * the descriptor addresses are set. Descriptor polling
355 * must be handled by the driver.
357 * Revision 1.18 1998/10/16 10:58:27 malthoff
358 * Remove temp. code for Diag prototype.
359 * Remove lint warning for dummy reads.
360 * Call SkGeLoadLnkSyncCnt() during SkGeInitPort().
362 * Revision 1.17 1998/10/14 09:16:06 malthoff
363 * Change parameter LimCount and programming of
364 * the limit counter in SkGeCfgSync().
366 * Revision 1.16 1998/10/13 09:21:16 malthoff
367 * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's
368 * like a Loopback Mode in half duplex.
370 * Revision 1.15 1998/10/09 06:47:40 malthoff
371 * SkGeInitMacArb(): set recovery counters init value
372 * to zero although this counters are not uesd.
373 * Bug fix in Rx Upper/Lower Pause Threshold calculation.
374 * Add XM_RX_SELF_RX to RxCmd.
376 * Revision 1.14 1998/10/06 15:15:53 malthoff
377 * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt().
379 * Revision 1.13 1998/10/06 14:09:36 malthoff
380 * Add SkGeLoadLnkSyncCnt(). Modify
381 * the 'port stopped' condition according
382 * to the current problem report.
384 * Revision 1.12 1998/10/05 08:17:21 malthoff
385 * Add functions: SkGePollRxD(), SkGePollTxD(),
386 * DoCalcAddr(), SkGeCheckQSize(),
387 * DoInitRamQueue(), and SkGeCfgSync().
388 * Add coding for SkGeInitMacArb(), SkGeInitPktArb(),
389 * SkGeInitMacFifo(), SkGeInitRamBufs(),
390 * SkGeInitRamIface(), and SkGeInitBmu().
392 * Revision 1.11 1998/09/29 08:26:29 malthoff
393 * bug fix: SkGeInit0() 'i' should be increment.
395 * Revision 1.10 1998/09/28 13:19:01 malthoff
396 * Coding time: Save the done work.
397 * Modify SkGeLinkLED(), add SkGeXmitLED(),
398 * define SkGeCheckQSize(), SkGeInitMacArb(),
399 * SkGeInitPktArb(), SkGeInitMacFifo(),
400 * SkGeInitRamBufs(), SkGeInitRamIface(),
401 * and SkGeInitBmu(). Do coding for SkGeStopPort(),
402 * SkGeInit1(), SkGeInit2(), and SkGeInit3().
403 * Do coding for SkGeDinit() and SkGeInitPort().
405 * Revision 1.9 1998/09/16 14:29:05 malthoff
406 * Some minor changes.
408 * Revision 1.8 1998/09/11 05:29:14 gklug
409 * add: init state of a port
411 * Revision 1.7 1998/09/04 09:26:25 malthoff
412 * Short temporary modification.
414 * Revision 1.6 1998/09/04 08:27:59 malthoff
415 * Remark the do-while in StopPort() because it never ends
416 * without a GE adapter.
418 * Revision 1.5 1998/09/03 14:05:45 malthoff
419 * Change comment for SkGeInitPort(). Do not
420 * repair the queue sizes if invalid.
422 * Revision 1.4 1998/09/03 10:03:19 malthoff
423 * Implement the new interface according to the
424 * reviewed interface specification.
426 * Revision 1.3 1998/08/19 09:11:25 gklug
427 * fix: struct are removed from c-source (see CCC)
429 * Revision 1.2 1998/07/28 12:33:58 malthoff
430 * Add 'IoC' parameter in function declaration and SK IO macros.
432 * Revision 1.1 1998/07/23 09:48:57 malthoff
433 * Creation. First dummy 'C' file.
434 * SkGeInit(Level 0) is card_start for GE.
435 * SkGeDeInit() is card_stop for GE.
438 ******************************************************************************/
440 #include "h/skdrv1st.h"
441 #include "h/skdrv2nd.h"
443 /* global variables ***********************************************************/
445 /* local variables ************************************************************/
447 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
448 static const char SysKonnectFileId
[] =
449 "@(#) $Id: skgeinit.c,v 1.93 2003/05/28 15:44:43 rschmidt Exp $ (C) Marvell.";
453 int RxQOff
; /* Receive Queue Address Offset */
454 int XsQOff
; /* Sync Tx Queue Address Offset */
455 int XaQOff
; /* Async Tx Queue Address Offset */
457 static struct s_QOffTab QOffTab
[] = {
458 {Q_R1
, Q_XS1
, Q_XA1
}, {Q_R2
, Q_XS2
, Q_XA2
}
466 static struct s_Config OemConfig
= {
467 {'O','E','M','_','C','o','n','f'},
475 /******************************************************************************
477 * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
480 * Enable or disable the descriptor polling of the receive descriptor
481 * ring (RxD) for port 'Port'.
482 * The new configuration is *not* saved over any SkGeStopPort() and
483 * SkGeInitPort() calls.
489 SK_AC
*pAC
, /* adapter context */
490 SK_IOC IoC
, /* IO context */
491 int Port
, /* Port Index (MAC_1 + n) */
492 SK_BOOL PollRxD
) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
496 pPrt
= &pAC
->GIni
.GP
[Port
];
498 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), (PollRxD
) ?
499 CSR_ENA_POL
: CSR_DIS_POL
);
503 /******************************************************************************
505 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
508 * Enable or disable the descriptor polling of the transmit descriptor
509 * ring(s) (TxD) for port 'Port'.
510 * The new configuration is *not* saved over any SkGeStopPort() and
511 * SkGeInitPort() calls.
517 SK_AC
*pAC
, /* adapter context */
518 SK_IOC IoC
, /* IO context */
519 int Port
, /* Port Index (MAC_1 + n) */
520 SK_BOOL PollTxD
) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
525 pPrt
= &pAC
->GIni
.GP
[Port
];
527 DWord
= (SK_U32
)(PollTxD
? CSR_ENA_POL
: CSR_DIS_POL
);
529 if (pPrt
->PXSQSize
!= 0) {
530 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), DWord
);
533 if (pPrt
->PXAQSize
!= 0) {
534 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), DWord
);
539 /******************************************************************************
541 * SkGeYellowLED() - Switch the yellow LED on or off.
544 * Switch the yellow LED on or off.
547 * This function may be called any time after SkGeInit(Level 1).
553 SK_AC
*pAC
, /* adapter context */
554 SK_IOC IoC
, /* IO context */
555 int State
) /* yellow LED state, 0 = OFF, 0 != ON */
558 /* Switch yellow LED OFF */
559 SK_OUT8(IoC
, B0_LED
, LED_STAT_OFF
);
562 /* Switch yellow LED ON */
563 SK_OUT8(IoC
, B0_LED
, LED_STAT_ON
);
565 } /* SkGeYellowLED */
568 #if (!defined(SK_SLIM) || defined(GENESIS))
569 /******************************************************************************
571 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
574 * The Rx or Tx LED which is specified by 'Led' will be
575 * enabled, disabled or switched on in test mode.
578 * 'Led' must contain the address offset of the LEDs INI register.
581 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
587 SK_AC
*pAC
, /* adapter context */
588 SK_IOC IoC
, /* IO context */
589 int Led
, /* offset to the LED Init Value register */
590 int Mode
) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
596 LedIni
= SK_XMIT_DUR
* (SK_U32
)pAC
->GIni
.GIHstClkFact
/ 100;
597 SK_OUT32(IoC
, Led
+ XMIT_LED_INI
, LedIni
);
598 SK_OUT8(IoC
, Led
+ XMIT_LED_CTRL
, LED_START
);
601 SK_OUT8(IoC
, Led
+ XMIT_LED_TST
, LED_T_ON
);
602 SK_OUT32(IoC
, Led
+ XMIT_LED_CNT
, 100);
603 SK_OUT8(IoC
, Led
+ XMIT_LED_CTRL
, LED_START
);
608 * Do NOT stop the LED Timer here. The LED might be
609 * in on state. But it needs to go off.
611 SK_OUT32(IoC
, Led
+ XMIT_LED_CNT
, 0);
612 SK_OUT8(IoC
, Led
+ XMIT_LED_TST
, LED_T_OFF
);
617 * 1000BT: The Transmit LED is driven by the PHY.
618 * But the default LED configuration is used for
619 * Level One and Broadcom PHYs.
620 * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
621 * (In this case it has to be added here. But we will see. XXX)
624 #endif /* !SK_SLIM || GENESIS */
627 /******************************************************************************
629 * DoCalcAddr() - Calculates the start and the end address of a queue.
632 * This function calculates the start and the end address of a queue.
633 * Afterwards the 'StartVal' is incremented to the next start position.
634 * If the port is already initialized the calculated values
635 * will be checked against the configured values and an
636 * error will be returned, if they are not equal.
637 * If the port is not initialized the values will be written to
638 * *StartAdr and *EndAddr.
642 * 1: configuration error
644 static int DoCalcAddr(
645 SK_AC
*pAC
, /* adapter context */
646 SK_GEPORT SK_FAR
*pPrt
, /* port index */
647 int QuSize
, /* size of the queue to configure in kB */
648 SK_U32 SK_FAR
*StartVal
, /* start value for address calculation */
649 SK_U32 SK_FAR
*QuStartAddr
,/* start addr to calculate */
650 SK_U32 SK_FAR
*QuEndAddr
) /* end address to calculate */
662 EndVal
= *StartVal
+ ((SK_U32
)QuSize
* 1024) - 1;
663 NextStart
= EndVal
+ 1;
666 if (pPrt
->PState
>= SK_PRT_INIT
) {
667 if (*StartVal
!= *QuStartAddr
|| EndVal
!= *QuEndAddr
) {
672 *QuStartAddr
= *StartVal
;
676 *StartVal
= NextStart
;
680 /******************************************************************************
682 * SkGeInitAssignRamToQueues() - allocate default queue sizes
685 * This function assigns the memory to the different queues and ports.
686 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
687 * Otherwise the first port gets most of the memory and all the
688 * other ports just the required minimum.
689 * This function can only be called when pAC->GIni.GIRamSize and
690 * pAC->GIni.GIMacsFound have been initialized, usually this happens
695 * 1 - invalid input values
696 * 2 - not enough memory
699 int SkGeInitAssignRamToQueues(
700 SK_AC
*pAC
, /* Adapter context */
701 int ActivePort
, /* Active Port in RLMT mode */
702 SK_BOOL DualNet
) /* adapter context */
705 int UsedKilobytes
; /* memory already assigned */
706 int ActivePortKilobytes
; /* memory available for active port */
711 if (ActivePort
>= pAC
->GIni
.GIMacsFound
) {
712 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
713 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
717 if (((pAC
->GIni
.GIMacsFound
* (SK_MIN_RXQ_SIZE
+ SK_MIN_TXQ_SIZE
)) +
718 ((RAM_QUOTA_SYNC
== 0) ? 0 : SK_MIN_TXQ_SIZE
)) > pAC
->GIni
.GIRamSize
) {
719 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
720 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
721 pAC
->GIni
.GIRamSize
));
726 /* every port gets the same amount of memory */
727 ActivePortKilobytes
= pAC
->GIni
.GIRamSize
/ pAC
->GIni
.GIMacsFound
;
728 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
730 pGePort
= &pAC
->GIni
.GP
[i
];
732 /* take away the minimum memory for active queues */
733 ActivePortKilobytes
-= (SK_MIN_RXQ_SIZE
+ SK_MIN_TXQ_SIZE
);
735 /* receive queue gets the minimum + 80% of the rest */
736 pGePort
->PRxQSize
= (int) (ROUND_QUEUE_SIZE_KB((
737 ActivePortKilobytes
* (unsigned long) RAM_QUOTA_RX
) / 100))
740 ActivePortKilobytes
-= (pGePort
->PRxQSize
- SK_MIN_RXQ_SIZE
);
742 /* synchronous transmit queue */
743 pGePort
->PXSQSize
= 0;
745 /* asynchronous transmit queue */
746 pGePort
->PXAQSize
= (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes
+
751 /* Rlmt Mode or single link adapter */
753 /* Set standby queue size defaults for all standby ports */
754 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
756 if (i
!= ActivePort
) {
757 pGePort
= &pAC
->GIni
.GP
[i
];
759 pGePort
->PRxQSize
= SK_MIN_RXQ_SIZE
;
760 pGePort
->PXAQSize
= SK_MIN_TXQ_SIZE
;
761 pGePort
->PXSQSize
= 0;
764 UsedKilobytes
+= pGePort
->PRxQSize
+ pGePort
->PXAQSize
;
768 ActivePortKilobytes
= pAC
->GIni
.GIRamSize
- UsedKilobytes
;
770 /* assign it to the active port */
771 /* first take away the minimum memory */
772 ActivePortKilobytes
-= (SK_MIN_RXQ_SIZE
+ SK_MIN_TXQ_SIZE
);
773 pGePort
= &pAC
->GIni
.GP
[ActivePort
];
775 /* receive queue get's the minimum + 80% of the rest */
776 pGePort
->PRxQSize
= (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes
*
777 (unsigned long) RAM_QUOTA_RX
) / 100)) + SK_MIN_RXQ_SIZE
;
779 ActivePortKilobytes
-= (pGePort
->PRxQSize
- SK_MIN_RXQ_SIZE
);
781 /* synchronous transmit queue */
782 pGePort
->PXSQSize
= 0;
784 /* asynchronous transmit queue */
785 pGePort
->PXAQSize
= (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes
) +
789 VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
790 pGePort
->PRxQSize
, pGePort
->PXSQSize
, pGePort
->PXAQSize
);
794 } /* SkGeInitAssignRamToQueues */
796 /******************************************************************************
798 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
801 * This function verifies the Queue Size Configuration specified
802 * in the variables PRxQSize, PXSQSize, and PXAQSize of all
804 * This requirements must be fullfilled to have a valid configuration:
805 * - The size of all queues must not exceed GIRamSize.
806 * - The queue sizes must be specified in units of 8 kB.
807 * - The size of Rx queues of available ports must not be
808 * smaller than 16 kB.
809 * - The size of at least one Tx queue (synch. or asynch.)
810 * of available ports must not be smaller than 16 kB
811 * when Jumbo Frames are used.
812 * - The RAM start and end addresses must not be changed
813 * for ports which are already initialized.
814 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
815 * of all ports and stores them into the HWAC port structure.
818 * 0: Queue Size Configuration valid
819 * 1: Queue Size Configuration invalid
821 static int SkGeCheckQSize(
822 SK_AC
*pAC
, /* adapter context */
823 int Port
) /* port index */
831 int UsedMem
; /* total memory used (max. found ports) */
839 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
840 pPrt
= &pAC
->GIni
.GP
[i
];
842 if ((pPrt
->PRxQSize
& QZ_UNITS
) != 0 ||
843 (pPrt
->PXSQSize
& QZ_UNITS
) != 0 ||
844 (pPrt
->PXAQSize
& QZ_UNITS
) != 0) {
846 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E012
, SKERR_HWI_E012MSG
);
850 if (i
== Port
&& pPrt
->PRxQSize
< SK_MIN_RXQ_SIZE
) {
851 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E011
, SKERR_HWI_E011MSG
);
856 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
857 * if Jumbo Frames are used, this size has to be >= 16 kB.
859 if ((i
== Port
&& pPrt
->PXSQSize
== 0 && pPrt
->PXAQSize
== 0) ||
860 (pAC
->GIni
.GIPortUsage
== SK_JUMBO_LINK
&&
861 ((pPrt
->PXSQSize
> 0 && pPrt
->PXSQSize
< SK_MIN_TXQ_SIZE
) ||
862 (pPrt
->PXAQSize
> 0 && pPrt
->PXAQSize
< SK_MIN_TXQ_SIZE
)))) {
863 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E023
, SKERR_HWI_E023MSG
);
867 UsedMem
+= pPrt
->PRxQSize
+ pPrt
->PXSQSize
+ pPrt
->PXAQSize
;
870 if (UsedMem
> pAC
->GIni
.GIRamSize
) {
871 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E012
, SKERR_HWI_E012MSG
);
874 #endif /* !SK_SLIM */
876 /* Now start address calculation */
877 StartAddr
= pAC
->GIni
.GIRamOffs
;
878 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
879 pPrt
= &pAC
->GIni
.GP
[i
];
881 /* Calculate/Check values for the receive queue */
882 Rtv2
= DoCalcAddr(pAC
, pPrt
, pPrt
->PRxQSize
, &StartAddr
,
883 &pPrt
->PRxQRamStart
, &pPrt
->PRxQRamEnd
);
886 /* Calculate/Check values for the synchronous Tx queue */
887 Rtv2
= DoCalcAddr(pAC
, pPrt
, pPrt
->PXSQSize
, &StartAddr
,
888 &pPrt
->PXsQRamStart
, &pPrt
->PXsQRamEnd
);
891 /* Calculate/Check values for the asynchronous Tx queue */
892 Rtv2
= DoCalcAddr(pAC
, pPrt
, pPrt
->PXAQSize
, &StartAddr
,
893 &pPrt
->PXaQRamStart
, &pPrt
->PXaQRamEnd
);
897 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E013
, SKERR_HWI_E013MSG
);
903 } /* SkGeCheckQSize */
907 /******************************************************************************
909 * SkGeInitMacArb() - Initialize the MAC Arbiter
912 * This function initializes the MAC Arbiter.
913 * It must not be called if there is still an
914 * initialized or active port.
919 static void SkGeInitMacArb(
920 SK_AC
*pAC
, /* adapter context */
921 SK_IOC IoC
) /* IO context */
923 /* release local reset */
924 SK_OUT16(IoC
, B3_MA_TO_CTRL
, MA_RST_CLR
);
926 /* configure timeout values */
927 SK_OUT8(IoC
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
928 SK_OUT8(IoC
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
929 SK_OUT8(IoC
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
930 SK_OUT8(IoC
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
932 SK_OUT8(IoC
, B3_MA_RCINI_RX1
, 0);
933 SK_OUT8(IoC
, B3_MA_RCINI_RX2
, 0);
934 SK_OUT8(IoC
, B3_MA_RCINI_TX1
, 0);
935 SK_OUT8(IoC
, B3_MA_RCINI_TX2
, 0);
937 /* recovery values are needed for XMAC II Rev. B2 only */
938 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
941 * There is no start or enable button to push, therefore
942 * the MAC arbiter is configured and enabled now.
944 } /* SkGeInitMacArb */
947 /******************************************************************************
949 * SkGeInitPktArb() - Initialize the Packet Arbiter
952 * This function initializes the Packet Arbiter.
953 * It must not be called if there is still an
954 * initialized or active port.
959 static void SkGeInitPktArb(
960 SK_AC
*pAC
, /* adapter context */
961 SK_IOC IoC
) /* IO context */
963 /* release local reset */
964 SK_OUT16(IoC
, B3_PA_CTRL
, PA_RST_CLR
);
966 /* configure timeout values */
967 SK_OUT16(IoC
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
968 SK_OUT16(IoC
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
969 SK_OUT16(IoC
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
970 SK_OUT16(IoC
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
973 * enable timeout timers if jumbo frames not used
974 * NOTE: the packet arbiter timeout interrupt is needed for
975 * half duplex hangup workaround
977 if (pAC
->GIni
.GIPortUsage
!= SK_JUMBO_LINK
) {
978 if (pAC
->GIni
.GIMacsFound
== 1) {
979 SK_OUT16(IoC
, B3_PA_CTRL
, PA_ENA_TO_TX1
);
982 SK_OUT16(IoC
, B3_PA_CTRL
, PA_ENA_TO_TX1
| PA_ENA_TO_TX2
);
985 } /* SkGeInitPktArb */
989 /******************************************************************************
991 * SkGeInitMacFifo() - Initialize the MAC FIFOs
994 * Initialize all MAC FIFOs of the specified port
999 static void SkGeInitMacFifo(
1000 SK_AC
*pAC
, /* adapter context */
1001 SK_IOC IoC
, /* IO context */
1002 int Port
) /* Port Index (MAC_1 + n) */
1010 * - release local reset
1011 * - use default value for MAC FIFO size
1012 * - setup defaults for the control register
1016 Word
= (SK_U16
)GMF_RX_CTRL_DEF
;
1019 if (pAC
->GIni
.GIGenesis
) {
1020 /* Configure Rx MAC FIFO */
1021 SK_OUT8(IoC
, MR_ADDR(Port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
1022 SK_OUT16(IoC
, MR_ADDR(Port
, RX_MFF_CTRL1
), MFF_RX_CTRL_DEF
);
1023 SK_OUT8(IoC
, MR_ADDR(Port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1025 /* Configure Tx MAC FIFO */
1026 SK_OUT8(IoC
, MR_ADDR(Port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
1027 SK_OUT16(IoC
, MR_ADDR(Port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
1028 SK_OUT8(IoC
, MR_ADDR(Port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1030 /* Enable frame flushing if jumbo frames used */
1031 if (pAC
->GIni
.GIPortUsage
== SK_JUMBO_LINK
) {
1032 SK_OUT16(IoC
, MR_ADDR(Port
, RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
1035 #endif /* GENESIS */
1038 if (pAC
->GIni
.GIYukon
) {
1039 /* set Rx GMAC FIFO Flush Mask */
1040 SK_OUT16(IoC
, MR_ADDR(Port
, RX_GMF_FL_MSK
), (SK_U16
)RX_FF_FL_DEF_MSK
);
1042 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1043 if (pAC
->GIni
.GIYukonLite
&& pAC
->GIni
.GIChipId
== CHIP_ID_YUKON
) {
1045 Word
&= ~GMF_RX_F_FL_ON
;
1048 /* Configure Rx MAC FIFO */
1049 SK_OUT8(IoC
, MR_ADDR(Port
, RX_GMF_CTRL_T
), (SK_U8
)GMF_RST_CLR
);
1050 SK_OUT16(IoC
, MR_ADDR(Port
, RX_GMF_CTRL_T
), Word
);
1052 /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
1053 SK_OUT16(IoC
, MR_ADDR(Port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
1055 /* Configure Tx MAC FIFO */
1056 SK_OUT8(IoC
, MR_ADDR(Port
, TX_GMF_CTRL_T
), (SK_U8
)GMF_RST_CLR
);
1057 SK_OUT16(IoC
, MR_ADDR(Port
, TX_GMF_CTRL_T
), (SK_U16
)GMF_TX_CTRL_DEF
);
1060 SK_IN32(IoC
, MR_ADDR(Port
, RX_GMF_AF_THR
), &DWord
);
1061 SK_IN32(IoC
, MR_ADDR(Port
, TX_GMF_AE_THR
), &DWord
);
1064 /* set Tx GMAC FIFO Almost Empty Threshold */
1065 /* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
1069 } /* SkGeInitMacFifo */
1071 #ifdef SK_LNK_SYNC_CNT
1072 /******************************************************************************
1074 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
1077 * This function starts the Link Sync Counter of the specified
1078 * port and enables the generation of an Link Sync IRQ.
1079 * The Link Sync Counter may be used to detect an active link,
1080 * if autonegotiation is not used.
1083 * o To ensure receiving the Link Sync Event the LinkSyncCounter
1084 * should be initialized BEFORE clearing the XMAC's reset!
1085 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
1091 void SkGeLoadLnkSyncCnt(
1092 SK_AC
*pAC
, /* adapter context */
1093 SK_IOC IoC
, /* IO context */
1094 int Port
, /* Port Index (MAC_1 + n) */
1095 SK_U32 CntVal
) /* Counter value */
1103 SK_OUT8(IoC
, MR_ADDR(Port
, LNK_SYNC_CTRL
), LED_STOP
);
1107 * Each time starting the Link Sync Counter an IRQ is generated
1108 * by the adapter. See problem report entry from 21.07.98
1110 * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
1111 * if no IRQ is already pending.
1114 SK_IN32(IoC
, B0_ISRC
, &ISrc
);
1115 SK_IN32(IoC
, B0_IMSK
, &OrgIMsk
);
1116 if (Port
== MAC_1
) {
1117 NewIMsk
= OrgIMsk
& ~IS_LNK_SYNC_M1
;
1118 if ((ISrc
& IS_LNK_SYNC_M1
) != 0) {
1123 NewIMsk
= OrgIMsk
& ~IS_LNK_SYNC_M2
;
1124 if ((ISrc
& IS_LNK_SYNC_M2
) != 0) {
1129 SK_OUT32(IoC
, B0_IMSK
, NewIMsk
);
1133 SK_OUT32(IoC
, MR_ADDR(Port
, LNK_SYNC_INI
), CntVal
);
1136 SK_OUT8(IoC
, MR_ADDR(Port
, LNK_SYNC_CTRL
), LED_START
);
1139 /* clear the unexpected IRQ, and restore the interrupt mask */
1140 SK_OUT8(IoC
, MR_ADDR(Port
, LNK_SYNC_CTRL
), LED_CLR_IRQ
);
1141 SK_OUT32(IoC
, B0_IMSK
, OrgIMsk
);
1143 } /* SkGeLoadLnkSyncCnt*/
1144 #endif /* SK_LNK_SYNC_CNT */
1146 #if defined(SK_DIAG) || defined(SK_CFG_SYNC)
1147 /******************************************************************************
1149 * SkGeCfgSync() - Configure synchronous bandwidth for this port.
1152 * This function may be used to configure synchronous bandwidth
1153 * to the specified port. This may be done any time after
1154 * initializing the port. The configuration values are NOT saved
1155 * in the HWAC port structure and will be overwritten any
1156 * time when stopping and starting the port.
1157 * Any values for the synchronous configuration will be ignored
1158 * if the size of the synchronous queue is zero!
1160 * The default configuration for the synchronous service is
1161 * TXA_ENA_FSYNC. This means if the size of
1162 * the synchronous queue is unequal zero but no specific
1163 * synchronous bandwidth is configured, the synchronous queue
1164 * will always have the 'unlimited' transmit priority!
1166 * This mode will be restored if the synchronous bandwidth is
1167 * deallocated ('IntTime' = 0 and 'LimCount' = 0).
1171 * 1: parameter configuration error
1172 * 2: try to configure quality of service although no
1173 * synchronous queue is configured
1176 SK_AC
*pAC
, /* adapter context */
1177 SK_IOC IoC
, /* IO context */
1178 int Port
, /* Port Index (MAC_1 + n) */
1179 SK_U32 IntTime
, /* Interval Timer Value in units of 8ns */
1180 SK_U32 LimCount
, /* Number of bytes to transfer during IntTime */
1181 int SyncMode
) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
1187 /* check the parameters */
1188 if (LimCount
> IntTime
||
1189 (LimCount
== 0 && IntTime
!= 0) ||
1190 (LimCount
!= 0 && IntTime
== 0)) {
1192 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E010
, SKERR_HWI_E010MSG
);
1196 if (pAC
->GIni
.GP
[Port
].PXSQSize
== 0) {
1197 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E009
, SKERR_HWI_E009MSG
);
1201 /* calculate register values */
1202 IntTime
= (IntTime
/ 2) * pAC
->GIni
.GIHstClkFact
/ 100;
1203 LimCount
= LimCount
/ 8;
1205 if (IntTime
> TXA_MAX_VAL
|| LimCount
> TXA_MAX_VAL
) {
1206 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E010
, SKERR_HWI_E010MSG
);
1211 * - Enable 'Force Sync' to ensure the synchronous queue
1212 * has the priority while configuring the new values.
1213 * - Also 'disable alloc' to ensure the settings complies
1214 * to the SyncMode parameter.
1215 * - Disable 'Rate Control' to configure the new values.
1216 * - write IntTime and LimCount
1217 * - start 'Rate Control' and disable 'Force Sync'
1218 * if Interval Timer or Limit Counter not zero.
1220 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
),
1221 TXA_ENA_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1223 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_ITI_INI
), IntTime
);
1224 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_LIM_INI
), LimCount
);
1226 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
),
1227 (SK_U8
)(SyncMode
& (TXA_ENA_ALLOC
| TXA_DIS_ALLOC
)));
1229 if (IntTime
!= 0 || LimCount
!= 0) {
1230 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
), TXA_DIS_FSYNC
| TXA_START_RC
);
1235 #endif /* SK_DIAG || SK_CFG_SYNC*/
1238 /******************************************************************************
1240 * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue
1243 * If the queue is used, enable and initialize it.
1244 * Make sure the queue is still reset, if it is not used.
1249 static void DoInitRamQueue(
1250 SK_AC
*pAC
, /* adapter context */
1251 SK_IOC IoC
, /* IO context */
1252 int QuIoOffs
, /* Queue IO Address Offset */
1253 SK_U32 QuStartAddr
, /* Queue Start Address */
1254 SK_U32 QuEndAddr
, /* Queue End Address */
1255 int QuType
) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
1257 SK_U32 RxUpThresVal
;
1258 SK_U32 RxLoThresVal
;
1260 if (QuStartAddr
!= QuEndAddr
) {
1261 /* calculate thresholds, assume we have a big Rx queue */
1262 RxUpThresVal
= (QuEndAddr
+ 1 - QuStartAddr
- SK_RB_ULPP
) / 8;
1263 RxLoThresVal
= (QuEndAddr
+ 1 - QuStartAddr
- SK_RB_LLPP_B
)/8;
1265 /* build HW address format */
1266 QuStartAddr
= QuStartAddr
/ 8;
1267 QuEndAddr
= QuEndAddr
/ 8;
1269 /* release local reset */
1270 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_RST_CLR
);
1272 /* configure addresses */
1273 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_START
), QuStartAddr
);
1274 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_END
), QuEndAddr
);
1275 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_WP
), QuStartAddr
);
1276 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_RP
), QuStartAddr
);
1280 /* configure threshold for small Rx Queue */
1281 RxLoThresVal
+= (SK_RB_LLPP_B
- SK_RB_LLPP_S
) / 8;
1283 /* continue with SK_RX_BRAM_Q */
1285 /* write threshold for Rx Queue */
1287 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_RX_UTPP
), RxUpThresVal
);
1288 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_RX_LTPP
), RxLoThresVal
);
1290 /* the high priority threshold not used */
1294 * Do NOT use Store & Forward under normal operation due to
1295 * performance optimization (GENESIS only).
1296 * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB)
1297 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
1298 * we NEED Store & Forward of the RAM buffer.
1300 if (pAC
->GIni
.GIPortUsage
== SK_JUMBO_LINK
||
1301 pAC
->GIni
.GIYukon
) {
1302 /* enable Store & Forward Mode for the Tx Side */
1303 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_ENA_STFWD
);
1308 /* set queue operational */
1309 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_ENA_OP_MD
);
1312 /* ensure the queue is still disabled */
1313 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_RST_SET
);
1315 } /* DoInitRamQueue */
1318 /******************************************************************************
1320 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
1323 * Initialize all RAM Buffer Queues of the specified port
1328 static void SkGeInitRamBufs(
1329 SK_AC
*pAC
, /* adapter context */
1330 SK_IOC IoC
, /* IO context */
1331 int Port
) /* Port Index (MAC_1 + n) */
1336 pPrt
= &pAC
->GIni
.GP
[Port
];
1338 if (pPrt
->PRxQSize
== SK_MIN_RXQ_SIZE
) {
1339 RxQType
= SK_RX_SRAM_Q
; /* small Rx Queue */
1342 RxQType
= SK_RX_BRAM_Q
; /* big Rx Queue */
1345 DoInitRamQueue(pAC
, IoC
, pPrt
->PRxQOff
, pPrt
->PRxQRamStart
,
1346 pPrt
->PRxQRamEnd
, RxQType
);
1348 DoInitRamQueue(pAC
, IoC
, pPrt
->PXsQOff
, pPrt
->PXsQRamStart
,
1349 pPrt
->PXsQRamEnd
, SK_TX_RAM_Q
);
1351 DoInitRamQueue(pAC
, IoC
, pPrt
->PXaQOff
, pPrt
->PXaQRamStart
,
1352 pPrt
->PXaQRamEnd
, SK_TX_RAM_Q
);
1354 } /* SkGeInitRamBufs */
1357 /******************************************************************************
1359 * SkGeInitRamIface() - Initialize the RAM Interface
1362 * This function initializes the Adapters RAM Interface.
1365 * This function is used in the diagnostics.
1370 void SkGeInitRamIface(
1371 SK_AC
*pAC
, /* adapter context */
1372 SK_IOC IoC
) /* IO context */
1374 /* release local reset */
1375 SK_OUT16(IoC
, B3_RI_CTRL
, RI_RST_CLR
);
1377 /* configure timeout values */
1378 SK_OUT8(IoC
, B3_RI_WTO_R1
, SK_RI_TO_53
);
1379 SK_OUT8(IoC
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
1380 SK_OUT8(IoC
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
1381 SK_OUT8(IoC
, B3_RI_RTO_R1
, SK_RI_TO_53
);
1382 SK_OUT8(IoC
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
1383 SK_OUT8(IoC
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
1384 SK_OUT8(IoC
, B3_RI_WTO_R2
, SK_RI_TO_53
);
1385 SK_OUT8(IoC
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
1386 SK_OUT8(IoC
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
1387 SK_OUT8(IoC
, B3_RI_RTO_R2
, SK_RI_TO_53
);
1388 SK_OUT8(IoC
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
1389 SK_OUT8(IoC
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
1391 } /* SkGeInitRamIface */
1394 /******************************************************************************
1396 * SkGeInitBmu() - Initialize the BMU state machines
1399 * Initialize all BMU state machines of the specified port
1404 static void SkGeInitBmu(
1405 SK_AC
*pAC
, /* adapter context */
1406 SK_IOC IoC
, /* IO context */
1407 int Port
) /* Port Index (MAC_1 + n) */
1413 pPrt
= &pAC
->GIni
.GP
[Port
];
1415 RxWm
= SK_BMU_RX_WM
;
1416 TxWm
= SK_BMU_TX_WM
;
1418 if (!pAC
->GIni
.GIPciSlot64
&& !pAC
->GIni
.GIPciClock66
) {
1419 /* for better performance */
1424 /* Rx Queue: Release all local resets and set the watermark */
1425 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), CSR_CLR_RESET
);
1426 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_F
), RxWm
);
1429 * Tx Queue: Release all local resets if the queue is used !
1432 if (pPrt
->PXSQSize
!= 0) {
1433 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_CLR_RESET
);
1434 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_F
), TxWm
);
1437 if (pPrt
->PXAQSize
!= 0) {
1438 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_CLR_RESET
);
1439 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_F
), TxWm
);
1442 * Do NOT enable the descriptor poll timers here, because
1443 * the descriptor addresses are not specified yet.
1448 /******************************************************************************
1450 * TestStopBit() - Test the stop bit of the queue
1453 * Stopping a queue is not as simple as it seems to be.
1454 * If descriptor polling is enabled, it may happen
1455 * that RX/TX stop is done and SV idle is NOT set.
1456 * In this case we have to issue another stop command.
1459 * The queues control status register
1461 static SK_U32
TestStopBit(
1462 SK_AC
*pAC
, /* Adapter Context */
1463 SK_IOC IoC
, /* IO Context */
1464 int QuIoOffs
) /* Queue IO Address Offset */
1466 SK_U32 QuCsr
; /* CSR contents */
1468 SK_IN32(IoC
, Q_ADDR(QuIoOffs
, Q_CSR
), &QuCsr
);
1470 if ((QuCsr
& (CSR_STOP
| CSR_SV_IDLE
)) == 0) {
1471 /* Stop Descriptor overridden by start command */
1472 SK_OUT32(IoC
, Q_ADDR(QuIoOffs
, Q_CSR
), CSR_STOP
);
1474 SK_IN32(IoC
, Q_ADDR(QuIoOffs
, Q_CSR
), &QuCsr
);
1481 /******************************************************************************
1483 * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
1486 * After calling this function the descriptor rings and Rx and Tx
1487 * queues of this port may be reconfigured.
1489 * It is possible to stop the receive and transmit path separate or
1492 * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC.
1493 * The receive queue is still active and
1494 * the pending Rx frames may be still transferred
1496 * SK_STOP_RX Stop the receive path. The tansmit path
1497 * has to be stopped once before.
1498 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
1500 * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
1501 * SK_HARD_RST Resets the MAC and the PHY.
1504 * 1) A Link Down event was signaled for a port. Therefore the activity
1505 * of this port should be stopped and a hardware reset should be issued
1506 * to enable the workaround of XMAC Errata #2. But the received frames
1507 * should not be discarded.
1509 * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
1510 * (transfer all pending Rx frames)
1511 * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
1514 * 2) An event was issued which request the driver to switch
1515 * the 'virtual active' link to an other already active port
1516 * as soon as possible. The frames in the receive queue of this
1517 * port may be lost. But the PHY must not be reset during this
1520 * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
1523 * Extended Description:
1524 * If SK_STOP_TX is set,
1525 * o disable the MAC's receive and transmitter to prevent
1526 * from sending incomplete frames
1527 * o stop the port's transmit queues before terminating the
1528 * BMUs to prevent from performing incomplete PCI cycles
1530 * - The network Rx and Tx activity and PCI Tx transfer is
1532 * o reset the MAC depending on the RstMode
1533 * o Stop Interval Timer and Limit Counter of Tx Arbiter,
1534 * also disable Force Sync bit and Enable Alloc bit.
1535 * o perform a local reset of the port's Tx path
1536 * - reset the PCI FIFO of the async Tx queue
1537 * - reset the PCI FIFO of the sync Tx queue
1538 * - reset the RAM Buffer async Tx queue
1539 * - reset the RAM Buffer sync Tx queue
1540 * - reset the MAC Tx FIFO
1541 * o switch Link and Tx LED off, stop the LED counters
1543 * If SK_STOP_RX is set,
1544 * o stop the port's receive queue
1545 * - The path data transfer activity is fully stopped now.
1546 * o perform a local reset of the port's Rx path
1547 * - reset the PCI FIFO of the Rx queue
1548 * - reset the RAM Buffer receive queue
1549 * - reset the MAC Rx FIFO
1550 * o switch Rx LED off, stop the LED counter
1552 * If all ports are stopped,
1553 * o reset the RAM Interface.
1556 * o This function may be called during the driver states RESET_PORT and
1560 SK_AC
*pAC
, /* adapter context */
1561 SK_IOC IoC
, /* I/O context */
1562 int Port
, /* port to stop (MAC_1 + n) */
1563 int Dir
, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
1564 int RstMode
)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
1568 #endif /* !SK_DIAG */
1577 pPrt
= &pAC
->GIni
.GP
[Port
];
1579 if ((Dir
& SK_STOP_TX
) != 0) {
1580 /* disable receiver and transmitter */
1581 SkMacRxTxDisable(pAC
, IoC
, Port
);
1583 /* stop both transmit queues */
1585 * If the BMU is in the reset state CSR_STOP will terminate
1588 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_STOP
);
1589 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_STOP
);
1591 ToutStart
= SkOsGetTime(pAC
);
1595 * Clear packet arbiter timeout to make sure
1596 * this loop will terminate.
1598 SK_OUT16(IoC
, B3_PA_CTRL
, (SK_U16
)((Port
== MAC_1
) ?
1599 PA_CLR_TO_TX1
: PA_CLR_TO_TX2
));
1602 * If the transfer stucks at the MAC the STOP command will not
1603 * terminate if we don't flush the XMAC's transmit FIFO !
1605 SkMacFlushTxFifo(pAC
, IoC
, Port
);
1607 XsCsr
= TestStopBit(pAC
, IoC
, pPrt
->PXsQOff
);
1608 XaCsr
= TestStopBit(pAC
, IoC
, pPrt
->PXaQOff
);
1610 if (SkOsGetTime(pAC
) - ToutStart
> (SK_TICKS_PER_SEC
/ 18)) {
1612 * Timeout of 1/18 second reached.
1613 * This needs to be checked at 1/18 sec only.
1617 /* Might be a problem when the driver event handler
1618 * calls StopPort again. XXX.
1621 /* Fatal Error, Loop aborted */
1622 SK_ERR_LOG(pAC
, SK_ERRCL_HW
, SKERR_HWI_E018
,
1626 SkEventQueue(pAC
, SKGE_DRV
, SK_DRV_PORT_FAIL
, Para
);
1627 #endif /* !SK_DIAG */
1631 * Cache incoherency workaround: Assume a start command
1632 * has been lost while sending the frame.
1634 ToutStart
= SkOsGetTime(pAC
);
1636 if ((XsCsr
& CSR_STOP
) != 0) {
1637 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_START
);
1639 if ((XaCsr
& CSR_STOP
) != 0) {
1640 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_START
);
1645 * Because of the ASIC problem report entry from 21.08.1998 it is
1646 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
1648 } while ((XsCsr
& (CSR_STOP
| CSR_SV_IDLE
)) != CSR_SV_IDLE
||
1649 (XaCsr
& (CSR_STOP
| CSR_SV_IDLE
)) != CSR_SV_IDLE
);
1651 /* Reset the MAC depending on the RstMode */
1652 if (RstMode
== SK_SOFT_RST
) {
1653 SkMacSoftRst(pAC
, IoC
, Port
);
1656 SkMacHardRst(pAC
, IoC
, Port
);
1659 /* Disable Force Sync bit and Enable Alloc bit */
1660 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
),
1661 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1663 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1664 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_ITI_INI
), 0L);
1665 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_LIM_INI
), 0L);
1667 /* Perform a local reset of the port's Tx path */
1669 /* Reset the PCI FIFO of the async Tx queue */
1670 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_SET_RESET
);
1671 /* Reset the PCI FIFO of the sync Tx queue */
1672 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_SET_RESET
);
1673 /* Reset the RAM Buffer async Tx queue */
1674 SK_OUT8(IoC
, RB_ADDR(pPrt
->PXaQOff
, RB_CTRL
), RB_RST_SET
);
1675 /* Reset the RAM Buffer sync Tx queue */
1676 SK_OUT8(IoC
, RB_ADDR(pPrt
->PXsQOff
, RB_CTRL
), RB_RST_SET
);
1678 /* Reset Tx MAC FIFO */
1680 if (pAC
->GIni
.GIGenesis
) {
1681 /* Note: MFF_RST_SET does NOT reset the XMAC ! */
1682 SK_OUT8(IoC
, MR_ADDR(Port
, TX_MFF_CTRL2
), MFF_RST_SET
);
1684 /* switch Link and Tx LED off, stop the LED counters */
1685 /* Link LED is switched off by the RLMT and the Diag itself */
1686 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, TX_LED_INI
), SK_LED_DIS
);
1688 #endif /* GENESIS */
1691 if (pAC
->GIni
.GIYukon
) {
1692 /* Reset TX MAC FIFO */
1693 SK_OUT8(IoC
, MR_ADDR(Port
, TX_GMF_CTRL_T
), (SK_U8
)GMF_RST_SET
);
1698 if ((Dir
& SK_STOP_RX
) != 0) {
1700 * The RX Stop Command will not terminate if no buffers
1701 * are queued in the RxD ring. But it will always reach
1702 * the Idle state. Therefore we can use this feature to
1703 * stop the transfer of received packets.
1705 /* stop the port's receive queue */
1706 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), CSR_STOP
);
1711 * Clear packet arbiter timeout to make sure
1712 * this loop will terminate
1714 SK_OUT16(IoC
, B3_PA_CTRL
, (SK_U16
)((Port
== MAC_1
) ?
1715 PA_CLR_TO_RX1
: PA_CLR_TO_RX2
));
1717 DWord
= TestStopBit(pAC
, IoC
, pPrt
->PRxQOff
);
1719 /* timeout if i==0 (bug fix for #10748) */
1721 SK_ERR_LOG(pAC
, SK_ERRCL_HW
, SKERR_HWI_E024
,
1726 * because of the ASIC problem report entry from 21.08.98
1727 * it is required to wait until CSR_STOP is reset and
1728 * CSR_SV_IDLE is set.
1730 } while ((DWord
& (CSR_STOP
| CSR_SV_IDLE
)) != CSR_SV_IDLE
);
1732 /* The path data transfer activity is fully stopped now */
1734 /* Perform a local reset of the port's Rx path */
1736 /* Reset the PCI FIFO of the Rx queue */
1737 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), CSR_SET_RESET
);
1738 /* Reset the RAM Buffer receive queue */
1739 SK_OUT8(IoC
, RB_ADDR(pPrt
->PRxQOff
, RB_CTRL
), RB_RST_SET
);
1741 /* Reset Rx MAC FIFO */
1743 if (pAC
->GIni
.GIGenesis
) {
1745 SK_OUT8(IoC
, MR_ADDR(Port
, RX_MFF_CTRL2
), MFF_RST_SET
);
1747 /* switch Rx LED off, stop the LED counter */
1748 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, RX_LED_INI
), SK_LED_DIS
);
1750 #endif /* GENESIS */
1753 if (pAC
->GIni
.GIYukon
) {
1754 /* Reset Rx MAC FIFO */
1755 SK_OUT8(IoC
, MR_ADDR(Port
, RX_GMF_CTRL_T
), (SK_U8
)GMF_RST_SET
);
1759 } /* SkGeStopPort */
1762 /******************************************************************************
1764 * SkGeInit0() - Level 0 Initialization
1767 * - Initialize the BMU address offsets
1772 static void SkGeInit0(
1773 SK_AC
*pAC
, /* adapter context */
1774 SK_IOC IoC
) /* IO context */
1779 for (i
= 0; i
< SK_MAX_MACS
; i
++) {
1780 pPrt
= &pAC
->GIni
.GP
[i
];
1782 pPrt
->PState
= SK_PRT_RESET
;
1783 pPrt
->PRxQOff
= QOffTab
[i
].RxQOff
;
1784 pPrt
->PXsQOff
= QOffTab
[i
].XsQOff
;
1785 pPrt
->PXaQOff
= QOffTab
[i
].XaQOff
;
1786 pPrt
->PCheckPar
= SK_FALSE
;
1788 pPrt
->PPrevShorts
= 0;
1789 pPrt
->PLinkResCt
= 0;
1790 pPrt
->PAutoNegTOCt
= 0;
1793 pPrt
->PRxLim
= SK_DEF_RX_WA_LIM
;
1794 pPrt
->PLinkMode
= (SK_U8
)SK_LMODE_AUTOFULL
;
1795 pPrt
->PLinkSpeedCap
= (SK_U8
)SK_LSPEED_CAP_1000MBPS
;
1796 pPrt
->PLinkSpeed
= (SK_U8
)SK_LSPEED_1000MBPS
;
1797 pPrt
->PLinkSpeedUsed
= (SK_U8
)SK_LSPEED_STAT_UNKNOWN
;
1798 pPrt
->PLinkModeConf
= (SK_U8
)SK_LMODE_AUTOSENSE
;
1799 pPrt
->PFlowCtrlMode
= (SK_U8
)SK_FLOW_MODE_SYM_OR_REM
;
1800 pPrt
->PLinkCap
= (SK_U8
)(SK_LMODE_CAP_HALF
| SK_LMODE_CAP_FULL
|
1801 SK_LMODE_CAP_AUTOHALF
| SK_LMODE_CAP_AUTOFULL
);
1802 pPrt
->PLinkModeStatus
= (SK_U8
)SK_LMODE_STAT_UNKNOWN
;
1803 pPrt
->PFlowCtrlCap
= (SK_U8
)SK_FLOW_MODE_SYM_OR_REM
;
1804 pPrt
->PFlowCtrlStatus
= (SK_U8
)SK_FLOW_STAT_NONE
;
1806 pPrt
->PMSMode
= (SK_U8
)SK_MS_MODE_AUTO
;
1807 pPrt
->PMSStatus
= (SK_U8
)SK_MS_STAT_UNSET
;
1808 pPrt
->PLipaAutoNeg
= (SK_U8
)SK_LIPA_UNKNOWN
;
1809 pPrt
->PAutoNegFail
= SK_FALSE
;
1810 pPrt
->PHWLinkUp
= SK_FALSE
;
1811 pPrt
->PLinkBroken
= SK_TRUE
; /* See WA code */
1814 pAC
->GIni
.GIPortUsage
= SK_RED_LINK
;
1815 pAC
->GIni
.GILedBlinkCtrl
= (SK_U16
)OemConfig
.Value
;
1816 pAC
->GIni
.GIValIrqMask
= IS_ALL_MSK
;
1822 /******************************************************************************
1824 * SkGePciReset() - Reset PCI interface
1827 * o Read PCI configuration.
1828 * o Change power state to 3.
1829 * o Change power state to 0.
1830 * o Restore PCI configuration.
1834 * 1: Power state could not be changed to 3.
1836 static int SkGePciReset(
1837 SK_AC
*pAC
, /* adapter context */
1838 SK_IOC IoC
) /* IO context */
1847 SK_U8 ConfigSpace
[PCI_CFG_SIZE
];
1850 * Note: Switching to D3 state is like a software reset.
1851 * Switching from D3 to D0 is a hardware reset.
1852 * We have to save and restore the configuration space.
1854 for (i
= 0; i
< PCI_CFG_SIZE
; i
++) {
1855 SkPciReadCfgDWord(pAC
, i
*4, &ConfigSpace
[i
]);
1858 /* We know the RAM Interface Arbiter is enabled. */
1859 SkPciWriteCfgWord(pAC
, PCI_PM_CTL_STS
, PCI_PM_STATE_D3
);
1860 SkPciReadCfgWord(pAC
, PCI_PM_CTL_STS
, &PmCtlSts
);
1862 if ((PmCtlSts
& PCI_PM_STATE_MSK
) != PCI_PM_STATE_D3
) {
1866 /* Return to D0 state. */
1867 SkPciWriteCfgWord(pAC
, PCI_PM_CTL_STS
, PCI_PM_STATE_D0
);
1869 /* Check for D0 state. */
1870 SkPciReadCfgWord(pAC
, PCI_PM_CTL_STS
, &PmCtlSts
);
1872 if ((PmCtlSts
& PCI_PM_STATE_MSK
) != PCI_PM_STATE_D0
) {
1876 /* Check PCI Config Registers. */
1877 SkPciReadCfgWord(pAC
, PCI_COMMAND
, &PciCmd
);
1878 SkPciReadCfgByte(pAC
, PCI_CACHE_LSZ
, &Cls
);
1879 SkPciReadCfgDWord(pAC
, PCI_BASE_1ST
, &Bp1
);
1880 SkPciReadCfgDWord(pAC
, PCI_BASE_2ND
, &Bp2
);
1881 SkPciReadCfgByte(pAC
, PCI_LAT_TIM
, &Lat
);
1883 if (PciCmd
!= 0 || Cls
!= (SK_U8
)0 || Lat
!= (SK_U8
)0 ||
1884 (Bp1
& 0xfffffff0L
) != 0 || Bp2
!= 1) {
1888 /* Restore PCI Config Space. */
1889 for (i
= 0; i
< PCI_CFG_SIZE
; i
++) {
1890 SkPciWriteCfgDWord(pAC
, i
*4, ConfigSpace
[i
]);
1894 } /* SkGePciReset */
1896 #endif /* SK_PCI_RESET */
1898 /******************************************************************************
1900 * SkGeInit1() - Level 1 Initialization
1903 * o Do a software reset.
1904 * o Clear all reset bits.
1905 * o Verify that the detected hardware is present.
1906 * Return an error if not.
1907 * o Get the hardware configuration
1908 * + Read the number of MACs/Ports.
1909 * + Read the RAM size.
1910 * + Read the PCI Revision Id.
1911 * + Find out the adapters host clock speed
1912 * + Read and check the PHY type
1916 * 5: Unexpected PHY type detected
1917 * 6: HW self test failed
1919 static int SkGeInit1(
1920 SK_AC
*pAC
, /* adapter context */
1921 SK_IOC IoC
) /* IO context */
1932 /* save CLK_RUN bits (YUKON-Lite) */
1933 SK_IN16(IoC
, B0_CTST
, &CtrlStat
);
1936 (void)SkGePciReset(pAC
, IoC
);
1937 #endif /* SK_PCI_RESET */
1939 /* do the SW-reset */
1940 SK_OUT8(IoC
, B0_CTST
, CS_RST_SET
);
1942 /* release the SW-reset */
1943 SK_OUT8(IoC
, B0_CTST
, CS_RST_CLR
);
1945 /* reset all error bits in the PCI STATUS register */
1947 * Note: PCI Cfg cycles cannot be used, because they are not
1948 * available on some platforms after 'boot time'.
1950 SK_IN16(IoC
, PCI_C(PCI_STATUS
), &Word
);
1952 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
1953 SK_OUT16(IoC
, PCI_C(PCI_STATUS
), (SK_U16
)(Word
| PCI_ERRBITS
));
1954 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
1956 /* release Master Reset */
1957 SK_OUT8(IoC
, B0_CTST
, CS_MRST_CLR
);
1960 CtrlStat
|= CS_CLK_RUN_ENA
;
1961 #endif /* CLK_RUN */
1963 /* restore CLK_RUN bits */
1964 SK_OUT16(IoC
, B0_CTST
, (SK_U16
)(CtrlStat
&
1965 (CS_CLK_RUN_HOT
| CS_CLK_RUN_RST
| CS_CLK_RUN_ENA
)));
1967 /* read Chip Identification Number */
1968 SK_IN8(IoC
, B2_CHIP_ID
, &Byte
);
1969 pAC
->GIni
.GIChipId
= Byte
;
1971 /* read number of MACs */
1972 SK_IN8(IoC
, B2_MAC_CFG
, &Byte
);
1973 pAC
->GIni
.GIMacsFound
= (Byte
& CFG_SNG_MAC
) ? 1 : 2;
1975 /* get Chip Revision Number */
1976 pAC
->GIni
.GIChipRev
= (SK_U8
)((Byte
& CFG_CHIP_R_MSK
) >> 4);
1978 /* get diff. PCI parameters */
1979 SK_IN16(IoC
, B0_CTST
, &CtrlStat
);
1981 /* read the adapters RAM size */
1982 SK_IN8(IoC
, B2_E_0
, &Byte
);
1984 pAC
->GIni
.GIGenesis
= SK_FALSE
;
1985 pAC
->GIni
.GIYukon
= SK_FALSE
;
1986 pAC
->GIni
.GIYukonLite
= SK_FALSE
;
1989 if (pAC
->GIni
.GIChipId
== CHIP_ID_GENESIS
) {
1991 pAC
->GIni
.GIGenesis
= SK_TRUE
;
1993 if (Byte
== (SK_U8
)3) {
1994 /* special case: 4 x 64k x 36, offset = 0x80000 */
1995 pAC
->GIni
.GIRamSize
= 1024;
1996 pAC
->GIni
.GIRamOffs
= (SK_U32
)512 * 1024;
1999 pAC
->GIni
.GIRamSize
= (int)Byte
* 512;
2000 pAC
->GIni
.GIRamOffs
= 0;
2002 /* all GE adapters work with 53.125 MHz host clock */
2003 pAC
->GIni
.GIHstClkFact
= SK_FACT_53
;
2005 /* set Descr. Poll Timer Init Value to 250 ms */
2006 pAC
->GIni
.GIPollTimerVal
=
2007 SK_DPOLL_DEF
* (SK_U32
)pAC
->GIni
.GIHstClkFact
/ 100;
2009 #endif /* GENESIS */
2012 if (pAC
->GIni
.GIChipId
!= CHIP_ID_GENESIS
) {
2014 pAC
->GIni
.GIYukon
= SK_TRUE
;
2016 pAC
->GIni
.GIRamSize
= (Byte
== (SK_U8
)0) ? 128 : (int)Byte
* 4;
2018 pAC
->GIni
.GIRamOffs
= 0;
2020 /* WA for chip Rev. A */
2021 pAC
->GIni
.GIWolOffs
= (pAC
->GIni
.GIChipId
== CHIP_ID_YUKON
&&
2022 pAC
->GIni
.GIChipRev
== 0) ? WOL_REG_OFFS
: 0;
2024 /* get PM Capabilities of PCI config space */
2025 SK_IN16(IoC
, PCI_C(PCI_PM_CAP_REG
), &Word
);
2027 /* check if VAUX is available */
2028 if (((CtrlStat
& CS_VAUX_AVAIL
) != 0) &&
2029 /* check also if PME from D3cold is set */
2030 ((Word
& PCI_PME_D3C_SUP
) != 0)) {
2031 /* set entry in GE init struct */
2032 pAC
->GIni
.GIVauxAvail
= SK_TRUE
;
2035 if (pAC
->GIni
.GIChipId
== CHIP_ID_YUKON_LITE
) {
2036 /* this is Rev. A1 */
2037 pAC
->GIni
.GIYukonLite
= SK_TRUE
;
2040 /* save Flash-Address Register */
2041 SK_IN32(IoC
, B2_FAR
, &DWord
);
2043 /* test Flash-Address Register */
2044 SK_OUT8(IoC
, B2_FAR
+ 3, 0xff);
2045 SK_IN8(IoC
, B2_FAR
+ 3, &Byte
);
2048 /* this is Rev. A0 */
2049 pAC
->GIni
.GIYukonLite
= SK_TRUE
;
2051 /* restore Flash-Address Register */
2052 SK_OUT32(IoC
, B2_FAR
, DWord
);
2056 /* read the Interrupt source */
2057 SK_IN32(IoC
, B0_ISRC
, &DWord
);
2059 if ((DWord
& IS_HW_ERR
) != 0) {
2060 /* read the HW Error Interrupt source */
2061 SK_IN32(IoC
, B0_HWE_ISRC
, &DWord
);
2063 if ((DWord
& IS_IRQ_SENSOR
) != 0) {
2064 /* disable HW Error IRQ */
2065 pAC
->GIni
.GIValIrqMask
&= ~IS_HW_ERR
;
2069 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
2070 /* set GMAC Link Control reset */
2071 SK_OUT16(IoC
, MR_ADDR(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2073 /* clear GMAC Link Control reset */
2074 SK_OUT16(IoC
, MR_ADDR(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2076 /* all YU chips work with 78.125 MHz host clock */
2077 pAC
->GIni
.GIHstClkFact
= SK_FACT_78
;
2079 pAC
->GIni
.GIPollTimerVal
= SK_DPOLL_MAX
; /* 215 ms */
2083 /* check if 64-bit PCI Slot is present */
2084 pAC
->GIni
.GIPciSlot64
= (SK_BOOL
)((CtrlStat
& CS_BUS_SLOT_SZ
) != 0);
2086 /* check if 66 MHz PCI Clock is active */
2087 pAC
->GIni
.GIPciClock66
= (SK_BOOL
)((CtrlStat
& CS_BUS_CLOCK
) != 0);
2089 /* read PCI HW Revision Id. */
2090 SK_IN8(IoC
, PCI_C(PCI_REV_ID
), &Byte
);
2091 pAC
->GIni
.GIPciHwRev
= Byte
;
2093 /* read the PMD type */
2094 SK_IN8(IoC
, B2_PMD_TYP
, &Byte
);
2095 pAC
->GIni
.GICopperType
= (SK_U8
)(Byte
== 'T');
2097 /* read the PHY type */
2098 SK_IN8(IoC
, B2_E_1
, &Byte
);
2100 Byte
&= 0x0f; /* the PHY type is stored in the lower nibble */
2101 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
2104 if (pAC
->GIni
.GIGenesis
) {
2107 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_XMAC
;
2110 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_BCOM
;
2111 pAC
->GIni
.GP
[i
].PMSCap
= (SK_U8
)(SK_MS_CAP_AUTO
|
2112 SK_MS_CAP_MASTER
| SK_MS_CAP_SLAVE
);
2116 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_LONE
;
2119 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_NAT
;
2121 #endif /* OTHER_PHY */
2123 /* ERROR: unexpected PHY type detected */
2128 #endif /* GENESIS */
2131 if (pAC
->GIni
.GIYukon
) {
2133 if (Byte
< (SK_U8
)SK_PHY_MARV_COPPER
) {
2134 /* if this field is not initialized */
2135 Byte
= (SK_U8
)SK_PHY_MARV_COPPER
;
2137 pAC
->GIni
.GICopperType
= SK_TRUE
;
2140 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_MARV
;
2142 if (pAC
->GIni
.GICopperType
) {
2144 pAC
->GIni
.GP
[i
].PLinkSpeedCap
= (SK_U8
)(SK_LSPEED_CAP_AUTO
|
2145 SK_LSPEED_CAP_10MBPS
| SK_LSPEED_CAP_100MBPS
|
2146 SK_LSPEED_CAP_1000MBPS
);
2148 pAC
->GIni
.GP
[i
].PLinkSpeed
= (SK_U8
)SK_LSPEED_AUTO
;
2150 pAC
->GIni
.GP
[i
].PMSCap
= (SK_U8
)(SK_MS_CAP_AUTO
|
2151 SK_MS_CAP_MASTER
| SK_MS_CAP_SLAVE
);
2154 Byte
= (SK_U8
)SK_PHY_MARV_FIBER
;
2159 pAC
->GIni
.GP
[i
].PhyType
= (int)Byte
;
2161 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
2162 ("PHY type: %d PHY addr: %04x\n", Byte
,
2163 pAC
->GIni
.GP
[i
].PhyAddr
));
2166 /* get MAC Type & set function pointers dependent on */
2168 if (pAC
->GIni
.GIGenesis
) {
2170 pAC
->GIni
.GIMacType
= SK_MAC_XMAC
;
2172 pAC
->GIni
.GIFunc
.pFnMacUpdateStats
= SkXmUpdateStats
;
2173 pAC
->GIni
.GIFunc
.pFnMacStatistic
= SkXmMacStatistic
;
2174 pAC
->GIni
.GIFunc
.pFnMacResetCounter
= SkXmResetCounter
;
2175 pAC
->GIni
.GIFunc
.pFnMacOverflow
= SkXmOverflowStatus
;
2177 #endif /* GENESIS */
2180 if (pAC
->GIni
.GIYukon
) {
2182 pAC
->GIni
.GIMacType
= SK_MAC_GMAC
;
2184 pAC
->GIni
.GIFunc
.pFnMacUpdateStats
= SkGmUpdateStats
;
2185 pAC
->GIni
.GIFunc
.pFnMacStatistic
= SkGmMacStatistic
;
2186 pAC
->GIni
.GIFunc
.pFnMacResetCounter
= SkGmResetCounter
;
2187 pAC
->GIni
.GIFunc
.pFnMacOverflow
= SkGmOverflowStatus
;
2189 #ifdef SPECIAL_HANDLING
2190 if (pAC
->GIni
.GIChipId
== CHIP_ID_YUKON
) {
2191 /* check HW self test result */
2192 SK_IN8(IoC
, B2_E_3
, &Byte
);
2193 if (Byte
& B2_E3_RES_MASK
) {
2205 /******************************************************************************
2207 * SkGeInit2() - Level 2 Initialization
2210 * - start the Blink Source Counter
2211 * - start the Descriptor Poll Timer
2212 * - configure the MAC-Arbiter
2213 * - configure the Packet-Arbiter
2214 * - enable the Tx Arbiters
2215 * - enable the RAM Interface Arbiter
2220 static void SkGeInit2(
2221 SK_AC
*pAC
, /* adapter context */
2222 SK_IOC IoC
) /* IO context */
2226 #endif /* GENESIS */
2229 /* start the Descriptor Poll Timer */
2230 if (pAC
->GIni
.GIPollTimerVal
!= 0) {
2231 if (pAC
->GIni
.GIPollTimerVal
> SK_DPOLL_MAX
) {
2232 pAC
->GIni
.GIPollTimerVal
= SK_DPOLL_MAX
;
2234 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E017
, SKERR_HWI_E017MSG
);
2236 SK_OUT32(IoC
, B28_DPT_INI
, pAC
->GIni
.GIPollTimerVal
);
2237 SK_OUT8(IoC
, B28_DPT_CTRL
, DPT_START
);
2241 if (pAC
->GIni
.GIGenesis
) {
2242 /* start the Blink Source Counter */
2243 DWord
= SK_BLK_DUR
* (SK_U32
)pAC
->GIni
.GIHstClkFact
/ 100;
2245 SK_OUT32(IoC
, B2_BSC_INI
, DWord
);
2246 SK_OUT8(IoC
, B2_BSC_CTRL
, BSC_START
);
2249 * Configure the MAC Arbiter and the Packet Arbiter.
2250 * They will be started once and never be stopped.
2252 SkGeInitMacArb(pAC
, IoC
);
2254 SkGeInitPktArb(pAC
, IoC
);
2256 #endif /* GENESIS */
2259 if (pAC
->GIni
.GIYukon
) {
2260 /* start Time Stamp Timer */
2261 SK_OUT8(IoC
, GMAC_TI_ST_CTRL
, (SK_U8
)GMT_ST_START
);
2265 /* enable the Tx Arbiters */
2266 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
2267 SK_OUT8(IoC
, MR_ADDR(i
, TXA_CTRL
), TXA_ENA_ARB
);
2270 /* enable the RAM Interface Arbiter */
2271 SkGeInitRamIface(pAC
, IoC
);
2275 /******************************************************************************
2277 * SkGeInit() - Initialize the GE Adapter with the specified level.
2280 * Level 0: Initialize the Module structures.
2281 * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has
2282 * to be set before calling this level.
2284 * o Do a software reset.
2285 * o Clear all reset bits.
2286 * o Verify that the detected hardware is present.
2287 * Return an error if not.
2288 * o Get the hardware configuration
2289 * + Set GIMacsFound with the number of MACs.
2290 * + Store the RAM size in GIRamSize.
2291 * + Save the PCI Revision ID in GIPciHwRev.
2293 * if Number of MACs > SK_MAX_MACS
2295 * After returning from Level 0 the adapter
2296 * may be accessed with IO operations.
2298 * Level 2: start the Blink Source Counter
2302 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
2303 * 2: Adapter not present or not accessible
2304 * 3: Illegal initialization level
2305 * 4: Initialization Level 1 Call missing
2306 * 5: Unexpected PHY type detected
2307 * 6: HW self test failed
2310 SK_AC
*pAC
, /* adapter context */
2311 SK_IOC IoC
, /* IO context */
2312 int Level
) /* initialization level */
2314 int RetVal
; /* return value */
2318 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
2319 ("SkGeInit(Level %d)\n", Level
));
2323 /* Initialization Level 0 */
2324 SkGeInit0(pAC
, IoC
);
2325 pAC
->GIni
.GILevel
= SK_INIT_DATA
;
2329 /* Initialization Level 1 */
2330 RetVal
= SkGeInit1(pAC
, IoC
);
2335 /* check if the adapter seems to be accessible */
2336 SK_OUT32(IoC
, B2_IRQM_INI
, SK_TEST_VAL
);
2337 SK_IN32(IoC
, B2_IRQM_INI
, &DWord
);
2338 SK_OUT32(IoC
, B2_IRQM_INI
, 0L);
2340 if (DWord
!= SK_TEST_VAL
) {
2345 /* check if the number of GIMacsFound matches SK_MAX_MACS */
2346 if (pAC
->GIni
.GIMacsFound
> SK_MAX_MACS
) {
2351 /* Level 1 successfully passed */
2352 pAC
->GIni
.GILevel
= SK_INIT_IO
;
2356 /* Initialization Level 2 */
2357 if (pAC
->GIni
.GILevel
!= SK_INIT_IO
) {
2359 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E002
, SKERR_HWI_E002MSG
);
2360 #endif /* !SK_DIAG */
2364 SkGeInit2(pAC
, IoC
);
2366 /* Level 2 successfully passed */
2367 pAC
->GIni
.GILevel
= SK_INIT_RUN
;
2371 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E003
, SKERR_HWI_E003MSG
);
2380 /******************************************************************************
2382 * SkGeDeInit() - Deinitialize the adapter
2385 * All ports of the adapter will be stopped if not already done.
2386 * Do a software reset and switch off all LEDs.
2392 SK_AC
*pAC
, /* adapter context */
2393 SK_IOC IoC
) /* IO context */
2398 #if (!defined(SK_SLIM) && !defined(VCPU))
2399 /* ensure I2C is ready */
2400 SkI2cWaitIrq(pAC
, IoC
);
2403 /* stop all current transfer activity */
2404 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
2405 if (pAC
->GIni
.GP
[i
].PState
!= SK_PRT_STOP
&&
2406 pAC
->GIni
.GP
[i
].PState
!= SK_PRT_RESET
) {
2408 SkGeStopPort(pAC
, IoC
, i
, SK_STOP_ALL
, SK_HARD_RST
);
2412 /* Reset all bits in the PCI STATUS register */
2414 * Note: PCI Cfg cycles cannot be used, because they are not
2415 * available on some platforms after 'boot time'.
2417 SK_IN16(IoC
, PCI_C(PCI_STATUS
), &Word
);
2419 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2420 SK_OUT16(IoC
, PCI_C(PCI_STATUS
), (SK_U16
)(Word
| PCI_ERRBITS
));
2421 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2423 /* do the reset, all LEDs are switched off now */
2424 SK_OUT8(IoC
, B0_CTST
, CS_RST_SET
);
2426 pAC
->GIni
.GILevel
= SK_INIT_DATA
;
2430 /******************************************************************************
2432 * SkGeInitPort() Initialize the specified port.
2435 * PRxQSize, PXSQSize, and PXAQSize has to be
2436 * configured for the specified port before calling this function.
2437 * The descriptor rings has to be initialized too.
2439 * o (Re)configure queues of the specified port.
2440 * o configure the MAC of the specified port.
2441 * o put ASIC and MAC(s) in operational mode.
2442 * o initialize Rx/Tx and Sync LED
2443 * o initialize RAM Buffers and MAC FIFOs
2445 * The port is ready to connect when returning.
2448 * The MAC's Rx and Tx state machine is still disabled when returning.
2452 * 1: Queue size initialization error. The configured values
2453 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
2454 * or more queues. The specified port was NOT initialized.
2455 * An error log entry was generated.
2456 * 2: The port has to be stopped before it can be initialized again.
2459 SK_AC
*pAC
, /* adapter context */
2460 SK_IOC IoC
, /* IO context */
2461 int Port
) /* Port to configure */
2465 pPrt
= &pAC
->GIni
.GP
[Port
];
2467 if (SkGeCheckQSize(pAC
, Port
) != 0) {
2468 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E004
, SKERR_HWI_E004MSG
);
2472 if (pPrt
->PState
== SK_PRT_INIT
|| pPrt
->PState
== SK_PRT_RUN
) {
2473 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E005
, SKERR_HWI_E005MSG
);
2477 /* configuration ok, initialize the Port now */
2480 if (pAC
->GIni
.GIGenesis
) {
2481 /* initialize Rx, Tx and Link LED */
2483 * If 1000BT Phy needs LED initialization than swap
2484 * LED and XMAC initialization order
2486 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, TX_LED_INI
), SK_LED_ENA
);
2487 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, RX_LED_INI
), SK_LED_ENA
);
2488 /* The Link LED is initialized by RLMT or Diagnostics itself */
2490 SkXmInitMac(pAC
, IoC
, Port
);
2492 #endif /* GENESIS */
2495 if (pAC
->GIni
.GIYukon
) {
2497 SkGmInitMac(pAC
, IoC
, Port
);
2501 /* do NOT initialize the Link Sync Counter */
2503 SkGeInitMacFifo(pAC
, IoC
, Port
);
2505 SkGeInitRamBufs(pAC
, IoC
, Port
);
2507 if (pPrt
->PXSQSize
!= 0) {
2508 /* enable Force Sync bit if synchronous queue available */
2509 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
), TXA_ENA_FSYNC
);
2512 SkGeInitBmu(pAC
, IoC
, Port
);
2514 /* mark port as initialized */
2515 pPrt
->PState
= SK_PRT_INIT
;
2518 } /* SkGeInitPort */