drivers/media/dvb/frontends/mt352.h

   1 /*
   2  *  Driver for Zarlink DVB-T MT352 demodulator
   3  *
   4  *  Written by Holger Waechtler <holger@qanu.de>
   5  *       and Daniel Mack <daniel@qanu.de>
   6  *
   7  *  AVerMedia AVerTV DVB-T 771 support by
   8  *       Wolfram Joost <dbox2@frokaschwei.de>
   9  *
  10  *  Support for Samsung TDTC9251DH01C(M) tuner
  11  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
  12  *                     Amauri  Celani  <acelani@essegi.net>
  13  *
  14  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
  15  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *
  26  *  GNU General Public License for more details.
  27  *
  28  *  You should have received a copy of the GNU General Public License
  29  *  along with this program; if not, write to the Free Software
  30  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
  31  */
  32
  33 #ifndef _MT352_
  34 #define _MT352_
  35
  36 #define I2C_MT352_ADDR  0x0f
  37 #define ID_MT352        0x13
  38
  39 #define CARD_AVDVBT771      0x00
  40 #define CARD_TUA6034        0x01
  41 #define CARD_TDTC9251DH01C  0x02
  42 #define CARD_DVICODVBT1     0x03
  43 #define CARD_DVICODVBTLITE  0x04
  44
  45 #define msb(x) (((x) >> 8) & 0xff)
  46 #define lsb(x) ((x) & 0xff)
  47
  48 enum mt352_reg_addr {
  49         STATUS_0           = 0x00,
  50         STATUS_1           = 0x01,
  51         STATUS_2           = 0x02,
  52         STATUS_3           = 0x03,
  53         STATUS_4           = 0x04,
  54         INTERRUPT_0        = 0x05,
  55         INTERRUPT_1        = 0x06,
  56         INTERRUPT_2        = 0x07,
  57         INTERRUPT_3        = 0x08,
  58         SNR                = 0x09,
  59         VIT_ERR_CNT_2      = 0x0A,
  60         VIT_ERR_CNT_1      = 0x0B,
  61         VIT_ERR_CNT_0      = 0x0C,
  62         RS_ERR_CNT_2       = 0x0D,
  63         RS_ERR_CNT_1       = 0x0E,
  64         RS_ERR_CNT_0       = 0x0F,
  65         RS_UBC_1           = 0x10,
  66         RS_UBC_0           = 0x11,
  67         AGC_GAIN_3         = 0x12,
  68         AGC_GAIN_2         = 0x13,
  69         AGC_GAIN_1         = 0x14,
  70         AGC_GAIN_0         = 0x15,
  71         FREQ_OFFSET_2      = 0x17,
  72         FREQ_OFFSET_1      = 0x18,
  73         FREQ_OFFSET_0      = 0x19,
  74         TIMING_OFFSET_1    = 0x1A,
  75         TIMING_OFFSET_0    = 0x1B,
  76         CHAN_FREQ_1        = 0x1C,
  77         CHAN_FREQ_0        = 0x1D,
  78         TPS_RECEIVED_1     = 0x1E,
  79         TPS_RECEIVED_0     = 0x1F,
  80         TPS_CURRENT_1      = 0x20,
  81         TPS_CURRENT_0      = 0x21,
  82         TPS_CELL_ID_1      = 0x22,
  83         TPS_CELL_ID_0      = 0x23,
  84         TPS_MISC_DATA_2    = 0x24,
  85         TPS_MISC_DATA_1    = 0x25,
  86         TPS_MISC_DATA_0    = 0x26,
  87         RESET              = 0x50,
  88         TPS_GIVEN_1        = 0x51,
  89         TPS_GIVEN_0        = 0x52,
  90         ACQ_CTL            = 0x53,
  91         TRL_NOMINAL_RATE_1 = 0x54,
  92         TRL_NOMINAL_RATE_0 = 0x55,
  93         INPUT_FREQ_1       = 0x56,
  94         INPUT_FREQ_0       = 0x57,
  95         TUNER_ADDR         = 0x58,
  96         CHAN_START_1       = 0x59,
  97         CHAN_START_0       = 0x5A,
  98         CONT_1             = 0x5B,
  99         CONT_0             = 0x5C,
 100         TUNER_GO           = 0x5D,
 101         STATUS_EN_0        = 0x5F,
 102         STATUS_EN_1        = 0x60,
 103         INTERRUPT_EN_0     = 0x61,
 104         INTERRUPT_EN_1     = 0x62,
 105         INTERRUPT_EN_2     = 0x63,
 106         INTERRUPT_EN_3     = 0x64,
 107         AGC_TARGET         = 0x67,
 108         AGC_CTL            = 0x68,
 109         CAPT_RANGE         = 0x75,
 110         SNR_SELECT_1       = 0x79,
 111         SNR_SELECT_0       = 0x7A,
 112         RS_ERR_PER_1       = 0x7C,
 113         RS_ERR_PER_0       = 0x7D,
 114         CHIP_ID            = 0x7F,
 115         CHAN_STOP_1        = 0x80,
 116         CHAN_STOP_0        = 0x81,
 117         CHAN_STEP_1        = 0x82,
 118         CHAN_STEP_0        = 0x83,
 119         FEC_LOCK_TIME      = 0x85,
 120         OFDM_LOCK_TIME     = 0x86,
 121         ACQ_DELAY          = 0x87,
 122         SCAN_CTL           = 0x88,
 123         CLOCK_CTL          = 0x89,
 124         CONFIG             = 0x8A,
 125         MCLK_RATIO         = 0x8B,
 126         GPP_CTL            = 0x8C,
 127         ADC_CTL_1          = 0x8E,
 128         ADC_CTL_0          = 0x8F
 129 };
 130
 131 struct _tuner_info {
 132         char *fe_name;
 133 #define FE_NAME tuner_info[card_type].fe_name
 134
 135         __u32 fe_frequency_min;
 136 #define FE_FREQ_MIN tuner_info[card_type].fe_frequency_min
 137
 138         __u32 fe_frequency_max;
 139 #define FE_FREQ_MAX tuner_info[card_type].fe_frequency_max
 140
 141         __u32 fe_frequency_stepsize; //verificare se u32 e' corretto
 142 #define FE_FREQ_STEPSIZE  tuner_info[card_type].fe_frequency_stepsize
 143
 144         u8 pll_i2c_addr;
 145 #define PLL_I2C_ADDR tuner_info[card_type].pll_i2c_addr
 146
 147         int (* mt352_init) (struct i2c_adapter *i2c);
 148 #define MT352_INIT tuner_info[card_type].mt352_init
 149
 150         unsigned char (* mt352_charge_pump) (u32 freq);
 151 #define MT352_CHARGE_PUMP tuner_info[card_type].mt352_charge_pump
 152
 153         unsigned char (* mt352_band_select) (u32 freq);
 154 #define MT352_BAND_SELECT tuner_info[card_type].mt352_band_select
 155 };
 156
 157 static int mt352_init_TUA6034(struct i2c_adapter *i2c);
 158 static int mt352_init_AVERMEDIA771(struct i2c_adapter *i2c);
 159 static int mt352_init_TDTC9251DH01C(struct i2c_adapter *i2c);
 160 static int mt352_init_DVICODVBT1(struct i2c_adapter *i2c);
 161 static int mt352_init_DVICODVBTLITE(struct i2c_adapter *i2c);
 162 static unsigned char mt352_cp_TUA6034(u32 freq);
 163 static unsigned char mt352_cp_AVERMEDIA771(u32 freq);
 164 static unsigned char mt352_cp_TDTC9251DH01C(u32 freq);
 165 static unsigned char mt352_cp_DVICODVBT1(u32 freq);
 166 static unsigned char mt352_cp_DVICODVBTLITE(u32 freq);
 167 static unsigned char mt352_bs_TUA6034(u32 freq);
 168 static unsigned char mt352_bs_AVERMEDIA771(u32 freq);
 169 static unsigned char mt352_bs_TDTC9251DH01C(u32 freq);
 170 static unsigned char mt352_bs_DVICODVBT1(u32 freq);
 171 static unsigned char mt352_bs_DVICODVBTLITE(u32 freq);
 172 static u8 mt352_read_register(struct i2c_adapter *i2c, u8 reg);
 173
 174 #endif                          /* _MT352_ */