1 /*****************************************************************************/
2 /* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
8 /* Copyright (C) 1999 IBM Corporation */
9 /* Copyright (C) 2003 Adaptec, Inc. */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
45 /* Bugs/Comments/Suggestions should be mailed to: */
46 /* ipslinux@adaptec.com */
48 /*****************************************************************************/
53 #include <asm/uaccess.h>
57 extern int ips_detect(Scsi_Host_Template
*);
58 extern int ips_release(struct Scsi_Host
*);
59 extern int ips_eh_abort(Scsi_Cmnd
*);
60 extern int ips_eh_reset(Scsi_Cmnd
*);
61 extern int ips_queue(Scsi_Cmnd
*, void (*) (Scsi_Cmnd
*));
62 extern const char * ips_info(struct Scsi_Host
*);
67 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) || defined CONFIG_HIGHIO
71 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
72 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
73 #define IPS_IS_TROMBONE(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
74 (ha->revision_id >= IPS_REVID_TROMBONE32) && \
75 (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
76 #define IPS_IS_CLARINET(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
77 (ha->revision_id >= IPS_REVID_CLARINETP1) && \
78 (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
79 #define IPS_IS_MORPHEUS(ha) (ha->device_id == IPS_DEVICEID_MORPHEUS)
80 #define IPS_IS_MARCO(ha) (ha->device_id == IPS_DEVICEID_MARCO)
81 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
82 (IPS_IS_TROMBONE(ha) && \
83 (ips_force_i2o))) ? 1 : 0)
84 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
85 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
86 (ips_force_memio))) ? 1 : 0)
88 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
89 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
90 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
91 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
93 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,4)
94 #define pci_set_dma_mask(dev,mask) ( mask > 0xffffffff ? 1:0 )
95 #define scsi_set_pci_device(sh,dev) (0)
98 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
101 typedef void irqreturn_t
;
106 #define IRQ_RETVAL(x)
107 #define IPS_REGISTER_HOSTS(SHT) scsi_register_module(MODULE_SCSI_HA,SHT)
108 #define IPS_UNREGISTER_HOSTS(SHT) scsi_unregister_module(MODULE_SCSI_HA,SHT)
109 #define IPS_ADD_HOST(shost,device)
110 #define IPS_REMOVE_HOST(shost)
111 #define IPS_SCSI_SET_DEVICE(sh,ha) scsi_set_pci_device(sh, (ha)->pcidev)
112 #define IPS_PRINTK(level, pcidev, format, arg...) \
113 printk(level "%s %s:" format , "ips" , \
114 (pcidev)->slot_name , ## arg)
115 #define scsi_host_alloc(sh,size) scsi_register(sh,size)
116 #define scsi_host_put(sh) scsi_unregister(sh)
118 #define IPS_REGISTER_HOSTS(SHT) (!ips_detect(SHT))
119 #define IPS_UNREGISTER_HOSTS(SHT)
120 #define IPS_ADD_HOST(shost,device) do { scsi_add_host(shost,device); scsi_scan_host(shost); } while (0)
121 #define IPS_REMOVE_HOST(shost) scsi_remove_host(shost)
122 #define IPS_SCSI_SET_DEVICE(sh,ha) scsi_set_device(sh, &(ha)->pcidev->dev)
123 #define IPS_PRINTK(level, pcidev, format, arg...) \
124 dev_printk(level , &((pcidev)->dev) , format , ## arg)
128 #define MDELAY mdelay
132 #define min(x,y) ((x) < (y) ? x : y)
135 #define pci_dma_hi32(a) ((a >> 16) >> 16)
136 #define pci_dma_lo32(a) (a & 0xffffffff)
138 #if (BITS_PER_LONG > 32) || (defined CONFIG_HIGHMEM64G && defined IPS_HIGHIO)
139 #define IPS_ENABLE_DMA64 (1)
141 #define IPS_ENABLE_DMA64 (0)
145 * Adapter address map equates
147 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
148 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
149 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
150 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
151 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
152 #define IPS_REG_SQER 0x28 /* Status Q End Reg */
153 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
154 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
155 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
156 #define IPS_REG_CBSP 0x07 /* CBSP register */
157 #define IPS_REG_FLAP 0x18 /* Flash address port */
158 #define IPS_REG_FLDP 0x1C /* Flash data port */
159 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
160 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
161 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
162 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
163 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
164 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
165 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
166 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
169 * Adapter register bit equates
171 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
172 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
173 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
174 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
175 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
176 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
177 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
178 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
179 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
180 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
181 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
182 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
183 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
184 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
187 * Adapter Command ID Equates
189 #define IPS_CMD_GET_LD_INFO 0x19
190 #define IPS_CMD_GET_SUBSYS 0x40
191 #define IPS_CMD_READ_CONF 0x38
192 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
193 #define IPS_CMD_READ 0x02
194 #define IPS_CMD_WRITE 0x03
195 #define IPS_CMD_FFDC 0xD7
196 #define IPS_CMD_ENQUIRY 0x05
197 #define IPS_CMD_FLUSH 0x0A
198 #define IPS_CMD_READ_SG 0x82
199 #define IPS_CMD_WRITE_SG 0x83
200 #define IPS_CMD_DCDB 0x04
201 #define IPS_CMD_DCDB_SG 0x84
202 #define IPS_CMD_EXTENDED_DCDB 0x95
203 #define IPS_CMD_EXTENDED_DCDB_SG 0x96
204 #define IPS_CMD_CONFIG_SYNC 0x58
205 #define IPS_CMD_ERROR_TABLE 0x17
206 #define IPS_CMD_DOWNLOAD 0x20
207 #define IPS_CMD_RW_BIOSFW 0x22
208 #define IPS_CMD_GET_VERSION_INFO 0xC6
209 #define IPS_CMD_RESET_CHANNEL 0x1A
215 #define IPS_POCL 0x30
216 #define IPS_NORM_STATE 0x00
217 #define IPS_MAX_ADAPTER_TYPES 3
218 #define IPS_MAX_ADAPTERS 16
219 #define IPS_MAX_IOCTL 1
220 #define IPS_MAX_IOCTL_QUEUE 8
221 #define IPS_MAX_QUEUE 128
222 #define IPS_BLKSIZE 512
223 #define IPS_MAX_SG 17
225 #define IPS_MAX_CHANNELS 4
226 #define IPS_MAX_TARGETS 15
227 #define IPS_MAX_CHUNKS 16
228 #define IPS_MAX_CMDS 128
229 #define IPS_MAX_XFER 0x10000
230 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
231 #define IPS_MAX_POST_BYTES 0x02
232 #define IPS_MAX_CONFIG_BYTES 0x02
233 #define IPS_GOOD_POST_STATUS 0x80
234 #define IPS_SEM_TIMEOUT 2000
235 #define IPS_IOCTL_COMMAND 0x0D
236 #define IPS_INTR_ON 0
237 #define IPS_INTR_IORL 1
239 #define IPS_ADAPTER_ID 0xF
240 #define IPS_VENDORID_IBM 0x1014
241 #define IPS_VENDORID_ADAPTEC 0x9005
242 #define IPS_DEVICEID_COPPERHEAD 0x002E
243 #define IPS_DEVICEID_MORPHEUS 0x01BD
244 #define IPS_DEVICEID_MARCO 0x0250
245 #define IPS_SUBDEVICEID_4M 0x01BE
246 #define IPS_SUBDEVICEID_4L 0x01BF
247 #define IPS_SUBDEVICEID_4MX 0x0208
248 #define IPS_SUBDEVICEID_4LX 0x020E
249 #define IPS_SUBDEVICEID_5I2 0x0259
250 #define IPS_SUBDEVICEID_5I1 0x0258
251 #define IPS_SUBDEVICEID_6M 0x0279
252 #define IPS_SUBDEVICEID_6I 0x028C
253 #define IPS_SUBDEVICEID_7k 0x028E
254 #define IPS_SUBDEVICEID_7M 0x028F
255 #define IPS_IOCTL_SIZE 8192
256 #define IPS_STATUS_SIZE 4
257 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
258 #define IPS_IMAGE_SIZE 500 * 1024
259 #define IPS_MEMMAP_SIZE 128
260 #define IPS_ONE_MSEC 1
261 #define IPS_ONE_SEC 1000
266 #define IPS_COMP_HEADS 128
267 #define IPS_COMP_SECTORS 32
268 #define IPS_NORM_HEADS 254
269 #define IPS_NORM_SECTORS 63
272 * Adapter Basic Status Codes
274 #define IPS_BASIC_STATUS_MASK 0xFF
275 #define IPS_GSC_STATUS_MASK 0x0F
276 #define IPS_CMD_SUCCESS 0x00
277 #define IPS_CMD_RECOVERED_ERROR 0x01
278 #define IPS_INVAL_OPCO 0x03
279 #define IPS_INVAL_CMD_BLK 0x04
280 #define IPS_INVAL_PARM_BLK 0x05
281 #define IPS_BUSY 0x08
282 #define IPS_CMD_CMPLT_WERROR 0x0C
283 #define IPS_LD_ERROR 0x0D
284 #define IPS_CMD_TIMEOUT 0x0E
285 #define IPS_PHYS_DRV_ERROR 0x0F
288 * Adapter Extended Status Equates
290 #define IPS_ERR_SEL_TO 0xF0
291 #define IPS_ERR_OU_RUN 0xF2
292 #define IPS_ERR_HOST_RESET 0xF7
293 #define IPS_ERR_DEV_RESET 0xF8
294 #define IPS_ERR_RECOVERY 0xFC
295 #define IPS_ERR_CKCOND 0xFF
298 * Operating System Defines
300 #define IPS_OS_WINDOWS_NT 0x01
301 #define IPS_OS_NETWARE 0x02
302 #define IPS_OS_OPENSERVER 0x03
303 #define IPS_OS_UNIXWARE 0x04
304 #define IPS_OS_SOLARIS 0x05
305 #define IPS_OS_OS2 0x06
306 #define IPS_OS_LINUX 0x07
307 #define IPS_OS_FREEBSD 0x08
310 * Adapter Revision ID's
312 #define IPS_REVID_SERVERAID 0x02
313 #define IPS_REVID_NAVAJO 0x03
314 #define IPS_REVID_SERVERAID2 0x04
315 #define IPS_REVID_CLARINETP1 0x05
316 #define IPS_REVID_CLARINETP2 0x07
317 #define IPS_REVID_CLARINETP3 0x0D
318 #define IPS_REVID_TROMBONE32 0x0F
319 #define IPS_REVID_TROMBONE64 0x10
322 * NVRAM Page 5 Adapter Defines
324 #define IPS_ADTYPE_SERVERAID 0x01
325 #define IPS_ADTYPE_SERVERAID2 0x02
326 #define IPS_ADTYPE_NAVAJO 0x03
327 #define IPS_ADTYPE_KIOWA 0x04
328 #define IPS_ADTYPE_SERVERAID3 0x05
329 #define IPS_ADTYPE_SERVERAID3L 0x06
330 #define IPS_ADTYPE_SERVERAID4H 0x07
331 #define IPS_ADTYPE_SERVERAID4M 0x08
332 #define IPS_ADTYPE_SERVERAID4L 0x09
333 #define IPS_ADTYPE_SERVERAID4MX 0x0A
334 #define IPS_ADTYPE_SERVERAID4LX 0x0B
335 #define IPS_ADTYPE_SERVERAID5I2 0x0C
336 #define IPS_ADTYPE_SERVERAID5I1 0x0D
337 #define IPS_ADTYPE_SERVERAID6M 0x0E
338 #define IPS_ADTYPE_SERVERAID6I 0x0F
339 #define IPS_ADTYPE_SERVERAID7t 0x10
340 #define IPS_ADTYPE_SERVERAID7k 0x11
341 #define IPS_ADTYPE_SERVERAID7M 0x12
344 * Adapter Command/Status Packet Definitions
346 #define IPS_SUCCESS 0x01 /* Successfully completed */
347 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
348 #define IPS_FAILURE 0x04 /* Completed with Error */
351 * Logical Drive Equates
353 #define IPS_LD_OFFLINE 0x02
354 #define IPS_LD_OKAY 0x03
355 #define IPS_LD_FREE 0x00
356 #define IPS_LD_SYS 0x06
357 #define IPS_LD_CRS 0x24
362 #define IPS_NO_DISCONNECT 0x00
363 #define IPS_DISCONNECT_ALLOWED 0x80
364 #define IPS_NO_AUTO_REQSEN 0x40
365 #define IPS_DATA_NONE 0x00
366 #define IPS_DATA_UNK 0x00
367 #define IPS_DATA_IN 0x01
368 #define IPS_DATA_OUT 0x02
369 #define IPS_TRANSFER64K 0x08
370 #define IPS_NOTIMEOUT 0x00
371 #define IPS_TIMEOUT10 0x10
372 #define IPS_TIMEOUT60 0x20
373 #define IPS_TIMEOUT20M 0x30
376 * SCSI Inquiry Data Flags
378 #define IPS_SCSI_INQ_TYPE_DASD 0x00
379 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
380 #define IPS_SCSI_INQ_LU_CONNECTED 0x00
381 #define IPS_SCSI_INQ_RD_REV2 0x02
382 #define IPS_SCSI_INQ_REV2 0x02
383 #define IPS_SCSI_INQ_REV3 0x03
384 #define IPS_SCSI_INQ_Address16 0x01
385 #define IPS_SCSI_INQ_Address32 0x02
386 #define IPS_SCSI_INQ_MedChanger 0x08
387 #define IPS_SCSI_INQ_MultiPort 0x10
388 #define IPS_SCSI_INQ_EncServ 0x40
389 #define IPS_SCSI_INQ_SoftReset 0x01
390 #define IPS_SCSI_INQ_CmdQue 0x02
391 #define IPS_SCSI_INQ_Linked 0x08
392 #define IPS_SCSI_INQ_Sync 0x10
393 #define IPS_SCSI_INQ_WBus16 0x20
394 #define IPS_SCSI_INQ_WBus32 0x40
395 #define IPS_SCSI_INQ_RelAdr 0x80
398 * SCSI Request Sense Data Flags
400 #define IPS_SCSI_REQSEN_VALID 0x80
401 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
402 #define IPS_SCSI_REQSEN_NO_SENSE 0x00
405 * SCSI Mode Page Equates
407 #define IPS_SCSI_MP3_SoftSector 0x01
408 #define IPS_SCSI_MP3_HardSector 0x02
409 #define IPS_SCSI_MP3_Removeable 0x04
410 #define IPS_SCSI_MP3_AllocateSurface 0x08
416 #define IPS_HA_ENH_SG 0x1
421 #define IPS_SCB_MAP_SG 0x00008
422 #define IPS_SCB_MAP_SINGLE 0X00010
427 #define IPS_COPPUSRCMD (('C'<<8) | 65)
428 #define IPS_COPPIOCCMD (('C'<<8) | 66)
429 #define IPS_NUMCTRLS (('C'<<8) | 68)
430 #define IPS_CTRLINFO (('C'<<8) | 69)
432 /* flashing defines */
433 #define IPS_FW_IMAGE 0x00
434 #define IPS_BIOS_IMAGE 0x01
435 #define IPS_WRITE_FW 0x01
436 #define IPS_WRITE_BIOS 0x02
437 #define IPS_ERASE_BIOS 0x03
438 #define IPS_BIOS_HEADER 0xC0
440 /* time oriented stuff */
441 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
442 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
444 #define IPS_SECS_MIN 60
445 #define IPS_SECS_HOUR 3600
446 #define IPS_SECS_8HOURS 28800
447 #define IPS_SECS_DAY 86400
448 #define IPS_DAYS_NORMAL_YEAR 365
449 #define IPS_DAYS_LEAP_YEAR 366
450 #define IPS_EPOCH_YEAR 1970
455 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
456 static int ips_proc24_info(char *, char **, off_t
, int, int, int);
457 static void ips_select_queue_depth(struct Scsi_Host
*, Scsi_Device
*);
458 static int ips_biosparam(Disk
*disk
, kdev_t dev
, int geom
[]);
460 int ips_proc_info(struct Scsi_Host
*, char *, char **, off_t
, int, int);
461 static int ips_biosparam(struct scsi_device
*sdev
, struct block_device
*bdev
,
462 sector_t capacity
, int geom
[]);
463 int ips_slave_configure(Scsi_Device
*SDptr
);
467 * Raid Command Formats
476 uint16_t sector_count
;
481 } IPS_IO_CMD
, *PIPS_IO_CMD
;
488 uint32_t buffer_addr
;
492 } IPS_LD_CMD
, *PIPS_LD_CMD
;
500 uint32_t buffer_addr
;
502 } IPS_IOCTL_CMD
, *PIPS_IOCTL_CMD
;
520 uint8_t adapter_flag
;
521 } IPS_RESET_CMD
, *PIPS_RESET_CMD
;
528 uint32_t dcdb_address
;
534 } IPS_DCDB_CMD
, *PIPS_DCDB_CMD
;
540 uint8_t source_target
;
546 } IPS_CS_CMD
, *PIPS_CS_CMD
;
558 } IPS_US_CMD
, *PIPS_US_CMD
;
570 } IPS_FC_CMD
, *PIPS_FC_CMD
;
578 uint32_t buffer_addr
;
582 } IPS_STATUS_CMD
, *PIPS_STATUS_CMD
;
590 uint32_t buffer_addr
;
594 } IPS_NVRAM_CMD
, *PIPS_NVRAM_CMD
;
602 uint32_t buffer_addr
;
604 } IPS_VERSION_INFO
, *PIPS_VERSION_INFO
;
615 uint8_t reserved1
[4];
620 } IPS_FFDC_CMD
, *PIPS_FFDC_CMD
;
628 uint32_t buffer_addr
;
629 uint8_t total_packets
;
632 } IPS_FLASHFW_CMD
, *PIPS_FLASHFW_CMD
;
640 uint32_t buffer_addr
;
642 } IPS_FLASHBIOS_CMD
, *PIPS_FLASHBIOS_CMD
;
646 IPS_LD_CMD logical_info
;
647 IPS_IOCTL_CMD ioctl_info
;
649 IPS_CS_CMD config_sync
;
650 IPS_US_CMD unlock_stripe
;
651 IPS_FC_CMD flush_cache
;
652 IPS_STATUS_CMD status
;
655 IPS_FLASHFW_CMD flashfw
;
656 IPS_FLASHBIOS_CMD flashbios
;
657 IPS_VERSION_INFO version_info
;
659 } IPS_HOST_COMMAND
, *PIPS_HOST_COMMAND
;
666 uint32_t sector_count
;
667 } IPS_DRIVE_INFO
, *PIPS_DRIVE_INFO
;
670 uint8_t no_of_log_drive
;
672 IPS_DRIVE_INFO drive_info
[IPS_MAX_LD
];
673 } IPS_LD_INFO
, *PIPS_LD_INFO
;
676 uint8_t device_address
;
677 uint8_t cmd_attribute
;
678 uint16_t transfer_length
;
679 uint32_t buffer_pointer
;
681 uint8_t sense_length
;
684 uint8_t scsi_cdb
[12];
685 uint8_t sense_info
[64];
687 uint8_t reserved2
[3];
688 } IPS_DCDB_TABLE
, *PIPS_DCDB_TABLE
;
691 uint8_t device_address
;
692 uint8_t cmd_attribute
;
694 uint8_t reserved_for_LUN
;
695 uint32_t transfer_length
;
696 uint32_t buffer_pointer
;
698 uint8_t sense_length
;
701 uint8_t scsi_cdb
[16];
702 uint8_t sense_info
[56];
703 } IPS_DCDB_TABLE_TAPE
, *PIPS_DCDB_TABLE_TAPE
;
707 volatile uint8_t reserved
;
708 volatile uint8_t command_id
;
709 volatile uint8_t basic_status
;
710 volatile uint8_t extended_status
;
713 volatile uint32_t value
;
714 } IPS_STATUS
, *PIPS_STATUS
;
717 IPS_STATUS status
[IPS_MAX_CMDS
+ 1];
718 volatile PIPS_STATUS p_status_start
;
719 volatile PIPS_STATUS p_status_end
;
720 volatile PIPS_STATUS p_status_tail
;
721 volatile uint32_t hw_status_start
;
722 volatile uint32_t hw_status_tail
;
723 } IPS_ADAPTER
, *PIPS_ADAPTER
;
726 uint8_t ucLogDriveCount
;
731 uint8_t ucWrongAdrCnt
;
732 uint8_t ucUnidentCnt
;
733 uint8_t ucNVramDevChgCnt
;
734 uint8_t CodeBlkVersion
[8];
735 uint8_t BootBlkVersion
[8];
736 uint32_t ulDriveSize
[IPS_MAX_LD
];
737 uint8_t ucConcurrentCmdCount
;
738 uint8_t ucMaxPhysicalDevices
;
739 uint16_t usFlashRepgmCount
;
740 uint8_t ucDefunctDiskCount
;
741 uint8_t ucRebuildFlag
;
742 uint8_t ucOfflineLogDrvCount
;
743 uint8_t ucCriticalDrvCount
;
744 uint16_t usConfigUpdateCount
;
747 uint16_t usAddrDeadDisk
[IPS_MAX_CHANNELS
* (IPS_MAX_TARGETS
+ 1)];
748 } IPS_ENQ
, *PIPS_ENQ
;
752 uint8_t ucParameters
;
755 uint32_t ulBlockCount
;
756 uint8_t ucDeviceId
[28];
757 } IPS_DEVSTATE
, *PIPS_DEVSTATE
;
763 uint32_t ulStartSect
;
764 uint32_t ulNoOfSects
;
765 } IPS_CHUNK
, *PIPS_CHUNK
;
768 uint16_t ucUserField
;
770 uint8_t ucRaidCacheParam
;
771 uint8_t ucNoOfChunkUnits
;
772 uint8_t ucStripeSize
;
775 uint32_t ulLogDrvSize
;
776 IPS_CHUNK chunk
[IPS_MAX_CHUNKS
];
780 uint8_t board_disc
[8];
781 uint8_t processor
[8];
782 uint8_t ucNoChanType
;
783 uint8_t ucNoHostIntType
;
784 uint8_t ucCompression
;
786 uint32_t ulNvramSize
;
787 } IPS_HARDWARE
, *PIPS_HARDWARE
;
790 uint8_t ucLogDriveCount
;
796 uint8_t time_sign
[8];
799 uint8_t ucRebuildRate
;
801 IPS_HARDWARE hardware_disc
;
802 IPS_LD logical_drive
[IPS_MAX_LD
];
803 IPS_DEVSTATE dev
[IPS_MAX_CHANNELS
][IPS_MAX_TARGETS
+1];
804 uint8_t reserved
[512];
805 } IPS_CONF
, *PIPS_CONF
;
810 uint8_t adapter_slot
;
811 uint16_t adapter_type
;
812 uint8_t ctrl_bios
[8];
813 uint8_t versioning
; /* 1 = Versioning Supported, else 0 */
814 uint8_t version_mismatch
; /* 1 = Versioning MisMatch, else 0 */
816 uint8_t operating_system
;
817 uint8_t driver_high
[4];
818 uint8_t driver_low
[4];
819 uint8_t BiosCompatibilityID
[8];
820 uint8_t ReservedForOS2
[8];
821 uint8_t bios_high
[4]; /* Adapter's Flashed BIOS Version */
823 uint8_t adapter_order
[16]; /* BIOS Telling us the Sort Order */
825 } IPS_NVRAM_P5
, *PIPS_NVRAM_P5
;
827 /*--------------------------------------------------------------------------*/
828 /* Data returned from a GetVersion Command */
829 /*--------------------------------------------------------------------------*/
831 /* SubSystem Parameter[4] */
832 #define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
837 uint8_t bootBlkVersion
[32];
838 uint8_t bootBlkAttributes
[4];
839 uint8_t codeBlkVersion
[32];
840 uint8_t biosVersion
[32];
841 uint8_t biosAttributes
[4];
842 uint8_t compatibilityId
[32];
847 typedef struct _IPS_SUBSYS
{
849 } IPS_SUBSYS
, *PIPS_SUBSYS
;
856 * Inquiry Data Format
860 uint8_t DeviceTypeQualifier
;
862 uint8_t ResponseDataFormat
;
863 uint8_t AdditionalLength
;
867 uint8_t ProductId
[16];
868 uint8_t ProductRevisionLevel
[4];
869 uint8_t Reserved2
; /* Provides NULL terminator to name */
870 } IPS_SCSI_INQ_DATA
, *PIPS_SCSI_INQ_DATA
;
873 * Read Capacity Data Format
881 * Request Sense Data Format
884 uint8_t ResponseCode
;
885 uint8_t SegmentNumber
;
887 uint8_t Information
[4];
888 uint8_t AdditionalLength
;
889 uint8_t CommandSpecific
[4];
890 uint8_t AdditionalSenseCode
;
891 uint8_t AdditionalSenseCodeQual
;
893 uint8_t SenseKeySpecific
[3];
897 * Sense Data Format - Page 3
902 uint16_t TracksPerZone
;
903 uint16_t AltSectorsPerZone
;
904 uint16_t AltTracksPerZone
;
905 uint16_t AltTracksPerVolume
;
906 uint16_t SectorsPerTrack
;
907 uint16_t BytesPerSector
;
910 uint16_t CylinderSkew
;
913 } IPS_SCSI_MODE_PAGE3
;
916 * Sense Data Format - Page 4
921 uint16_t CylindersHigh
;
922 uint8_t CylindersLow
;
924 uint16_t WritePrecompHigh
;
925 uint8_t WritePrecompLow
;
926 uint16_t ReducedWriteCurrentHigh
;
927 uint8_t ReducedWriteCurrentLow
;
929 uint16_t LandingZoneHigh
;
930 uint8_t LandingZoneLow
;
932 uint8_t RotationalOffset
;
934 uint16_t MediumRotationRate
;
935 uint8_t Reserved2
[2];
936 } IPS_SCSI_MODE_PAGE4
;
939 * Sense Data Format - Page 8
946 uint16_t DisPrefetchLen
;
947 uint16_t MinPrefetchLen
;
948 uint16_t MaxPrefetchLen
;
949 uint16_t MaxPrefetchCeiling
;
950 } IPS_SCSI_MODE_PAGE8
;
953 * Sense Data Format - Block Descriptor (DASD)
956 uint32_t NumberOfBlocks
;
958 uint16_t BlockLengthHigh
;
959 uint8_t BlockLengthLow
;
960 } IPS_SCSI_MODE_PAGE_BLKDESC
;
963 * Sense Data Format - Mode Page Header
969 uint8_t BlockDescLength
;
970 } IPS_SCSI_MODE_PAGE_HEADER
;
973 IPS_SCSI_MODE_PAGE_HEADER hdr
;
974 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc
;
977 IPS_SCSI_MODE_PAGE3 pg3
;
978 IPS_SCSI_MODE_PAGE4 pg4
;
979 IPS_SCSI_MODE_PAGE8 pg8
;
981 } IPS_SCSI_MODE_PAGE_DATA
;
984 * Scatter Gather list format
986 typedef struct ips_sglist
{
991 typedef struct ips_enh_sglist
{
1000 IPS_STD_SG_LIST
*std_list
;
1001 IPS_ENH_SG_LIST
*enh_list
;
1004 typedef struct _IPS_INFOSTR
{
1021 typedef struct ips_stat
{
1022 uint32_t residue_len
;
1024 uint8_t padding
[12 - sizeof(void *)];
1030 typedef struct ips_scb_queue
{
1031 struct ips_scb
*head
;
1032 struct ips_scb
*tail
;
1039 typedef struct ips_wait_queue
{
1045 typedef struct ips_copp_wait_item
{
1046 Scsi_Cmnd
*scsi_cmd
;
1047 struct ips_copp_wait_item
*next
;
1048 } ips_copp_wait_item_t
;
1050 typedef struct ips_copp_queue
{
1051 struct ips_copp_wait_item
*head
;
1052 struct ips_copp_wait_item
*tail
;
1056 /* forward decl for host structure */
1060 int (*reset
)(struct ips_ha
*);
1061 int (*issue
)(struct ips_ha
*, struct ips_scb
*);
1062 int (*isinit
)(struct ips_ha
*);
1063 int (*isintr
)(struct ips_ha
*);
1064 int (*init
)(struct ips_ha
*);
1065 int (*erasebios
)(struct ips_ha
*);
1066 int (*programbios
)(struct ips_ha
*, char *, uint32_t, uint32_t);
1067 int (*verifybios
)(struct ips_ha
*, char *, uint32_t, uint32_t);
1068 void (*statinit
)(struct ips_ha
*);
1069 int (*intr
)(struct ips_ha
*);
1070 void (*enableint
)(struct ips_ha
*);
1071 uint32_t (*statupd
)(struct ips_ha
*);
1074 typedef struct ips_ha
{
1075 uint8_t ha_id
[IPS_MAX_CHANNELS
+1];
1076 uint32_t dcdb_active
[IPS_MAX_CHANNELS
];
1077 uint32_t io_addr
; /* Base I/O address */
1078 uint8_t irq
; /* IRQ for adapter */
1079 uint8_t ntargets
; /* Number of targets */
1080 uint8_t nbus
; /* Number of buses */
1081 uint8_t nlun
; /* Number of Luns */
1082 uint16_t ad_type
; /* Adapter type */
1083 uint16_t host_num
; /* Adapter number */
1084 uint32_t max_xfer
; /* Maximum Xfer size */
1085 uint32_t max_cmds
; /* Max concurrent commands */
1086 uint32_t num_ioctl
; /* Number of Ioctls */
1087 ips_stat_t sp
; /* Status packer pointer */
1088 struct ips_scb
*scbs
; /* Array of all CCBS */
1089 struct ips_scb
*scb_freelist
; /* SCB free list */
1090 ips_wait_queue_t scb_waitlist
; /* Pending SCB list */
1091 ips_copp_queue_t copp_waitlist
; /* Pending PT list */
1092 ips_scb_queue_t scb_activelist
; /* Active SCB list */
1093 IPS_IO_CMD
*dummy
; /* dummy command */
1094 IPS_ADAPTER
*adapt
; /* Adapter status area */
1095 IPS_LD_INFO
*logical_drive_info
; /* Adapter Logical Drive Info */
1096 dma_addr_t logical_drive_info_dma_addr
; /* Logical Drive Info DMA Address */
1097 IPS_ENQ
*enq
; /* Adapter Enquiry data */
1098 IPS_CONF
*conf
; /* Adapter config data */
1099 IPS_NVRAM_P5
*nvram
; /* NVRAM page 5 data */
1100 IPS_SUBSYS
*subsys
; /* Subsystem parameters */
1101 char *ioctl_data
; /* IOCTL data area */
1102 uint32_t ioctl_datasize
; /* IOCTL data size */
1103 uint32_t cmd_in_progress
; /* Current command in progress*/
1105 uint8_t waitflag
; /* are we waiting for cmd */
1107 int ioctl_reset
; /* IOCTL Requested Reset Flag */
1108 uint16_t reset_count
; /* number of resets */
1109 time_t last_ffdc
; /* last time we sent ffdc info*/
1110 uint8_t revision_id
; /* Revision level */
1111 uint16_t device_id
; /* PCI device ID */
1112 uint8_t slot_num
; /* PCI Slot Number */
1113 uint16_t subdevice_id
; /* Subsystem device ID */
1114 int ioctl_len
; /* size of ioctl buffer */
1115 dma_addr_t ioctl_busaddr
; /* dma address of ioctl buffer*/
1116 uint8_t bios_version
[8]; /* BIOS Revision */
1117 uint32_t mem_addr
; /* Memory mapped address */
1118 uint32_t io_len
; /* Size of IO Address */
1119 uint32_t mem_len
; /* Size of memory address */
1120 char __iomem
*mem_ptr
; /* Memory mapped Ptr */
1121 char __iomem
*ioremap_ptr
;/* ioremapped memory pointer */
1122 ips_hw_func_t func
; /* hw function pointers */
1123 struct pci_dev
*pcidev
; /* PCI device handle */
1124 char *flash_data
; /* Save Area for flash data */
1125 int flash_len
; /* length of flash buffer */
1126 u32 flash_datasize
; /* Save Area for flash data size */
1127 dma_addr_t flash_busaddr
; /* dma address of flash buffer*/
1128 dma_addr_t enq_busaddr
; /* dma address of enq struct */
1129 uint8_t requires_esl
; /* Requires an EraseStripeLock */
1132 typedef void (*ips_scb_callback
) (ips_ha_t
*, struct ips_scb
*);
1137 typedef struct ips_scb
{
1138 IPS_HOST_COMMAND cmd
;
1139 IPS_DCDB_TABLE dcdb
;
1144 uint32_t scb_busaddr
;
1145 uint32_t old_data_busaddr
; // Obsolete, but kept for old utility compatibility
1147 uint8_t basic_status
;
1148 uint8_t extended_status
;
1155 IPS_SG_LIST sg_list
;
1156 Scsi_Cmnd
*scsi_cmd
;
1157 struct ips_scb
*q_next
;
1158 ips_scb_callback callback
;
1159 uint32_t sg_busaddr
;
1161 dma_addr_t data_busaddr
;
1164 typedef struct ips_scb_pt
{
1165 IPS_HOST_COMMAND cmd
;
1166 IPS_DCDB_TABLE dcdb
;
1171 uint32_t scb_busaddr
;
1172 uint32_t data_busaddr
;
1174 uint8_t basic_status
;
1175 uint8_t extended_status
;
1181 IPS_SG_LIST
*sg_list
;
1182 Scsi_Cmnd
*scsi_cmd
;
1183 struct ips_scb
*q_next
;
1184 ips_scb_callback callback
;
1188 * Passthru Command Format
1196 ips_scb_pt_t CoppCP
;
1198 uint8_t BasicStatus
;
1199 uint8_t ExtendedStatus
;
1200 uint8_t AdapterType
;
1206 /* The Version Information below gets created by SED during the build process. */
1207 /* Do not modify the next line; it's what SED is looking for to do the insert. */
1209 /*************************************************************************
1211 * VERSION.H -- version numbers and copyright notices in various formats
1213 *************************************************************************/
1215 #define IPS_VER_MAJOR 7
1216 #define IPS_VER_MAJOR_STRING "7"
1217 #define IPS_VER_MINOR 10
1218 #define IPS_VER_MINOR_STRING "10"
1219 #define IPS_VER_BUILD 18
1220 #define IPS_VER_BUILD_STRING "18"
1221 #define IPS_VER_STRING "7.10.18"
1222 #define IPS_RELEASE_ID 0x00020000
1223 #define IPS_BUILD_IDENT 731
1224 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1225 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1226 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1227 #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1229 /* Version numbers for various adapters */
1230 #define IPS_VER_SERVERAID1 "2.25.01"
1231 #define IPS_VER_SERVERAID2 "2.88.13"
1232 #define IPS_VER_NAVAJO "2.88.13"
1233 #define IPS_VER_SERVERAID3 "6.10.24"
1234 #define IPS_VER_SERVERAID4H "7.10.11"
1235 #define IPS_VER_SERVERAID4MLx "7.10.18"
1236 #define IPS_VER_SARASOTA "7.10.18"
1237 #define IPS_VER_MARCO "7.10.18"
1238 #define IPS_VER_SEBRING "7.10.18"
1239 #define IPS_VER_KEYWEST "7.10.18"
1241 /* Compatability IDs for various adapters */
1242 #define IPS_COMPAT_UNKNOWN ""
1243 #define IPS_COMPAT_CURRENT "KW710"
1244 #define IPS_COMPAT_SERVERAID1 "2.25.01"
1245 #define IPS_COMPAT_SERVERAID2 "2.88.13"
1246 #define IPS_COMPAT_NAVAJO "2.88.13"
1247 #define IPS_COMPAT_KIOWA "2.88.13"
1248 #define IPS_COMPAT_SERVERAID3H "SB610"
1249 #define IPS_COMPAT_SERVERAID3L "SB610"
1250 #define IPS_COMPAT_SERVERAID4H "KW710"
1251 #define IPS_COMPAT_SERVERAID4M "KW710"
1252 #define IPS_COMPAT_SERVERAID4L "KW710"
1253 #define IPS_COMPAT_SERVERAID4Mx "KW710"
1254 #define IPS_COMPAT_SERVERAID4Lx "KW710"
1255 #define IPS_COMPAT_SARASOTA "KW710"
1256 #define IPS_COMPAT_MARCO "KW710"
1257 #define IPS_COMPAT_SEBRING "KW710"
1258 #define IPS_COMPAT_TAMPA "KW710"
1259 #define IPS_COMPAT_KEYWEST "KW710"
1260 #define IPS_COMPAT_BIOS "KW710"
1262 #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1263 #define IPS_COMPAT_ID_LENGTH 8
1265 #define IPS_DEFINE_COMPAT_TABLE(tablename) \
1266 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1267 IPS_COMPAT_UNKNOWN, \
1268 IPS_COMPAT_SERVERAID1, \
1269 IPS_COMPAT_SERVERAID2, \
1270 IPS_COMPAT_NAVAJO, \
1272 IPS_COMPAT_SERVERAID3H, \
1273 IPS_COMPAT_SERVERAID3L, \
1274 IPS_COMPAT_SERVERAID4H, \
1275 IPS_COMPAT_SERVERAID4M, \
1276 IPS_COMPAT_SERVERAID4L, \
1277 IPS_COMPAT_SERVERAID4Mx, \
1278 IPS_COMPAT_SERVERAID4Lx, \
1279 IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
1280 IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
1282 IPS_COMPAT_SEBRING, \
1284 IPS_COMPAT_KEYWEST \
1289 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1290 * Emacs will notice this stuff at the end of the file and automatically
1291 * adjust the settings for this buffer only. This must remain at the end
1293 * ---------------------------------------------------------------------------
1296 * c-brace-imaginary-offset: 0
1297 * c-brace-offset: -2
1298 * c-argdecl-indent: 2
1299 * c-label-offset: -2
1300 * c-continued-statement-offset: 2
1301 * c-continued-brace-offset: 0
1302 * indent-tabs-mode: nil