arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kdev_t.h>
  40 #include <linux/types.h>
  41 #include <linux/console.h>
  42 #include <linux/sched.h>
  43 #include <linux/pci.h>
  44 #include <linux/ide.h>
  45 #include <linux/ioport.h>
  46 #include <linux/param.h>        /* for HZ */
  47 #include <linux/delay.h>
  48
  49 #include <asm/addrspace.h>
  50 #include <asm/time.h>
  51 #include <asm/bcache.h>
  52 #include <asm/irq.h>
  53 #include <asm/reboot.h>
  54 #include <asm/gdb-stub.h>
  55 #include <asm/jmr3927/jmr3927.h>
  56 #include <asm/mipsregs.h>
  57 #include <asm/traps.h>
  58
  59 /* Tick Timer divider */
  60 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  61 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  62
  63 unsigned char led_state = 0xf;
  64
  65 struct {
  66     struct resource ram0;
  67     struct resource ram1;
  68     struct resource pcimem;
  69     struct resource iob;
  70     struct resource ioc;
  71     struct resource pciio;
  72     struct resource jmy1394;
  73     struct resource rom1;
  74     struct resource rom0;
  75     struct resource sio0;
  76     struct resource sio1;
  77 } jmr3927_resources = {
  78     { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
  79     { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
  80     { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
  81     { "IOB",           0x10000000, 0x13FFFFFF                  },
  82     { "IOC",           0x14000000, 0x14FFFFFF                  },
  83     { "PCIIO",         0x15000000, 0x15FFFFFF                  },
  84     { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
  85     { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
  86     { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
  87     { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
  88     { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
  89 };
  90
  91 /* don't enable - see errata */
  92 int jmr3927_ccfg_toeon = 0;
  93
  94 static inline void do_reset(void)
  95 {
  96 #ifdef CONFIG_TC35815
  97         extern void tc35815_killall(void);
  98         tc35815_killall();
  99 #endif
 100 #if 1   /* Resetting PCI bus */
 101         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 102         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
 103         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
 104         mdelay(1);
 105         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 106 #endif
 107         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
 108 }
 109
 110 static void jmr3927_machine_restart(char *command)
 111 {
 112         cli();
 113         puts("Rebooting...");
 114         do_reset();
 115 }
 116
 117 static void jmr3927_machine_halt(void)
 118 {
 119         puts("JMR-TX3927 halted.\n");
 120         while (1);
 121 }
 122
 123 static void jmr3927_machine_power_off(void)
 124 {
 125         puts("JMR-TX3927 halted. Please turn off the power.\n");
 126         while (1);
 127 }
 128
 129 #define USE_RTC_DS1742
 130 #ifdef USE_RTC_DS1742
 131 extern void rtc_ds1742_init(unsigned long base);
 132 #endif
 133 static void __init jmr3927_time_init(void)
 134 {
 135 #ifdef USE_RTC_DS1742
 136         if (jmr3927_have_nvram()) {
 137                 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
 138         }
 139 #endif
 140 }
 141
 142 unsigned long jmr3927_do_gettimeoffset(void);
 143 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 144
 145 static void __init jmr3927_timer_setup(struct irqaction *irq)
 146 {
 147         do_gettimeoffset = jmr3927_do_gettimeoffset;
 148
 149         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 150         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 151         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 152         jmr3927_tmrptr->tcr =
 153                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 154
 155         setup_irq(JMR3927_IRQ_TICK, irq);
 156 }
 157
 158 #define USECS_PER_JIFFY (1000000/HZ)
 159
 160 unsigned long jmr3927_do_gettimeoffset(void)
 161 {
 162        unsigned long count;
 163        unsigned long res = 0;
 164
 165        /* MUST read TRR before TISR. */
 166        count = jmr3927_tmrptr->trr;
 167
 168        if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
 169                /* timer interrupt is pending.  use Max value. */
 170                res = USECS_PER_JIFFY - 1;
 171        } else {
 172                /* convert to usec */
 173                /* res = count / (JMR3927_TIMER_CLK / 1000000); */
 174                res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
 175
 176                /*
 177                 * Due to possible jiffies inconsistencies, we need to check
 178                 * the result so that we'll get a timer that is monotonic.
 179                 */
 180                if (res >= USECS_PER_JIFFY)
 181                        res = USECS_PER_JIFFY-1;
 182        }
 183
 184        return res;
 185 }
 186
 187
 188 #if defined(CONFIG_BLK_DEV_INITRD)
 189 extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
 190 #endif
 191
 192 //#undef DO_WRITE_THROUGH
 193 #define DO_WRITE_THROUGH
 194 #define DO_ENABLE_CACHE
 195
 196 extern char * __init prom_getcmdline(void);
 197 static void jmr3927_board_init(void);
 198 extern void jmr3927_irq_setup(void);
 199 extern struct resource pci_io_resource;
 200 extern struct resource pci_mem_resource;
 201
 202 void __init jmr3927_setup(void)
 203 {
 204         extern int panic_timeout;
 205         char *argptr;
 206
 207         irq_setup = jmr3927_irq_setup;
 208         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 209
 210         board_time_init = jmr3927_time_init;
 211         board_timer_setup = jmr3927_timer_setup;
 212
 213         _machine_restart = jmr3927_machine_restart;
 214         _machine_halt = jmr3927_machine_halt;
 215         _machine_power_off = jmr3927_machine_power_off;
 216
 217         /*
 218          * IO/MEM resources.
 219          */
 220         ioport_resource.start = pci_io_resource.start;
 221         ioport_resource.end = pci_io_resource.end;
 222         iomem_resource.start = pci_mem_resource.start;
 223         iomem_resource.end = pci_mem_resource.end;
 224
 225         /* Reboot on panic */
 226         panic_timeout = 180;
 227
 228         {
 229                 unsigned int conf;
 230                 conf = read_c0_conf();
 231         }
 232
 233 #if 1
 234         /* cache setup */
 235         {
 236                 unsigned int conf;
 237 #ifdef DO_ENABLE_CACHE
 238                 int mips_ic_disable = 0, mips_dc_disable = 0;
 239 #else
 240                 int mips_ic_disable = 1, mips_dc_disable = 1;
 241 #endif
 242 #ifdef DO_WRITE_THROUGH
 243                 int mips_config_cwfon = 0;
 244                 int mips_config_wbon = 0;
 245 #else
 246                 int mips_config_cwfon = 1;
 247                 int mips_config_wbon = 1;
 248 #endif
 249
 250                 conf = read_c0_conf();
 251                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 252                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 253                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 254                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 255                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 256
 257                 write_c0_conf(conf);
 258                 write_c0_cache(0);
 259         }
 260 #endif
 261
 262         /* initialize board */
 263         jmr3927_board_init();
 264
 265         argptr = prom_getcmdline();
 266
 267         if ((argptr = strstr(argptr, "toeon")) != NULL) {
 268                         jmr3927_ccfg_toeon = 1;
 269         }
 270         argptr = prom_getcmdline();
 271         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 272                 argptr = prom_getcmdline();
 273                 strcat(argptr, " ip=bootp");
 274         }
 275
 276 #ifdef CONFIG_TXX927_SERIAL_CONSOLE
 277         argptr = prom_getcmdline();
 278         if ((argptr = strstr(argptr, "console=")) == NULL) {
 279                 argptr = prom_getcmdline();
 280                 strcat(argptr, " console=ttyS1,115200");
 281         }
 282 #endif
 283 }
 284
 285
 286 static void tx3927_setup(void);
 287
 288 #ifdef CONFIG_PCI
 289 unsigned long mips_pci_io_base;
 290 unsigned long mips_pci_io_size;
 291 unsigned long mips_pci_mem_base;
 292 unsigned long mips_pci_mem_size;
 293 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 294 unsigned long mips_pci_io_pciaddr = 0;
 295 #endif
 296
 297 extern struct rtc_ops *rtc_ops;
 298 extern struct rtc_ops jmr3927_rtc_ops;
 299
 300 static void __init jmr3927_board_init(void)
 301 {
 302         char *argptr;
 303
 304 #ifdef CONFIG_PCI
 305         mips_pci_io_base = JMR3927_PCIIO;
 306         mips_pci_io_size = JMR3927_PCIIO_SIZE;
 307         mips_pci_mem_base = JMR3927_PCIMEM;
 308         mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 309 #endif
 310
 311         tx3927_setup();
 312
 313 #ifdef CONFIG_VT
 314         conswitchp = &dummy_con;
 315 #endif
 316
 317         if (jmr3927_have_isac()) {
 318
 319 #ifdef CONFIG_FB_E1355
 320                 argptr = prom_getcmdline();
 321                 if ((argptr = strstr(argptr, "video=")) == NULL) {
 322                         argptr = prom_getcmdline();
 323                         strcat(argptr, " video=e1355fb:crt16h");
 324                 }
 325 #endif
 326
 327 #ifdef CONFIG_BLK_DEV_IDE
 328                 /* overrides PCI-IDE */
 329 #endif
 330         }
 331 #ifdef USE_RTC_DS1742
 332         if (jmr3927_have_nvram()) {
 333                 rtc_ops = &jmr3927_rtc_ops;
 334         }
 335 #endif
 336
 337         /* SIO0 DTR on */
 338         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 339
 340         jmr3927_led_set(0);
 341
 342
 343         if (jmr3927_have_isac())
 344                 jmr3927_io_led_set(0);
 345         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 346                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 347                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 348                jmr3927_dipsw1(), jmr3927_dipsw2(),
 349                jmr3927_dipsw3(), jmr3927_dipsw4());
 350         if (jmr3927_have_isac())
 351                 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
 352                        jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 353                        jmr3927_io_dipsw());
 354 }
 355
 356 static void __init tx3927_setup(void)
 357 {
 358         int i;
 359
 360         /* SDRAMC are configured by PROM */
 361
 362         /* ROMC */
 363         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 364         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 365         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 366         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 367
 368         /* CCFG */
 369         /* enable Timeout BusError */
 370         if (jmr3927_ccfg_toeon)
 371                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 372
 373         /* clear BusErrorOnWrite flag */
 374         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 375         /* Disable PCI snoop */
 376         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 377
 378 #ifdef DO_WRITE_THROUGH
 379         /* Enable PCI SNOOP - with write through only */
 380         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 381 #endif
 382
 383         /* Pin selection */
 384         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 385         tx3927_ccfgptr->pcfg |=
 386                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 387                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 388
 389         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 390                tx3927_ccfgptr->crir,
 391                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 392
 393         /* IRC */
 394         /* disable interrupt control */
 395         tx3927_ircptr->cer = 0;
 396         /* mask all IRC interrupts */
 397         tx3927_ircptr->imr = 0;
 398         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 399                 tx3927_ircptr->ilr[i] = 0;
 400         }
 401         /* setup IRC interrupt mode (Low Active) */
 402         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 403                 tx3927_ircptr->cr[i] = 0;
 404         }
 405
 406         /* TMR */
 407         /* disable all timers */
 408         for (i = 0; i < TX3927_NR_TMR; i++) {
 409                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 410                 tx3927_tmrptr(i)->tisr = 0;
 411                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 412                 tx3927_tmrptr(i)->itmr = 0;
 413                 tx3927_tmrptr(i)->ccdr = 0;
 414                 tx3927_tmrptr(i)->pgmr = 0;
 415         }
 416
 417         /* DMA */
 418         tx3927_dmaptr->mcr = 0;
 419         for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
 420                 /* reset channel */
 421                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 422                 tx3927_dmaptr->ch[i].ccr = 0;
 423         }
 424         /* enable DMA */
 425 #ifdef __BIG_ENDIAN
 426         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 427 #else
 428         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 429 #endif
 430
 431 #ifdef CONFIG_PCI
 432         /* PCIC */
 433         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 434                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 435                tx3927_pcicptr->rid);
 436         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 437                 printk("External\n");
 438                 /* XXX */
 439         } else {
 440                 printk("Internal\n");
 441
 442                 /* Reset PCI Bus */
 443                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 444                 udelay(100);
 445                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 446                                     JMR3927_IOC_RESET_ADDR);
 447                 udelay(100);
 448                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 449
 450
 451                 /* Disable External PCI Config. Access */
 452                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 453 #ifdef __BIG_ENDIAN
 454                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 455                         TX3927_PCIC_LBC_TIBSE |
 456                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 457 #endif
 458                 /* LB->PCI mappings */
 459                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 460                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 461                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 462                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 463                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 464                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 465                 /* PCI->LB mappings */
 466                 tx3927_pcicptr->iobas = 0xffffffff;
 467                 tx3927_pcicptr->ioba = 0;
 468                 tx3927_pcicptr->tlbioma = 0;
 469                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 470                 tx3927_pcicptr->mba = 0;
 471                 tx3927_pcicptr->tlbmma = 0;
 472 #ifndef JMR3927_INIT_INDIRECT_PCI
 473                 /* Enable Direct mapping Address Space Decoder */
 474                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 475 #endif
 476
 477                 /* Clear All Local Bus Status */
 478                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 479                 /* Enable All Local Bus Interrupts */
 480                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 481                 /* Clear All PCI Status Error */
 482                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 483                 /* Enable All PCI Status Error Interrupts */
 484                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 485
 486                 /* PCIC Int => IRC IRQ10 */
 487                 tx3927_pcicptr->il = TX3927_IR_PCI;
 488 #if 1
 489                 /* Target Control (per errata) */
 490                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 491 #endif
 492
 493                 /* Enable Bus Arbiter */
 494 #if 0
 495                 tx3927_pcicptr->req_trace = 0x73737373;
 496 #endif
 497                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 498
 499                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 500                         PCI_COMMAND_MEMORY |
 501 #if 1
 502                         PCI_COMMAND_IO |
 503 #endif
 504                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 505         }
 506 #endif /* CONFIG_PCI */
 507
 508         /* PIO */
 509         /* PIO[15:12] connected to LEDs */
 510         tx3927_pioptr->dir = 0x0000f000;
 511         tx3927_pioptr->maskcpu = 0;
 512         tx3927_pioptr->maskext = 0;
 513         {
 514                 unsigned int conf;
 515
 516         conf = read_c0_conf();
 517                if (!(conf & TX39_CONF_ICE))
 518                        printk("TX3927 I-Cache disabled.\n");
 519                if (!(conf & TX39_CONF_DCE))
 520                        printk("TX3927 D-Cache disabled.\n");
 521                else if (!(conf & TX39_CONF_WBON))
 522                        printk("TX3927 D-Cache WriteThrough.\n");
 523                else if (!(conf & TX39_CONF_CWFON))
 524                        printk("TX3927 D-Cache WriteBack.\n");
 525                else
 526                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 527         }
 528 }