drivers/media/dvb/frontends/alps_bsrv2.c

   1 /*
   2     Driver for Alps BSRV2 QPSK Frontend
   3
   4     Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28
  29 #include "dvb_frontend.h"
  30
  31 static int debug = 0;
  32 #define dprintk if (debug) printk
  33
  34
  35 static struct dvb_frontend_info bsrv2_info = {
  36         .name                   = "Alps BSRV2",
  37         .type                   = FE_QPSK,
  38         .frequency_min          = 950000,
  39         .frequency_max          = 2150000,
  40         .frequency_stepsize     = 250,           /* kHz for QPSK frontends */
  41         .frequency_tolerance    = 29500,
  42         .symbol_rate_min        = 1000000,
  43         .symbol_rate_max        = 45000000,
  44 /*     . symbol_rate_tolerance  =       ???,*/
  45         .notifier_delay         = 50,                /* 1/20 s */
  46         .caps = FE_CAN_INVERSION_AUTO |
  47                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  48                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  49                 FE_CAN_QPSK
  50 };
  51
  52
  53
  54 static u8 init_1893_tab [] = {
  55         0x01, 0xA4, 0x35, 0x81, 0x2A, 0x0d, 0x55, 0xC4,
  56         0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7F, 0x00,
  57         0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  58         0x80, 0x00, 0x31, 0xb0, 0x14, 0x00, 0xDC, 0x00,
  59         0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  60         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  61         0x00, 0x55, 0x00, 0x00, 0x7f, 0x00
  62 };
  63
  64
  65 static u8 init_1893_wtab[] =
  66 {
  67         1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
  68         0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1,
  69         1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
  70         1,1,1,0,1,1
  71 };
  72
  73
  74 static int ves1893_writereg (struct dvb_i2c_bus *i2c, u8 reg, u8 data)
  75 {
  76         u8 buf [] = { 0x00, reg, data };
  77         struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 3 };
  78         int err;
  79
  80         if ((err = i2c->xfer (i2c, &msg, 1)) != 1) {
  81                 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __FUNCTION__, err, reg, data);
  82                 return -EREMOTEIO;
  83         }
  84
  85         return 0;
  86 }
  87
  88
  89 static u8 ves1893_readreg (struct dvb_i2c_bus *i2c, u8 reg)
  90 {
  91         int ret;
  92         u8 b0 [] = { 0x00, reg };
  93         u8 b1 [] = { 0 };
  94         struct i2c_msg msg [] = { { .addr = 0x08, .flags = 0, .buf = b0, .len = 2 },
  95                            { .addr = 0x08, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
  96
  97         ret = i2c->xfer (i2c, msg, 2);
  98
  99         if (ret != 2)
 100                 dprintk("%s: readreg error (ret == %i)\n", __FUNCTION__, ret);
 101
 102         return b1[0];
 103 }
 104
 105
 106 static int sp5659_write (struct dvb_i2c_bus *i2c, u8 data [4])
 107 {
 108         int ret;
 109         struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = 4 };
 110
 111         ret = i2c->xfer (i2c, &msg, 1);
 112
 113         if (ret != 1)
 114                 printk("%s: i/o error (ret == %i)\n", __FUNCTION__, ret);
 115
 116         return (ret != 1) ? -1 : 0;
 117 }
 118
 119
 120
 121 /**
 122  *   set up the downconverter frequency divisor for a
 123  *   reference clock comparision frequency of 125 kHz.
 124  */
 125 static int sp5659_set_tv_freq (struct dvb_i2c_bus *i2c, u32 freq, u8 pwr)
 126 {
 127         u32 div = (freq + 479500) / 125;
 128         u8 buf [4] = { (div >> 8) & 0x7f, div & 0xff, 0x95, (pwr << 5) | 0x30 };
 129
 130         return sp5659_write (i2c, buf);
 131 }
 132
 133
 134 static int ves1893_init (struct dvb_i2c_bus *i2c)
 135 {
 136         int i;
 137
 138         dprintk("%s: init chip\n", __FUNCTION__);
 139
 140         for (i=0; i<54; i++)
 141                 if (init_1893_wtab[i])
 142                         ves1893_writereg (i2c, i, init_1893_tab[i]);
 143
 144         return 0;
 145 }
 146
 147
 148 static int ves1893_clr_bit (struct dvb_i2c_bus *i2c)
 149 {
 150         ves1893_writereg (i2c, 0, init_1893_tab[0] & 0xfe);
 151         ves1893_writereg (i2c, 0, init_1893_tab[0]);
 152         ves1893_writereg (i2c, 3, 0x00);
 153         return ves1893_writereg (i2c, 3, init_1893_tab[3]);
 154 }
 155
 156
 157 static int ves1893_set_inversion (struct dvb_i2c_bus *i2c, fe_spectral_inversion_t inversion)
 158 {
 159         u8 val;
 160
 161         /*
 162          * inversion on/off are interchanged because i and q seem to
 163          * be swapped on the hardware
 164          */
 165
 166         switch (inversion) {
 167         case INVERSION_OFF:
 168                 val = 0xc0;
 169                 break;
 170         case INVERSION_ON:
 171                 val = 0x80;
 172                 break;
 173         case INVERSION_AUTO:
 174                 val = 0x00;
 175                 break;
 176         default:
 177                 return -EINVAL;
 178         }
 179
 180         /* needs to be saved for FE_GET_FRONTEND */
 181         init_1893_tab[0x0c] = (init_1893_tab[0x0c] & 0x3f) | val;
 182
 183         return ves1893_writereg (i2c, 0x0c, init_1893_tab[0x0c]);
 184 }
 185
 186
 187 static int ves1893_set_fec (struct dvb_i2c_bus *i2c, fe_code_rate_t fec)
 188 {
 189         if (fec == FEC_AUTO)
 190                 return ves1893_writereg (i2c, 0x0d, 0x08);
 191         else if (fec < FEC_1_2 || fec > FEC_8_9)
 192                 return -EINVAL;
 193         else
 194                 return ves1893_writereg (i2c, 0x0d, fec - FEC_1_2);
 195 }
 196
 197
 198 static fe_code_rate_t ves1893_get_fec (struct dvb_i2c_bus *i2c)
 199 {
 200         return FEC_1_2 + ((ves1893_readreg (i2c, 0x0d) >> 4) & 0x7);
 201 }
 202
 203
 204 static int ves1893_set_symbolrate (struct dvb_i2c_bus *i2c, u32 srate)
 205 {
 206         u32 BDR;
 207         u32 ratio;
 208         u8  ADCONF, FCONF, FNR;
 209         u32 BDRI;
 210         u32 tmp;
 211
 212         dprintk("%s: srate == %ud\n", __FUNCTION__, (unsigned int) srate);
 213
 214         if (srate > 90100000UL/2)
 215                 srate = 90100000UL/2;
 216
 217         if (srate < 500000)
 218                 srate = 500000;
 219
 220 #define MUL (1UL<<26)
 221 #define FIN (90106000UL>>4)
 222
 223         tmp = srate << 6;
 224         ratio = tmp / FIN;
 225
 226         tmp = (tmp % FIN) << 8;
 227         ratio = (ratio << 8) + tmp / FIN;
 228
 229         tmp = (tmp % FIN) << 8;
 230         ratio = (ratio << 8) + tmp / FIN;
 231
 232         FNR = 0xff;
 233
 234         if (ratio < MUL/3)           FNR = 0;
 235         if (ratio < (MUL*11)/50)     FNR = 1;
 236         if (ratio < MUL/6)           FNR = 2;
 237         if (ratio < MUL/9)           FNR = 3;
 238         if (ratio < MUL/12)          FNR = 4;
 239         if (ratio < (MUL*11)/200)    FNR = 5;
 240         if (ratio < MUL/24)          FNR = 6;
 241         if (ratio < (MUL*27)/1000)   FNR = 7;
 242         if (ratio < MUL/48)          FNR = 8;
 243         if (ratio < (MUL*137)/10000) FNR = 9;
 244
 245         if (FNR == 0xff) {
 246                 ADCONF = 0x89;
 247                 FCONF  = 0x80;
 248                 FNR     = 0;
 249         } else {
 250                 ADCONF = 0x81;
 251                 FCONF  = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5);
 252         }
 253
 254         BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1;
 255         BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1;
 256
 257         dprintk("FNR= %d\n", FNR);
 258         dprintk("ratio= %08x\n", (unsigned int) ratio);
 259         dprintk("BDR= %08x\n", (unsigned int) BDR);
 260         dprintk("BDRI= %02x\n", (unsigned int) BDRI);
 261
 262         if (BDRI > 0xff)
 263                 BDRI = 0xff;
 264
 265         ves1893_writereg (i2c, 0x06, 0xff & BDR);
 266         ves1893_writereg (i2c, 0x07, 0xff & (BDR >> 8));
 267         ves1893_writereg (i2c, 0x08, 0x0f & (BDR >> 16));
 268
 269         ves1893_writereg (i2c, 0x09, BDRI);
 270         ves1893_writereg (i2c, 0x20, ADCONF);
 271         ves1893_writereg (i2c, 0x21, FCONF);
 272
 273         if (srate < 6000000)
 274                 ves1893_writereg (i2c, 0x05, init_1893_tab[0x05] | 0x80);
 275         else
 276                 ves1893_writereg (i2c, 0x05, init_1893_tab[0x05] & 0x7f);
 277
 278         ves1893_writereg (i2c, 0x00, 0x00);
 279         ves1893_writereg (i2c, 0x00, 0x01);
 280
 281         ves1893_clr_bit (i2c);
 282
 283         return 0;
 284 }
 285
 286
 287 static int ves1893_set_voltage (struct dvb_i2c_bus *i2c, fe_sec_voltage_t voltage)
 288 {
 289         switch (voltage) {
 290         case SEC_VOLTAGE_13:
 291                 return ves1893_writereg (i2c, 0x1f, 0x20);
 292         case SEC_VOLTAGE_18:
 293                 return ves1893_writereg (i2c, 0x1f, 0x30);
 294         case SEC_VOLTAGE_OFF:
 295                 return ves1893_writereg (i2c, 0x1f, 0x00);
 296         default:
 297                 return -EINVAL;
 298         }
 299 }
 300
 301
 302 static int bsrv2_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg)
 303 {
 304         struct dvb_i2c_bus *i2c = fe->i2c;
 305
 306         switch (cmd) {
 307         case FE_GET_INFO:
 308                 memcpy (arg, &bsrv2_info, sizeof(struct dvb_frontend_info));
 309                 break;
 310
 311         case FE_READ_STATUS:
 312         {
 313                 fe_status_t *status = arg;
 314                 u8 sync = ves1893_readreg (i2c, 0x0e);
 315
 316                 *status = 0;
 317
 318                 if (sync & 1)
 319                         *status |= FE_HAS_SIGNAL;
 320
 321                 if (sync & 2)
 322                         *status |= FE_HAS_CARRIER;
 323
 324                 if (sync & 4)
 325                         *status |= FE_HAS_VITERBI;
 326
 327                 if (sync & 8)
 328                         *status |= FE_HAS_SYNC;
 329
 330                 if ((sync & 0x1f) == 0x1f)
 331                         *status |= FE_HAS_LOCK;
 332
 333                 break;
 334         }
 335
 336         case FE_READ_BER:
 337         {
 338                 u32 *ber = (u32 *) arg;
 339
 340                 *ber = ves1893_readreg (i2c, 0x15);
 341                 *ber |= (ves1893_readreg (i2c, 0x16) << 8);
 342                 *ber |= ((ves1893_readreg (i2c, 0x17) & 0x0f) << 16);
 343                 *ber *= 10;
 344                 break;
 345         }
 346
 347         case FE_READ_SIGNAL_STRENGTH:
 348         {
 349                 u8 signal = ~ves1893_readreg (i2c, 0x0b);
 350                 *((u16*) arg) = (signal << 8) | signal;
 351                 break;
 352         }
 353
 354         case FE_READ_SNR:
 355         {
 356                 u8 snr = ~ves1893_readreg (i2c, 0x1c);
 357                 *(u16*) arg = (snr << 8) | snr;
 358                 break;
 359         }
 360
 361         case FE_READ_UNCORRECTED_BLOCKS:
 362         {
 363                 *(u32*) arg = ves1893_readreg (i2c, 0x18) & 0x7f;
 364
 365                 if (*(u32*) arg == 0x7f)
 366                         *(u32*) arg = 0xffffffff;   /* counter overflow... */
 367
 368                 ves1893_writereg (i2c, 0x18, 0x00);  /* reset the counter */
 369                 ves1893_writereg (i2c, 0x18, 0x80);  /* dto. */
 370                 break;
 371         }
 372
 373         case FE_SET_FRONTEND:
 374         {
 375                 struct dvb_frontend_parameters *p = arg;
 376
 377                 sp5659_set_tv_freq (i2c, p->frequency, 0);
 378                 ves1893_set_inversion (i2c, p->inversion);
 379                 ves1893_set_fec (i2c, p->u.qpsk.fec_inner);
 380 //              sp5659_set_tv_freq (i2c, p->frequency, 0);
 381                 ves1893_set_symbolrate (i2c, p->u.qpsk.symbol_rate);
 382                 break;
 383         }
 384
 385         case FE_GET_FRONTEND:
 386         {
 387                 struct dvb_frontend_parameters *p = arg;
 388                 int afc;
 389
 390                 afc = ((int)((char)(ves1893_readreg (i2c, 0x0a) << 1)))/2;
 391                 afc = (afc * (int)(p->u.qpsk.symbol_rate/1000/8))/16;
 392
 393                 p->frequency -= afc;
 394
 395                 /*
 396                  * inversion indicator is only valid
 397                  * if auto inversion was used
 398                  */
 399                 if (!(init_1893_tab[0x0c] & 0x80))
 400                 p->inversion = (ves1893_readreg (i2c, 0x0f) & 2) ?
 401                                         INVERSION_OFF : INVERSION_ON;
 402                 p->u.qpsk.fec_inner = ves1893_get_fec (i2c);
 403         /*  XXX FIXME: timing offset !! */
 404                 break;
 405         }
 406
 407         case FE_SLEEP:
 408                 ves1893_writereg (i2c, 0x1f, 0x00);    /*  LNB power off  */
 409                 return ves1893_writereg (i2c, 0x00, 0x08);
 410
 411         case FE_INIT:
 412                 return ves1893_init (i2c);
 413
 414         case FE_RESET:
 415                 return ves1893_clr_bit (i2c);
 416
 417         case FE_SET_TONE:
 418                 return -EOPNOTSUPP;  /* the ves1893 can generate the 22k */
 419                                      /* let's implement this when we have */
 420                                      /* a box that uses the 22K_0 pin... */
 421         case FE_SET_VOLTAGE:
 422                 return ves1893_set_voltage (i2c, (fe_sec_voltage_t) arg);
 423
 424         default:
 425                 return -EOPNOTSUPP;
 426         };
 427
 428         return 0;
 429 }
 430
 431
 432 static int bsrv2_attach (struct dvb_i2c_bus *i2c)
 433 {
 434         if ((ves1893_readreg (i2c, 0x1e) & 0xf0) != 0xd0)
 435                 return -ENODEV;
 436
 437         dvb_register_frontend (bsrv2_ioctl, i2c, NULL, &bsrv2_info);
 438
 439         return 0;
 440 }
 441
 442
 443 static void bsrv2_detach (struct dvb_i2c_bus *i2c)
 444 {
 445         dvb_unregister_frontend (bsrv2_ioctl, i2c);
 446 }
 447
 448
 449 static int __init init_bsrv2 (void)
 450 {
 451         return dvb_register_i2c_device (THIS_MODULE, bsrv2_attach, bsrv2_detach);
 452 }
 453
 454
 455 static void __exit exit_bsrv2 (void)
 456 {
 457         dvb_unregister_i2c_device (bsrv2_attach);
 458 }
 459
 460
 461 module_init(init_bsrv2);
 462 module_exit(exit_bsrv2);
 463
 464
 465 MODULE_DESCRIPTION("BSRV2 DVB-S Frontend");
 466 MODULE_AUTHOR("Ralph Metzler");
 467 MODULE_LICENSE("GPL");
 468 MODULE_PARM(debug,"i");
 469