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[PATCH] DVB core update
[linux-2.6/history.git] / drivers / net / sb1250-mac.c
blob3e5a78e2f30b584bcbd697515da426f7b3f66d50
1 /*
2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19 /*
20 This driver is designed for the Broadcom SiByte SOC built-in
21 Ethernet controllers.
22
23 Written by Mitch Lichtenberg at Broadcom Corp.
24 */
25
26
27
28 #define CONFIG_SBMAC_COALESCE
29
30 /* A few user-configurable values.
31 These may be modified when a driver module is loaded. */
32
33 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
34 static int noisy_mii = 1; /* mii status msgs */
35
36 /* Used to pass the media type, etc.
37 Both 'options[]' and 'full_duplex[]' should exist for driver
38 interoperability.
39 The media type is usually passed in 'options[]'.
40 */
41
42 #define MAX_UNITS 3 /* More are supported, limit only on options */
43 #ifdef MODULE
44 static int options[MAX_UNITS] = {-1, -1, -1};
45 static int full_duplex[MAX_UNITS] = {-1, -1, -1};
46 #endif
47
48 #ifdef CONFIG_SBMAC_COALESCE
49 static int int_pktcnt = 0;
50 static int int_timeout = 0;
51 #endif
52
53 /* Operational parameters that usually are not changed. */
54
55 /* Time in jiffies before concluding the transmitter is hung. */
56 #define TX_TIMEOUT (2*HZ)
57
58 #if !defined(__OPTIMIZE__) || !defined(__KERNEL__)
59 #warning You must compile this file with the correct options!
60 #warning See the last lines of the source file.
61 #error You must compile this driver with "-O".
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/timer.h>
68 #include <linux/errno.h>
69 #include <linux/ioport.h>
70 #include <linux/slab.h>
71 #include <linux/interrupt.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/init.h>
76 #include <linux/config.h>
77 #include <asm/processor.h> /* Processor type for cache alignment. */
78 #include <asm/bitops.h>
79 #include <asm/io.h>
80 #include <asm/cache.h>
81
82 /* This is only here until the firmware is ready. In that case,
83 the firmware leaves the ethernet address in the register for us. */
84 #ifdef CONFIG_SIBYTE_STANDALONE
85 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
86 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
87 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
88 #endif
89
90
91 /* These identify the driver base version and may not be removed. */
92 #if 0
93 static char version1[] __devinitdata =
94 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
95 #endif
96
97
98
99 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
100 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
101 MODULE_PARM(debug, "i");
102 MODULE_PARM(noisy_mii, "i");
103 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
104 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
105
106 MODULE_PARM(int_pktcnt, "i");
107 MODULE_PARM(int_timeout, "i");
108
109 #include <asm/sibyte/sb1250.h>
110 #include <asm/sibyte/sb1250_defs.h>
111 #include <asm/sibyte/sb1250_regs.h>
112 #include <asm/sibyte/sb1250_mac.h>
113 #include <asm/sibyte/sb1250_dma.h>
114 #include <asm/sibyte/sb1250_int.h>
115 #include <asm/sibyte/sb1250_scd.h>
116 #include <asm/sibyte/64bit.h>
117
118
119 /**********************************************************************
120 * Simple types
121 ********************************************************************* */
122
123
124 typedef unsigned long sbmac_port_t;
125
126 typedef enum { sbmac_speed_auto, sbmac_speed_10,
127 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
128
129 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
130 sbmac_duplex_full } sbmac_duplex_t;
131
132 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
133 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
134
135 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
136 sbmac_state_broken } sbmac_state_t;
137
138
139 /**********************************************************************
140 * Macros
141 ********************************************************************* */
142
143
144 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
145 (d)->sbdma_dscrtable : (d)->f+1)
146
147
148 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
149
150 #define SBMAC_READCSR(t) in64((unsigned long)t)
151 #define SBMAC_WRITECSR(t,v) out64(v, (unsigned long)t)
152
153
154 #define SBMAC_MAX_TXDESCR 32
155 #define SBMAC_MAX_RXDESCR 32
156
157 #define ETHER_ALIGN 2
158 #define ETHER_ADDR_LEN 6
159 #define ENET_PACKET_SIZE 1518
160 /*#define ENET_PACKET_SIZE 9216 */
161
162 /**********************************************************************
163 * DMA Descriptor structure
164 ********************************************************************* */
165
166 typedef struct sbdmadscr_s {
167 uint64_t dscr_a;
168 uint64_t dscr_b;
169 } sbdmadscr_t;
170
171 typedef unsigned long paddr_t;
172
173 /**********************************************************************
174 * DMA Controller structure
175 ********************************************************************* */
176
177 typedef struct sbmacdma_s {
178
179 /*
180 * This stuff is used to identify the channel and the registers
181 * associated with it.
182 */
183
184 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
185 int sbdma_channel; /* channel number */
186 int sbdma_txdir; /* direction (1=transmit) */
187 int sbdma_maxdescr; /* total # of descriptors in ring */
188 #ifdef CONFIG_SBMAC_COALESCE
189 int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/
190 int sbdma_int_timeout; /* # usec rx/tx interrupt */
191 #endif
192
193 sbmac_port_t sbdma_config0; /* DMA config register 0 */
194 sbmac_port_t sbdma_config1; /* DMA config register 1 */
195 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */
196 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */
197 sbmac_port_t sbdma_curdscr; /* current descriptor address */
198
199 /*
200 * This stuff is for maintenance of the ring
201 */
202
203 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
204 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
205
206 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
207
208 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
209 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
210 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
211 } sbmacdma_t;
212
213
214 /**********************************************************************
215 * Ethernet softc structure
216 ********************************************************************* */
217
218 struct sbmac_softc {
219
220 /*
221 * Linux-specific things
222 */
223
224 struct net_device *sbm_dev; /* pointer to linux device */
225 spinlock_t sbm_lock; /* spin lock */
226 struct timer_list sbm_timer; /* for monitoring MII */
227 struct net_device_stats sbm_stats;
228 int sbm_devflags; /* current device flags */
229
230 int sbm_phy_oldbmsr;
231 int sbm_phy_oldanlpar;
232 int sbm_phy_oldk1stsr;
233 int sbm_phy_oldlinkstat;
234 int sbm_buffersize;
235
236 unsigned char sbm_phys[2];
237
238 /*
239 * Controller-specific things
240 */
241
242 unsigned long sbm_base; /* MAC's base address */
243 sbmac_state_t sbm_state; /* current state */
244
245 sbmac_port_t sbm_macenable; /* MAC Enable Register */
246 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */
247 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */
248 sbmac_port_t sbm_framecfg; /* Frame configuration register */
249 sbmac_port_t sbm_rxfilter; /* receive filter register */
250 sbmac_port_t sbm_isr; /* Interrupt status register */
251 sbmac_port_t sbm_imr; /* Interrupt mask register */
252 sbmac_port_t sbm_mdio; /* MDIO register */
253
254 sbmac_speed_t sbm_speed; /* current speed */
255 sbmac_duplex_t sbm_duplex; /* current duplex */
256 sbmac_fc_t sbm_fc; /* current flow control setting */
257
258 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
259
260 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
261 sbmacdma_t sbm_rxdma;
262 int rx_hw_checksum;
263 int sbe_idx;
264 };
265
266
267 /**********************************************************************
268 * Externs
269 ********************************************************************* */
270
271 /**********************************************************************
272 * Prototypes
273 ********************************************************************* */
274
275 static void sbdma_initctx(sbmacdma_t *d,
276 struct sbmac_softc *s,
277 int chan,
278 int txrx,
279 int maxdescr);
280 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
281 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
282 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
283 static void sbdma_emptyring(sbmacdma_t *d);
284 static void sbdma_fillring(sbmacdma_t *d);
285 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
286 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
287 static int sbmac_initctx(struct sbmac_softc *s);
288 static void sbmac_channel_start(struct sbmac_softc *s);
289 static void sbmac_channel_stop(struct sbmac_softc *s);
290 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
291 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
292 static uint64_t sbmac_addr2reg(unsigned char *ptr);
293 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
294 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
295 static void sbmac_setmulti(struct sbmac_softc *sc);
296 static int sbmac_init(struct net_device *dev, int idx);
297 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
298 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
299
300 static int sbmac_open(struct net_device *dev);
301 static void sbmac_timer(unsigned long data);
302 static void sbmac_tx_timeout (struct net_device *dev);
303 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
304 static void sbmac_set_rx_mode(struct net_device *dev);
305 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
306 static int sbmac_close(struct net_device *dev);
307 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
308
309 static void sbmac_mii_sync(struct sbmac_softc *s);
310 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
311 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
312 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
313 unsigned int regval);
314
315
316 /**********************************************************************
317 * Globals
318 ********************************************************************* */
319
320 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
321
322
323 /**********************************************************************
324 * MDIO constants
325 ********************************************************************* */
326
327 #define MII_COMMAND_START 0x01
328 #define MII_COMMAND_READ 0x02
329 #define MII_COMMAND_WRITE 0x01
330 #define MII_COMMAND_ACK 0x02
331
332 #define BMCR_RESET 0x8000
333 #define BMCR_LOOPBACK 0x4000
334 #define BMCR_SPEED0 0x2000
335 #define BMCR_ANENABLE 0x1000
336 #define BMCR_POWERDOWN 0x0800
337 #define BMCR_ISOLATE 0x0400
338 #define BMCR_RESTARTAN 0x0200
339 #define BMCR_DUPLEX 0x0100
340 #define BMCR_COLTEST 0x0080
341 #define BMCR_SPEED1 0x0040
342 #define BMCR_SPEED1000 BMCR_SPEED1
343 #define BMCR_SPEED100 BMCR_SPEED0
344 #define BMCR_SPEED10 0
345
346 #define BMSR_100BT4 0x8000
347 #define BMSR_100BT_FDX 0x4000
348 #define BMSR_100BT_HDX 0x2000
349 #define BMSR_10BT_FDX 0x1000
350 #define BMSR_10BT_HDX 0x0800
351 #define BMSR_100BT2_FDX 0x0400
352 #define BMSR_100BT2_HDX 0x0200
353 #define BMSR_1000BT_XSR 0x0100
354 #define BMSR_PRESUP 0x0040
355 #define BMSR_ANCOMPLT 0x0020
356 #define BMSR_REMFAULT 0x0010
357 #define BMSR_AUTONEG 0x0008
358 #define BMSR_LINKSTAT 0x0004
359 #define BMSR_JABDETECT 0x0002
360 #define BMSR_EXTCAPAB 0x0001
361
362 #define PHYIDR1 0x2000
363 #define PHYIDR2 0x5C60
364
365 #define ANAR_NP 0x8000
366 #define ANAR_RF 0x2000
367 #define ANAR_ASYPAUSE 0x0800
368 #define ANAR_PAUSE 0x0400
369 #define ANAR_T4 0x0200
370 #define ANAR_TXFD 0x0100
371 #define ANAR_TXHD 0x0080
372 #define ANAR_10FD 0x0040
373 #define ANAR_10HD 0x0020
374 #define ANAR_PSB 0x0001
375
376 #define ANLPAR_NP 0x8000
377 #define ANLPAR_ACK 0x4000
378 #define ANLPAR_RF 0x2000
379 #define ANLPAR_ASYPAUSE 0x0800
380 #define ANLPAR_PAUSE 0x0400
381 #define ANLPAR_T4 0x0200
382 #define ANLPAR_TXFD 0x0100
383 #define ANLPAR_TXHD 0x0080
384 #define ANLPAR_10FD 0x0040
385 #define ANLPAR_10HD 0x0020
386 #define ANLPAR_PSB 0x0001 /* 802.3 */
387
388 #define ANER_PDF 0x0010
389 #define ANER_LPNPABLE 0x0008
390 #define ANER_NPABLE 0x0004
391 #define ANER_PAGERX 0x0002
392 #define ANER_LPANABLE 0x0001
393
394 #define ANNPTR_NP 0x8000
395 #define ANNPTR_MP 0x2000
396 #define ANNPTR_ACK2 0x1000
397 #define ANNPTR_TOGTX 0x0800
398 #define ANNPTR_CODE 0x0008
399
400 #define ANNPRR_NP 0x8000
401 #define ANNPRR_MP 0x2000
402 #define ANNPRR_ACK3 0x1000
403 #define ANNPRR_TOGTX 0x0800
404 #define ANNPRR_CODE 0x0008
405
406 #define K1TCR_TESTMODE 0x0000
407 #define K1TCR_MSMCE 0x1000
408 #define K1TCR_MSCV 0x0800
409 #define K1TCR_RPTR 0x0400
410 #define K1TCR_1000BT_FDX 0x200
411 #define K1TCR_1000BT_HDX 0x100
412
413 #define K1STSR_MSMCFLT 0x8000
414 #define K1STSR_MSCFGRES 0x4000
415 #define K1STSR_LRSTAT 0x2000
416 #define K1STSR_RRSTAT 0x1000
417 #define K1STSR_LP1KFD 0x0800
418 #define K1STSR_LP1KHD 0x0400
419 #define K1STSR_LPASMDIR 0x0200
420
421 #define K1SCR_1KX_FDX 0x8000
422 #define K1SCR_1KX_HDX 0x4000
423 #define K1SCR_1KT_FDX 0x2000
424 #define K1SCR_1KT_HDX 0x1000
425
426 #define STRAP_PHY1 0x0800
427 #define STRAP_NCMODE 0x0400
428 #define STRAP_MANMSCFG 0x0200
429 #define STRAP_ANENABLE 0x0100
430 #define STRAP_MSVAL 0x0080
431 #define STRAP_1KHDXADV 0x0010
432 #define STRAP_1KFDXADV 0x0008
433 #define STRAP_100ADV 0x0004
434 #define STRAP_SPEEDSEL 0x0000
435 #define STRAP_SPEED100 0x0001
436
437 #define PHYSUP_SPEED1000 0x10
438 #define PHYSUP_SPEED100 0x08
439 #define PHYSUP_SPEED10 0x00
440 #define PHYSUP_LINKUP 0x04
441 #define PHYSUP_FDX 0x02
442
443 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
444 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
445 #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
446 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
447
448
449 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
450
451 #define ENABLE 1
452 #define DISABLE 0
453
454 /**********************************************************************
455 * SBMAC_MII_SYNC(s)
456 *
457 * Synchronize with the MII - send a pattern of bits to the MII
458 * that will guarantee that it is ready to accept a command.
459 *
460 * Input parameters:
461 * s - sbmac structure
462 *
463 * Return value:
464 * nothing
465 ********************************************************************* */
466
467 static void sbmac_mii_sync(struct sbmac_softc *s)
468 {
469 int cnt;
470 uint64_t bits;
471
472 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
473
474 SBMAC_WRITECSR(s->sbm_mdio,bits);
475
476 for (cnt = 0; cnt < 32; cnt++) {
477 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC);
478 SBMAC_WRITECSR(s->sbm_mdio,bits);
479 }
480 }
481
482 /**********************************************************************
483 * SBMAC_MII_SENDDATA(s,data,bitcnt)
484 *
485 * Send some bits to the MII. The bits to be sent are right-
486 * justified in the 'data' parameter.
487 *
488 * Input parameters:
489 * s - sbmac structure
490 * data - data to send
491 * bitcnt - number of bits to send
492 ********************************************************************* */
493
494 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
495 {
496 int i;
497 uint64_t bits;
498 unsigned int curmask;
499
500 bits = M_MAC_MDIO_DIR_OUTPUT;
501 SBMAC_WRITECSR(s->sbm_mdio,bits);
502
503 curmask = 1 << (bitcnt - 1);
504
505 for (i = 0; i < bitcnt; i++) {
506 if (data & curmask)
507 bits |= M_MAC_MDIO_OUT;
508 else bits &= ~M_MAC_MDIO_OUT;
509 SBMAC_WRITECSR(s->sbm_mdio,bits);
510 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC);
511 SBMAC_WRITECSR(s->sbm_mdio,bits);
512 curmask >>= 1;
513 }
514 }
515
516
517
518 /**********************************************************************
519 * SBMAC_MII_READ(s,phyaddr,regidx)
520 *
521 * Read a PHY register.
522 *
523 * Input parameters:
524 * s - sbmac structure
525 * phyaddr - PHY's address
526 * regidx = index of register to read
527 *
528 * Return value:
529 * value read, or 0 if an error occurred.
530 ********************************************************************* */
531
532 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
533 {
534 int idx;
535 int error;
536 int regval;
537
538 /*
539 * Synchronize ourselves so that the PHY knows the next
540 * thing coming down is a command
541 */
542
543 sbmac_mii_sync(s);
544
545 /*
546 * Send the data to the PHY. The sequence is
547 * a "start" command (2 bits)
548 * a "read" command (2 bits)
549 * the PHY addr (5 bits)
550 * the register index (5 bits)
551 */
552
553 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
554 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
555 sbmac_mii_senddata(s,phyaddr, 5);
556 sbmac_mii_senddata(s,regidx, 5);
557
558 /*
559 * Switch the port around without a clock transition.
560 */
561 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
562
563 /*
564 * Send out a clock pulse to signal we want the status
565 */
566
567 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC);
568 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
569
570 /*
571 * If an error occurred, the PHY will signal '1' back
572 */
573 error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN;
574
575 /*
576 * Issue an 'idle' clock pulse, but keep the direction
577 * the same.
578 */
579 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC);
580 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
581
582 regval = 0;
583
584 for (idx = 0; idx < 16; idx++) {
585 regval <<= 1;
586
587 if (error == 0) {
588 if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN)
589 regval |= 1;
590 }
591
592 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC);
593 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
594 }
595
596 /* Switch back to output */
597 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT);
598
599 if (error == 0)
600 return regval;
601 return 0;
602 }
603
604
605 /**********************************************************************
606 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
607 *
608 * Write a value to a PHY register.
609 *
610 * Input parameters:
611 * s - sbmac structure
612 * phyaddr - PHY to use
613 * regidx - register within the PHY
614 * regval - data to write to register
615 *
616 * Return value:
617 * nothing
618 ********************************************************************* */
619
620 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
621 unsigned int regval)
622 {
623
624 sbmac_mii_sync(s);
625
626 sbmac_mii_senddata(s,MII_COMMAND_START,2);
627 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
628 sbmac_mii_senddata(s,phyaddr, 5);
629 sbmac_mii_senddata(s,regidx, 5);
630 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
631 sbmac_mii_senddata(s,regval,16);
632
633 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT);
634 }
635
636
637
638 /**********************************************************************
639 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
640 *
641 * Initialize a DMA channel context. Since there are potentially
642 * eight DMA channels per MAC, it's nice to do this in a standard
643 * way.
644 *
645 * Input parameters:
646 * d - sbmacdma_t structure (DMA channel context)
647 * s - sbmac_softc structure (pointer to a MAC)
648 * chan - channel number (0..1 right now)
649 * txrx - Identifies DMA_TX or DMA_RX for channel direction
650 * maxdescr - number of descriptors
651 *
652 * Return value:
653 * nothing
654 ********************************************************************* */
655
656 static void sbdma_initctx(sbmacdma_t *d,
657 struct sbmac_softc *s,
658 int chan,
659 int txrx,
660 int maxdescr)
661 {
662 /*
663 * Save away interesting stuff in the structure
664 */
665
666 d->sbdma_eth = s;
667 d->sbdma_channel = chan;
668 d->sbdma_txdir = txrx;
669
670 #if 0
671 /* RMON clearing */
672 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
673 #endif
674
675 SBMAC_WRITECSR(KSEG1ADDR(
676 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
677 SBMAC_WRITECSR(KSEG1ADDR(
678 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
679 SBMAC_WRITECSR(KSEG1ADDR(
680 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
681 SBMAC_WRITECSR(KSEG1ADDR(
682 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
683 SBMAC_WRITECSR(KSEG1ADDR(
684 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
685 SBMAC_WRITECSR(KSEG1ADDR(
686 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
687 SBMAC_WRITECSR(KSEG1ADDR(
688 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
689 SBMAC_WRITECSR(KSEG1ADDR(
690 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
691 SBMAC_WRITECSR(KSEG1ADDR(
692 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
693 SBMAC_WRITECSR(KSEG1ADDR(
694 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
695 SBMAC_WRITECSR(KSEG1ADDR(
696 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
697 SBMAC_WRITECSR(KSEG1ADDR(
698 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
699 SBMAC_WRITECSR(KSEG1ADDR(
700 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
701 SBMAC_WRITECSR(KSEG1ADDR(
702 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
703 SBMAC_WRITECSR(KSEG1ADDR(
704 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
705 SBMAC_WRITECSR(KSEG1ADDR(
706 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
707 SBMAC_WRITECSR(KSEG1ADDR(
708 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
709 SBMAC_WRITECSR(KSEG1ADDR(
710 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
711 SBMAC_WRITECSR(KSEG1ADDR(
712 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
713 SBMAC_WRITECSR(KSEG1ADDR(
714 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
715 SBMAC_WRITECSR(KSEG1ADDR(
716 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
717
718 /*
719 * initialize register pointers
720 */
721
722 d->sbdma_config0 =
723 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
724 d->sbdma_config1 =
725 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
726 d->sbdma_dscrbase =
727 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
728 d->sbdma_dscrcnt =
729 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
730 d->sbdma_curdscr =
731 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
732
733 /*
734 * Allocate memory for the ring
735 */
736
737 d->sbdma_maxdescr = maxdescr;
738
739 d->sbdma_dscrtable = (sbdmadscr_t *)
740 kmalloc(d->sbdma_maxdescr*sizeof(sbdmadscr_t), GFP_KERNEL);
741
742 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
743
744 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
745
746 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
747
748 /*
749 * And context table
750 */
751
752 d->sbdma_ctxtable = (struct sk_buff **)
753 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
754
755 memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
756
757 #ifdef CONFIG_SBMAC_COALESCE
758 /*
759 * Setup Rx/Tx DMA coalescing defaults
760 */
761
762 if ( int_pktcnt ) {
763 d->sbdma_int_pktcnt = int_pktcnt;
764 } else {
765 d->sbdma_int_pktcnt = 1;
766 }
767
768 if ( int_timeout ) {
769 d->sbdma_int_timeout = int_timeout;
770 } else {
771 d->sbdma_int_timeout = 0;
772 }
773 #endif
774
775 }
776
777 /**********************************************************************
778 * SBDMA_CHANNEL_START(d)
779 *
780 * Initialize the hardware registers for a DMA channel.
781 *
782 * Input parameters:
783 * d - DMA channel to init (context must be previously init'd
784 * rxtx - DMA_RX or DMA_TX depending on what type of channel
785 *
786 * Return value:
787 * nothing
788 ********************************************************************* */
789
790 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
791 {
792 /*
793 * Turn on the DMA channel
794 */
795
796 #ifdef CONFIG_SBMAC_COALESCE
797 SBMAC_WRITECSR(d->sbdma_config1,
798 V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
799 0);
800 SBMAC_WRITECSR(d->sbdma_config0,
801 M_DMA_EOP_INT_EN |
802 V_DMA_RINGSZ(d->sbdma_maxdescr) |
803 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
804 0);
805 #else
806 SBMAC_WRITECSR(d->sbdma_config1,0);
807 SBMAC_WRITECSR(d->sbdma_config0,
808 V_DMA_RINGSZ(d->sbdma_maxdescr) |
809 0);
810 #endif
811
812 SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
813
814 /*
815 * Initialize ring pointers
816 */
817
818 d->sbdma_addptr = d->sbdma_dscrtable;
819 d->sbdma_remptr = d->sbdma_dscrtable;
820 }
821
822 /**********************************************************************
823 * SBDMA_CHANNEL_STOP(d)
824 *
825 * Initialize the hardware registers for a DMA channel.
826 *
827 * Input parameters:
828 * d - DMA channel to init (context must be previously init'd
829 *
830 * Return value:
831 * nothing
832 ********************************************************************* */
833
834 static void sbdma_channel_stop(sbmacdma_t *d)
835 {
836 /*
837 * Turn off the DMA channel
838 */
839
840 SBMAC_WRITECSR(d->sbdma_config1,0);
841
842 SBMAC_WRITECSR(d->sbdma_dscrbase,0);
843
844 SBMAC_WRITECSR(d->sbdma_config0,0);
845
846 /*
847 * Zero ring pointers
848 */
849
850 d->sbdma_addptr = 0;
851 d->sbdma_remptr = 0;
852 }
853
854 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
855 {
856 unsigned long addr;
857 unsigned long newaddr;
858
859 addr = (unsigned long) skb->data;
860
861 newaddr = (addr + power2 - 1) & ~(power2 - 1);
862
863 skb_reserve(skb,newaddr-addr+offset);
864 }
865
866
867 /**********************************************************************
868 * SBDMA_ADD_RCVBUFFER(d,sb)
869 *
870 * Add a buffer to the specified DMA channel. For receive channels,
871 * this queues a buffer for inbound packets.
872 *
873 * Input parameters:
874 * d - DMA channel descriptor
875 * sb - sk_buff to add, or NULL if we should allocate one
876 *
877 * Return value:
878 * 0 if buffer could not be added (ring is full)
879 * 1 if buffer added successfully
880 ********************************************************************* */
881
882
883 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
884 {
885 sbdmadscr_t *dsc;
886 sbdmadscr_t *nextdsc;
887 struct sk_buff *sb_new = NULL;
888 int pktsize = ENET_PACKET_SIZE;
889
890 /* get pointer to our current place in the ring */
891
892 dsc = d->sbdma_addptr;
893 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
894
895 /*
896 * figure out if the ring is full - if the next descriptor
897 * is the same as the one that we're going to remove from
898 * the ring, the ring is full
899 */
900
901 if (nextdsc == d->sbdma_remptr) {
902 return -ENOSPC;
903 }
904
905 /*
906 * Allocate a sk_buff if we don't already have one.
907 * If we do have an sk_buff, reset it so that it's empty.
908 *
909 * Note: sk_buffs don't seem to be guaranteed to have any sort
910 * of alignment when they are allocated. Therefore, allocate enough
911 * extra space to make sure that:
912 *
913 * 1. the data does not start in the middle of a cache line.
914 * 2. The data does not end in the middle of a cache line
915 * 3. The buffer can be aligned such that the IP addresses are
916 * naturally aligned.
917 *
918 * Remember, the SOCs MAC writes whole cache lines at a time,
919 * without reading the old contents first. So, if the sk_buff's
920 * data portion starts in the middle of a cache line, the SOC
921 * DMA will trash the beginning (and ending) portions.
922 */
923
924 if (sb == NULL) {
925 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
926 if (sb_new == NULL) {
927 printk(KERN_INFO "%s: sk_buff allocation failed\n",
928 d->sbdma_eth->sbm_dev->name);
929 return -ENOBUFS;
930 }
931
932 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
933
934 /* mark skbuff owned by our device */
935 sb_new->dev = d->sbdma_eth->sbm_dev;
936 }
937 else {
938 sb_new = sb;
939 /*
940 * nothing special to reinit buffer, it's already aligned
941 * and sb->data already points to a good place.
942 */
943 }
944
945 /*
946 * fill in the descriptor
947 */
948
949 #ifdef CONFIG_SBMAC_COALESCE
950 /*
951 * Do not interrupt per DMA transfer.
952 */
953 dsc->dscr_a = virt_to_phys(sb_new->tail) |
954 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
955 0;
956 #else
957 dsc->dscr_a = virt_to_phys(sb_new->tail) |
958 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
959 M_DMA_DSCRA_INTERRUPT;
960 #endif
961
962 /* receiving: no options */
963 dsc->dscr_b = 0;
964
965 /*
966 * fill in the context
967 */
968
969 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
970
971 /*
972 * point at next packet
973 */
974
975 d->sbdma_addptr = nextdsc;
976
977 /*
978 * Give the buffer to the DMA engine.
979 */
980
981 SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
982
983 return 0; /* we did it */
984 }
985
986 /**********************************************************************
987 * SBDMA_ADD_TXBUFFER(d,sb)
988 *
989 * Add a transmit buffer to the specified DMA channel, causing a
990 * transmit to start.
991 *
992 * Input parameters:
993 * d - DMA channel descriptor
994 * sb - sk_buff to add
995 *
996 * Return value:
997 * 0 transmit queued successfully
998 * otherwise error code
999 ********************************************************************* */
1000
1001
1002 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1003 {
1004 sbdmadscr_t *dsc;
1005 sbdmadscr_t *nextdsc;
1006 uint64_t phys;
1007 uint64_t ncb;
1008 int length;
1009
1010 /* get pointer to our current place in the ring */
1011
1012 dsc = d->sbdma_addptr;
1013 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1014
1015 /*
1016 * figure out if the ring is full - if the next descriptor
1017 * is the same as the one that we're going to remove from
1018 * the ring, the ring is full
1019 */
1020
1021 if (nextdsc == d->sbdma_remptr) {
1022 return -ENOSPC;
1023 }
1024
1025 /*
1026 * Under Linux, it's not necessary to copy/coalesce buffers
1027 * like it is on NetBSD. We think they're all contiguous,
1028 * but that may not be true for GBE.
1029 */
1030
1031 length = sb->len;
1032
1033 /*
1034 * fill in the descriptor. Note that the number of cache
1035 * blocks in the descriptor is the number of blocks
1036 * *spanned*, so we need to add in the offset (if any)
1037 * while doing the calculation.
1038 */
1039
1040 phys = virt_to_phys(sb->data);
1041 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1042
1043 dsc->dscr_a = phys |
1044 V_DMA_DSCRA_A_SIZE(ncb) |
1045 #ifndef CONFIG_SBMAC_COALESCE
1046 M_DMA_DSCRA_INTERRUPT |
1047 #endif
1048 M_DMA_ETHTX_SOP;
1049
1050 /* transmitting: set outbound options and length */
1051
1052 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1053 V_DMA_DSCRB_PKT_SIZE(length);
1054
1055 /*
1056 * fill in the context
1057 */
1058
1059 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1060
1061 /*
1062 * point at next packet
1063 */
1064
1065 d->sbdma_addptr = nextdsc;
1066
1067 /*
1068 * Give the buffer to the DMA engine.
1069 */
1070
1071 SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1072
1073 return 0; /* we did it */
1074 }
1075
1076
1077
1078
1079 /**********************************************************************
1080 * SBDMA_EMPTYRING(d)
1081 *
1082 * Free all allocated sk_buffs on the specified DMA channel;
1083 *
1084 * Input parameters:
1085 * d - DMA channel
1086 *
1087 * Return value:
1088 * nothing
1089 ********************************************************************* */
1090
1091 static void sbdma_emptyring(sbmacdma_t *d)
1092 {
1093 int idx;
1094 struct sk_buff *sb;
1095
1096 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1097 sb = d->sbdma_ctxtable[idx];
1098 if (sb) {
1099 dev_kfree_skb(sb);
1100 d->sbdma_ctxtable[idx] = NULL;
1101 }
1102 }
1103 }
1104
1105
1106 /**********************************************************************
1107 * SBDMA_FILLRING(d)
1108 *
1109 * Fill the specified DMA channel (must be receive channel)
1110 * with sk_buffs
1111 *
1112 * Input parameters:
1113 * d - DMA channel
1114 *
1115 * Return value:
1116 * nothing
1117 ********************************************************************* */
1118
1119 static void sbdma_fillring(sbmacdma_t *d)
1120 {
1121 int idx;
1122
1123 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1124 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1125 break;
1126 }
1127 }
1128
1129
1130 /**********************************************************************
1131 * SBDMA_RX_PROCESS(sc,d)
1132 *
1133 * Process "completed" receive buffers on the specified DMA channel.
1134 * Note that this isn't really ideal for priority channels, since
1135 * it processes all of the packets on a given channel before
1136 * returning.
1137 *
1138 * Input parameters:
1139 * sc - softc structure
1140 * d - DMA channel context
1141 *
1142 * Return value:
1143 * nothing
1144 ********************************************************************* */
1145
1146 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1147 {
1148 int curidx;
1149 int hwidx;
1150 sbdmadscr_t *dsc;
1151 struct sk_buff *sb;
1152 int len;
1153
1154 for (;;) {
1155 /*
1156 * figure out where we are (as an index) and where
1157 * the hardware is (also as an index)
1158 *
1159 * This could be done faster if (for example) the
1160 * descriptor table was page-aligned and contiguous in
1161 * both virtual and physical memory -- you could then
1162 * just compare the low-order bits of the virtual address
1163 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1164 */
1165
1166 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1167 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1168 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1169
1170 /*
1171 * If they're the same, that means we've processed all
1172 * of the descriptors up to (but not including) the one that
1173 * the hardware is working on right now.
1174 */
1175
1176 if (curidx == hwidx)
1177 break;
1178
1179 /*
1180 * Otherwise, get the packet's sk_buff ptr back
1181 */
1182
1183 dsc = &(d->sbdma_dscrtable[curidx]);
1184 sb = d->sbdma_ctxtable[curidx];
1185 d->sbdma_ctxtable[curidx] = NULL;
1186
1187 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1188
1189 /*
1190 * Check packet status. If good, process it.
1191 * If not, silently drop it and put it back on the
1192 * receive ring.
1193 */
1194
1195 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1196
1197 /*
1198 * Add a new buffer to replace the old one. If we fail
1199 * to allocate a buffer, we're going to drop this
1200 * packet and put it right back on the receive ring.
1201 */
1202
1203 if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1204 sc->sbm_stats.rx_dropped++;
1205 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1206 } else {
1207 /*
1208 * Set length into the packet
1209 */
1210 skb_put(sb,len);
1211
1212 /*
1213 * Buffer has been replaced on the
1214 * receive ring. Pass the buffer to
1215 * the kernel */
1216 sc->sbm_stats.rx_bytes += len;
1217 sc->sbm_stats.rx_packets++;
1218 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1219 if (sc->rx_hw_checksum == ENABLE) {
1220 /* if the ip checksum is good
1221 indicate in skb. else set
1222 CHECKSUM_NONE as device
1223 failed to checksum the
1224 packet */
1225
1226 if (((dsc->dscr_b) |M_DMA_ETHRX_BADTCPCS) ||
1227 ((dsc->dscr_a)| M_DMA_ETHRX_BADIP4CS)) {
1228 sb->ip_summed = CHECKSUM_NONE;
1229 } else {
1230 printk(KERN_DEBUG "hw checksum fail .\n");
1231 sb->ip_summed = CHECKSUM_UNNECESSARY;
1232 }
1233 } /* rx_hw_checksum */
1234
1235 netif_rx(sb);
1236 }
1237 } else {
1238 /*
1239 * Packet was mangled somehow. Just drop it and
1240 * put it back on the receive ring.
1241 */
1242 sc->sbm_stats.rx_errors++;
1243 sbdma_add_rcvbuffer(d,sb);
1244 }
1245
1246
1247 /*
1248 * .. and advance to the next buffer.
1249 */
1250
1251 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1252
1253 }
1254 }
1255
1256
1257
1258 /**********************************************************************
1259 * SBDMA_TX_PROCESS(sc,d)
1260 *
1261 * Process "completed" transmit buffers on the specified DMA channel.
1262 * This is normally called within the interrupt service routine.
1263 * Note that this isn't really ideal for priority channels, since
1264 * it processes all of the packets on a given channel before
1265 * returning.
1266 *
1267 * Input parameters:
1268 * sc - softc structure
1269 * d - DMA channel context
1270 *
1271 * Return value:
1272 * nothing
1273 ********************************************************************* */
1274
1275 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1276 {
1277 int curidx;
1278 int hwidx;
1279 sbdmadscr_t *dsc;
1280 struct sk_buff *sb;
1281 unsigned long flags;
1282
1283 spin_lock_irqsave(&(sc->sbm_lock), flags);
1284
1285 for (;;) {
1286 /*
1287 * figure out where we are (as an index) and where
1288 * the hardware is (also as an index)
1289 *
1290 * This could be done faster if (for example) the
1291 * descriptor table was page-aligned and contiguous in
1292 * both virtual and physical memory -- you could then
1293 * just compare the low-order bits of the virtual address
1294 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1295 */
1296
1297 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1298 {
1299 /* XXX This is gross, ugly, and only here
1300 * because justin hacked it in to fix a
1301 * problem without really understanding it.
1302 *
1303 * It seems that, for whatever reason, this
1304 * routine is invoked immediately upon the
1305 * enabling of interrupts. So then the Read
1306 * below returns zero, making hwidx a negative
1307 * number, and anti-hilarity ensues.
1308 *
1309 * I'm guessing there's a proper fix involving
1310 * clearing out interrupt state from old
1311 * packets before enabling interrupts, but I'm
1312 * not sure.
1313 *
1314 * Anyways, this hack seems to work, and is
1315 * Good Enough for 11 PM. :)
1316 *
1317 * -Justin
1318 */
1319
1320 uint64_t tmp = SBMAC_READCSR(d->sbdma_curdscr);
1321 if (!tmp) {
1322 break;
1323 }
1324 hwidx = (int) (((tmp & M_DMA_CURDSCR_ADDR) -
1325 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1326 }
1327 /*
1328 * If they're the same, that means we've processed all
1329 * of the descriptors up to (but not including) the one that
1330 * the hardware is working on right now.
1331 */
1332
1333 if (curidx == hwidx)
1334 break;
1335
1336 /*
1337 * Otherwise, get the packet's sk_buff ptr back
1338 */
1339
1340 dsc = &(d->sbdma_dscrtable[curidx]);
1341 sb = d->sbdma_ctxtable[curidx];
1342 d->sbdma_ctxtable[curidx] = NULL;
1343
1344 /*
1345 * Stats
1346 */
1347
1348 sc->sbm_stats.tx_bytes += sb->len;
1349 sc->sbm_stats.tx_packets++;
1350
1351 /*
1352 * for transmits, we just free buffers.
1353 */
1354
1355 dev_kfree_skb_irq(sb);
1356
1357 /*
1358 * .. and advance to the next buffer.
1359 */
1360
1361 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1362
1363 }
1364
1365 /*
1366 * Decide if we should wake up the protocol or not.
1367 * Other drivers seem to do this when we reach a low
1368 * watermark on the transmit queue.
1369 */
1370
1371 netif_wake_queue(d->sbdma_eth->sbm_dev);
1372
1373 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1374
1375 }
1376
1377
1378
1379 /**********************************************************************
1380 * SBMAC_INITCTX(s)
1381 *
1382 * Initialize an Ethernet context structure - this is called
1383 * once per MAC on the 1250. Memory is allocated here, so don't
1384 * call it again from inside the ioctl routines that bring the
1385 * interface up/down
1386 *
1387 * Input parameters:
1388 * s - sbmac context structure
1389 *
1390 * Return value:
1391 * 0
1392 ********************************************************************* */
1393
1394 static int sbmac_initctx(struct sbmac_softc *s)
1395 {
1396
1397 /*
1398 * figure out the addresses of some ports
1399 */
1400
1401 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1402 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1403 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1404 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1405 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1406 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1407 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1408 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1409
1410 s->sbm_phys[0] = 1;
1411 s->sbm_phys[1] = 0;
1412
1413 s->sbm_phy_oldbmsr = 0;
1414 s->sbm_phy_oldanlpar = 0;
1415 s->sbm_phy_oldk1stsr = 0;
1416 s->sbm_phy_oldlinkstat = 0;
1417
1418 /*
1419 * Initialize the DMA channels. Right now, only one per MAC is used
1420 * Note: Only do this _once_, as it allocates memory from the kernel!
1421 */
1422
1423 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1424 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1425
1426 /*
1427 * initial state is OFF
1428 */
1429
1430 s->sbm_state = sbmac_state_off;
1431
1432 /*
1433 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1434 */
1435
1436 s->sbm_speed = sbmac_speed_10;
1437 s->sbm_duplex = sbmac_duplex_half;
1438 s->sbm_fc = sbmac_fc_disabled;
1439
1440 return 0;
1441 }
1442
1443
1444 static void sbdma_uninitctx(struct sbmacdma_s *d)
1445 {
1446 if (d->sbdma_dscrtable) {
1447 kfree(d->sbdma_dscrtable);
1448 d->sbdma_dscrtable = NULL;
1449 }
1450
1451 if (d->sbdma_ctxtable) {
1452 kfree(d->sbdma_ctxtable);
1453 d->sbdma_ctxtable = NULL;
1454 }
1455 }
1456
1457
1458 static void sbmac_uninitctx(struct sbmac_softc *sc)
1459 {
1460 sbdma_uninitctx(&(sc->sbm_txdma));
1461 sbdma_uninitctx(&(sc->sbm_rxdma));
1462 }
1463
1464
1465 /**********************************************************************
1466 * SBMAC_CHANNEL_START(s)
1467 *
1468 * Start packet processing on this MAC.
1469 *
1470 * Input parameters:
1471 * s - sbmac structure
1472 *
1473 * Return value:
1474 * nothing
1475 ********************************************************************* */
1476
1477 static void sbmac_channel_start(struct sbmac_softc *s)
1478 {
1479 uint64_t reg;
1480 sbmac_port_t port;
1481 uint64_t cfg,fifo,framecfg;
1482 int idx, th_value;
1483
1484 /*
1485 * Don't do this if running
1486 */
1487
1488 if (s->sbm_state == sbmac_state_on)
1489 return;
1490
1491 /*
1492 * Bring the controller out of reset, but leave it off.
1493 */
1494
1495 SBMAC_WRITECSR(s->sbm_macenable,0);
1496
1497 /*
1498 * Ignore all received packets
1499 */
1500
1501 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1502
1503 /*
1504 * Calculate values for various control registers.
1505 */
1506
1507 cfg = M_MAC_RETRY_EN |
1508 M_MAC_TX_HOLD_SOP_EN |
1509 V_MAC_TX_PAUSE_CNT_16K |
1510 M_MAC_AP_STAT_EN |
1511 M_MAC_FAST_SYNC |
1512 M_MAC_SS_EN |
1513 0;
1514
1515 /*
1516 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1517 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1518 * Use a larger RD_THRSH for gigabit
1519 */
1520 if (periph_rev >= 2)
1521 th_value = 64;
1522 else
1523 th_value = 28;
1524
1525 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1526 ((s->sbm_speed == sbmac_speed_1000)
1527 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1528 V_MAC_TX_RL_THRSH(4) |
1529 V_MAC_RX_PL_THRSH(4) |
1530 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1531 V_MAC_RX_PL_THRSH(4) |
1532 V_MAC_RX_RL_THRSH(8) |
1533 0;
1534
1535 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1536 V_MAC_MAX_FRAMESZ_DEFAULT |
1537 V_MAC_BACKOFF_SEL(1);
1538
1539 /*
1540 * Clear out the hash address map
1541 */
1542
1543 port = s->sbm_base + R_MAC_HASH_BASE;
1544 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1545 SBMAC_WRITECSR(port,0);
1546 port += sizeof(uint64_t);
1547 }
1548
1549 /*
1550 * Clear out the exact-match table
1551 */
1552
1553 port = s->sbm_base + R_MAC_ADDR_BASE;
1554 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1555 SBMAC_WRITECSR(port,0);
1556 port += sizeof(uint64_t);
1557 }
1558
1559 /*
1560 * Clear out the DMA Channel mapping table registers
1561 */
1562
1563 port = s->sbm_base + R_MAC_CHUP0_BASE;
1564 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1565 SBMAC_WRITECSR(port,0);
1566 port += sizeof(uint64_t);
1567 }
1568
1569
1570 port = s->sbm_base + R_MAC_CHLO0_BASE;
1571 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1572 SBMAC_WRITECSR(port,0);
1573 port += sizeof(uint64_t);
1574 }
1575
1576 /*
1577 * Program the hardware address. It goes into the hardware-address
1578 * register as well as the first filter register.
1579 */
1580
1581 reg = sbmac_addr2reg(s->sbm_hwaddr);
1582
1583 port = s->sbm_base + R_MAC_ADDR_BASE;
1584 SBMAC_WRITECSR(port,reg);
1585 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1586
1587 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1588 /*
1589 * Pass1 SOCs do not receive packets addressed to the
1590 * destination address in the R_MAC_ETHERNET_ADDR register.
1591 * Set the value to zero.
1592 */
1593 SBMAC_WRITECSR(port,0);
1594 #else
1595 SBMAC_WRITECSR(port,reg);
1596 #endif
1597
1598 /*
1599 * Set the receive filter for no packets, and write values
1600 * to the various config registers
1601 */
1602
1603 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1604 SBMAC_WRITECSR(s->sbm_imr,0);
1605 SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1606 SBMAC_WRITECSR(s->sbm_fifocfg,fifo);
1607 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1608
1609 /*
1610 * Initialize DMA channels (rings should be ok now)
1611 */
1612
1613 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1614 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1615
1616 /*
1617 * Configure the speed, duplex, and flow control
1618 */
1619
1620 sbmac_set_speed(s,s->sbm_speed);
1621 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1622
1623 /*
1624 * Fill the receive ring
1625 */
1626
1627 sbdma_fillring(&(s->sbm_rxdma));
1628
1629 /*
1630 * Turn on the rest of the bits in the enable register
1631 */
1632
1633 SBMAC_WRITECSR(s->sbm_macenable,
1634 M_MAC_RXDMA_EN0 |
1635 M_MAC_TXDMA_EN0 |
1636 M_MAC_RX_ENABLE |
1637 M_MAC_TX_ENABLE);
1638
1639
1640
1641
1642 #ifdef CONFIG_SBMAC_COALESCE
1643 /*
1644 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1645 */
1646 SBMAC_WRITECSR(s->sbm_imr,
1647 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1648 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
1649 #else
1650 /*
1651 * Accept any kind of interrupt on TX and RX DMA channel 0
1652 */
1653 SBMAC_WRITECSR(s->sbm_imr,
1654 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1655 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
1656 #endif
1657
1658 /*
1659 * Enable receiving unicasts and broadcasts
1660 */
1661
1662 SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);
1663
1664 /*
1665 * we're running now.
1666 */
1667
1668 s->sbm_state = sbmac_state_on;
1669
1670 /*
1671 * Program multicast addresses
1672 */
1673
1674 sbmac_setmulti(s);
1675
1676 /*
1677 * If channel was in promiscuous mode before, turn that on
1678 */
1679
1680 if (s->sbm_devflags & IFF_PROMISC) {
1681 sbmac_promiscuous_mode(s,1);
1682 }
1683
1684 }
1685
1686
1687 /**********************************************************************
1688 * SBMAC_CHANNEL_STOP(s)
1689 *
1690 * Stop packet processing on this MAC.
1691 *
1692 * Input parameters:
1693 * s - sbmac structure
1694 *
1695 * Return value:
1696 * nothing
1697 ********************************************************************* */
1698
1699 static void sbmac_channel_stop(struct sbmac_softc *s)
1700 {
1701 /* don't do this if already stopped */
1702
1703 if (s->sbm_state == sbmac_state_off)
1704 return;
1705
1706 /* don't accept any packets, disable all interrupts */
1707
1708 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1709 SBMAC_WRITECSR(s->sbm_imr,0);
1710
1711 /* Turn off ticker */
1712
1713 /* XXX */
1714
1715 /* turn off receiver and transmitter */
1716
1717 SBMAC_WRITECSR(s->sbm_macenable,0);
1718
1719 /* We're stopped now. */
1720
1721 s->sbm_state = sbmac_state_off;
1722
1723 /*
1724 * Stop DMA channels (rings should be ok now)
1725 */
1726
1727 sbdma_channel_stop(&(s->sbm_rxdma));
1728 sbdma_channel_stop(&(s->sbm_txdma));
1729
1730 /* Empty the receive and transmit rings */
1731
1732 sbdma_emptyring(&(s->sbm_rxdma));
1733 sbdma_emptyring(&(s->sbm_txdma));
1734
1735 }
1736
1737 /**********************************************************************
1738 * SBMAC_SET_CHANNEL_STATE(state)
1739 *
1740 * Set the channel's state ON or OFF
1741 *
1742 * Input parameters:
1743 * state - new state
1744 *
1745 * Return value:
1746 * old state
1747 ********************************************************************* */
1748 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1749 sbmac_state_t state)
1750 {
1751 sbmac_state_t oldstate = sc->sbm_state;
1752
1753 /*
1754 * If same as previous state, return
1755 */
1756
1757 if (state == oldstate) {
1758 return oldstate;
1759 }
1760
1761 /*
1762 * If new state is ON, turn channel on
1763 */
1764
1765 if (state == sbmac_state_on) {
1766 sbmac_channel_start(sc);
1767 }
1768 else {
1769 sbmac_channel_stop(sc);
1770 }
1771
1772 /*
1773 * Return previous state
1774 */
1775
1776 return oldstate;
1777 }
1778
1779
1780 /**********************************************************************
1781 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1782 *
1783 * Turn on or off promiscuous mode
1784 *
1785 * Input parameters:
1786 * sc - softc
1787 * onoff - 1 to turn on, 0 to turn off
1788 *
1789 * Return value:
1790 * nothing
1791 ********************************************************************* */
1792
1793 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1794 {
1795 uint64_t reg;
1796
1797 if (sc->sbm_state != sbmac_state_on)
1798 return;
1799
1800 if (onoff) {
1801 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1802 reg |= M_MAC_ALLPKT_EN;
1803 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1804 }
1805 else {
1806 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1807 reg &= ~M_MAC_ALLPKT_EN;
1808 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1809 }
1810 }
1811
1812 /**********************************************************************
1813 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1814 *
1815 * Set the iphdr offset as 15 assuming ethernet encapsulation
1816 *
1817 * Input parameters:
1818 * sc - softc
1819 *
1820 * Return value:
1821 * nothing
1822 ********************************************************************* */
1823
1824 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1825 {
1826 uint64_t reg;
1827
1828 /* Hard code the off set to 15 for now */
1829 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1830 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1831 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1832
1833 /* read system identification to determine revision */
1834 if (periph_rev >= 2) {
1835 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
1836 sc->sbm_dev->name);
1837 sc->rx_hw_checksum = ENABLE;
1838 } else {
1839 sc->rx_hw_checksum = DISABLE;
1840 }
1841 }
1842
1843
1844 /**********************************************************************
1845 * SBMAC_ADDR2REG(ptr)
1846 *
1847 * Convert six bytes into the 64-bit register value that
1848 * we typically write into the SBMAC's address/mcast registers
1849 *
1850 * Input parameters:
1851 * ptr - pointer to 6 bytes
1852 *
1853 * Return value:
1854 * register value
1855 ********************************************************************* */
1856
1857 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1858 {
1859 uint64_t reg = 0;
1860
1861 ptr += 6;
1862
1863 reg |= (uint64_t) *(--ptr);
1864 reg <<= 8;
1865 reg |= (uint64_t) *(--ptr);
1866 reg <<= 8;
1867 reg |= (uint64_t) *(--ptr);
1868 reg <<= 8;
1869 reg |= (uint64_t) *(--ptr);
1870 reg <<= 8;
1871 reg |= (uint64_t) *(--ptr);
1872 reg <<= 8;
1873 reg |= (uint64_t) *(--ptr);
1874
1875 return reg;
1876 }
1877
1878
1879 /**********************************************************************
1880 * SBMAC_SET_SPEED(s,speed)
1881 *
1882 * Configure LAN speed for the specified MAC.
1883 * Warning: must be called when MAC is off!
1884 *
1885 * Input parameters:
1886 * s - sbmac structure
1887 * speed - speed to set MAC to (see sbmac_speed_t enum)
1888 *
1889 * Return value:
1890 * 1 if successful
1891 * 0 indicates invalid parameters
1892 ********************************************************************* */
1893
1894 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1895 {
1896 uint64_t cfg;
1897 uint64_t framecfg;
1898
1899 /*
1900 * Save new current values
1901 */
1902
1903 s->sbm_speed = speed;
1904
1905 if (s->sbm_state == sbmac_state_on)
1906 return 0; /* save for next restart */
1907
1908 /*
1909 * Read current register values
1910 */
1911
1912 cfg = SBMAC_READCSR(s->sbm_maccfg);
1913 framecfg = SBMAC_READCSR(s->sbm_framecfg);
1914
1915 /*
1916 * Mask out the stuff we want to change
1917 */
1918
1919 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1920 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1921 M_MAC_SLOT_SIZE);
1922
1923 /*
1924 * Now add in the new bits
1925 */
1926
1927 switch (speed) {
1928 case sbmac_speed_10:
1929 framecfg |= V_MAC_IFG_RX_10 |
1930 V_MAC_IFG_TX_10 |
1931 K_MAC_IFG_THRSH_10 |
1932 V_MAC_SLOT_SIZE_10;
1933 cfg |= V_MAC_SPEED_SEL_10MBPS;
1934 break;
1935
1936 case sbmac_speed_100:
1937 framecfg |= V_MAC_IFG_RX_100 |
1938 V_MAC_IFG_TX_100 |
1939 V_MAC_IFG_THRSH_100 |
1940 V_MAC_SLOT_SIZE_100;
1941 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1942 break;
1943
1944 case sbmac_speed_1000:
1945 framecfg |= V_MAC_IFG_RX_1000 |
1946 V_MAC_IFG_TX_1000 |
1947 V_MAC_IFG_THRSH_1000 |
1948 V_MAC_SLOT_SIZE_1000;
1949 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1950 break;
1951
1952 case sbmac_speed_auto: /* XXX not implemented */
1953 /* fall through */
1954 default:
1955 return 0;
1956 }
1957
1958 /*
1959 * Send the bits back to the hardware
1960 */
1961
1962 SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1963 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1964
1965 return 1;
1966 }
1967
1968 /**********************************************************************
1969 * SBMAC_SET_DUPLEX(s,duplex,fc)
1970 *
1971 * Set Ethernet duplex and flow control options for this MAC
1972 * Warning: must be called when MAC is off!
1973 *
1974 * Input parameters:
1975 * s - sbmac structure
1976 * duplex - duplex setting (see sbmac_duplex_t)
1977 * fc - flow control setting (see sbmac_fc_t)
1978 *
1979 * Return value:
1980 * 1 if ok
1981 * 0 if an invalid parameter combination was specified
1982 ********************************************************************* */
1983
1984 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1985 {
1986 uint64_t cfg;
1987
1988 /*
1989 * Save new current values
1990 */
1991
1992 s->sbm_duplex = duplex;
1993 s->sbm_fc = fc;
1994
1995 if (s->sbm_state == sbmac_state_on)
1996 return 0; /* save for next restart */
1997
1998 /*
1999 * Read current register values
2000 */
2001
2002 cfg = SBMAC_READCSR(s->sbm_maccfg);
2003
2004 /*
2005 * Mask off the stuff we're about to change
2006 */
2007
2008 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
2009
2010
2011 switch (duplex) {
2012 case sbmac_duplex_half:
2013 switch (fc) {
2014 case sbmac_fc_disabled:
2015 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2016 break;
2017
2018 case sbmac_fc_collision:
2019 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2020 break;
2021
2022 case sbmac_fc_carrier:
2023 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2024 break;
2025
2026 case sbmac_fc_auto: /* XXX not implemented */
2027 /* fall through */
2028 case sbmac_fc_frame: /* not valid in half duplex */
2029 default: /* invalid selection */
2030 return 0;
2031 }
2032 break;
2033
2034 case sbmac_duplex_full:
2035 switch (fc) {
2036 case sbmac_fc_disabled:
2037 cfg |= V_MAC_FC_CMD_DISABLED;
2038 break;
2039
2040 case sbmac_fc_frame:
2041 cfg |= V_MAC_FC_CMD_ENABLED;
2042 break;
2043
2044 case sbmac_fc_collision: /* not valid in full duplex */
2045 case sbmac_fc_carrier: /* not valid in full duplex */
2046 case sbmac_fc_auto: /* XXX not implemented */
2047 /* fall through */
2048 default:
2049 return 0;
2050 }
2051 break;
2052 case sbmac_duplex_auto:
2053 /* XXX not implemented */
2054 break;
2055 }
2056
2057 /*
2058 * Send the bits back to the hardware
2059 */
2060
2061 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
2062
2063 return 1;
2064 }
2065
2066
2067
2068
2069 /**********************************************************************
2070 * SBMAC_INTR()
2071 *
2072 * Interrupt handler for MAC interrupts
2073 *
2074 * Input parameters:
2075 * MAC structure
2076 *
2077 * Return value:
2078 * nothing
2079 ********************************************************************* */
2080 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2081 {
2082 struct net_device *dev = (struct net_device *) dev_instance;
2083 struct sbmac_softc *sc = (struct sbmac_softc *) (dev->priv);
2084 uint64_t isr;
2085 int handled = 0;
2086
2087 for (;;) {
2088
2089 /*
2090 * Read the ISR (this clears the bits in the real
2091 * register, except for counter addr)
2092 */
2093
2094 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2095
2096 if (isr == 0)
2097 break;
2098
2099 handled = 1;
2100
2101 /*
2102 * Transmits on channel 0
2103 */
2104
2105 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2106 sbdma_tx_process(sc,&(sc->sbm_txdma));
2107 }
2108
2109 /*
2110 * Receives on channel 0
2111 */
2112
2113 /*
2114 * It's important to test all the bits (or at least the
2115 * EOP_SEEN bit) when deciding to do the RX process
2116 * particularly when coalescing, to make sure we
2117 * take care of the following:
2118 *
2119 * If you have some packets waiting (have been received
2120 * but no interrupt) and get a TX interrupt before
2121 * the RX timer or counter expires, reading the ISR
2122 * above will clear the timer and counter, and you
2123 * won't get another interrupt until a packet shows
2124 * up to start the timer again. Testing
2125 * EOP_SEEN here takes care of this case.
2126 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2127 */
2128
2129
2130 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2131 sbdma_rx_process(sc,&(sc->sbm_rxdma));
2132 }
2133 }
2134 return IRQ_RETVAL(handled);
2135 }
2136
2137
2138 /**********************************************************************
2139 * SBMAC_START_TX(skb,dev)
2140 *
2141 * Start output on the specified interface. Basically, we
2142 * queue as many buffers as we can until the ring fills up, or
2143 * we run off the end of the queue, whichever comes first.
2144 *
2145 * Input parameters:
2146 *
2147 *
2148 * Return value:
2149 * nothing
2150 ********************************************************************* */
2151 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2152 {
2153 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2154
2155 /* lock eth irq */
2156 spin_lock_irq (&sc->sbm_lock);
2157
2158 /*
2159 * Put the buffer on the transmit ring. If we
2160 * don't have room, stop the queue.
2161 */
2162
2163 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2164 /* XXX save skb that we could not send */
2165 netif_stop_queue(dev);
2166 spin_unlock_irq(&sc->sbm_lock);
2167
2168 return 1;
2169 }
2170
2171 dev->trans_start = jiffies;
2172
2173 spin_unlock_irq (&sc->sbm_lock);
2174
2175 return 0;
2176 }
2177
2178 /**********************************************************************
2179 * SBMAC_SETMULTI(sc)
2180 *
2181 * Reprogram the multicast table into the hardware, given
2182 * the list of multicasts associated with the interface
2183 * structure.
2184 *
2185 * Input parameters:
2186 * sc - softc
2187 *
2188 * Return value:
2189 * nothing
2190 ********************************************************************* */
2191
2192 static void sbmac_setmulti(struct sbmac_softc *sc)
2193 {
2194 uint64_t reg;
2195 sbmac_port_t port;
2196 int idx;
2197 struct dev_mc_list *mclist;
2198 struct net_device *dev = sc->sbm_dev;
2199
2200 /*
2201 * Clear out entire multicast table. We do this by nuking
2202 * the entire hash table and all the direct matches except
2203 * the first one, which is used for our station address
2204 */
2205
2206 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2207 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2208 SBMAC_WRITECSR(port,0);
2209 }
2210
2211 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2212 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2213 SBMAC_WRITECSR(port,0);
2214 }
2215
2216 /*
2217 * Clear the filter to say we don't want any multicasts.
2218 */
2219
2220 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2221 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2222 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2223
2224 if (dev->flags & IFF_ALLMULTI) {
2225 /*
2226 * Enable ALL multicasts. Do this by inverting the
2227 * multicast enable bit.
2228 */
2229 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2230 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2231 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2232 return;
2233 }
2234
2235
2236 /*
2237 * Progam new multicast entries. For now, only use the
2238 * perfect filter. In the future we'll need to use the
2239 * hash filter if the perfect filter overflows
2240 */
2241
2242 /* XXX only using perfect filter for now, need to use hash
2243 * XXX if the table overflows */
2244
2245 idx = 1; /* skip station address */
2246 mclist = dev->mc_list;
2247 while (mclist && (idx < MAC_ADDR_COUNT)) {
2248 reg = sbmac_addr2reg(mclist->dmi_addr);
2249 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2250 SBMAC_WRITECSR(port,reg);
2251 idx++;
2252 mclist = mclist->next;
2253 }
2254
2255 /*
2256 * Enable the "accept multicast bits" if we programmed at least one
2257 * multicast.
2258 */
2259
2260 if (idx > 1) {
2261 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2262 reg |= M_MAC_MCAST_EN;
2263 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2264 }
2265 }
2266
2267
2268
2269 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2270 /**********************************************************************
2271 * SBMAC_PARSE_XDIGIT(str)
2272 *
2273 * Parse a hex digit, returning its value
2274 *
2275 * Input parameters:
2276 * str - character
2277 *
2278 * Return value:
2279 * hex value, or -1 if invalid
2280 ********************************************************************* */
2281
2282 static int sbmac_parse_xdigit(char str)
2283 {
2284 int digit;
2285
2286 if ((str >= '0') && (str <= '9'))
2287 digit = str - '0';
2288 else if ((str >= 'a') && (str <= 'f'))
2289 digit = str - 'a' + 10;
2290 else if ((str >= 'A') && (str <= 'F'))
2291 digit = str - 'A' + 10;
2292 else
2293 return -1;
2294
2295 return digit;
2296 }
2297
2298 /**********************************************************************
2299 * SBMAC_PARSE_HWADDR(str,hwaddr)
2300 *
2301 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2302 * Ethernet address.
2303 *
2304 * Input parameters:
2305 * str - string
2306 * hwaddr - pointer to hardware address
2307 *
2308 * Return value:
2309 * 0 if ok, else -1
2310 ********************************************************************* */
2311
2312 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2313 {
2314 int digit1,digit2;
2315 int idx = 6;
2316
2317 while (*str && (idx > 0)) {
2318 digit1 = sbmac_parse_xdigit(*str);
2319 if (digit1 < 0)
2320 return -1;
2321 str++;
2322 if (!*str)
2323 return -1;
2324
2325 if ((*str == ':') || (*str == '-')) {
2326 digit2 = digit1;
2327 digit1 = 0;
2328 }
2329 else {
2330 digit2 = sbmac_parse_xdigit(*str);
2331 if (digit2 < 0)
2332 return -1;
2333 str++;
2334 }
2335
2336 *hwaddr++ = (digit1 << 4) | digit2;
2337 idx--;
2338
2339 if (*str == '-')
2340 str++;
2341 if (*str == ':')
2342 str++;
2343 }
2344 return 0;
2345 }
2346 #endif
2347
2348 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2349 {
2350 if (new_mtu > ENET_PACKET_SIZE)
2351 return -EINVAL;
2352 _dev->mtu = new_mtu;
2353 printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2354 return 0;
2355 }
2356
2357 /**********************************************************************
2358 * SBMAC_INIT(dev)
2359 *
2360 * Attach routine - init hardware and hook ourselves into linux
2361 *
2362 * Input parameters:
2363 * dev - net_device structure
2364 *
2365 * Return value:
2366 * status
2367 ********************************************************************* */
2368
2369 static int sbmac_init(struct net_device *dev, int idx)
2370 {
2371 struct sbmac_softc *sc;
2372 unsigned char *eaddr;
2373 uint64_t ea_reg;
2374 int i;
2375
2376 sc = (struct sbmac_softc *)dev->priv;
2377
2378 /* Determine controller base address */
2379
2380 sc->sbm_base = KSEG1ADDR(dev->base_addr);
2381 sc->sbm_dev = dev;
2382 sc->sbe_idx = idx;
2383
2384 eaddr = sc->sbm_hwaddr;
2385
2386 /*
2387 * Read the ethernet address. The firwmare left this programmed
2388 * for us in the ethernet address register for each mac.
2389 */
2390
2391 ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2392 SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0);
2393 for (i = 0; i < 6; i++) {
2394 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2395 ea_reg >>= 8;
2396 }
2397
2398 for (i = 0; i < 6; i++) {
2399 dev->dev_addr[i] = eaddr[i];
2400 }
2401
2402
2403 /*
2404 * Init packet size
2405 */
2406
2407 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2408
2409 /*
2410 * Initialize context (get pointers to registers and stuff), then
2411 * allocate the memory for the descriptor tables.
2412 */
2413
2414 sbmac_initctx(sc);
2415
2416
2417 /*
2418 * Display Ethernet address (this is called during the config
2419 * process so we need to finish off the config message that
2420 * was being displayed)
2421 */
2422 printk(KERN_INFO
2423 "%s: SiByte Ethernet at 0x%08lX, address: %02X-%02X-%02X-%02X-%02X-%02X\n",
2424 dev->name, dev->base_addr,
2425 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2426
2427 /*
2428 * Set up Linux device callins
2429 */
2430
2431 spin_lock_init(&(sc->sbm_lock));
2432
2433 ether_setup(dev);
2434 dev->open = sbmac_open;
2435 dev->hard_start_xmit = sbmac_start_tx;
2436 dev->stop = sbmac_close;
2437 dev->get_stats = sbmac_get_stats;
2438 dev->set_multicast_list = sbmac_set_rx_mode;
2439 dev->do_ioctl = sbmac_mii_ioctl;
2440 dev->tx_timeout = sbmac_tx_timeout;
2441 dev->watchdog_timeo = TX_TIMEOUT;
2442
2443 dev->change_mtu = sb1250_change_mtu;
2444
2445 /* This is needed for PASS2 for Rx H/W checksum feature */
2446 sbmac_set_iphdr_offset(sc);
2447
2448 return 0;
2449 }
2450
2451
2452 static int sbmac_open(struct net_device *dev)
2453 {
2454 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2455
2456 MOD_INC_USE_COUNT;
2457
2458 if (debug > 1) {
2459 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2460 }
2461
2462 /*
2463 * map/route interrupt
2464 */
2465
2466 if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev)) {
2467 MOD_DEC_USE_COUNT;
2468 return -EBUSY;
2469 }
2470
2471 /*
2472 * Configure default speed
2473 */
2474
2475 sbmac_mii_poll(sc,noisy_mii);
2476
2477 /*
2478 * Turn on the channel
2479 */
2480
2481 sbmac_set_channel_state(sc,sbmac_state_on);
2482
2483 /*
2484 * XXX Station address is in dev->dev_addr
2485 */
2486
2487 if (dev->if_port == 0)
2488 dev->if_port = 0;
2489
2490 netif_start_queue(dev);
2491
2492 sbmac_set_rx_mode(dev);
2493
2494 /* Set the timer to check for link beat. */
2495 init_timer(&sc->sbm_timer);
2496 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2497 sc->sbm_timer.data = (unsigned long)dev;
2498 sc->sbm_timer.function = &sbmac_timer;
2499 add_timer(&sc->sbm_timer);
2500
2501 return 0;
2502 }
2503
2504
2505
2506 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2507 {
2508 int bmsr,bmcr,k1stsr,anlpar;
2509 int chg;
2510 char buffer[100];
2511 char *p = buffer;
2512
2513 /* Read the mode status and mode control registers. */
2514 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2515 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2516
2517 /* get the link partner status */
2518 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2519
2520 /* if supported, read the 1000baseT register */
2521 if (bmsr & BMSR_1000BT_XSR) {
2522 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2523 }
2524 else {
2525 k1stsr = 0;
2526 }
2527
2528 chg = 0;
2529
2530 if ((bmsr & BMSR_LINKSTAT) == 0) {
2531 /*
2532 * If link status is down, clear out old info so that when
2533 * it comes back up it will force us to reconfigure speed
2534 */
2535 s->sbm_phy_oldbmsr = 0;
2536 s->sbm_phy_oldanlpar = 0;
2537 s->sbm_phy_oldk1stsr = 0;
2538 return 0;
2539 }
2540
2541 if ((s->sbm_phy_oldbmsr != bmsr) ||
2542 (s->sbm_phy_oldanlpar != anlpar) ||
2543 (s->sbm_phy_oldk1stsr != k1stsr)) {
2544 if (debug > 1) {
2545 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2546 s->sbm_dev->name,
2547 s->sbm_phy_oldbmsr,bmsr,
2548 s->sbm_phy_oldanlpar,anlpar,
2549 s->sbm_phy_oldk1stsr,k1stsr);
2550 }
2551 s->sbm_phy_oldbmsr = bmsr;
2552 s->sbm_phy_oldanlpar = anlpar;
2553 s->sbm_phy_oldk1stsr = k1stsr;
2554 chg = 1;
2555 }
2556
2557 if (chg == 0)
2558 return 0;
2559
2560 p += sprintf(p,"Link speed: ");
2561
2562 if (k1stsr & K1STSR_LP1KFD) {
2563 s->sbm_speed = sbmac_speed_1000;
2564 s->sbm_duplex = sbmac_duplex_full;
2565 s->sbm_fc = sbmac_fc_frame;
2566 p += sprintf(p,"1000BaseT FDX");
2567 }
2568 else if (k1stsr & K1STSR_LP1KHD) {
2569 s->sbm_speed = sbmac_speed_1000;
2570 s->sbm_duplex = sbmac_duplex_half;
2571 s->sbm_fc = sbmac_fc_disabled;
2572 p += sprintf(p,"1000BaseT HDX");
2573 }
2574 else if (anlpar & ANLPAR_TXFD) {
2575 s->sbm_speed = sbmac_speed_100;
2576 s->sbm_duplex = sbmac_duplex_full;
2577 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2578 p += sprintf(p,"100BaseT FDX");
2579 }
2580 else if (anlpar & ANLPAR_TXHD) {
2581 s->sbm_speed = sbmac_speed_100;
2582 s->sbm_duplex = sbmac_duplex_half;
2583 s->sbm_fc = sbmac_fc_disabled;
2584 p += sprintf(p,"100BaseT HDX");
2585 }
2586 else if (anlpar & ANLPAR_10FD) {
2587 s->sbm_speed = sbmac_speed_10;
2588 s->sbm_duplex = sbmac_duplex_full;
2589 s->sbm_fc = sbmac_fc_frame;
2590 p += sprintf(p,"10BaseT FDX");
2591 }
2592 else if (anlpar & ANLPAR_10HD) {
2593 s->sbm_speed = sbmac_speed_10;
2594 s->sbm_duplex = sbmac_duplex_half;
2595 s->sbm_fc = sbmac_fc_collision;
2596 p += sprintf(p,"10BaseT HDX");
2597 }
2598 else {
2599 p += sprintf(p,"Unknown");
2600 }
2601
2602 if (noisy) {
2603 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2604 }
2605
2606 return 1;
2607 }
2608
2609
2610 static void sbmac_timer(unsigned long data)
2611 {
2612 struct net_device *dev = (struct net_device *)data;
2613 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2614 int next_tick = HZ;
2615 int mii_status;
2616
2617 spin_lock_irq (&sc->sbm_lock);
2618
2619 /* make IFF_RUNNING follow the MII status bit "Link established" */
2620 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2621
2622 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2623 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2624 if (mii_status & BMSR_LINKSTAT) {
2625 netif_carrier_on(dev);
2626 }
2627 else {
2628 netif_carrier_off(dev);
2629 }
2630 }
2631
2632 /*
2633 * Poll the PHY to see what speed we should be running at
2634 */
2635
2636 if (sbmac_mii_poll(sc,noisy_mii)) {
2637 if (sc->sbm_state != sbmac_state_off) {
2638 /*
2639 * something changed, restart the channel
2640 */
2641 if (debug > 1) {
2642 printk("%s: restarting channel because speed changed\n",
2643 sc->sbm_dev->name);
2644 }
2645 sbmac_channel_stop(sc);
2646 sbmac_channel_start(sc);
2647 }
2648 }
2649
2650 spin_unlock_irq (&sc->sbm_lock);
2651
2652 sc->sbm_timer.expires = jiffies + next_tick;
2653 add_timer(&sc->sbm_timer);
2654 }
2655
2656
2657 static void sbmac_tx_timeout (struct net_device *dev)
2658 {
2659 struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv;
2660
2661 spin_lock_irq (&sc->sbm_lock);
2662
2663
2664 dev->trans_start = jiffies;
2665 sc->sbm_stats.tx_errors++;
2666
2667 spin_unlock_irq (&sc->sbm_lock);
2668
2669 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2670 }
2671
2672
2673
2674
2675 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2676 {
2677 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2678 unsigned long flags;
2679
2680 spin_lock_irqsave(&sc->sbm_lock, flags);
2681
2682 /* XXX update other stats here */
2683
2684 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2685
2686 return &sc->sbm_stats;
2687 }
2688
2689
2690
2691 static void sbmac_set_rx_mode(struct net_device *dev)
2692 {
2693 unsigned long flags;
2694 int msg_flag = 0;
2695 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2696
2697 spin_lock_irqsave(&sc->sbm_lock, flags);
2698 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2699 /*
2700 * Promiscuous changed.
2701 */
2702
2703 if (dev->flags & IFF_PROMISC) {
2704 /* Unconditionally log net taps. */
2705 msg_flag = 1;
2706 sbmac_promiscuous_mode(sc,1);
2707 }
2708 else {
2709 msg_flag = 2;
2710 sbmac_promiscuous_mode(sc,0);
2711 }
2712 }
2713 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2714
2715 if (msg_flag) {
2716 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2717 dev->name,(msg_flag==1)?"en":"dis");
2718 }
2719
2720 /*
2721 * Program the multicasts. Do this every time.
2722 */
2723
2724 sbmac_setmulti(sc);
2725
2726 }
2727
2728 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2729 {
2730 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2731 u16 *data = (u16 *)&rq->ifr_data;
2732 unsigned long flags;
2733 int retval;
2734
2735 spin_lock_irqsave(&sc->sbm_lock, flags);
2736 retval = 0;
2737
2738 switch(cmd) {
2739 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2740 data[0] = sc->sbm_phys[0] & 0x1f;
2741 /* Fall Through */
2742 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2743 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2744 break;
2745 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2746 if (!capable(CAP_NET_ADMIN)) {
2747 retval = -EPERM;
2748 break;
2749 }
2750 if (debug > 1) {
2751 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2752 data[0],data[1],data[2]);
2753 }
2754 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2755 break;
2756 default:
2757 retval = -EOPNOTSUPP;
2758 }
2759
2760 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2761 return retval;
2762 }
2763
2764 static int sbmac_close(struct net_device *dev)
2765 {
2766 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2767 unsigned long flags;
2768 int irq;
2769
2770 sbmac_set_channel_state(sc,sbmac_state_off);
2771
2772 del_timer_sync(&sc->sbm_timer);
2773
2774 spin_lock_irqsave(&sc->sbm_lock, flags);
2775
2776 netif_stop_queue(dev);
2777
2778 if (debug > 1) {
2779 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2780 }
2781
2782 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2783
2784 irq = dev->irq;
2785 synchronize_irq(irq);
2786 free_irq(irq, dev);
2787
2788 sbdma_emptyring(&(sc->sbm_txdma));
2789 sbdma_emptyring(&(sc->sbm_rxdma));
2790
2791 MOD_DEC_USE_COUNT;
2792
2793 return 0;
2794 }
2795
2796
2797
2798 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2799 static void
2800 sbmac_setup_hwaddr(int chan,char *addr)
2801 {
2802 uint8_t eaddr[6];
2803 uint64_t val;
2804 sbmac_port_t port;
2805
2806 port = A_MAC_CHANNEL_BASE(chan);
2807 sbmac_parse_hwaddr(addr,eaddr);
2808 val = sbmac_addr2reg(eaddr);
2809 SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR),val);
2810 val = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR));
2811 }
2812 #endif
2813
2814 static struct net_device *dev_sbmac[MAX_UNITS] = {0,0,0};
2815
2816 static int __init
2817 sbmac_init_module(void)
2818 {
2819 int idx;
2820 int macidx = 0;
2821 struct net_device *dev;
2822 sbmac_port_t port;
2823 int chip_max_units;
2824
2825 /*
2826 * For bringup when not using the firmware, we can pre-fill
2827 * the MAC addresses using the environment variables
2828 * specified in this file (or maybe from the config file?)
2829 */
2830 #ifdef SBMAC_ETH0_HWADDR
2831 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2832 #endif
2833 #ifdef SBMAC_ETH1_HWADDR
2834 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2835 #endif
2836 #ifdef SBMAC_ETH2_HWADDR
2837 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2838 #endif
2839
2840 /*
2841 * Walk through the Ethernet controllers and find
2842 * those who have their MAC addresses set.
2843 */
2844 switch (soc_type) {
2845 case K_SYS_SOC_TYPE_BCM1250:
2846 case K_SYS_SOC_TYPE_BCM1250_ALT:
2847 chip_max_units = 3;
2848 break;
2849 case K_SYS_SOC_TYPE_BCM1120:
2850 case K_SYS_SOC_TYPE_BCM1125:
2851 case K_SYS_SOC_TYPE_BCM1125H:
2852 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2853 chip_max_units = 2;
2854 break;
2855 default:
2856 chip_max_units = 0;
2857 break;
2858 }
2859 if (chip_max_units > MAX_UNITS)
2860 chip_max_units = MAX_UNITS;
2861
2862 for (idx = 0; idx < chip_max_units; idx++) {
2863
2864 /*
2865 * This is the base address of the MAC.
2866 */
2867
2868 port = A_MAC_CHANNEL_BASE(idx);
2869
2870 /*
2871 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2872 * value for us by the firmware if we're going to use this MAC.
2873 * If we find a zero, skip this MAC.
2874 */
2875
2876 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR));
2877 if (sbmac_orig_hwaddr[idx] == 0) {
2878 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2879 "%lx\n", port);
2880 continue;
2881 }
2882
2883 /*
2884 * Okay, cool. Initialize this MAC.
2885 */
2886
2887 dev = init_etherdev(NULL,sizeof(struct sbmac_softc));
2888 if (!dev)
2889 return -ENOMEM; /* return ENOMEM */
2890
2891 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2892
2893 dev->irq = K_INT_MAC_0 + idx;
2894 dev->base_addr = port;
2895 dev->mem_end = 0;
2896 /*dev->init = sbmac_init;*/
2897 sbmac_init(dev, macidx);
2898
2899 dev_sbmac[macidx] = dev;
2900 macidx++;
2901 }
2902
2903 /*
2904 * Should we care, 'macidx' is the total number of enabled MACs.
2905 */
2906
2907 return 0;
2908 }
2909
2910
2911 static void __exit
2912 sbmac_cleanup_module(void)
2913 {
2914 int idx;
2915 struct net_device *dev;
2916 sbmac_port_t port;
2917 for (idx = 0; idx < MAX_UNITS; idx++) {
2918 dev = dev_sbmac[idx];
2919 if (dev == NULL)
2920 continue;
2921 if (dev->priv != NULL) {
2922 struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv;
2923
2924 unregister_netdev(dev);
2925
2926 sbmac_uninitctx(sc);
2927
2928 }
2929
2930 port = A_MAC_CHANNEL_BASE(idx);
2931 SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR), sbmac_orig_hwaddr[idx] );
2932 kfree(dev);
2933 dev_sbmac[idx] = NULL;
2934 }
2935 }
2936
2937 module_init(sbmac_init_module);
2938 module_exit(sbmac_cleanup_module);
Historical 2.5/2.6 development