2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <linux/sysdev.h>
25 #include <mach/hardware.h>
26 #include <mach/gpio.h>
27 #include <mach/pxa3xx-regs.h>
28 #include <mach/reset.h>
29 #include <mach/ohci.h>
33 #include <mach/regs-intc.h>
40 /* Crystal clock: 13MHz */
41 #define BASE_CLK 13000000
43 /* Ring Oscillator Clock: 60MHz */
44 #define RO_CLK 60000000
46 #define ACCR_D0CS (1 << 26)
47 #define ACCR_PCCE (1 << 11)
49 #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
50 #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
52 /* crystal frequency to static memory controller multiplier (SMCFS) */
53 static unsigned char smcfs_mult
[8] = { 6, 0, 8, 0, 0, 16, };
55 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
56 static unsigned char hss_mult
[4] = { 8, 12, 16, 0 };
59 * Get the clock frequency as reflected by CCSR and the turbo flag.
60 * We assume these values have been applied via a fcs.
61 * If info is not 0 we also display the current settings.
63 unsigned int pxa3xx_get_clk_frequency_khz(int info
)
65 unsigned long acsr
, xclkcfg
;
66 unsigned int t
, xl
, xn
, hss
, ro
, XL
, XN
, CLK
, HSS
;
68 /* Read XCLKCFG register turbo bit */
69 __asm__
__volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg
));
75 xn
= (acsr
>> 8) & 0x7;
76 hss
= (acsr
>> 14) & 0x3;
81 ro
= acsr
& ACCR_D0CS
;
83 CLK
= (ro
) ? RO_CLK
: ((t
) ? XN
: XL
);
84 HSS
= (ro
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
87 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
88 RO_CLK
/ 1000000, (RO_CLK
% 1000000) / 10000,
90 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
91 XL
/ 1000000, (XL
% 1000000) / 10000, xl
);
92 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
93 XN
/ 1000000, (XN
% 1000000) / 10000, xn
,
95 pr_info("HSIO bus clock: %d.%02dMHz\n",
96 HSS
/ 1000000, (HSS
% 1000000) / 10000);
103 * Return the current static memory controller clock frequency
106 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
109 unsigned int smcfs
, clk
= 0;
113 smcfs
= (acsr
>> 23) & 0x7;
114 clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: smcfs_mult
[smcfs
] * BASE_CLK
;
116 return (clk
/ 10000);
119 void pxa3xx_clear_reset_status(unsigned int mask
)
121 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
126 * Return the current AC97 clock frequency.
128 static unsigned long clk_pxa3xx_ac97_getrate(struct clk
*clk
)
130 unsigned long rate
= 312000000;
131 unsigned long ac97_div
;
135 /* This may loose precision for some rates but won't for the
136 * standard 24.576MHz.
138 rate
/= (ac97_div
>> 12) & 0x7fff;
139 rate
*= (ac97_div
& 0xfff);
145 * Return the current HSIO bus clock frequency
147 static unsigned long clk_pxa3xx_hsio_getrate(struct clk
*clk
)
150 unsigned int hss
, hsio_clk
;
154 hss
= (acsr
>> 14) & 0x3;
155 hsio_clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
160 void clk_pxa3xx_cken_enable(struct clk
*clk
)
162 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
170 void clk_pxa3xx_cken_disable(struct clk
*clk
)
172 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
180 const struct clkops clk_pxa3xx_cken_ops
= {
181 .enable
= clk_pxa3xx_cken_enable
,
182 .disable
= clk_pxa3xx_cken_disable
,
185 static const struct clkops clk_pxa3xx_hsio_ops
= {
186 .enable
= clk_pxa3xx_cken_enable
,
187 .disable
= clk_pxa3xx_cken_disable
,
188 .getrate
= clk_pxa3xx_hsio_getrate
,
191 static const struct clkops clk_pxa3xx_ac97_ops
= {
192 .enable
= clk_pxa3xx_cken_enable
,
193 .disable
= clk_pxa3xx_cken_disable
,
194 .getrate
= clk_pxa3xx_ac97_getrate
,
197 static void clk_pout_enable(struct clk
*clk
)
202 static void clk_pout_disable(struct clk
*clk
)
207 static const struct clkops clk_pout_ops
= {
208 .enable
= clk_pout_enable
,
209 .disable
= clk_pout_disable
,
212 static void clk_dummy_enable(struct clk
*clk
)
216 static void clk_dummy_disable(struct clk
*clk
)
220 static const struct clkops clk_dummy_ops
= {
221 .enable
= clk_dummy_enable
,
222 .disable
= clk_dummy_disable
,
225 static struct clk clk_pxa3xx_pout
= {
226 .ops
= &clk_pout_ops
,
231 static struct clk clk_dummy
= {
232 .ops
= &clk_dummy_ops
,
235 static DEFINE_PXA3_CK(pxa3xx_lcd
, LCD
, &clk_pxa3xx_hsio_ops
);
236 static DEFINE_PXA3_CK(pxa3xx_camera
, CAMERA
, &clk_pxa3xx_hsio_ops
);
237 static DEFINE_PXA3_CK(pxa3xx_ac97
, AC97
, &clk_pxa3xx_ac97_ops
);
238 static DEFINE_PXA3_CKEN(pxa3xx_ffuart
, FFUART
, 14857000, 1);
239 static DEFINE_PXA3_CKEN(pxa3xx_btuart
, BTUART
, 14857000, 1);
240 static DEFINE_PXA3_CKEN(pxa3xx_stuart
, STUART
, 14857000, 1);
241 static DEFINE_PXA3_CKEN(pxa3xx_i2c
, I2C
, 32842000, 0);
242 static DEFINE_PXA3_CKEN(pxa3xx_udc
, UDC
, 48000000, 5);
243 static DEFINE_PXA3_CKEN(pxa3xx_usbh
, USBH
, 48000000, 0);
244 static DEFINE_PXA3_CKEN(pxa3xx_u2d
, USB2
, 48000000, 0);
245 static DEFINE_PXA3_CKEN(pxa3xx_keypad
, KEYPAD
, 32768, 0);
246 static DEFINE_PXA3_CKEN(pxa3xx_ssp1
, SSP1
, 13000000, 0);
247 static DEFINE_PXA3_CKEN(pxa3xx_ssp2
, SSP2
, 13000000, 0);
248 static DEFINE_PXA3_CKEN(pxa3xx_ssp3
, SSP3
, 13000000, 0);
249 static DEFINE_PXA3_CKEN(pxa3xx_ssp4
, SSP4
, 13000000, 0);
250 static DEFINE_PXA3_CKEN(pxa3xx_pwm0
, PWM0
, 13000000, 0);
251 static DEFINE_PXA3_CKEN(pxa3xx_pwm1
, PWM1
, 13000000, 0);
252 static DEFINE_PXA3_CKEN(pxa3xx_mmc1
, MMC1
, 19500000, 0);
253 static DEFINE_PXA3_CKEN(pxa3xx_mmc2
, MMC2
, 19500000, 0);
255 static struct clk_lookup pxa3xx_clkregs
[] = {
256 INIT_CLKREG(&clk_pxa3xx_pout
, NULL
, "CLK_POUT"),
257 /* Power I2C clock is always on */
258 INIT_CLKREG(&clk_dummy
, "pxa3xx-pwri2c.1", NULL
),
259 INIT_CLKREG(&clk_pxa3xx_lcd
, "pxa2xx-fb", NULL
),
260 INIT_CLKREG(&clk_pxa3xx_camera
, NULL
, "CAMCLK"),
261 INIT_CLKREG(&clk_pxa3xx_ac97
, NULL
, "AC97CLK"),
262 INIT_CLKREG(&clk_pxa3xx_ffuart
, "pxa2xx-uart.0", NULL
),
263 INIT_CLKREG(&clk_pxa3xx_btuart
, "pxa2xx-uart.1", NULL
),
264 INIT_CLKREG(&clk_pxa3xx_stuart
, "pxa2xx-uart.2", NULL
),
265 INIT_CLKREG(&clk_pxa3xx_stuart
, "pxa2xx-ir", "UARTCLK"),
266 INIT_CLKREG(&clk_pxa3xx_i2c
, "pxa2xx-i2c.0", NULL
),
267 INIT_CLKREG(&clk_pxa3xx_udc
, "pxa27x-udc", NULL
),
268 INIT_CLKREG(&clk_pxa3xx_usbh
, "pxa27x-ohci", NULL
),
269 INIT_CLKREG(&clk_pxa3xx_u2d
, NULL
, "U2DCLK"),
270 INIT_CLKREG(&clk_pxa3xx_keypad
, "pxa27x-keypad", NULL
),
271 INIT_CLKREG(&clk_pxa3xx_ssp1
, "pxa27x-ssp.0", NULL
),
272 INIT_CLKREG(&clk_pxa3xx_ssp2
, "pxa27x-ssp.1", NULL
),
273 INIT_CLKREG(&clk_pxa3xx_ssp3
, "pxa27x-ssp.2", NULL
),
274 INIT_CLKREG(&clk_pxa3xx_ssp4
, "pxa27x-ssp.3", NULL
),
275 INIT_CLKREG(&clk_pxa3xx_pwm0
, "pxa27x-pwm.0", NULL
),
276 INIT_CLKREG(&clk_pxa3xx_pwm1
, "pxa27x-pwm.1", NULL
),
277 INIT_CLKREG(&clk_pxa3xx_mmc1
, "pxa2xx-mci.0", NULL
),
278 INIT_CLKREG(&clk_pxa3xx_mmc2
, "pxa2xx-mci.1", NULL
),
283 #define ISRAM_START 0x5c000000
284 #define ISRAM_SIZE SZ_256K
286 static void __iomem
*sram
;
287 static unsigned long wakeup_src
;
289 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
290 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
292 enum { SLEEP_SAVE_CKENA
,
299 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save
)
306 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save
)
314 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
315 * memory controller has to be reinitialised, so we place some code
316 * in the SRAM to perform this function.
318 * We disable FIQs across the standby - otherwise, we might receive a
319 * FIQ while the SDRAM is unavailable.
321 static void pxa3xx_cpu_standby(unsigned int pwrmode
)
323 extern const char pm_enter_standby_start
[], pm_enter_standby_end
[];
324 void (*fn
)(unsigned int) = (void __force
*)(sram
+ 0x8000);
326 memcpy_toio(sram
+ 0x8000, pm_enter_standby_start
,
327 pm_enter_standby_end
- pm_enter_standby_start
);
331 AD2D0ER
= wakeup_src
;
345 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
346 * PXA3xx development kits assumes that the resuming process continues
347 * with the address stored within the first 4 bytes of SDRAM. The PSPR
348 * register is used privately by BootROM and OBM, and _must_ be set to
349 * 0x5c014000 for the moment.
351 static void pxa3xx_cpu_pm_suspend(void)
353 volatile unsigned long *p
= (volatile void *)0xc0000000;
354 unsigned long saved_data
= *p
;
356 extern void pxa3xx_cpu_suspend(void);
357 extern void pxa3xx_cpu_resume(void);
359 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
360 CKENA
|= (1 << CKEN_BOOT
) | (1 << CKEN_TPM
);
361 CKENB
|= 1 << (CKEN_HSIO2
& 0x1f);
363 /* clear and setup wakeup source */
369 PCFR
|= (1u << 13); /* L1_DIS */
370 PCFR
&= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
374 /* overwrite with the resume address */
375 *p
= virt_to_phys(pxa3xx_cpu_resume
);
377 pxa3xx_cpu_suspend();
384 static void pxa3xx_cpu_pm_enter(suspend_state_t state
)
387 * Don't sleep if no wakeup sources are defined
389 if (wakeup_src
== 0) {
390 printk(KERN_ERR
"Not suspending: no wakeup sources\n");
395 case PM_SUSPEND_STANDBY
:
396 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2
);
400 pxa3xx_cpu_pm_suspend();
405 static int pxa3xx_cpu_pm_valid(suspend_state_t state
)
407 return state
== PM_SUSPEND_MEM
|| state
== PM_SUSPEND_STANDBY
;
410 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns
= {
411 .save_count
= SLEEP_SAVE_COUNT
,
412 .save
= pxa3xx_cpu_pm_save
,
413 .restore
= pxa3xx_cpu_pm_restore
,
414 .valid
= pxa3xx_cpu_pm_valid
,
415 .enter
= pxa3xx_cpu_pm_enter
,
418 static void __init
pxa3xx_init_pm(void)
420 sram
= ioremap(ISRAM_START
, ISRAM_SIZE
);
422 printk(KERN_ERR
"Unable to map ISRAM: disabling standby/suspend\n");
427 * Since we copy wakeup code into the SRAM, we need to ensure
428 * that it is preserved over the low power modes. Note: bit 8
429 * is undocumented in the developer manual, but must be set.
431 AD1R
|= ADXR_L2
| ADXR_R0
;
432 AD2R
|= ADXR_L2
| ADXR_R0
;
433 AD3R
|= ADXR_L2
| ADXR_R0
;
436 * Clear the resume enable registers.
443 pxa_cpu_pm_fns
= &pxa3xx_cpu_pm_fns
;
446 static int pxa3xx_set_wake(unsigned int irq
, unsigned int on
)
448 unsigned long flags
, mask
= 0;
452 mask
= ADXER_MFP_WSSP3
;
465 mask
= ADXER_MFP_WAC97
;
471 mask
= ADXER_MFP_WSSP2
;
474 mask
= ADXER_MFP_WI2C
;
477 mask
= ADXER_MFP_WUART3
;
480 mask
= ADXER_MFP_WUART2
;
483 mask
= ADXER_MFP_WUART1
;
486 mask
= ADXER_MFP_WMMC1
;
489 mask
= ADXER_MFP_WSSP1
;
495 mask
= ADXER_MFP_WSSP4
;
504 mask
= ADXER_MFP_WMMC2
;
507 mask
= ADXER_MFP_WFLASH
;
513 mask
= ADXER_WEXTWAKE0
;
516 mask
= ADXER_WEXTWAKE1
;
519 mask
= ADXER_MFP_GEN12
;
525 local_irq_save(flags
);
530 local_irq_restore(flags
);
535 static inline void pxa3xx_init_pm(void) {}
536 #define pxa3xx_set_wake NULL
539 static void pxa_ack_ext_wakeup(unsigned int irq
)
541 PECR
|= PECR_IS(irq
- IRQ_WAKEUP0
);
544 static void pxa_mask_ext_wakeup(unsigned int irq
)
546 ICMR2
&= ~(1 << ((irq
- PXA_IRQ(0)) & 0x1f));
547 PECR
&= ~PECR_IE(irq
- IRQ_WAKEUP0
);
550 static void pxa_unmask_ext_wakeup(unsigned int irq
)
552 ICMR2
|= 1 << ((irq
- PXA_IRQ(0)) & 0x1f);
553 PECR
|= PECR_IE(irq
- IRQ_WAKEUP0
);
556 static struct irq_chip pxa_ext_wakeup_chip
= {
558 .ack
= pxa_ack_ext_wakeup
,
559 .mask
= pxa_mask_ext_wakeup
,
560 .unmask
= pxa_unmask_ext_wakeup
,
563 static void __init
pxa_init_ext_wakeup_irq(set_wake_t fn
)
567 for (irq
= IRQ_WAKEUP0
; irq
<= IRQ_WAKEUP1
; irq
++) {
568 set_irq_chip(irq
, &pxa_ext_wakeup_chip
);
569 set_irq_handler(irq
, handle_edge_irq
);
570 set_irq_flags(irq
, IRQF_VALID
);
573 pxa_ext_wakeup_chip
.set_wake
= fn
;
576 void __init
pxa3xx_init_irq(void)
578 /* enable CP6 access */
580 __asm__
__volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value
));
582 __asm__
__volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value
));
584 pxa_init_irq(56, pxa3xx_set_wake
);
585 pxa_init_ext_wakeup_irq(pxa3xx_set_wake
);
586 pxa_init_gpio(IRQ_GPIO_2_x
, 2, 127, NULL
);
590 * device registration specific to PXA3xx.
593 void __init
pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data
*info
)
595 pxa_register_device(&pxa3xx_device_i2c_power
, info
);
598 static struct platform_device
*devices
[] __initdata
= {
611 static struct sys_device pxa3xx_sysdev
[] = {
613 .cls
= &pxa_irq_sysclass
,
615 .cls
= &pxa3xx_mfp_sysclass
,
617 .cls
= &pxa_gpio_sysclass
,
621 static int __init
pxa3xx_init(void)
625 if (cpu_is_pxa3xx()) {
630 * clear RDH bit every time after reset
632 * Note: the last 3 bits DxS are write-1-to-clear so carefully
633 * preserve them here in case they will be referenced later
635 ASCR
&= ~(ASCR_RDH
| ASCR_D1S
| ASCR_D2S
| ASCR_D3S
);
637 clkdev_add_table(pxa3xx_clkregs
, ARRAY_SIZE(pxa3xx_clkregs
));
639 if ((ret
= pxa_init_dma(IRQ_DMA
, 32)))
644 for (i
= 0; i
< ARRAY_SIZE(pxa3xx_sysdev
); i
++) {
645 ret
= sysdev_register(&pxa3xx_sysdev
[i
]);
647 pr_err("failed to register sysdev[%d]\n", i
);
650 ret
= platform_add_devices(devices
, ARRAY_SIZE(devices
));
656 postcore_initcall(pxa3xx_init
);