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eeepc-wmi: Build fix
[linux-2.6/cjktty.git] / arch / arm / mach-davinci / dma.c
blob53137387aee18b69a35526dacea7d9b0e1267f3c
1 /*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <mach/edma.h>
29
30 /* Offsets matching "struct edmacc_param" */
31 #define PARM_OPT 0x00
32 #define PARM_SRC 0x04
33 #define PARM_A_B_CNT 0x08
34 #define PARM_DST 0x0c
35 #define PARM_SRC_DST_BIDX 0x10
36 #define PARM_LINK_BCNTRLD 0x14
37 #define PARM_SRC_DST_CIDX 0x18
38 #define PARM_CCNT 0x1c
39
40 #define PARM_SIZE 0x20
41
42 /* Offsets for EDMA CC global channel registers and their shadows */
43 #define SH_ER 0x00 /* 64 bits */
44 #define SH_ECR 0x08 /* 64 bits */
45 #define SH_ESR 0x10 /* 64 bits */
46 #define SH_CER 0x18 /* 64 bits */
47 #define SH_EER 0x20 /* 64 bits */
48 #define SH_EECR 0x28 /* 64 bits */
49 #define SH_EESR 0x30 /* 64 bits */
50 #define SH_SER 0x38 /* 64 bits */
51 #define SH_SECR 0x40 /* 64 bits */
52 #define SH_IER 0x50 /* 64 bits */
53 #define SH_IECR 0x58 /* 64 bits */
54 #define SH_IESR 0x60 /* 64 bits */
55 #define SH_IPR 0x68 /* 64 bits */
56 #define SH_ICR 0x70 /* 64 bits */
57 #define SH_IEVAL 0x78
58 #define SH_QER 0x80
59 #define SH_QEER 0x84
60 #define SH_QEECR 0x88
61 #define SH_QEESR 0x8c
62 #define SH_QSER 0x90
63 #define SH_QSECR 0x94
64 #define SH_SIZE 0x200
65
66 /* Offsets for EDMA CC global registers */
67 #define EDMA_REV 0x0000
68 #define EDMA_CCCFG 0x0004
69 #define EDMA_QCHMAP 0x0200 /* 8 registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
71 #define EDMA_QDMAQNUM 0x0260
72 #define EDMA_QUETCMAP 0x0280
73 #define EDMA_QUEPRI 0x0284
74 #define EDMA_EMR 0x0300 /* 64 bits */
75 #define EDMA_EMCR 0x0308 /* 64 bits */
76 #define EDMA_QEMR 0x0310
77 #define EDMA_QEMCR 0x0314
78 #define EDMA_CCERR 0x0318
79 #define EDMA_CCERRCLR 0x031c
80 #define EDMA_EEVAL 0x0320
81 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
82 #define EDMA_QRAE 0x0380 /* 4 registers */
83 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
84 #define EDMA_QSTAT 0x0600 /* 2 registers */
85 #define EDMA_QWMTHRA 0x0620
86 #define EDMA_QWMTHRB 0x0624
87 #define EDMA_CCSTAT 0x0640
88
89 #define EDMA_M 0x1000 /* global channel registers */
90 #define EDMA_ECR 0x1008
91 #define EDMA_ECRH 0x100C
92 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
93 #define EDMA_PARM 0x4000 /* 128 param entries */
94
95 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
96
97 #define EDMA_DCHMAP 0x0100 /* 64 registers */
98 #define CHMAP_EXIST BIT(24)
99
100 #define EDMA_MAX_DMACH 64
101 #define EDMA_MAX_PARAMENTRY 512
102 #define EDMA_MAX_CC 2
103
104
105 /*****************************************************************************/
106
107 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
108
109 static inline unsigned int edma_read(unsigned ctlr, int offset)
110 {
111 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
112 }
113
114 static inline void edma_write(unsigned ctlr, int offset, int val)
115 {
116 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
117 }
118 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
119 unsigned or)
120 {
121 unsigned val = edma_read(ctlr, offset);
122 val &= and;
123 val |= or;
124 edma_write(ctlr, offset, val);
125 }
126 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
127 {
128 unsigned val = edma_read(ctlr, offset);
129 val &= and;
130 edma_write(ctlr, offset, val);
131 }
132 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
133 {
134 unsigned val = edma_read(ctlr, offset);
135 val |= or;
136 edma_write(ctlr, offset, val);
137 }
138 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
139 {
140 return edma_read(ctlr, offset + (i << 2));
141 }
142 static inline void edma_write_array(unsigned ctlr, int offset, int i,
143 unsigned val)
144 {
145 edma_write(ctlr, offset + (i << 2), val);
146 }
147 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
148 unsigned and, unsigned or)
149 {
150 edma_modify(ctlr, offset + (i << 2), and, or);
151 }
152 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
153 {
154 edma_or(ctlr, offset + (i << 2), or);
155 }
156 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
157 unsigned or)
158 {
159 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
160 }
161 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
162 unsigned val)
163 {
164 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
165 }
166 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
167 {
168 return edma_read(ctlr, EDMA_SHADOW0 + offset);
169 }
170 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
171 int i)
172 {
173 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
174 }
175 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
176 {
177 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
178 }
179 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
180 unsigned val)
181 {
182 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
183 }
184 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
185 int param_no)
186 {
187 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
188 }
189 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
190 unsigned val)
191 {
192 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
193 }
194 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
195 unsigned and, unsigned or)
196 {
197 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
198 }
199 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
200 unsigned and)
201 {
202 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
203 }
204 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
205 unsigned or)
206 {
207 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
208 }
209
210 /*****************************************************************************/
211
212 /* actual number of DMA channels and slots on this silicon */
213 struct edma {
214 /* how many dma resources of each type */
215 unsigned num_channels;
216 unsigned num_region;
217 unsigned num_slots;
218 unsigned num_tc;
219 unsigned num_cc;
220 enum dma_event_q default_queue;
221
222 /* list of channels with no even trigger; terminated by "-1" */
223 const s8 *noevent;
224
225 /* The edma_inuse bit for each PaRAM slot is clear unless the
226 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
227 */
228 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
229
230 /* The edma_unused bit for each channel is clear unless
231 * it is not being used on this platform. It uses a bit
232 * of SOC-specific initialization code.
233 */
234 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
235
236 unsigned irq_res_start;
237 unsigned irq_res_end;
238
239 struct dma_interrupt_data {
240 void (*callback)(unsigned channel, unsigned short ch_status,
241 void *data);
242 void *data;
243 } intr_data[EDMA_MAX_DMACH];
244 };
245
246 static struct edma *edma_info[EDMA_MAX_CC];
247 static int arch_num_cc;
248
249 /* dummy param set used to (re)initialize parameter RAM slots */
250 static const struct edmacc_param dummy_paramset = {
251 .link_bcntrld = 0xffff,
252 .ccnt = 1,
253 };
254
255 /*****************************************************************************/
256
257 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
258 enum dma_event_q queue_no)
259 {
260 int bit = (ch_no & 0x7) * 4;
261
262 /* default to low priority queue */
263 if (queue_no == EVENTQ_DEFAULT)
264 queue_no = edma_info[ctlr]->default_queue;
265
266 queue_no &= 7;
267 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
268 ~(0x7 << bit), queue_no << bit);
269 }
270
271 static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
272 {
273 int bit = queue_no * 4;
274 edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
275 }
276
277 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
278 int priority)
279 {
280 int bit = queue_no * 4;
281 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
282 ((priority & 0x7) << bit));
283 }
284
285 /**
286 * map_dmach_param - Maps channel number to param entry number
287 *
288 * This maps the dma channel number to param entry numberter. In
289 * other words using the DMA channel mapping registers a param entry
290 * can be mapped to any channel
291 *
292 * Callers are responsible for ensuring the channel mapping logic is
293 * included in that particular EDMA variant (Eg : dm646x)
294 *
295 */
296 static void __init map_dmach_param(unsigned ctlr)
297 {
298 int i;
299 for (i = 0; i < EDMA_MAX_DMACH; i++)
300 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
301 }
302
303 static inline void
304 setup_dma_interrupt(unsigned lch,
305 void (*callback)(unsigned channel, u16 ch_status, void *data),
306 void *data)
307 {
308 unsigned ctlr;
309
310 ctlr = EDMA_CTLR(lch);
311 lch = EDMA_CHAN_SLOT(lch);
312
313 if (!callback) {
314 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
315 (1 << (lch & 0x1f)));
316 }
317
318 edma_info[ctlr]->intr_data[lch].callback = callback;
319 edma_info[ctlr]->intr_data[lch].data = data;
320
321 if (callback) {
322 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
323 (1 << (lch & 0x1f)));
324 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
325 (1 << (lch & 0x1f)));
326 }
327 }
328
329 static int irq2ctlr(int irq)
330 {
331 if (irq >= edma_info[0]->irq_res_start &&
332 irq <= edma_info[0]->irq_res_end)
333 return 0;
334 else if (irq >= edma_info[1]->irq_res_start &&
335 irq <= edma_info[1]->irq_res_end)
336 return 1;
337
338 return -1;
339 }
340
341 /******************************************************************************
342 *
343 * DMA interrupt handler
344 *
345 *****************************************************************************/
346 static irqreturn_t dma_irq_handler(int irq, void *data)
347 {
348 int i;
349 unsigned ctlr;
350 unsigned int cnt = 0;
351
352 ctlr = irq2ctlr(irq);
353
354 dev_dbg(data, "dma_irq_handler\n");
355
356 if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
357 && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
358 return IRQ_NONE;
359
360 while (1) {
361 int j;
362 if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
363 j = 0;
364 else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
365 j = 1;
366 else
367 break;
368 dev_dbg(data, "IPR%d %08x\n", j,
369 edma_shadow0_read_array(ctlr, SH_IPR, j));
370 for (i = 0; i < 32; i++) {
371 int k = (j << 5) + i;
372 if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
373 (1 << i)) {
374 /* Clear the corresponding IPR bits */
375 edma_shadow0_write_array(ctlr, SH_ICR, j,
376 (1 << i));
377 if (edma_info[ctlr]->intr_data[k].callback) {
378 edma_info[ctlr]->intr_data[k].callback(
379 k, DMA_COMPLETE,
380 edma_info[ctlr]->intr_data[k].
381 data);
382 }
383 }
384 }
385 cnt++;
386 if (cnt > 10)
387 break;
388 }
389 edma_shadow0_write(ctlr, SH_IEVAL, 1);
390 return IRQ_HANDLED;
391 }
392
393 /******************************************************************************
394 *
395 * DMA error interrupt handler
396 *
397 *****************************************************************************/
398 static irqreturn_t dma_ccerr_handler(int irq, void *data)
399 {
400 int i;
401 unsigned ctlr;
402 unsigned int cnt = 0;
403
404 ctlr = irq2ctlr(irq);
405
406 dev_dbg(data, "dma_ccerr_handler\n");
407
408 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
409 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
410 (edma_read(ctlr, EDMA_QEMR) == 0) &&
411 (edma_read(ctlr, EDMA_CCERR) == 0))
412 return IRQ_NONE;
413
414 while (1) {
415 int j = -1;
416 if (edma_read_array(ctlr, EDMA_EMR, 0))
417 j = 0;
418 else if (edma_read_array(ctlr, EDMA_EMR, 1))
419 j = 1;
420 if (j >= 0) {
421 dev_dbg(data, "EMR%d %08x\n", j,
422 edma_read_array(ctlr, EDMA_EMR, j));
423 for (i = 0; i < 32; i++) {
424 int k = (j << 5) + i;
425 if (edma_read_array(ctlr, EDMA_EMR, j) &
426 (1 << i)) {
427 /* Clear the corresponding EMR bits */
428 edma_write_array(ctlr, EDMA_EMCR, j,
429 1 << i);
430 /* Clear any SER */
431 edma_shadow0_write_array(ctlr, SH_SECR,
432 j, (1 << i));
433 if (edma_info[ctlr]->intr_data[k].
434 callback) {
435 edma_info[ctlr]->intr_data[k].
436 callback(k,
437 DMA_CC_ERROR,
438 edma_info[ctlr]->intr_data
439 [k].data);
440 }
441 }
442 }
443 } else if (edma_read(ctlr, EDMA_QEMR)) {
444 dev_dbg(data, "QEMR %02x\n",
445 edma_read(ctlr, EDMA_QEMR));
446 for (i = 0; i < 8; i++) {
447 if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
448 /* Clear the corresponding IPR bits */
449 edma_write(ctlr, EDMA_QEMCR, 1 << i);
450 edma_shadow0_write(ctlr, SH_QSECR,
451 (1 << i));
452
453 /* NOTE: not reported!! */
454 }
455 }
456 } else if (edma_read(ctlr, EDMA_CCERR)) {
457 dev_dbg(data, "CCERR %08x\n",
458 edma_read(ctlr, EDMA_CCERR));
459 /* FIXME: CCERR.BIT(16) ignored! much better
460 * to just write CCERRCLR with CCERR value...
461 */
462 for (i = 0; i < 8; i++) {
463 if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
464 /* Clear the corresponding IPR bits */
465 edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
466
467 /* NOTE: not reported!! */
468 }
469 }
470 }
471 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
472 && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
473 && (edma_read(ctlr, EDMA_QEMR) == 0)
474 && (edma_read(ctlr, EDMA_CCERR) == 0)) {
475 break;
476 }
477 cnt++;
478 if (cnt > 10)
479 break;
480 }
481 edma_write(ctlr, EDMA_EEVAL, 1);
482 return IRQ_HANDLED;
483 }
484
485 /******************************************************************************
486 *
487 * Transfer controller error interrupt handlers
488 *
489 *****************************************************************************/
490
491 #define tc_errs_handled false /* disabled as long as they're NOPs */
492
493 static irqreturn_t dma_tc0err_handler(int irq, void *data)
494 {
495 dev_dbg(data, "dma_tc0err_handler\n");
496 return IRQ_HANDLED;
497 }
498
499 static irqreturn_t dma_tc1err_handler(int irq, void *data)
500 {
501 dev_dbg(data, "dma_tc1err_handler\n");
502 return IRQ_HANDLED;
503 }
504
505 static int reserve_contiguous_slots(int ctlr, unsigned int id,
506 unsigned int num_slots,
507 unsigned int start_slot)
508 {
509 int i, j;
510 unsigned int count = num_slots;
511 int stop_slot = start_slot;
512 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
513
514 for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
515 j = EDMA_CHAN_SLOT(i);
516 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
517 /* Record our current beginning slot */
518 if (count == num_slots)
519 stop_slot = i;
520
521 count--;
522 set_bit(j, tmp_inuse);
523
524 if (count == 0)
525 break;
526 } else {
527 clear_bit(j, tmp_inuse);
528
529 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
530 stop_slot = i;
531 break;
532 } else
533 count = num_slots;
534 }
535 }
536
537 /*
538 * We have to clear any bits that we set
539 * if we run out parameter RAM slots, i.e we do find a set
540 * of contiguous parameter RAM slots but do not find the exact number
541 * requested as we may reach the total number of parameter RAM slots
542 */
543 if (i == edma_info[ctlr]->num_slots)
544 stop_slot = i;
545
546 for (j = start_slot; j < stop_slot; j++)
547 if (test_bit(j, tmp_inuse))
548 clear_bit(j, edma_info[ctlr]->edma_inuse);
549
550 if (count)
551 return -EBUSY;
552
553 for (j = i - num_slots + 1; j <= i; ++j)
554 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
555 &dummy_paramset, PARM_SIZE);
556
557 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
558 }
559
560 static int prepare_unused_channel_list(struct device *dev, void *data)
561 {
562 struct platform_device *pdev = to_platform_device(dev);
563 int i, ctlr;
564
565 for (i = 0; i < pdev->num_resources; i++) {
566 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
567 (int)pdev->resource[i].start >= 0) {
568 ctlr = EDMA_CTLR(pdev->resource[i].start);
569 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
570 edma_info[ctlr]->edma_unused);
571 }
572 }
573
574 return 0;
575 }
576
577 /*-----------------------------------------------------------------------*/
578
579 static bool unused_chan_list_done;
580
581 /* Resource alloc/free: dma channels, parameter RAM slots */
582
583 /**
584 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
585 * @channel: specific channel to allocate; negative for "any unmapped channel"
586 * @callback: optional; to be issued on DMA completion or errors
587 * @data: passed to callback
588 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
589 * Controller (TC) executes requests using this channel. Use
590 * EVENTQ_DEFAULT unless you really need a high priority queue.
591 *
592 * This allocates a DMA channel and its associated parameter RAM slot.
593 * The parameter RAM is initialized to hold a dummy transfer.
594 *
595 * Normal use is to pass a specific channel number as @channel, to make
596 * use of hardware events mapped to that channel. When the channel will
597 * be used only for software triggering or event chaining, channels not
598 * mapped to hardware events (or mapped to unused events) are preferable.
599 *
600 * DMA transfers start from a channel using edma_start(), or by
601 * chaining. When the transfer described in that channel's parameter RAM
602 * slot completes, that slot's data may be reloaded through a link.
603 *
604 * DMA errors are only reported to the @callback associated with the
605 * channel driving that transfer, but transfer completion callbacks can
606 * be sent to another channel under control of the TCC field in
607 * the option word of the transfer's parameter RAM set. Drivers must not
608 * use DMA transfer completion callbacks for channels they did not allocate.
609 * (The same applies to TCC codes used in transfer chaining.)
610 *
611 * Returns the number of the channel, else negative errno.
612 */
613 int edma_alloc_channel(int channel,
614 void (*callback)(unsigned channel, u16 ch_status, void *data),
615 void *data,
616 enum dma_event_q eventq_no)
617 {
618 unsigned i, done = 0, ctlr = 0;
619 int ret = 0;
620
621 if (!unused_chan_list_done) {
622 /*
623 * Scan all the platform devices to find out the EDMA channels
624 * used and clear them in the unused list, making the rest
625 * available for ARM usage.
626 */
627 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
628 prepare_unused_channel_list);
629 if (ret < 0)
630 return ret;
631
632 unused_chan_list_done = true;
633 }
634
635 if (channel >= 0) {
636 ctlr = EDMA_CTLR(channel);
637 channel = EDMA_CHAN_SLOT(channel);
638 }
639
640 if (channel < 0) {
641 for (i = 0; i < arch_num_cc; i++) {
642 channel = 0;
643 for (;;) {
644 channel = find_next_bit(edma_info[i]->
645 edma_unused,
646 edma_info[i]->num_channels,
647 channel);
648 if (channel == edma_info[i]->num_channels)
649 break;
650 if (!test_and_set_bit(channel,
651 edma_info[i]->edma_inuse)) {
652 done = 1;
653 ctlr = i;
654 break;
655 }
656 channel++;
657 }
658 if (done)
659 break;
660 }
661 if (!done)
662 return -ENOMEM;
663 } else if (channel >= edma_info[ctlr]->num_channels) {
664 return -EINVAL;
665 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
666 return -EBUSY;
667 }
668
669 /* ensure access through shadow region 0 */
670 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
671
672 /* ensure no events are pending */
673 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
674 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
675 &dummy_paramset, PARM_SIZE);
676
677 if (callback)
678 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
679 callback, data);
680
681 map_dmach_queue(ctlr, channel, eventq_no);
682
683 return EDMA_CTLR_CHAN(ctlr, channel);
684 }
685 EXPORT_SYMBOL(edma_alloc_channel);
686
687
688 /**
689 * edma_free_channel - deallocate DMA channel
690 * @channel: dma channel returned from edma_alloc_channel()
691 *
692 * This deallocates the DMA channel and associated parameter RAM slot
693 * allocated by edma_alloc_channel().
694 *
695 * Callers are responsible for ensuring the channel is inactive, and
696 * will not be reactivated by linking, chaining, or software calls to
697 * edma_start().
698 */
699 void edma_free_channel(unsigned channel)
700 {
701 unsigned ctlr;
702
703 ctlr = EDMA_CTLR(channel);
704 channel = EDMA_CHAN_SLOT(channel);
705
706 if (channel >= edma_info[ctlr]->num_channels)
707 return;
708
709 setup_dma_interrupt(channel, NULL, NULL);
710 /* REVISIT should probably take out of shadow region 0 */
711
712 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
713 &dummy_paramset, PARM_SIZE);
714 clear_bit(channel, edma_info[ctlr]->edma_inuse);
715 }
716 EXPORT_SYMBOL(edma_free_channel);
717
718 /**
719 * edma_alloc_slot - allocate DMA parameter RAM
720 * @slot: specific slot to allocate; negative for "any unused slot"
721 *
722 * This allocates a parameter RAM slot, initializing it to hold a
723 * dummy transfer. Slots allocated using this routine have not been
724 * mapped to a hardware DMA channel, and will normally be used by
725 * linking to them from a slot associated with a DMA channel.
726 *
727 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
728 * slots may be allocated on behalf of DSP firmware.
729 *
730 * Returns the number of the slot, else negative errno.
731 */
732 int edma_alloc_slot(unsigned ctlr, int slot)
733 {
734 if (slot >= 0)
735 slot = EDMA_CHAN_SLOT(slot);
736
737 if (slot < 0) {
738 slot = edma_info[ctlr]->num_channels;
739 for (;;) {
740 slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
741 edma_info[ctlr]->num_slots, slot);
742 if (slot == edma_info[ctlr]->num_slots)
743 return -ENOMEM;
744 if (!test_and_set_bit(slot,
745 edma_info[ctlr]->edma_inuse))
746 break;
747 }
748 } else if (slot < edma_info[ctlr]->num_channels ||
749 slot >= edma_info[ctlr]->num_slots) {
750 return -EINVAL;
751 } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
752 return -EBUSY;
753 }
754
755 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
756 &dummy_paramset, PARM_SIZE);
757
758 return EDMA_CTLR_CHAN(ctlr, slot);
759 }
760 EXPORT_SYMBOL(edma_alloc_slot);
761
762 /**
763 * edma_free_slot - deallocate DMA parameter RAM
764 * @slot: parameter RAM slot returned from edma_alloc_slot()
765 *
766 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
767 * Callers are responsible for ensuring the slot is inactive, and will
768 * not be activated.
769 */
770 void edma_free_slot(unsigned slot)
771 {
772 unsigned ctlr;
773
774 ctlr = EDMA_CTLR(slot);
775 slot = EDMA_CHAN_SLOT(slot);
776
777 if (slot < edma_info[ctlr]->num_channels ||
778 slot >= edma_info[ctlr]->num_slots)
779 return;
780
781 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
782 &dummy_paramset, PARM_SIZE);
783 clear_bit(slot, edma_info[ctlr]->edma_inuse);
784 }
785 EXPORT_SYMBOL(edma_free_slot);
786
787
788 /**
789 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
790 * The API will return the starting point of a set of
791 * contiguous parameter RAM slots that have been requested
792 *
793 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
794 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
795 * @count: number of contiguous Paramter RAM slots
796 * @slot - the start value of Parameter RAM slot that should be passed if id
797 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
798 *
799 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
800 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
801 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
802 *
803 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
804 * set of contiguous parameter RAM slots from the "slot" that is passed as an
805 * argument to the API.
806 *
807 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
808 * starts looking for a set of contiguous parameter RAMs from the "slot"
809 * that is passed as an argument to the API. On failure the API will try to
810 * find a set of contiguous Parameter RAM slots from the remaining Parameter
811 * RAM slots
812 */
813 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
814 {
815 /*
816 * The start slot requested should be greater than
817 * the number of channels and lesser than the total number
818 * of slots
819 */
820 if ((id != EDMA_CONT_PARAMS_ANY) &&
821 (slot < edma_info[ctlr]->num_channels ||
822 slot >= edma_info[ctlr]->num_slots))
823 return -EINVAL;
824
825 /*
826 * The number of parameter RAM slots requested cannot be less than 1
827 * and cannot be more than the number of slots minus the number of
828 * channels
829 */
830 if (count < 1 || count >
831 (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels))
832 return -EINVAL;
833
834 switch (id) {
835 case EDMA_CONT_PARAMS_ANY:
836 return reserve_contiguous_slots(ctlr, id, count,
837 edma_info[ctlr]->num_channels);
838 case EDMA_CONT_PARAMS_FIXED_EXACT:
839 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
840 return reserve_contiguous_slots(ctlr, id, count, slot);
841 default:
842 return -EINVAL;
843 }
844
845 }
846 EXPORT_SYMBOL(edma_alloc_cont_slots);
847
848 /**
849 * edma_free_cont_slots - deallocate DMA parameter RAM slots
850 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
851 * @count: the number of contiguous parameter RAM slots to be freed
852 *
853 * This deallocates the parameter RAM slots allocated by
854 * edma_alloc_cont_slots.
855 * Callers/applications need to keep track of sets of contiguous
856 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
857 * API.
858 * Callers are responsible for ensuring the slots are inactive, and will
859 * not be activated.
860 */
861 int edma_free_cont_slots(unsigned slot, int count)
862 {
863 unsigned ctlr, slot_to_free;
864 int i;
865
866 ctlr = EDMA_CTLR(slot);
867 slot = EDMA_CHAN_SLOT(slot);
868
869 if (slot < edma_info[ctlr]->num_channels ||
870 slot >= edma_info[ctlr]->num_slots ||
871 count < 1)
872 return -EINVAL;
873
874 for (i = slot; i < slot + count; ++i) {
875 ctlr = EDMA_CTLR(i);
876 slot_to_free = EDMA_CHAN_SLOT(i);
877
878 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
879 &dummy_paramset, PARM_SIZE);
880 clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
881 }
882
883 return 0;
884 }
885 EXPORT_SYMBOL(edma_free_cont_slots);
886
887 /*-----------------------------------------------------------------------*/
888
889 /* Parameter RAM operations (i) -- read/write partial slots */
890
891 /**
892 * edma_set_src - set initial DMA source address in parameter RAM slot
893 * @slot: parameter RAM slot being configured
894 * @src_port: physical address of source (memory, controller FIFO, etc)
895 * @addressMode: INCR, except in very rare cases
896 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
897 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
898 *
899 * Note that the source address is modified during the DMA transfer
900 * according to edma_set_src_index().
901 */
902 void edma_set_src(unsigned slot, dma_addr_t src_port,
903 enum address_mode mode, enum fifo_width width)
904 {
905 unsigned ctlr;
906
907 ctlr = EDMA_CTLR(slot);
908 slot = EDMA_CHAN_SLOT(slot);
909
910 if (slot < edma_info[ctlr]->num_slots) {
911 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
912
913 if (mode) {
914 /* set SAM and program FWID */
915 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
916 } else {
917 /* clear SAM */
918 i &= ~SAM;
919 }
920 edma_parm_write(ctlr, PARM_OPT, slot, i);
921
922 /* set the source port address
923 in source register of param structure */
924 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
925 }
926 }
927 EXPORT_SYMBOL(edma_set_src);
928
929 /**
930 * edma_set_dest - set initial DMA destination address in parameter RAM slot
931 * @slot: parameter RAM slot being configured
932 * @dest_port: physical address of destination (memory, controller FIFO, etc)
933 * @addressMode: INCR, except in very rare cases
934 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
935 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
936 *
937 * Note that the destination address is modified during the DMA transfer
938 * according to edma_set_dest_index().
939 */
940 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
941 enum address_mode mode, enum fifo_width width)
942 {
943 unsigned ctlr;
944
945 ctlr = EDMA_CTLR(slot);
946 slot = EDMA_CHAN_SLOT(slot);
947
948 if (slot < edma_info[ctlr]->num_slots) {
949 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
950
951 if (mode) {
952 /* set DAM and program FWID */
953 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
954 } else {
955 /* clear DAM */
956 i &= ~DAM;
957 }
958 edma_parm_write(ctlr, PARM_OPT, slot, i);
959 /* set the destination port address
960 in dest register of param structure */
961 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
962 }
963 }
964 EXPORT_SYMBOL(edma_set_dest);
965
966 /**
967 * edma_get_position - returns the current transfer points
968 * @slot: parameter RAM slot being examined
969 * @src: pointer to source port position
970 * @dst: pointer to destination port position
971 *
972 * Returns current source and destination addresses for a particular
973 * parameter RAM slot. Its channel should not be active when this is called.
974 */
975 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
976 {
977 struct edmacc_param temp;
978 unsigned ctlr;
979
980 ctlr = EDMA_CTLR(slot);
981 slot = EDMA_CHAN_SLOT(slot);
982
983 edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
984 if (src != NULL)
985 *src = temp.src;
986 if (dst != NULL)
987 *dst = temp.dst;
988 }
989 EXPORT_SYMBOL(edma_get_position);
990
991 /**
992 * edma_set_src_index - configure DMA source address indexing
993 * @slot: parameter RAM slot being configured
994 * @src_bidx: byte offset between source arrays in a frame
995 * @src_cidx: byte offset between source frames in a block
996 *
997 * Offsets are specified to support either contiguous or discontiguous
998 * memory transfers, or repeated access to a hardware register, as needed.
999 * When accessing hardware registers, both offsets are normally zero.
1000 */
1001 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1002 {
1003 unsigned ctlr;
1004
1005 ctlr = EDMA_CTLR(slot);
1006 slot = EDMA_CHAN_SLOT(slot);
1007
1008 if (slot < edma_info[ctlr]->num_slots) {
1009 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1010 0xffff0000, src_bidx);
1011 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1012 0xffff0000, src_cidx);
1013 }
1014 }
1015 EXPORT_SYMBOL(edma_set_src_index);
1016
1017 /**
1018 * edma_set_dest_index - configure DMA destination address indexing
1019 * @slot: parameter RAM slot being configured
1020 * @dest_bidx: byte offset between destination arrays in a frame
1021 * @dest_cidx: byte offset between destination frames in a block
1022 *
1023 * Offsets are specified to support either contiguous or discontiguous
1024 * memory transfers, or repeated access to a hardware register, as needed.
1025 * When accessing hardware registers, both offsets are normally zero.
1026 */
1027 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1028 {
1029 unsigned ctlr;
1030
1031 ctlr = EDMA_CTLR(slot);
1032 slot = EDMA_CHAN_SLOT(slot);
1033
1034 if (slot < edma_info[ctlr]->num_slots) {
1035 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1036 0x0000ffff, dest_bidx << 16);
1037 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1038 0x0000ffff, dest_cidx << 16);
1039 }
1040 }
1041 EXPORT_SYMBOL(edma_set_dest_index);
1042
1043 /**
1044 * edma_set_transfer_params - configure DMA transfer parameters
1045 * @slot: parameter RAM slot being configured
1046 * @acnt: how many bytes per array (at least one)
1047 * @bcnt: how many arrays per frame (at least one)
1048 * @ccnt: how many frames per block (at least one)
1049 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1050 * the value to reload into bcnt when it decrements to zero
1051 * @sync_mode: ASYNC or ABSYNC
1052 *
1053 * See the EDMA3 documentation to understand how to configure and link
1054 * transfers using the fields in PaRAM slots. If you are not doing it
1055 * all at once with edma_write_slot(), you will use this routine
1056 * plus two calls each for source and destination, setting the initial
1057 * address and saying how to index that address.
1058 *
1059 * An example of an A-Synchronized transfer is a serial link using a
1060 * single word shift register. In that case, @acnt would be equal to
1061 * that word size; the serial controller issues a DMA synchronization
1062 * event to transfer each word, and memory access by the DMA transfer
1063 * controller will be word-at-a-time.
1064 *
1065 * An example of an AB-Synchronized transfer is a device using a FIFO.
1066 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1067 * The controller with the FIFO issues DMA synchronization events when
1068 * the FIFO threshold is reached, and the DMA transfer controller will
1069 * transfer one frame to (or from) the FIFO. It will probably use
1070 * efficient burst modes to access memory.
1071 */
1072 void edma_set_transfer_params(unsigned slot,
1073 u16 acnt, u16 bcnt, u16 ccnt,
1074 u16 bcnt_rld, enum sync_dimension sync_mode)
1075 {
1076 unsigned ctlr;
1077
1078 ctlr = EDMA_CTLR(slot);
1079 slot = EDMA_CHAN_SLOT(slot);
1080
1081 if (slot < edma_info[ctlr]->num_slots) {
1082 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1083 0x0000ffff, bcnt_rld << 16);
1084 if (sync_mode == ASYNC)
1085 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1086 else
1087 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1088 /* Set the acount, bcount, ccount registers */
1089 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1090 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1091 }
1092 }
1093 EXPORT_SYMBOL(edma_set_transfer_params);
1094
1095 /**
1096 * edma_link - link one parameter RAM slot to another
1097 * @from: parameter RAM slot originating the link
1098 * @to: parameter RAM slot which is the link target
1099 *
1100 * The originating slot should not be part of any active DMA transfer.
1101 */
1102 void edma_link(unsigned from, unsigned to)
1103 {
1104 unsigned ctlr_from, ctlr_to;
1105
1106 ctlr_from = EDMA_CTLR(from);
1107 from = EDMA_CHAN_SLOT(from);
1108 ctlr_to = EDMA_CTLR(to);
1109 to = EDMA_CHAN_SLOT(to);
1110
1111 if (from >= edma_info[ctlr_from]->num_slots)
1112 return;
1113 if (to >= edma_info[ctlr_to]->num_slots)
1114 return;
1115 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1116 PARM_OFFSET(to));
1117 }
1118 EXPORT_SYMBOL(edma_link);
1119
1120 /**
1121 * edma_unlink - cut link from one parameter RAM slot
1122 * @from: parameter RAM slot originating the link
1123 *
1124 * The originating slot should not be part of any active DMA transfer.
1125 * Its link is set to 0xffff.
1126 */
1127 void edma_unlink(unsigned from)
1128 {
1129 unsigned ctlr;
1130
1131 ctlr = EDMA_CTLR(from);
1132 from = EDMA_CHAN_SLOT(from);
1133
1134 if (from >= edma_info[ctlr]->num_slots)
1135 return;
1136 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1137 }
1138 EXPORT_SYMBOL(edma_unlink);
1139
1140 /*-----------------------------------------------------------------------*/
1141
1142 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1143
1144 /**
1145 * edma_write_slot - write parameter RAM data for slot
1146 * @slot: number of parameter RAM slot being modified
1147 * @param: data to be written into parameter RAM slot
1148 *
1149 * Use this to assign all parameters of a transfer at once. This
1150 * allows more efficient setup of transfers than issuing multiple
1151 * calls to set up those parameters in small pieces, and provides
1152 * complete control over all transfer options.
1153 */
1154 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1155 {
1156 unsigned ctlr;
1157
1158 ctlr = EDMA_CTLR(slot);
1159 slot = EDMA_CHAN_SLOT(slot);
1160
1161 if (slot >= edma_info[ctlr]->num_slots)
1162 return;
1163 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1164 PARM_SIZE);
1165 }
1166 EXPORT_SYMBOL(edma_write_slot);
1167
1168 /**
1169 * edma_read_slot - read parameter RAM data from slot
1170 * @slot: number of parameter RAM slot being copied
1171 * @param: where to store copy of parameter RAM data
1172 *
1173 * Use this to read data from a parameter RAM slot, perhaps to
1174 * save them as a template for later reuse.
1175 */
1176 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1177 {
1178 unsigned ctlr;
1179
1180 ctlr = EDMA_CTLR(slot);
1181 slot = EDMA_CHAN_SLOT(slot);
1182
1183 if (slot >= edma_info[ctlr]->num_slots)
1184 return;
1185 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1186 PARM_SIZE);
1187 }
1188 EXPORT_SYMBOL(edma_read_slot);
1189
1190 /*-----------------------------------------------------------------------*/
1191
1192 /* Various EDMA channel control operations */
1193
1194 /**
1195 * edma_pause - pause dma on a channel
1196 * @channel: on which edma_start() has been called
1197 *
1198 * This temporarily disables EDMA hardware events on the specified channel,
1199 * preventing them from triggering new transfers on its behalf
1200 */
1201 void edma_pause(unsigned channel)
1202 {
1203 unsigned ctlr;
1204
1205 ctlr = EDMA_CTLR(channel);
1206 channel = EDMA_CHAN_SLOT(channel);
1207
1208 if (channel < edma_info[ctlr]->num_channels) {
1209 unsigned int mask = (1 << (channel & 0x1f));
1210
1211 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1212 }
1213 }
1214 EXPORT_SYMBOL(edma_pause);
1215
1216 /**
1217 * edma_resume - resumes dma on a paused channel
1218 * @channel: on which edma_pause() has been called
1219 *
1220 * This re-enables EDMA hardware events on the specified channel.
1221 */
1222 void edma_resume(unsigned channel)
1223 {
1224 unsigned ctlr;
1225
1226 ctlr = EDMA_CTLR(channel);
1227 channel = EDMA_CHAN_SLOT(channel);
1228
1229 if (channel < edma_info[ctlr]->num_channels) {
1230 unsigned int mask = (1 << (channel & 0x1f));
1231
1232 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1233 }
1234 }
1235 EXPORT_SYMBOL(edma_resume);
1236
1237 /**
1238 * edma_start - start dma on a channel
1239 * @channel: channel being activated
1240 *
1241 * Channels with event associations will be triggered by their hardware
1242 * events, and channels without such associations will be triggered by
1243 * software. (At this writing there is no interface for using software
1244 * triggers except with channels that don't support hardware triggers.)
1245 *
1246 * Returns zero on success, else negative errno.
1247 */
1248 int edma_start(unsigned channel)
1249 {
1250 unsigned ctlr;
1251
1252 ctlr = EDMA_CTLR(channel);
1253 channel = EDMA_CHAN_SLOT(channel);
1254
1255 if (channel < edma_info[ctlr]->num_channels) {
1256 int j = channel >> 5;
1257 unsigned int mask = (1 << (channel & 0x1f));
1258
1259 /* EDMA channels without event association */
1260 if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
1261 pr_debug("EDMA: ESR%d %08x\n", j,
1262 edma_shadow0_read_array(ctlr, SH_ESR, j));
1263 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1264 return 0;
1265 }
1266
1267 /* EDMA channel with event association */
1268 pr_debug("EDMA: ER%d %08x\n", j,
1269 edma_shadow0_read_array(ctlr, SH_ER, j));
1270 /* Clear any pending event or error */
1271 edma_write_array(ctlr, EDMA_ECR, j, mask);
1272 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1273 /* Clear any SER */
1274 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1275 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1276 pr_debug("EDMA: EER%d %08x\n", j,
1277 edma_shadow0_read_array(ctlr, SH_EER, j));
1278 return 0;
1279 }
1280
1281 return -EINVAL;
1282 }
1283 EXPORT_SYMBOL(edma_start);
1284
1285 /**
1286 * edma_stop - stops dma on the channel passed
1287 * @channel: channel being deactivated
1288 *
1289 * When @lch is a channel, any active transfer is paused and
1290 * all pending hardware events are cleared. The current transfer
1291 * may not be resumed, and the channel's Parameter RAM should be
1292 * reinitialized before being reused.
1293 */
1294 void edma_stop(unsigned channel)
1295 {
1296 unsigned ctlr;
1297
1298 ctlr = EDMA_CTLR(channel);
1299 channel = EDMA_CHAN_SLOT(channel);
1300
1301 if (channel < edma_info[ctlr]->num_channels) {
1302 int j = channel >> 5;
1303 unsigned int mask = (1 << (channel & 0x1f));
1304
1305 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1306 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1307 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1308 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1309
1310 pr_debug("EDMA: EER%d %08x\n", j,
1311 edma_shadow0_read_array(ctlr, SH_EER, j));
1312
1313 /* REVISIT: consider guarding against inappropriate event
1314 * chaining by overwriting with dummy_paramset.
1315 */
1316 }
1317 }
1318 EXPORT_SYMBOL(edma_stop);
1319
1320 /******************************************************************************
1321 *
1322 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1323 * been removed before EDMA has finished.It is usedful for removable media.
1324 * Arguments:
1325 * ch_no - channel no
1326 *
1327 * Return: zero on success, or corresponding error no on failure
1328 *
1329 * FIXME this should not be needed ... edma_stop() should suffice.
1330 *
1331 *****************************************************************************/
1332
1333 void edma_clean_channel(unsigned channel)
1334 {
1335 unsigned ctlr;
1336
1337 ctlr = EDMA_CTLR(channel);
1338 channel = EDMA_CHAN_SLOT(channel);
1339
1340 if (channel < edma_info[ctlr]->num_channels) {
1341 int j = (channel >> 5);
1342 unsigned int mask = 1 << (channel & 0x1f);
1343
1344 pr_debug("EDMA: EMR%d %08x\n", j,
1345 edma_read_array(ctlr, EDMA_EMR, j));
1346 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1347 /* Clear the corresponding EMR bits */
1348 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1349 /* Clear any SER */
1350 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1351 edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
1352 }
1353 }
1354 EXPORT_SYMBOL(edma_clean_channel);
1355
1356 /*
1357 * edma_clear_event - clear an outstanding event on the DMA channel
1358 * Arguments:
1359 * channel - channel number
1360 */
1361 void edma_clear_event(unsigned channel)
1362 {
1363 unsigned ctlr;
1364
1365 ctlr = EDMA_CTLR(channel);
1366 channel = EDMA_CHAN_SLOT(channel);
1367
1368 if (channel >= edma_info[ctlr]->num_channels)
1369 return;
1370 if (channel < 32)
1371 edma_write(ctlr, EDMA_ECR, 1 << channel);
1372 else
1373 edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
1374 }
1375 EXPORT_SYMBOL(edma_clear_event);
1376
1377 /*-----------------------------------------------------------------------*/
1378
1379 static int __init edma_probe(struct platform_device *pdev)
1380 {
1381 struct edma_soc_info *info = pdev->dev.platform_data;
1382 const s8 (*queue_priority_mapping)[2];
1383 const s8 (*queue_tc_mapping)[2];
1384 int i, j, found = 0;
1385 int status = -1;
1386 int irq[EDMA_MAX_CC] = {0, 0};
1387 int err_irq[EDMA_MAX_CC] = {0, 0};
1388 struct resource *r[EDMA_MAX_CC] = {NULL};
1389 resource_size_t len[EDMA_MAX_CC];
1390 char res_name[10];
1391 char irq_name[10];
1392
1393 if (!info)
1394 return -ENODEV;
1395
1396 for (j = 0; j < EDMA_MAX_CC; j++) {
1397 sprintf(res_name, "edma_cc%d", j);
1398 r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1399 res_name);
1400 if (!r[j]) {
1401 if (found)
1402 break;
1403 else
1404 return -ENODEV;
1405 } else
1406 found = 1;
1407
1408 len[j] = resource_size(r[j]);
1409
1410 r[j] = request_mem_region(r[j]->start, len[j],
1411 dev_name(&pdev->dev));
1412 if (!r[j]) {
1413 status = -EBUSY;
1414 goto fail1;
1415 }
1416
1417 edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
1418 if (!edmacc_regs_base[j]) {
1419 status = -EBUSY;
1420 goto fail1;
1421 }
1422
1423 edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
1424 if (!edma_info[j]) {
1425 status = -ENOMEM;
1426 goto fail1;
1427 }
1428 memset(edma_info[j], 0, sizeof(struct edma));
1429
1430 edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
1431 EDMA_MAX_DMACH);
1432 edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
1433 EDMA_MAX_PARAMENTRY);
1434 edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
1435 EDMA_MAX_CC);
1436
1437 edma_info[j]->default_queue = info[j].default_queue;
1438 if (!edma_info[j]->default_queue)
1439 edma_info[j]->default_queue = EVENTQ_1;
1440
1441 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1442 edmacc_regs_base[j]);
1443
1444 for (i = 0; i < edma_info[j]->num_slots; i++)
1445 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1446 &dummy_paramset, PARM_SIZE);
1447
1448 /* Mark all channels as unused */
1449 memset(edma_info[j]->edma_unused, 0xff,
1450 sizeof(edma_info[j]->edma_unused));
1451
1452 sprintf(irq_name, "edma%d", j);
1453 irq[j] = platform_get_irq_byname(pdev, irq_name);
1454 edma_info[j]->irq_res_start = irq[j];
1455 status = request_irq(irq[j], dma_irq_handler, 0, "edma",
1456 &pdev->dev);
1457 if (status < 0) {
1458 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1459 irq[j], status);
1460 goto fail;
1461 }
1462
1463 sprintf(irq_name, "edma%d_err", j);
1464 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1465 edma_info[j]->irq_res_end = err_irq[j];
1466 status = request_irq(err_irq[j], dma_ccerr_handler, 0,
1467 "edma_error", &pdev->dev);
1468 if (status < 0) {
1469 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1470 err_irq[j], status);
1471 goto fail;
1472 }
1473
1474 /* Everything lives on transfer controller 1 until otherwise
1475 * specified. This way, long transfers on the low priority queue
1476 * started by the codec engine will not cause audio defects.
1477 */
1478 for (i = 0; i < edma_info[j]->num_channels; i++)
1479 map_dmach_queue(j, i, EVENTQ_1);
1480
1481 queue_tc_mapping = info[j].queue_tc_mapping;
1482 queue_priority_mapping = info[j].queue_priority_mapping;
1483
1484 /* Event queue to TC mapping */
1485 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1486 map_queue_tc(j, queue_tc_mapping[i][0],
1487 queue_tc_mapping[i][1]);
1488
1489 /* Event queue priority mapping */
1490 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1491 assign_priority_to_queue(j,
1492 queue_priority_mapping[i][0],
1493 queue_priority_mapping[i][1]);
1494
1495 /* Map the channel to param entry if channel mapping logic
1496 * exist
1497 */
1498 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1499 map_dmach_param(j);
1500
1501 for (i = 0; i < info[j].n_region; i++) {
1502 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1503 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1504 edma_write_array(j, EDMA_QRAE, i, 0x0);
1505 }
1506 arch_num_cc++;
1507 }
1508
1509 if (tc_errs_handled) {
1510 status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
1511 "edma_tc0", &pdev->dev);
1512 if (status < 0) {
1513 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1514 IRQ_TCERRINT0, status);
1515 return status;
1516 }
1517 status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
1518 "edma_tc1", &pdev->dev);
1519 if (status < 0) {
1520 dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
1521 IRQ_TCERRINT, status);
1522 return status;
1523 }
1524 }
1525
1526 return 0;
1527
1528 fail:
1529 for (i = 0; i < EDMA_MAX_CC; i++) {
1530 if (err_irq[i])
1531 free_irq(err_irq[i], &pdev->dev);
1532 if (irq[i])
1533 free_irq(irq[i], &pdev->dev);
1534 }
1535 fail1:
1536 for (i = 0; i < EDMA_MAX_CC; i++) {
1537 if (r[i])
1538 release_mem_region(r[i]->start, len[i]);
1539 if (edmacc_regs_base[i])
1540 iounmap(edmacc_regs_base[i]);
1541 kfree(edma_info[i]);
1542 }
1543 return status;
1544 }
1545
1546
1547 static struct platform_driver edma_driver = {
1548 .driver.name = "edma",
1549 };
1550
1551 static int __init edma_init(void)
1552 {
1553 return platform_driver_probe(&edma_driver, edma_probe);
1554 }
1555 arch_initcall(edma_init);
1556
CJK support for tty framebuffer vt