2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
30 #include <asm/div64.h>
32 #include <mach/sdrc.h>
36 #include "prm-regbits-24xx.h"
38 #include "cm-regbits-24xx.h"
39 #include "cm-regbits-34xx.h"
41 #define MAX_CLOCK_ENABLE_WAIT 100000
43 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
44 #define DPLL_MIN_MULTIPLIER 1
45 #define DPLL_MIN_DIVIDER 1
47 /* Possible error results from _dpll_test_mult */
48 #define DPLL_MULT_UNDERFLOW -1
51 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
52 * The higher the scale factor, the greater the risk of arithmetic overflow,
53 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
54 * must be a power of DPLL_SCALE_BASE.
56 #define DPLL_SCALE_FACTOR 64
57 #define DPLL_SCALE_BASE 2
58 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
59 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
61 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
62 #define DPLL_FINT_BAND1_MIN 750000
63 #define DPLL_FINT_BAND1_MAX 2100000
64 #define DPLL_FINT_BAND2_MIN 7500000
65 #define DPLL_FINT_BAND2_MAX 21000000
67 /* _dpll_test_fint() return codes */
68 #define DPLL_FINT_UNDERFLOW -1
69 #define DPLL_FINT_INVALID -2
73 /*-------------------------------------------------------------------------
74 * OMAP2/3 specific clock functions
75 *-------------------------------------------------------------------------*/
78 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
81 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
82 * don't take effect until the VALID_CONFIG bit is written, write the
83 * VALID_CONFIG bit and wait for the write to complete. No return value.
85 static void _omap2xxx_clk_commit(struct clk
*clk
)
87 if (!cpu_is_omap24xx())
90 if (!(clk
->flags
& DELAYED_APP
))
93 prm_write_mod_reg(OMAP24XX_VALID_CONFIG
, OMAP24XX_GR_MOD
,
94 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET
);
96 prm_read_mod_reg(OMAP24XX_GR_MOD
, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET
);
100 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
101 * @clk: DPLL struct clk to test
102 * @n: divider value (N) to test
104 * Tests whether a particular divider @n will result in a valid DPLL
105 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
106 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
107 * (assuming that it is counting N upwards), or -2 if the enclosing loop
108 * should skip to the next iteration (again assuming N is increasing).
110 static int _dpll_test_fint(struct clk
*clk
, u8 n
)
112 struct dpll_data
*dd
;
118 /* DPLL divider must result in a valid jitter correction val */
119 fint
= clk
->parent
->rate
/ (n
+ 1);
120 if (fint
< DPLL_FINT_BAND1_MIN
) {
122 pr_debug("rejecting n=%d due to Fint failure, "
123 "lowering max_divider\n", n
);
125 ret
= DPLL_FINT_UNDERFLOW
;
127 } else if (fint
> DPLL_FINT_BAND1_MAX
&&
128 fint
< DPLL_FINT_BAND2_MIN
) {
130 pr_debug("rejecting n=%d due to Fint failure\n", n
);
131 ret
= DPLL_FINT_INVALID
;
133 } else if (fint
> DPLL_FINT_BAND2_MAX
) {
135 pr_debug("rejecting n=%d due to Fint failure, "
136 "boosting min_divider\n", n
);
138 ret
= DPLL_FINT_INVALID
;
146 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
147 * @clk: OMAP clock struct ptr to use
149 * Convert a clockdomain name stored in a struct clk 'clk' into a
150 * clockdomain pointer, and save it into the struct clk. Intended to be
151 * called during clk_register(). No return value.
153 void omap2_init_clk_clkdm(struct clk
*clk
)
155 struct clockdomain
*clkdm
;
157 if (!clk
->clkdm_name
)
160 clkdm
= clkdm_lookup(clk
->clkdm_name
);
162 pr_debug("clock: associated clk %s to clkdm %s\n",
163 clk
->name
, clk
->clkdm_name
);
166 pr_debug("clock: could not associate clk %s to "
167 "clkdm %s\n", clk
->name
, clk
->clkdm_name
);
172 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
173 * @clk: OMAP clock struct ptr to use
175 * Given a pointer to a source-selectable struct clk, read the hardware
176 * register and determine what its parent is currently set to. Update the
177 * clk->parent field with the appropriate clk ptr.
179 void omap2_init_clksel_parent(struct clk
*clk
)
181 const struct clksel
*clks
;
182 const struct clksel_rate
*clkr
;
188 r
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
189 r
>>= __ffs(clk
->clksel_mask
);
191 for (clks
= clk
->clksel
; clks
->parent
&& !found
; clks
++) {
192 for (clkr
= clks
->rates
; clkr
->div
&& !found
; clkr
++) {
193 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== r
)) {
194 if (clk
->parent
!= clks
->parent
) {
195 pr_debug("clock: inited %s parent "
197 clk
->name
, clks
->parent
->name
,
199 clk
->parent
->name
: "NULL"));
200 clk_reparent(clk
, clks
->parent
);
208 printk(KERN_ERR
"clock: init parent: could not find "
209 "regval %0x for clock %s\n", r
, clk
->name
);
214 /* Returns the DPLL rate */
215 u32
omap2_get_dpll_rate(struct clk
*clk
)
218 u32 dpll_mult
, dpll_div
, dpll
;
219 struct dpll_data
*dd
;
222 /* REVISIT: What do we return on error? */
226 dpll
= __raw_readl(dd
->mult_div1_reg
);
227 dpll_mult
= dpll
& dd
->mult_mask
;
228 dpll_mult
>>= __ffs(dd
->mult_mask
);
229 dpll_div
= dpll
& dd
->div1_mask
;
230 dpll_div
>>= __ffs(dd
->div1_mask
);
232 dpll_clk
= (long long)clk
->parent
->rate
* dpll_mult
;
233 do_div(dpll_clk
, dpll_div
+ 1);
239 * Used for clocks that have the same value as the parent clock,
240 * divided by some factor
242 void omap2_fixed_divisor_recalc(struct clk
*clk
)
244 WARN_ON(!clk
->fixed_div
);
246 clk
->rate
= clk
->parent
->rate
/ clk
->fixed_div
;
250 * omap2_wait_clock_ready - wait for clock to enable
251 * @reg: physical address of clock IDLEST register
252 * @mask: value to mask against to determine if the clock is active
253 * @name: name of the clock (for printk)
255 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
256 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
258 int omap2_wait_clock_ready(void __iomem
*reg
, u32 mask
, const char *name
)
264 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
265 * 34xx reverses this, just to keep us on our toes
267 if (cpu_mask
& (RATE_IN_242X
| RATE_IN_243X
))
269 else if (cpu_mask
& RATE_IN_343X
)
273 while (((__raw_readl(reg
) & mask
) != ena
) &&
274 (i
++ < MAX_CLOCK_ENABLE_WAIT
)) {
278 if (i
< MAX_CLOCK_ENABLE_WAIT
)
279 pr_debug("Clock %s stable after %d loops\n", name
, i
);
281 printk(KERN_ERR
"Clock %s didn't enable in %d tries\n",
282 name
, MAX_CLOCK_ENABLE_WAIT
);
285 return (i
< MAX_CLOCK_ENABLE_WAIT
) ? 1 : 0;
290 * Note: We don't need special code here for INVERT_ENABLE
291 * for the time being since INVERT_ENABLE only applies to clocks enabled by
294 static void omap2_clk_wait_ready(struct clk
*clk
)
296 void __iomem
*reg
, *other_reg
, *st_reg
;
300 * REVISIT: This code is pretty ugly. It would be nice to generalize
301 * it and pull it into struct clk itself somehow.
303 reg
= clk
->enable_reg
;
306 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
307 * it's just a matter of XORing the bits.
309 other_reg
= (void __iomem
*)((u32
)reg
^ (CM_FCLKEN
^ CM_ICLKEN
));
311 /* Check if both functional and interface clocks
313 bit
= 1 << clk
->enable_bit
;
314 if (!(__raw_readl(other_reg
) & bit
))
316 st_reg
= (void __iomem
*)(((u32
)other_reg
& ~0xf0) | 0x20); /* CM_IDLEST* */
318 omap2_wait_clock_ready(st_reg
, bit
, clk
->name
);
321 static int omap2_dflt_clk_enable(struct clk
*clk
)
325 if (unlikely(clk
->enable_reg
== NULL
)) {
326 printk(KERN_ERR
"clock.c: Enable for %s without enable code\n",
328 return 0; /* REVISIT: -EINVAL */
331 v
= __raw_readl(clk
->enable_reg
);
332 if (clk
->flags
& INVERT_ENABLE
)
333 v
&= ~(1 << clk
->enable_bit
);
335 v
|= (1 << clk
->enable_bit
);
336 __raw_writel(v
, clk
->enable_reg
);
337 v
= __raw_readl(clk
->enable_reg
); /* OCP barrier */
342 static int omap2_dflt_clk_enable_wait(struct clk
*clk
)
346 if (!clk
->enable_reg
) {
347 printk(KERN_ERR
"clock.c: Enable for %s without enable code\n",
349 return 0; /* REVISIT: -EINVAL */
352 ret
= omap2_dflt_clk_enable(clk
);
354 omap2_clk_wait_ready(clk
);
358 static void omap2_dflt_clk_disable(struct clk
*clk
)
362 if (!clk
->enable_reg
) {
364 * 'Independent' here refers to a clock which is not
365 * controlled by its parent.
367 printk(KERN_ERR
"clock: clk_disable called on independent "
368 "clock %s which has no enable_reg\n", clk
->name
);
372 v
= __raw_readl(clk
->enable_reg
);
373 if (clk
->flags
& INVERT_ENABLE
)
374 v
|= (1 << clk
->enable_bit
);
376 v
&= ~(1 << clk
->enable_bit
);
377 __raw_writel(v
, clk
->enable_reg
);
378 /* No OCP barrier needed here since it is a disable operation */
381 const struct clkops clkops_omap2_dflt_wait
= {
382 .enable
= omap2_dflt_clk_enable_wait
,
383 .disable
= omap2_dflt_clk_disable
,
386 const struct clkops clkops_omap2_dflt
= {
387 .enable
= omap2_dflt_clk_enable
,
388 .disable
= omap2_dflt_clk_disable
,
391 /* Enables clock without considering parent dependencies or use count
392 * REVISIT: Maybe change this to use clk->enable like on omap1?
394 static int _omap2_clk_enable(struct clk
*clk
)
396 return clk
->ops
->enable(clk
);
399 /* Disables clock without considering parent dependencies or use count */
400 static void _omap2_clk_disable(struct clk
*clk
)
402 clk
->ops
->disable(clk
);
405 void omap2_clk_disable(struct clk
*clk
)
407 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
408 _omap2_clk_disable(clk
);
410 omap2_clk_disable(clk
->parent
);
412 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
417 int omap2_clk_enable(struct clk
*clk
)
421 if (clk
->usecount
++ == 0) {
423 ret
= omap2_clk_enable(clk
->parent
);
431 omap2_clkdm_clk_enable(clk
->clkdm
, clk
);
433 ret
= _omap2_clk_enable(clk
);
437 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
440 omap2_clk_disable(clk
->parent
);
450 * Used for clocks that are part of CLKSEL_xyz governed clocks.
451 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
453 void omap2_clksel_recalc(struct clk
*clk
)
457 pr_debug("clock: recalc'ing clksel clk %s\n", clk
->name
);
459 div
= omap2_clksel_get_divisor(clk
);
463 if (clk
->rate
== (clk
->parent
->rate
/ div
))
465 clk
->rate
= clk
->parent
->rate
/ div
;
467 pr_debug("clock: new clock rate is %ld (div %d)\n", clk
->rate
, div
);
471 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
472 * @clk: OMAP struct clk ptr to inspect
473 * @src_clk: OMAP struct clk ptr of the parent clk to search for
475 * Scan the struct clksel array associated with the clock to find
476 * the element associated with the supplied parent clock address.
477 * Returns a pointer to the struct clksel on success or NULL on error.
479 static const struct clksel
*omap2_get_clksel_by_parent(struct clk
*clk
,
482 const struct clksel
*clks
;
487 for (clks
= clk
->clksel
; clks
->parent
; clks
++) {
488 if (clks
->parent
== src_clk
)
489 break; /* Found the requested parent */
493 printk(KERN_ERR
"clock: Could not find parent clock %s in "
494 "clksel array of clock %s\n", src_clk
->name
,
503 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
504 * @clk: OMAP struct clk to use
505 * @target_rate: desired clock rate
506 * @new_div: ptr to where we should store the divisor
508 * Finds 'best' divider value in an array based on the source and target
509 * rates. The divider array must be sorted with smallest divider first.
510 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
511 * they are only settable as part of virtual_prcm set.
513 * Returns the rounded clock rate or returns 0xffffffff on error.
515 u32
omap2_clksel_round_rate_div(struct clk
*clk
, unsigned long target_rate
,
518 unsigned long test_rate
;
519 const struct clksel
*clks
;
520 const struct clksel_rate
*clkr
;
523 printk(KERN_INFO
"clock: clksel_round_rate_div: %s target_rate %ld\n",
524 clk
->name
, target_rate
);
528 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
532 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
533 if (!(clkr
->flags
& cpu_mask
))
537 if (clkr
->div
<= last_div
)
538 printk(KERN_ERR
"clock: clksel_rate table not sorted "
539 "for clock %s", clk
->name
);
541 last_div
= clkr
->div
;
543 test_rate
= clk
->parent
->rate
/ clkr
->div
;
545 if (test_rate
<= target_rate
)
546 break; /* found it */
550 printk(KERN_ERR
"clock: Could not find divisor for target "
551 "rate %ld for clock %s parent %s\n", target_rate
,
552 clk
->name
, clk
->parent
->name
);
556 *new_div
= clkr
->div
;
558 printk(KERN_INFO
"clock: new_div = %d, new_rate = %ld\n", *new_div
,
559 (clk
->parent
->rate
/ clkr
->div
));
561 return (clk
->parent
->rate
/ clkr
->div
);
565 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
566 * @clk: OMAP struct clk to use
567 * @target_rate: desired clock rate
569 * Compatibility wrapper for OMAP clock framework
570 * Finds best target rate based on the source clock and possible dividers.
571 * rates. The divider array must be sorted with smallest divider first.
572 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
573 * they are only settable as part of virtual_prcm set.
575 * Returns the rounded clock rate or returns 0xffffffff on error.
577 long omap2_clksel_round_rate(struct clk
*clk
, unsigned long target_rate
)
581 return omap2_clksel_round_rate_div(clk
, target_rate
, &new_div
);
585 /* Given a clock and a rate apply a clock specific rounding function */
586 long omap2_clk_round_rate(struct clk
*clk
, unsigned long rate
)
589 return clk
->round_rate(clk
, rate
);
591 if (clk
->flags
& RATE_FIXED
)
592 printk(KERN_ERR
"clock: generic omap2_clk_round_rate called "
593 "on fixed-rate clock %s\n", clk
->name
);
599 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
600 * @clk: OMAP struct clk to use
601 * @field_val: register field value to find
603 * Given a struct clk of a rate-selectable clksel clock, and a register field
604 * value to search for, find the corresponding clock divisor. The register
605 * field value should be pre-masked and shifted down so the LSB is at bit 0
606 * before calling. Returns 0 on error
608 u32
omap2_clksel_to_divisor(struct clk
*clk
, u32 field_val
)
610 const struct clksel
*clks
;
611 const struct clksel_rate
*clkr
;
613 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
617 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
618 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== field_val
))
623 printk(KERN_ERR
"clock: Could not find fieldval %d for "
624 "clock %s parent %s\n", field_val
, clk
->name
,
633 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
634 * @clk: OMAP struct clk to use
635 * @div: integer divisor to search for
637 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
638 * find the corresponding register field value. The return register value is
639 * the value before left-shifting. Returns 0xffffffff on error
641 u32
omap2_divisor_to_clksel(struct clk
*clk
, u32 div
)
643 const struct clksel
*clks
;
644 const struct clksel_rate
*clkr
;
646 /* should never happen */
649 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
653 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
654 if ((clkr
->flags
& cpu_mask
) && (clkr
->div
== div
))
659 printk(KERN_ERR
"clock: Could not find divisor %d for "
660 "clock %s parent %s\n", div
, clk
->name
,
669 * omap2_clksel_get_divisor - get current divider applied to parent clock.
670 * @clk: OMAP struct clk to use.
672 * Returns the integer divisor upon success or 0 on error.
674 u32
omap2_clksel_get_divisor(struct clk
*clk
)
678 if (!clk
->clksel_mask
)
681 v
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
682 v
>>= __ffs(clk
->clksel_mask
);
684 return omap2_clksel_to_divisor(clk
, v
);
687 int omap2_clksel_set_rate(struct clk
*clk
, unsigned long rate
)
689 u32 v
, field_val
, validrate
, new_div
= 0;
691 if (!clk
->clksel_mask
)
694 validrate
= omap2_clksel_round_rate_div(clk
, rate
, &new_div
);
695 if (validrate
!= rate
)
698 field_val
= omap2_divisor_to_clksel(clk
, new_div
);
702 v
= __raw_readl(clk
->clksel_reg
);
703 v
&= ~clk
->clksel_mask
;
704 v
|= field_val
<< __ffs(clk
->clksel_mask
);
705 __raw_writel(v
, clk
->clksel_reg
);
706 v
= __raw_readl(clk
->clksel_reg
); /* OCP barrier */
708 clk
->rate
= clk
->parent
->rate
/ new_div
;
710 _omap2xxx_clk_commit(clk
);
716 /* Set the clock rate for a clock source */
717 int omap2_clk_set_rate(struct clk
*clk
, unsigned long rate
)
721 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk
->name
, rate
);
723 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
724 rate table mechanism, driven by mpu_speed */
725 if (clk
->flags
& CONFIG_PARTICIPANT
)
728 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
730 ret
= clk
->set_rate(clk
, rate
);
736 * Converts encoded control register address into a full address
737 * On error, the return value (parent_div) will be 0.
739 static u32
_omap2_clksel_get_src_field(struct clk
*src_clk
, struct clk
*clk
,
742 const struct clksel
*clks
;
743 const struct clksel_rate
*clkr
;
745 clks
= omap2_get_clksel_by_parent(clk
, src_clk
);
749 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
750 if (clkr
->flags
& (cpu_mask
| DEFAULT_RATE
))
751 break; /* Found the default rate for this platform */
755 printk(KERN_ERR
"clock: Could not find default rate for "
756 "clock %s parent %s\n", clk
->name
,
757 src_clk
->parent
->name
);
761 /* Should never happen. Add a clksel mask to the struct clk. */
762 WARN_ON(clk
->clksel_mask
== 0);
764 *field_val
= clkr
->val
;
769 int omap2_clk_set_parent(struct clk
*clk
, struct clk
*new_parent
)
771 u32 field_val
, v
, parent_div
;
773 if (clk
->flags
& CONFIG_PARTICIPANT
)
779 parent_div
= _omap2_clksel_get_src_field(new_parent
, clk
, &field_val
);
783 if (clk
->usecount
> 0)
784 _omap2_clk_disable(clk
);
786 /* Set new source value (previous dividers if any in effect) */
787 v
= __raw_readl(clk
->clksel_reg
);
788 v
&= ~clk
->clksel_mask
;
789 v
|= field_val
<< __ffs(clk
->clksel_mask
);
790 __raw_writel(v
, clk
->clksel_reg
);
791 v
= __raw_readl(clk
->clksel_reg
); /* OCP barrier */
793 _omap2xxx_clk_commit(clk
);
795 if (clk
->usecount
> 0)
796 _omap2_clk_enable(clk
);
798 clk_reparent(clk
, new_parent
);
800 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
801 clk
->rate
= new_parent
->rate
;
804 clk
->rate
/= parent_div
;
806 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
807 clk
->name
, clk
->parent
->name
, clk
->rate
);
812 /* DPLL rate rounding code */
815 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
816 * @clk: struct clk * of the DPLL
817 * @tolerance: maximum rate error tolerance
819 * Set the maximum DPLL rate error tolerance for the rate rounding
820 * algorithm. The rate tolerance is an attempt to balance DPLL power
821 * saving (the least divider value "n") vs. rate fidelity (the least
822 * difference between the desired DPLL target rate and the rounded
823 * rate out of the algorithm). So, increasing the tolerance is likely
824 * to decrease DPLL power consumption and increase DPLL rate error.
825 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
826 * DPLL; or 0 upon success.
828 int omap2_dpll_set_rate_tolerance(struct clk
*clk
, unsigned int tolerance
)
830 if (!clk
|| !clk
->dpll_data
)
833 clk
->dpll_data
->rate_tolerance
= tolerance
;
838 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate
,
839 unsigned int m
, unsigned int n
)
841 unsigned long long num
;
843 num
= (unsigned long long)parent_rate
* m
;
849 * _dpll_test_mult - test a DPLL multiplier value
850 * @m: pointer to the DPLL m (multiplier) value under test
851 * @n: current DPLL n (divider) value under test
852 * @new_rate: pointer to storage for the resulting rounded rate
853 * @target_rate: the desired DPLL rate
854 * @parent_rate: the DPLL's parent clock rate
856 * This code tests a DPLL multiplier value, ensuring that the
857 * resulting rate will not be higher than the target_rate, and that
858 * the multiplier value itself is valid for the DPLL. Initially, the
859 * integer pointed to by the m argument should be prescaled by
860 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
861 * a non-scaled m upon return. This non-scaled m will result in a
862 * new_rate as close as possible to target_rate (but not greater than
863 * target_rate) given the current (parent_rate, n, prescaled m)
864 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
865 * non-scaled m attempted to underflow, which can allow the calling
866 * function to bail out early; or 0 upon success.
868 static int _dpll_test_mult(int *m
, int n
, unsigned long *new_rate
,
869 unsigned long target_rate
,
870 unsigned long parent_rate
)
872 int r
= 0, carry
= 0;
874 /* Unscale m and round if necessary */
875 if (*m
% DPLL_SCALE_FACTOR
>= DPLL_ROUNDING_VAL
)
877 *m
= (*m
/ DPLL_SCALE_FACTOR
) + carry
;
880 * The new rate must be <= the target rate to avoid programming
881 * a rate that is impossible for the hardware to handle
883 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
884 if (*new_rate
> target_rate
) {
889 /* Guard against m underflow */
890 if (*m
< DPLL_MIN_MULTIPLIER
) {
891 *m
= DPLL_MIN_MULTIPLIER
;
893 r
= DPLL_MULT_UNDERFLOW
;
897 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
903 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
904 * @clk: struct clk * for a DPLL
905 * @target_rate: desired DPLL clock rate
907 * Given a DPLL, a desired target rate, and a rate tolerance, round
908 * the target rate to a possible, programmable rate for this DPLL.
909 * Rate tolerance is assumed to be set by the caller before this
910 * function is called. Attempts to select the minimum possible n
911 * within the tolerance to reduce power consumption. Stores the
912 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
913 * will not need to call this (expensive) function again. Returns ~0
914 * if the target rate cannot be rounded, either because the rate is
915 * too low or because the rate tolerance is set too tightly; or the
916 * rounded rate upon success.
918 long omap2_dpll_round_rate(struct clk
*clk
, unsigned long target_rate
)
920 int m
, n
, r
, e
, scaled_max_m
;
921 unsigned long scaled_rt_rp
, new_rate
;
922 int min_e
= -1, min_e_m
= -1, min_e_n
= -1;
923 struct dpll_data
*dd
;
925 if (!clk
|| !clk
->dpll_data
)
930 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
931 "%ld\n", clk
->name
, target_rate
);
933 scaled_rt_rp
= target_rate
/ (clk
->parent
->rate
/ DPLL_SCALE_FACTOR
);
934 scaled_max_m
= dd
->max_multiplier
* DPLL_SCALE_FACTOR
;
936 dd
->last_rounded_rate
= 0;
938 for (n
= dd
->min_divider
; n
<= dd
->max_divider
; n
++) {
940 /* Is the (input clk, divider) pair valid for the DPLL? */
941 r
= _dpll_test_fint(clk
, n
);
942 if (r
== DPLL_FINT_UNDERFLOW
)
944 else if (r
== DPLL_FINT_INVALID
)
947 /* Compute the scaled DPLL multiplier, based on the divider */
948 m
= scaled_rt_rp
* n
;
951 * Since we're counting n up, a m overflow means we
952 * can bail out completely (since as n increases in
953 * the next iteration, there's no way that m can
954 * increase beyond the current m)
956 if (m
> scaled_max_m
)
959 r
= _dpll_test_mult(&m
, n
, &new_rate
, target_rate
,
962 /* m can't be set low enough for this n - try with a larger n */
963 if (r
== DPLL_MULT_UNDERFLOW
)
966 e
= target_rate
- new_rate
;
967 pr_debug("clock: n = %d: m = %d: rate error is %d "
968 "(new_rate = %ld)\n", n
, m
, e
, new_rate
);
971 min_e
>= (int)(abs(e
) - dd
->rate_tolerance
)) {
976 pr_debug("clock: found new least error %d\n", min_e
);
978 /* We found good settings -- bail out now */
979 if (min_e
<= dd
->rate_tolerance
)
985 pr_debug("clock: error: target rate or tolerance too low\n");
989 dd
->last_rounded_m
= min_e_m
;
990 dd
->last_rounded_n
= min_e_n
;
991 dd
->last_rounded_rate
= _dpll_compute_new_rate(clk
->parent
->rate
,
994 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
995 min_e
, min_e_m
, min_e_n
);
996 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
997 dd
->last_rounded_rate
, target_rate
);
999 return dd
->last_rounded_rate
;
1002 /*-------------------------------------------------------------------------
1003 * Omap2 clock reset and init functions
1004 *-------------------------------------------------------------------------*/
1006 #ifdef CONFIG_OMAP_RESET_CLOCKS
1007 void omap2_clk_disable_unused(struct clk
*clk
)
1011 v
= (clk
->flags
& INVERT_ENABLE
) ? (1 << clk
->enable_bit
) : 0;
1013 regval32
= __raw_readl(clk
->enable_reg
);
1014 if ((regval32
& (1 << clk
->enable_bit
)) == v
)
1017 printk(KERN_INFO
"Disabling unused clock \"%s\"\n", clk
->name
);
1018 if (cpu_is_omap34xx()) {
1019 omap2_clk_enable(clk
);
1020 omap2_clk_disable(clk
);
1022 _omap2_clk_disable(clk
);