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ath9k: Change return value of ath9k_hw_fill_cap_info
[linux-2.6/cjktty.git] / drivers / net / wireless / ath9k / hw.c
blob4ad1508e4752b8f27ae05c7ae88bdd145c99d2ef
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
88 {
89 int i;
90
91 BUG_ON(timeout < AH_TIME_QUANTUM);
92
93 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
94 if ((REG_READ(ah, reg) & mask) == val)
95 return true;
96
97 udelay(AH_TIME_QUANTUM);
98 }
99
100 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val);
103
104 return false;
105 }
106
107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
108 {
109 u32 retval;
110 int i;
111
112 for (i = 0, retval = 0; i < n; i++) {
113 retval = (retval << 1) | (val & 1);
114 val >>= 1;
115 }
116 return retval;
117 }
118
119 bool ath9k_get_channel_edges(struct ath_hw *ah,
120 u16 flags, u16 *low,
121 u16 *high)
122 {
123 struct ath9k_hw_capabilities *pCap = &ah->caps;
124
125 if (flags & CHANNEL_5GHZ) {
126 *low = pCap->low_5ghz_chan;
127 *high = pCap->high_5ghz_chan;
128 return true;
129 }
130 if ((flags & CHANNEL_2GHZ)) {
131 *low = pCap->low_2ghz_chan;
132 *high = pCap->high_2ghz_chan;
133 return true;
134 }
135 return false;
136 }
137
138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
139 struct ath_rate_table *rates,
140 u32 frameLen, u16 rateix,
141 bool shortPreamble)
142 {
143 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
144 u32 kbps;
145
146 kbps = rates->info[rateix].ratekbps;
147
148 if (kbps == 0)
149 return 0;
150
151 switch (rates->info[rateix].phy) {
152 case WLAN_RC_PHY_CCK:
153 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
154 if (shortPreamble && rates->info[rateix].short_preamble)
155 phyTime >>= 1;
156 numBits = frameLen << 3;
157 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
158 break;
159 case WLAN_RC_PHY_OFDM:
160 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_QUARTER
165 + OFDM_PREAMBLE_TIME_QUARTER
166 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
167 } else if (ah->curchan &&
168 IS_CHAN_HALF_RATE(ah->curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_HALF +
173 OFDM_PREAMBLE_TIME_HALF
174 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
175 } else {
176 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
177 numBits = OFDM_PLCP_BITS + (frameLen << 3);
178 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
179 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
180 + (numSymbols * OFDM_SYMBOL_TIME);
181 }
182 break;
183 default:
184 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
185 "Unknown phy %u (rate ix %u)\n",
186 rates->info[rateix].phy, rateix);
187 txTime = 0;
188 break;
189 }
190
191 return txTime;
192 }
193
194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
195 struct ath9k_channel *chan,
196 struct chan_centers *centers)
197 {
198 int8_t extoff;
199
200 if (!IS_CHAN_HT40(chan)) {
201 centers->ctl_center = centers->ext_center =
202 centers->synth_center = chan->channel;
203 return;
204 }
205
206 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
207 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
208 centers->synth_center =
209 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
210 extoff = 1;
211 } else {
212 centers->synth_center =
213 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
214 extoff = -1;
215 }
216
217 centers->ctl_center =
218 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
219 centers->ext_center =
220 centers->synth_center + (extoff *
221 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
222 HT40_CHANNEL_CENTER_SHIFT : 15));
223 }
224
225 /******************/
226 /* Chip Revisions */
227 /******************/
228
229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
230 {
231 u32 val;
232
233 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
234
235 if (val == 0xFF) {
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macVersion =
238 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
239 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
240 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
241 } else {
242 if (!AR_SREV_9100(ah))
243 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
244
245 ah->hw_version.macRev = val & AR_SREV_REVISION;
246
247 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
248 ah->is_pciexpress = true;
249 }
250 }
251
252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
253 {
254 u32 val;
255 int i;
256
257 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
258
259 for (i = 0; i < 8; i++)
260 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
261 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
262 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
263
264 return ath9k_hw_reverse_bits(val, 8);
265 }
266
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
270
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
272 {
273 if (AR_SREV_9100(ah))
274 return;
275
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
285
286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
287 }
288
289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
290 {
291 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
292 u32 regHold[2];
293 u32 patternData[4] = { 0x55555555,
294 0xaaaaaaaa,
295 0x66666666,
296 0x99999999 };
297 int i, j;
298
299 for (i = 0; i < 2; i++) {
300 u32 addr = regAddr[i];
301 u32 wrData, rdData;
302
303 regHold[i] = REG_READ(ah, addr);
304 for (j = 0; j < 0x100; j++) {
305 wrData = (j << 16) | j;
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr, wrData, rdData);
313 return false;
314 }
315 }
316 for (j = 0; j < 4; j++) {
317 wrData = patternData[j];
318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr, wrData, rdData);
325 return false;
326 }
327 }
328 REG_WRITE(ah, regAddr[i], regHold[i]);
329 }
330 udelay(100);
331
332 return true;
333 }
334
335 static const char *ath9k_hw_devname(u16 devid)
336 {
337 switch (devid) {
338 case AR5416_DEVID_PCI:
339 return "Atheros 5416";
340 case AR5416_DEVID_PCIE:
341 return "Atheros 5418";
342 case AR9160_DEVID_PCI:
343 return "Atheros 9160";
344 case AR5416_AR9100_DEVID:
345 return "Atheros 9100";
346 case AR9280_DEVID_PCI:
347 case AR9280_DEVID_PCIE:
348 return "Atheros 9280";
349 case AR9285_DEVID_PCIE:
350 return "Atheros 9285";
351 }
352
353 return NULL;
354 }
355
356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
357 {
358 int i;
359
360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_clock_req = 0;
367 ah->config.pcie_waen = 0;
368 ah->config.analog_shiftreg = 1;
369 ah->config.ht_enable = 1;
370 ah->config.ofdm_trig_low = 200;
371 ah->config.ofdm_trig_high = 500;
372 ah->config.cck_trig_high = 200;
373 ah->config.cck_trig_low = 100;
374 ah->config.enable_ani = 1;
375 ah->config.diversity_control = 0;
376 ah->config.antenna_switch_swap = 0;
377
378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
381 }
382
383 ah->config.intr_mitigation = 1;
384
385 /*
386 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
387 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
388 * This means we use it for all AR5416 devices, and the few
389 * minor PCI AR9280 devices out there.
390 *
391 * Serialization is required because these devices do not handle
392 * well the case of two concurrent reads/writes due to the latency
393 * involved. During one read/write another read/write can be issued
394 * on another CPU while the previous read/write may still be working
395 * on our hardware, if we hit this case the hardware poops in a loop.
396 * We prevent this by serializing reads and writes.
397 *
398 * This issue is not present on PCI-Express devices or pre-AR5416
399 * devices (legacy, 802.11abg).
400 */
401 if (num_possible_cpus() > 1)
402 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
403 }
404
405 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
406 int *status)
407 {
408 struct ath_hw *ah;
409
410 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
411 if (ah == NULL) {
412 DPRINTF(sc, ATH_DBG_FATAL,
413 "Cannot allocate memory for state block\n");
414 *status = -ENOMEM;
415 return NULL;
416 }
417
418 ah->ah_sc = sc;
419 ah->hw_version.magic = AR5416_MAGIC;
420 ah->regulatory.country_code = CTRY_DEFAULT;
421 ah->hw_version.devid = devid;
422 ah->hw_version.subvendorid = 0;
423
424 ah->ah_flags = 0;
425 if ((devid == AR5416_AR9100_DEVID))
426 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
427 if (!AR_SREV_9100(ah))
428 ah->ah_flags = AH_USE_EEPROM;
429
430 ah->regulatory.power_limit = MAX_RATE_POWER;
431 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
432 ah->atim_window = 0;
433 ah->diversity_control = ah->config.diversity_control;
434 ah->antenna_switch_swap =
435 ah->config.antenna_switch_swap;
436 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
437 ah->beacon_interval = 100;
438 ah->enable_32kHz_clock = DONT_USE_32KHZ;
439 ah->slottime = (u32) -1;
440 ah->acktimeout = (u32) -1;
441 ah->ctstimeout = (u32) -1;
442 ah->globaltxtimeout = (u32) -1;
443
444 ah->gbeacon_rate = 0;
445
446 return ah;
447 }
448
449 static int ath9k_hw_rfattach(struct ath_hw *ah)
450 {
451 bool rfStatus = false;
452 int ecode = 0;
453
454 rfStatus = ath9k_hw_init_rf(ah, &ecode);
455 if (!rfStatus) {
456 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
457 "RF setup failed, status: %u\n", ecode);
458 return ecode;
459 }
460
461 return 0;
462 }
463
464 static int ath9k_hw_rf_claim(struct ath_hw *ah)
465 {
466 u32 val;
467
468 REG_WRITE(ah, AR_PHY(0), 0x00000007);
469
470 val = ath9k_hw_get_radiorev(ah);
471 switch (val & AR_RADIO_SREV_MAJOR) {
472 case 0:
473 val = AR_RAD5133_SREV_MAJOR;
474 break;
475 case AR_RAD5133_SREV_MAJOR:
476 case AR_RAD5122_SREV_MAJOR:
477 case AR_RAD2133_SREV_MAJOR:
478 case AR_RAD2122_SREV_MAJOR:
479 break;
480 default:
481 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
482 "Radio Chip Rev 0x%02X not supported\n",
483 val & AR_RADIO_SREV_MAJOR);
484 return -EOPNOTSUPP;
485 }
486
487 ah->hw_version.analog5GhzRev = val;
488
489 return 0;
490 }
491
492 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
493 {
494 u32 sum;
495 int i;
496 u16 eeval;
497
498 sum = 0;
499 for (i = 0; i < 3; i++) {
500 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
501 sum += eeval;
502 ah->macaddr[2 * i] = eeval >> 8;
503 ah->macaddr[2 * i + 1] = eeval & 0xff;
504 }
505 if (sum == 0 || sum == 0xffff * 3)
506 return -EADDRNOTAVAIL;
507
508 return 0;
509 }
510
511 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
512 {
513 u32 rxgain_type;
514
515 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
516 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
517
518 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
519 INIT_INI_ARRAY(&ah->iniModesRxGain,
520 ar9280Modes_backoff_13db_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
522 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
523 INIT_INI_ARRAY(&ah->iniModesRxGain,
524 ar9280Modes_backoff_23db_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
526 else
527 INIT_INI_ARRAY(&ah->iniModesRxGain,
528 ar9280Modes_original_rxgain_9280_2,
529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
530 } else {
531 INIT_INI_ARRAY(&ah->iniModesRxGain,
532 ar9280Modes_original_rxgain_9280_2,
533 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
534 }
535 }
536
537 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
538 {
539 u32 txgain_type;
540
541 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
542 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
543
544 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
545 INIT_INI_ARRAY(&ah->iniModesTxGain,
546 ar9280Modes_high_power_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
548 else
549 INIT_INI_ARRAY(&ah->iniModesTxGain,
550 ar9280Modes_original_tx_gain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
552 } else {
553 INIT_INI_ARRAY(&ah->iniModesTxGain,
554 ar9280Modes_original_tx_gain_9280_2,
555 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
556 }
557 }
558
559 static int ath9k_hw_post_attach(struct ath_hw *ah)
560 {
561 int ecode;
562
563 if (!ath9k_hw_chip_test(ah))
564 return -ENODEV;
565
566 ecode = ath9k_hw_rf_claim(ah);
567 if (ecode != 0)
568 return ecode;
569
570 ecode = ath9k_hw_eeprom_attach(ah);
571 if (ecode != 0)
572 return ecode;
573
574 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
575 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
576
577 ecode = ath9k_hw_rfattach(ah);
578 if (ecode != 0)
579 return ecode;
580
581 if (!AR_SREV_9100(ah)) {
582 ath9k_hw_ani_setup(ah);
583 ath9k_hw_ani_attach(ah);
584 }
585
586 return 0;
587 }
588
589 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
590 int *status)
591 {
592 struct ath_hw *ah;
593 int ecode;
594 u32 i, j;
595
596 ah = ath9k_hw_newstate(devid, sc, status);
597 if (ah == NULL)
598 return NULL;
599
600 ath9k_hw_set_defaults(ah);
601
602 if (ah->config.intr_mitigation != 0)
603 ah->intr_mitigation = true;
604
605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
606 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
607 ecode = -EIO;
608 goto bad;
609 }
610
611 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
612 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
613 ecode = -EIO;
614 goto bad;
615 }
616
617 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
618 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
619 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
620 ah->config.serialize_regmode =
621 SER_REG_MODE_ON;
622 } else {
623 ah->config.serialize_regmode =
624 SER_REG_MODE_OFF;
625 }
626 }
627
628 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
629 ah->config.serialize_regmode);
630
631 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
632 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
633 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
634 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
635 DPRINTF(sc, ATH_DBG_FATAL,
636 "Mac Chip Rev 0x%02x.%x is not supported by "
637 "this driver\n", ah->hw_version.macVersion,
638 ah->hw_version.macRev);
639 ecode = -EOPNOTSUPP;
640 goto bad;
641 }
642
643 if (AR_SREV_9100(ah)) {
644 ah->iq_caldata.calData = &iq_cal_multi_sample;
645 ah->supp_cals = IQ_MISMATCH_CAL;
646 ah->is_pciexpress = false;
647 }
648 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
649
650 if (AR_SREV_9160_10_OR_LATER(ah)) {
651 if (AR_SREV_9280_10_OR_LATER(ah)) {
652 ah->iq_caldata.calData = &iq_cal_single_sample;
653 ah->adcgain_caldata.calData =
654 &adc_gain_cal_single_sample;
655 ah->adcdc_caldata.calData =
656 &adc_dc_cal_single_sample;
657 ah->adcdc_calinitdata.calData =
658 &adc_init_dc_cal;
659 } else {
660 ah->iq_caldata.calData = &iq_cal_multi_sample;
661 ah->adcgain_caldata.calData =
662 &adc_gain_cal_multi_sample;
663 ah->adcdc_caldata.calData =
664 &adc_dc_cal_multi_sample;
665 ah->adcdc_calinitdata.calData =
666 &adc_init_dc_cal;
667 }
668 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
669 }
670
671 ah->ani_function = ATH9K_ANI_ALL;
672 if (AR_SREV_9280_10_OR_LATER(ah))
673 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
674
675 if (AR_SREV_9285_12_OR_LATER(ah)) {
676
677 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
678 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
679 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
680 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
681
682 if (ah->config.pcie_clock_req) {
683 INIT_INI_ARRAY(&ah->iniPcieSerdes,
684 ar9285PciePhy_clkreq_off_L1_9285_1_2,
685 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
686 } else {
687 INIT_INI_ARRAY(&ah->iniPcieSerdes,
688 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
689 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
690 2);
691 }
692 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
693 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
694 ARRAY_SIZE(ar9285Modes_9285), 6);
695 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
696 ARRAY_SIZE(ar9285Common_9285), 2);
697
698 if (ah->config.pcie_clock_req) {
699 INIT_INI_ARRAY(&ah->iniPcieSerdes,
700 ar9285PciePhy_clkreq_off_L1_9285,
701 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
702 } else {
703 INIT_INI_ARRAY(&ah->iniPcieSerdes,
704 ar9285PciePhy_clkreq_always_on_L1_9285,
705 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
706 }
707 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
708 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
709 ARRAY_SIZE(ar9280Modes_9280_2), 6);
710 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
711 ARRAY_SIZE(ar9280Common_9280_2), 2);
712
713 if (ah->config.pcie_clock_req) {
714 INIT_INI_ARRAY(&ah->iniPcieSerdes,
715 ar9280PciePhy_clkreq_off_L1_9280,
716 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
717 } else {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
719 ar9280PciePhy_clkreq_always_on_L1_9280,
720 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
721 }
722 INIT_INI_ARRAY(&ah->iniModesAdditional,
723 ar9280Modes_fast_clock_9280_2,
724 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
725 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
726 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
727 ARRAY_SIZE(ar9280Modes_9280), 6);
728 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
729 ARRAY_SIZE(ar9280Common_9280), 2);
730 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
731 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
732 ARRAY_SIZE(ar5416Modes_9160), 6);
733 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
734 ARRAY_SIZE(ar5416Common_9160), 2);
735 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
736 ARRAY_SIZE(ar5416Bank0_9160), 2);
737 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
738 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
739 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
740 ARRAY_SIZE(ar5416Bank1_9160), 2);
741 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
742 ARRAY_SIZE(ar5416Bank2_9160), 2);
743 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
744 ARRAY_SIZE(ar5416Bank3_9160), 3);
745 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
746 ARRAY_SIZE(ar5416Bank6_9160), 3);
747 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
748 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
749 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
750 ARRAY_SIZE(ar5416Bank7_9160), 2);
751 if (AR_SREV_9160_11(ah)) {
752 INIT_INI_ARRAY(&ah->iniAddac,
753 ar5416Addac_91601_1,
754 ARRAY_SIZE(ar5416Addac_91601_1), 2);
755 } else {
756 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
757 ARRAY_SIZE(ar5416Addac_9160), 2);
758 }
759 } else if (AR_SREV_9100_OR_LATER(ah)) {
760 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
761 ARRAY_SIZE(ar5416Modes_9100), 6);
762 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
763 ARRAY_SIZE(ar5416Common_9100), 2);
764 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
765 ARRAY_SIZE(ar5416Bank0_9100), 2);
766 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
767 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
768 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
769 ARRAY_SIZE(ar5416Bank1_9100), 2);
770 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
771 ARRAY_SIZE(ar5416Bank2_9100), 2);
772 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
773 ARRAY_SIZE(ar5416Bank3_9100), 3);
774 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
775 ARRAY_SIZE(ar5416Bank6_9100), 3);
776 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
777 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
778 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
779 ARRAY_SIZE(ar5416Bank7_9100), 2);
780 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
781 ARRAY_SIZE(ar5416Addac_9100), 2);
782 } else {
783 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
784 ARRAY_SIZE(ar5416Modes), 6);
785 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
786 ARRAY_SIZE(ar5416Common), 2);
787 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
788 ARRAY_SIZE(ar5416Bank0), 2);
789 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
790 ARRAY_SIZE(ar5416BB_RfGain), 3);
791 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
792 ARRAY_SIZE(ar5416Bank1), 2);
793 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
794 ARRAY_SIZE(ar5416Bank2), 2);
795 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
796 ARRAY_SIZE(ar5416Bank3), 3);
797 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
798 ARRAY_SIZE(ar5416Bank6), 3);
799 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
800 ARRAY_SIZE(ar5416Bank6TPC), 3);
801 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
802 ARRAY_SIZE(ar5416Bank7), 2);
803 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
804 ARRAY_SIZE(ar5416Addac), 2);
805 }
806
807 if (ah->is_pciexpress)
808 ath9k_hw_configpcipowersave(ah, 0);
809 else
810 ath9k_hw_disablepcie(ah);
811
812 ecode = ath9k_hw_post_attach(ah);
813 if (ecode != 0)
814 goto bad;
815
816 if (AR_SREV_9285_12_OR_LATER(ah)) {
817 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
818
819 /* txgain table */
820 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
821 INIT_INI_ARRAY(&ah->iniModesTxGain,
822 ar9285Modes_high_power_tx_gain_9285_1_2,
823 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
824 } else {
825 INIT_INI_ARRAY(&ah->iniModesTxGain,
826 ar9285Modes_original_tx_gain_9285_1_2,
827 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
828 }
829
830 }
831
832 /* rxgain table */
833 if (AR_SREV_9280_20(ah))
834 ath9k_hw_init_rxgain_ini(ah);
835
836 /* txgain table */
837 if (AR_SREV_9280_20(ah))
838 ath9k_hw_init_txgain_ini(ah);
839
840 ath9k_hw_fill_cap_info(ah);
841
842 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
843 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
844
845 /* EEPROM Fixup */
846 for (i = 0; i < ah->iniModes.ia_rows; i++) {
847 u32 reg = INI_RA(&ah->iniModes, i, 0);
848
849 for (j = 1; j < ah->iniModes.ia_columns; j++) {
850 u32 val = INI_RA(&ah->iniModes, i, j);
851
852 INI_RA(&ah->iniModes, i, j) =
853 ath9k_hw_ini_fixup(ah,
854 &ah->eeprom.def,
855 reg, val);
856 }
857 }
858 }
859
860 ecode = ath9k_hw_init_macaddr(ah);
861 if (ecode != 0) {
862 DPRINTF(sc, ATH_DBG_FATAL,
863 "Failed to initialize MAC address\n");
864 goto bad;
865 }
866
867 if (AR_SREV_9285(ah))
868 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
869 else
870 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
871
872 ath9k_init_nfcal_hist_buffer(ah);
873
874 return ah;
875 bad:
876 if (ah)
877 ath9k_hw_detach(ah);
878 if (status)
879 *status = ecode;
880
881 return NULL;
882 }
883
884 static void ath9k_hw_init_bb(struct ath_hw *ah,
885 struct ath9k_channel *chan)
886 {
887 u32 synthDelay;
888
889 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
890 if (IS_CHAN_B(chan))
891 synthDelay = (4 * synthDelay) / 22;
892 else
893 synthDelay /= 10;
894
895 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
896
897 udelay(synthDelay + BASE_ACTIVATE_DELAY);
898 }
899
900 static void ath9k_hw_init_qos(struct ath_hw *ah)
901 {
902 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
903 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
904
905 REG_WRITE(ah, AR_QOS_NO_ACK,
906 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
907 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
908 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
909
910 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
911 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
912 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
913 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
914 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
915 }
916
917 static void ath9k_hw_init_pll(struct ath_hw *ah,
918 struct ath9k_channel *chan)
919 {
920 u32 pll;
921
922 if (AR_SREV_9100(ah)) {
923 if (chan && IS_CHAN_5GHZ(chan))
924 pll = 0x1450;
925 else
926 pll = 0x1458;
927 } else {
928 if (AR_SREV_9280_10_OR_LATER(ah)) {
929 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
930
931 if (chan && IS_CHAN_HALF_RATE(chan))
932 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
933 else if (chan && IS_CHAN_QUARTER_RATE(chan))
934 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
935
936 if (chan && IS_CHAN_5GHZ(chan)) {
937 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
938
939
940 if (AR_SREV_9280_20(ah)) {
941 if (((chan->channel % 20) == 0)
942 || ((chan->channel % 10) == 0))
943 pll = 0x2850;
944 else
945 pll = 0x142c;
946 }
947 } else {
948 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
949 }
950
951 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
952
953 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
954
955 if (chan && IS_CHAN_HALF_RATE(chan))
956 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
957 else if (chan && IS_CHAN_QUARTER_RATE(chan))
958 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
959
960 if (chan && IS_CHAN_5GHZ(chan))
961 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
962 else
963 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
964 } else {
965 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
966
967 if (chan && IS_CHAN_HALF_RATE(chan))
968 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
969 else if (chan && IS_CHAN_QUARTER_RATE(chan))
970 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
971
972 if (chan && IS_CHAN_5GHZ(chan))
973 pll |= SM(0xa, AR_RTC_PLL_DIV);
974 else
975 pll |= SM(0xb, AR_RTC_PLL_DIV);
976 }
977 }
978 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
979
980 udelay(RTC_PLL_SETTLE_DELAY);
981
982 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
983 }
984
985 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
986 {
987 int rx_chainmask, tx_chainmask;
988
989 rx_chainmask = ah->rxchainmask;
990 tx_chainmask = ah->txchainmask;
991
992 switch (rx_chainmask) {
993 case 0x5:
994 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
995 AR_PHY_SWAP_ALT_CHAIN);
996 case 0x3:
997 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
998 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
999 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1000 break;
1001 }
1002 case 0x1:
1003 case 0x2:
1004 case 0x7:
1005 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1006 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1007 break;
1008 default:
1009 break;
1010 }
1011
1012 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1013 if (tx_chainmask == 0x5) {
1014 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1015 AR_PHY_SWAP_ALT_CHAIN);
1016 }
1017 if (AR_SREV_9100(ah))
1018 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1019 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1020 }
1021
1022 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1023 enum nl80211_iftype opmode)
1024 {
1025 ah->mask_reg = AR_IMR_TXERR |
1026 AR_IMR_TXURN |
1027 AR_IMR_RXERR |
1028 AR_IMR_RXORN |
1029 AR_IMR_BCNMISC;
1030
1031 if (ah->intr_mitigation)
1032 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1033 else
1034 ah->mask_reg |= AR_IMR_RXOK;
1035
1036 ah->mask_reg |= AR_IMR_TXOK;
1037
1038 if (opmode == NL80211_IFTYPE_AP)
1039 ah->mask_reg |= AR_IMR_MIB;
1040
1041 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1042 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1043
1044 if (!AR_SREV_9100(ah)) {
1045 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1046 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1047 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1048 }
1049 }
1050
1051 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1052 {
1053 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1054 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1055 ah->acktimeout = (u32) -1;
1056 return false;
1057 } else {
1058 REG_RMW_FIELD(ah, AR_TIME_OUT,
1059 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1060 ah->acktimeout = us;
1061 return true;
1062 }
1063 }
1064
1065 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1066 {
1067 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1068 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1069 ah->ctstimeout = (u32) -1;
1070 return false;
1071 } else {
1072 REG_RMW_FIELD(ah, AR_TIME_OUT,
1073 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1074 ah->ctstimeout = us;
1075 return true;
1076 }
1077 }
1078
1079 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1080 {
1081 if (tu > 0xFFFF) {
1082 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1083 "bad global tx timeout %u\n", tu);
1084 ah->globaltxtimeout = (u32) -1;
1085 return false;
1086 } else {
1087 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1088 ah->globaltxtimeout = tu;
1089 return true;
1090 }
1091 }
1092
1093 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1094 {
1095 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1096 ah->misc_mode);
1097
1098 if (ah->misc_mode != 0)
1099 REG_WRITE(ah, AR_PCU_MISC,
1100 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1101 if (ah->slottime != (u32) -1)
1102 ath9k_hw_setslottime(ah, ah->slottime);
1103 if (ah->acktimeout != (u32) -1)
1104 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1105 if (ah->ctstimeout != (u32) -1)
1106 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1107 if (ah->globaltxtimeout != (u32) -1)
1108 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1109 }
1110
1111 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1112 {
1113 return vendorid == ATHEROS_VENDOR_ID ?
1114 ath9k_hw_devname(devid) : NULL;
1115 }
1116
1117 void ath9k_hw_detach(struct ath_hw *ah)
1118 {
1119 if (!AR_SREV_9100(ah))
1120 ath9k_hw_ani_detach(ah);
1121
1122 ath9k_hw_rfdetach(ah);
1123 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1124 kfree(ah);
1125 }
1126
1127 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1128 {
1129 struct ath_hw *ah = NULL;
1130
1131 switch (devid) {
1132 case AR5416_DEVID_PCI:
1133 case AR5416_DEVID_PCIE:
1134 case AR5416_AR9100_DEVID:
1135 case AR9160_DEVID_PCI:
1136 case AR9280_DEVID_PCI:
1137 case AR9280_DEVID_PCIE:
1138 case AR9285_DEVID_PCIE:
1139 ah = ath9k_hw_do_attach(devid, sc, error);
1140 break;
1141 default:
1142 *error = -ENXIO;
1143 break;
1144 }
1145
1146 return ah;
1147 }
1148
1149 /*******/
1150 /* INI */
1151 /*******/
1152
1153 static void ath9k_hw_override_ini(struct ath_hw *ah,
1154 struct ath9k_channel *chan)
1155 {
1156 /*
1157 * Set the RX_ABORT and RX_DIS and clear if off only after
1158 * RXE is set for MAC. This prevents frames with corrupted
1159 * descriptor status.
1160 */
1161 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1162
1163
1164 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1165 AR_SREV_9280_10_OR_LATER(ah))
1166 return;
1167
1168 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1169 }
1170
1171 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1172 struct ar5416_eeprom_def *pEepData,
1173 u32 reg, u32 value)
1174 {
1175 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1176
1177 switch (ah->hw_version.devid) {
1178 case AR9280_DEVID_PCI:
1179 if (reg == 0x7894) {
1180 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1181 "ini VAL: %x EEPROM: %x\n", value,
1182 (pBase->version & 0xff));
1183
1184 if ((pBase->version & 0xff) > 0x0a) {
1185 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1186 "PWDCLKIND: %d\n",
1187 pBase->pwdclkind);
1188 value &= ~AR_AN_TOP2_PWDCLKIND;
1189 value |= AR_AN_TOP2_PWDCLKIND &
1190 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1191 } else {
1192 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1193 "PWDCLKIND Earlier Rev\n");
1194 }
1195
1196 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1197 "final ini VAL: %x\n", value);
1198 }
1199 break;
1200 }
1201
1202 return value;
1203 }
1204
1205 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1206 struct ar5416_eeprom_def *pEepData,
1207 u32 reg, u32 value)
1208 {
1209 if (ah->eep_map == EEP_MAP_4KBITS)
1210 return value;
1211 else
1212 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1213 }
1214
1215 static void ath9k_olc_init(struct ath_hw *ah)
1216 {
1217 u32 i;
1218
1219 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1220 ah->originalGain[i] =
1221 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1222 AR_PHY_TX_GAIN);
1223 ah->PDADCdelta = 0;
1224 }
1225
1226 static int ath9k_hw_process_ini(struct ath_hw *ah,
1227 struct ath9k_channel *chan,
1228 enum ath9k_ht_macmode macmode)
1229 {
1230 int i, regWrites = 0;
1231 struct ieee80211_channel *channel = chan->chan;
1232 u32 modesIndex, freqIndex;
1233 int status;
1234
1235 switch (chan->chanmode) {
1236 case CHANNEL_A:
1237 case CHANNEL_A_HT20:
1238 modesIndex = 1;
1239 freqIndex = 1;
1240 break;
1241 case CHANNEL_A_HT40PLUS:
1242 case CHANNEL_A_HT40MINUS:
1243 modesIndex = 2;
1244 freqIndex = 1;
1245 break;
1246 case CHANNEL_G:
1247 case CHANNEL_G_HT20:
1248 case CHANNEL_B:
1249 modesIndex = 4;
1250 freqIndex = 2;
1251 break;
1252 case CHANNEL_G_HT40PLUS:
1253 case CHANNEL_G_HT40MINUS:
1254 modesIndex = 3;
1255 freqIndex = 2;
1256 break;
1257
1258 default:
1259 return -EINVAL;
1260 }
1261
1262 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1263 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1264 ah->eep_ops->set_addac(ah, chan);
1265
1266 if (AR_SREV_5416_22_OR_LATER(ah)) {
1267 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1268 } else {
1269 struct ar5416IniArray temp;
1270 u32 addacSize =
1271 sizeof(u32) * ah->iniAddac.ia_rows *
1272 ah->iniAddac.ia_columns;
1273
1274 memcpy(ah->addac5416_21,
1275 ah->iniAddac.ia_array, addacSize);
1276
1277 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1278
1279 temp.ia_array = ah->addac5416_21;
1280 temp.ia_columns = ah->iniAddac.ia_columns;
1281 temp.ia_rows = ah->iniAddac.ia_rows;
1282 REG_WRITE_ARRAY(&temp, 1, regWrites);
1283 }
1284
1285 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1286
1287 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1288 u32 reg = INI_RA(&ah->iniModes, i, 0);
1289 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1290
1291 REG_WRITE(ah, reg, val);
1292
1293 if (reg >= 0x7800 && reg < 0x78a0
1294 && ah->config.analog_shiftreg) {
1295 udelay(100);
1296 }
1297
1298 DO_DELAY(regWrites);
1299 }
1300
1301 if (AR_SREV_9280(ah))
1302 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1303
1304 if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1305 AR_SREV_9285_12_OR_LATER(ah)))
1306 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1307
1308 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1309 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1310 u32 val = INI_RA(&ah->iniCommon, i, 1);
1311
1312 REG_WRITE(ah, reg, val);
1313
1314 if (reg >= 0x7800 && reg < 0x78a0
1315 && ah->config.analog_shiftreg) {
1316 udelay(100);
1317 }
1318
1319 DO_DELAY(regWrites);
1320 }
1321
1322 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1323
1324 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1325 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1326 regWrites);
1327 }
1328
1329 ath9k_hw_override_ini(ah, chan);
1330 ath9k_hw_set_regs(ah, chan, macmode);
1331 ath9k_hw_init_chain_masks(ah);
1332
1333 if (OLC_FOR_AR9280_20_LATER)
1334 ath9k_olc_init(ah);
1335
1336 status = ah->eep_ops->set_txpower(ah, chan,
1337 ath9k_regd_get_ctl(ah, chan),
1338 channel->max_antenna_gain * 2,
1339 channel->max_power * 2,
1340 min((u32) MAX_RATE_POWER,
1341 (u32) ah->regulatory.power_limit));
1342 if (status != 0) {
1343 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1344 "Error initializing transmit power\n");
1345 return -EIO;
1346 }
1347
1348 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1349 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1350 "ar5416SetRfRegs failed\n");
1351 return -EIO;
1352 }
1353
1354 return 0;
1355 }
1356
1357 /****************************************/
1358 /* Reset and Channel Switching Routines */
1359 /****************************************/
1360
1361 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1362 {
1363 u32 rfMode = 0;
1364
1365 if (chan == NULL)
1366 return;
1367
1368 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1369 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1370
1371 if (!AR_SREV_9280_10_OR_LATER(ah))
1372 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1373 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1374
1375 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1376 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1377
1378 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1379 }
1380
1381 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1382 {
1383 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1384 }
1385
1386 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1387 {
1388 u32 regval;
1389
1390 regval = REG_READ(ah, AR_AHB_MODE);
1391 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1392
1393 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1394 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1395
1396 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1397
1398 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1399 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1400
1401 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1402
1403 if (AR_SREV_9285(ah)) {
1404 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1405 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1406 } else {
1407 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1408 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1409 }
1410 }
1411
1412 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1413 {
1414 u32 val;
1415
1416 val = REG_READ(ah, AR_STA_ID1);
1417 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1418 switch (opmode) {
1419 case NL80211_IFTYPE_AP:
1420 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1421 | AR_STA_ID1_KSRCH_MODE);
1422 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1423 break;
1424 case NL80211_IFTYPE_ADHOC:
1425 case NL80211_IFTYPE_MESH_POINT:
1426 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1427 | AR_STA_ID1_KSRCH_MODE);
1428 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1429 break;
1430 case NL80211_IFTYPE_STATION:
1431 case NL80211_IFTYPE_MONITOR:
1432 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1433 break;
1434 }
1435 }
1436
1437 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1438 u32 coef_scaled,
1439 u32 *coef_mantissa,
1440 u32 *coef_exponent)
1441 {
1442 u32 coef_exp, coef_man;
1443
1444 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1445 if ((coef_scaled >> coef_exp) & 0x1)
1446 break;
1447
1448 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1449
1450 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1451
1452 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1453 *coef_exponent = coef_exp - 16;
1454 }
1455
1456 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1457 struct ath9k_channel *chan)
1458 {
1459 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1460 u32 clockMhzScaled = 0x64000000;
1461 struct chan_centers centers;
1462
1463 if (IS_CHAN_HALF_RATE(chan))
1464 clockMhzScaled = clockMhzScaled >> 1;
1465 else if (IS_CHAN_QUARTER_RATE(chan))
1466 clockMhzScaled = clockMhzScaled >> 2;
1467
1468 ath9k_hw_get_channel_centers(ah, chan, &centers);
1469 coef_scaled = clockMhzScaled / centers.synth_center;
1470
1471 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1472 &ds_coef_exp);
1473
1474 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1475 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1476 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1477 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1478
1479 coef_scaled = (9 * coef_scaled) / 10;
1480
1481 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1482 &ds_coef_exp);
1483
1484 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1485 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1486 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1487 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1488 }
1489
1490 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1491 {
1492 u32 rst_flags;
1493 u32 tmpReg;
1494
1495 if (AR_SREV_9100(ah)) {
1496 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1497 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1498 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1499 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1500 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1501 }
1502
1503 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1504 AR_RTC_FORCE_WAKE_ON_INT);
1505
1506 if (AR_SREV_9100(ah)) {
1507 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1508 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1509 } else {
1510 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1511 if (tmpReg &
1512 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1513 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1514 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1515 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1516 } else {
1517 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1518 }
1519
1520 rst_flags = AR_RTC_RC_MAC_WARM;
1521 if (type == ATH9K_RESET_COLD)
1522 rst_flags |= AR_RTC_RC_MAC_COLD;
1523 }
1524
1525 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1526 udelay(50);
1527
1528 REG_WRITE(ah, AR_RTC_RC, 0);
1529 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1530 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1531 "RTC stuck in MAC reset\n");
1532 return false;
1533 }
1534
1535 if (!AR_SREV_9100(ah))
1536 REG_WRITE(ah, AR_RC, 0);
1537
1538 ath9k_hw_init_pll(ah, NULL);
1539
1540 if (AR_SREV_9100(ah))
1541 udelay(50);
1542
1543 return true;
1544 }
1545
1546 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1547 {
1548 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1549 AR_RTC_FORCE_WAKE_ON_INT);
1550
1551 REG_WRITE(ah, AR_RTC_RESET, 0);
1552 udelay(2);
1553 REG_WRITE(ah, AR_RTC_RESET, 1);
1554
1555 if (!ath9k_hw_wait(ah,
1556 AR_RTC_STATUS,
1557 AR_RTC_STATUS_M,
1558 AR_RTC_STATUS_ON,
1559 AH_WAIT_TIMEOUT)) {
1560 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1561 return false;
1562 }
1563
1564 ath9k_hw_read_revisions(ah);
1565
1566 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1567 }
1568
1569 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1570 {
1571 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1572 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1573
1574 switch (type) {
1575 case ATH9K_RESET_POWER_ON:
1576 return ath9k_hw_set_reset_power_on(ah);
1577 break;
1578 case ATH9K_RESET_WARM:
1579 case ATH9K_RESET_COLD:
1580 return ath9k_hw_set_reset(ah, type);
1581 break;
1582 default:
1583 return false;
1584 }
1585 }
1586
1587 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1588 enum ath9k_ht_macmode macmode)
1589 {
1590 u32 phymode;
1591 u32 enableDacFifo = 0;
1592
1593 if (AR_SREV_9285_10_OR_LATER(ah))
1594 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1595 AR_PHY_FC_ENABLE_DAC_FIFO);
1596
1597 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1598 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1599
1600 if (IS_CHAN_HT40(chan)) {
1601 phymode |= AR_PHY_FC_DYN2040_EN;
1602
1603 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1604 (chan->chanmode == CHANNEL_G_HT40PLUS))
1605 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1606
1607 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1608 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1609 }
1610 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1611
1612 ath9k_hw_set11nmac2040(ah, macmode);
1613
1614 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1615 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1616 }
1617
1618 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1619 struct ath9k_channel *chan)
1620 {
1621 if (OLC_FOR_AR9280_20_LATER) {
1622 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1623 return false;
1624 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1625 return false;
1626
1627 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1628 return false;
1629
1630 ah->chip_fullsleep = false;
1631 ath9k_hw_init_pll(ah, chan);
1632 ath9k_hw_set_rfmode(ah, chan);
1633
1634 return true;
1635 }
1636
1637 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1638 struct ath9k_channel *chan,
1639 enum ath9k_ht_macmode macmode)
1640 {
1641 struct ieee80211_channel *channel = chan->chan;
1642 u32 synthDelay, qnum;
1643
1644 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1645 if (ath9k_hw_numtxpending(ah, qnum)) {
1646 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1647 "Transmit frames pending on queue %d\n", qnum);
1648 return false;
1649 }
1650 }
1651
1652 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1653 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1654 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1655 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1656 "Could not kill baseband RX\n");
1657 return false;
1658 }
1659
1660 ath9k_hw_set_regs(ah, chan, macmode);
1661
1662 if (AR_SREV_9280_10_OR_LATER(ah)) {
1663 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1664 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1665 "Failed to set channel\n");
1666 return false;
1667 }
1668 } else {
1669 if (!(ath9k_hw_set_channel(ah, chan))) {
1670 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1671 "Failed to set channel\n");
1672 return false;
1673 }
1674 }
1675
1676 if (ah->eep_ops->set_txpower(ah, chan,
1677 ath9k_regd_get_ctl(ah, chan),
1678 channel->max_antenna_gain * 2,
1679 channel->max_power * 2,
1680 min((u32) MAX_RATE_POWER,
1681 (u32) ah->regulatory.power_limit)) != 0) {
1682 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1683 "Error initializing transmit power\n");
1684 return false;
1685 }
1686
1687 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1688 if (IS_CHAN_B(chan))
1689 synthDelay = (4 * synthDelay) / 22;
1690 else
1691 synthDelay /= 10;
1692
1693 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1694
1695 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1696
1697 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1698 ath9k_hw_set_delta_slope(ah, chan);
1699
1700 if (AR_SREV_9280_10_OR_LATER(ah))
1701 ath9k_hw_9280_spur_mitigate(ah, chan);
1702 else
1703 ath9k_hw_spur_mitigate(ah, chan);
1704
1705 if (!chan->oneTimeCalsDone)
1706 chan->oneTimeCalsDone = true;
1707
1708 return true;
1709 }
1710
1711 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1712 {
1713 int bb_spur = AR_NO_SPUR;
1714 int freq;
1715 int bin, cur_bin;
1716 int bb_spur_off, spur_subchannel_sd;
1717 int spur_freq_sd;
1718 int spur_delta_phase;
1719 int denominator;
1720 int upper, lower, cur_vit_mask;
1721 int tmp, newVal;
1722 int i;
1723 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1724 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1725 };
1726 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1727 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1728 };
1729 int inc[4] = { 0, 100, 0, 0 };
1730 struct chan_centers centers;
1731
1732 int8_t mask_m[123];
1733 int8_t mask_p[123];
1734 int8_t mask_amt;
1735 int tmp_mask;
1736 int cur_bb_spur;
1737 bool is2GHz = IS_CHAN_2GHZ(chan);
1738
1739 memset(&mask_m, 0, sizeof(int8_t) * 123);
1740 memset(&mask_p, 0, sizeof(int8_t) * 123);
1741
1742 ath9k_hw_get_channel_centers(ah, chan, &centers);
1743 freq = centers.synth_center;
1744
1745 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1746 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1747 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1748
1749 if (is2GHz)
1750 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1751 else
1752 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1753
1754 if (AR_NO_SPUR == cur_bb_spur)
1755 break;
1756 cur_bb_spur = cur_bb_spur - freq;
1757
1758 if (IS_CHAN_HT40(chan)) {
1759 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1760 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1761 bb_spur = cur_bb_spur;
1762 break;
1763 }
1764 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1765 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1766 bb_spur = cur_bb_spur;
1767 break;
1768 }
1769 }
1770
1771 if (AR_NO_SPUR == bb_spur) {
1772 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1773 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1774 return;
1775 } else {
1776 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1777 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1778 }
1779
1780 bin = bb_spur * 320;
1781
1782 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1783
1784 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1785 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1786 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1787 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1788 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1789
1790 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1791 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1792 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1793 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1794 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1795 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1796
1797 if (IS_CHAN_HT40(chan)) {
1798 if (bb_spur < 0) {
1799 spur_subchannel_sd = 1;
1800 bb_spur_off = bb_spur + 10;
1801 } else {
1802 spur_subchannel_sd = 0;
1803 bb_spur_off = bb_spur - 10;
1804 }
1805 } else {
1806 spur_subchannel_sd = 0;
1807 bb_spur_off = bb_spur;
1808 }
1809
1810 if (IS_CHAN_HT40(chan))
1811 spur_delta_phase =
1812 ((bb_spur * 262144) /
1813 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1814 else
1815 spur_delta_phase =
1816 ((bb_spur * 524288) /
1817 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1818
1819 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1820 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1821
1822 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1823 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1824 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1825 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1826
1827 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1828 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1829
1830 cur_bin = -6000;
1831 upper = bin + 100;
1832 lower = bin - 100;
1833
1834 for (i = 0; i < 4; i++) {
1835 int pilot_mask = 0;
1836 int chan_mask = 0;
1837 int bp = 0;
1838 for (bp = 0; bp < 30; bp++) {
1839 if ((cur_bin > lower) && (cur_bin < upper)) {
1840 pilot_mask = pilot_mask | 0x1 << bp;
1841 chan_mask = chan_mask | 0x1 << bp;
1842 }
1843 cur_bin += 100;
1844 }
1845 cur_bin += inc[i];
1846 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1847 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1848 }
1849
1850 cur_vit_mask = 6100;
1851 upper = bin + 120;
1852 lower = bin - 120;
1853
1854 for (i = 0; i < 123; i++) {
1855 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1856
1857 /* workaround for gcc bug #37014 */
1858 volatile int tmp_v = abs(cur_vit_mask - bin);
1859
1860 if (tmp_v < 75)
1861 mask_amt = 1;
1862 else
1863 mask_amt = 0;
1864 if (cur_vit_mask < 0)
1865 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1866 else
1867 mask_p[cur_vit_mask / 100] = mask_amt;
1868 }
1869 cur_vit_mask -= 100;
1870 }
1871
1872 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1873 | (mask_m[48] << 26) | (mask_m[49] << 24)
1874 | (mask_m[50] << 22) | (mask_m[51] << 20)
1875 | (mask_m[52] << 18) | (mask_m[53] << 16)
1876 | (mask_m[54] << 14) | (mask_m[55] << 12)
1877 | (mask_m[56] << 10) | (mask_m[57] << 8)
1878 | (mask_m[58] << 6) | (mask_m[59] << 4)
1879 | (mask_m[60] << 2) | (mask_m[61] << 0);
1880 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1881 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1882
1883 tmp_mask = (mask_m[31] << 28)
1884 | (mask_m[32] << 26) | (mask_m[33] << 24)
1885 | (mask_m[34] << 22) | (mask_m[35] << 20)
1886 | (mask_m[36] << 18) | (mask_m[37] << 16)
1887 | (mask_m[48] << 14) | (mask_m[39] << 12)
1888 | (mask_m[40] << 10) | (mask_m[41] << 8)
1889 | (mask_m[42] << 6) | (mask_m[43] << 4)
1890 | (mask_m[44] << 2) | (mask_m[45] << 0);
1891 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1892 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1893
1894 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1895 | (mask_m[18] << 26) | (mask_m[18] << 24)
1896 | (mask_m[20] << 22) | (mask_m[20] << 20)
1897 | (mask_m[22] << 18) | (mask_m[22] << 16)
1898 | (mask_m[24] << 14) | (mask_m[24] << 12)
1899 | (mask_m[25] << 10) | (mask_m[26] << 8)
1900 | (mask_m[27] << 6) | (mask_m[28] << 4)
1901 | (mask_m[29] << 2) | (mask_m[30] << 0);
1902 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1903 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1904
1905 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1906 | (mask_m[2] << 26) | (mask_m[3] << 24)
1907 | (mask_m[4] << 22) | (mask_m[5] << 20)
1908 | (mask_m[6] << 18) | (mask_m[7] << 16)
1909 | (mask_m[8] << 14) | (mask_m[9] << 12)
1910 | (mask_m[10] << 10) | (mask_m[11] << 8)
1911 | (mask_m[12] << 6) | (mask_m[13] << 4)
1912 | (mask_m[14] << 2) | (mask_m[15] << 0);
1913 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1914 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1915
1916 tmp_mask = (mask_p[15] << 28)
1917 | (mask_p[14] << 26) | (mask_p[13] << 24)
1918 | (mask_p[12] << 22) | (mask_p[11] << 20)
1919 | (mask_p[10] << 18) | (mask_p[9] << 16)
1920 | (mask_p[8] << 14) | (mask_p[7] << 12)
1921 | (mask_p[6] << 10) | (mask_p[5] << 8)
1922 | (mask_p[4] << 6) | (mask_p[3] << 4)
1923 | (mask_p[2] << 2) | (mask_p[1] << 0);
1924 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1925 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1926
1927 tmp_mask = (mask_p[30] << 28)
1928 | (mask_p[29] << 26) | (mask_p[28] << 24)
1929 | (mask_p[27] << 22) | (mask_p[26] << 20)
1930 | (mask_p[25] << 18) | (mask_p[24] << 16)
1931 | (mask_p[23] << 14) | (mask_p[22] << 12)
1932 | (mask_p[21] << 10) | (mask_p[20] << 8)
1933 | (mask_p[19] << 6) | (mask_p[18] << 4)
1934 | (mask_p[17] << 2) | (mask_p[16] << 0);
1935 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1936 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1937
1938 tmp_mask = (mask_p[45] << 28)
1939 | (mask_p[44] << 26) | (mask_p[43] << 24)
1940 | (mask_p[42] << 22) | (mask_p[41] << 20)
1941 | (mask_p[40] << 18) | (mask_p[39] << 16)
1942 | (mask_p[38] << 14) | (mask_p[37] << 12)
1943 | (mask_p[36] << 10) | (mask_p[35] << 8)
1944 | (mask_p[34] << 6) | (mask_p[33] << 4)
1945 | (mask_p[32] << 2) | (mask_p[31] << 0);
1946 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1947 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1948
1949 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1950 | (mask_p[59] << 26) | (mask_p[58] << 24)
1951 | (mask_p[57] << 22) | (mask_p[56] << 20)
1952 | (mask_p[55] << 18) | (mask_p[54] << 16)
1953 | (mask_p[53] << 14) | (mask_p[52] << 12)
1954 | (mask_p[51] << 10) | (mask_p[50] << 8)
1955 | (mask_p[49] << 6) | (mask_p[48] << 4)
1956 | (mask_p[47] << 2) | (mask_p[46] << 0);
1957 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1958 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1959 }
1960
1961 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1962 {
1963 int bb_spur = AR_NO_SPUR;
1964 int bin, cur_bin;
1965 int spur_freq_sd;
1966 int spur_delta_phase;
1967 int denominator;
1968 int upper, lower, cur_vit_mask;
1969 int tmp, new;
1970 int i;
1971 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1972 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1973 };
1974 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1975 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1976 };
1977 int inc[4] = { 0, 100, 0, 0 };
1978
1979 int8_t mask_m[123];
1980 int8_t mask_p[123];
1981 int8_t mask_amt;
1982 int tmp_mask;
1983 int cur_bb_spur;
1984 bool is2GHz = IS_CHAN_2GHZ(chan);
1985
1986 memset(&mask_m, 0, sizeof(int8_t) * 123);
1987 memset(&mask_p, 0, sizeof(int8_t) * 123);
1988
1989 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1990 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1991 if (AR_NO_SPUR == cur_bb_spur)
1992 break;
1993 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1994 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1995 bb_spur = cur_bb_spur;
1996 break;
1997 }
1998 }
1999
2000 if (AR_NO_SPUR == bb_spur)
2001 return;
2002
2003 bin = bb_spur * 32;
2004
2005 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2006 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2007 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2008 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2009 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2010
2011 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2012
2013 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2014 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2015 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2016 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2017 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2018 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2019
2020 spur_delta_phase = ((bb_spur * 524288) / 100) &
2021 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2022
2023 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2024 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2025
2026 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2027 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2028 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2029 REG_WRITE(ah, AR_PHY_TIMING11, new);
2030
2031 cur_bin = -6000;
2032 upper = bin + 100;
2033 lower = bin - 100;
2034
2035 for (i = 0; i < 4; i++) {
2036 int pilot_mask = 0;
2037 int chan_mask = 0;
2038 int bp = 0;
2039 for (bp = 0; bp < 30; bp++) {
2040 if ((cur_bin > lower) && (cur_bin < upper)) {
2041 pilot_mask = pilot_mask | 0x1 << bp;
2042 chan_mask = chan_mask | 0x1 << bp;
2043 }
2044 cur_bin += 100;
2045 }
2046 cur_bin += inc[i];
2047 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2048 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2049 }
2050
2051 cur_vit_mask = 6100;
2052 upper = bin + 120;
2053 lower = bin - 120;
2054
2055 for (i = 0; i < 123; i++) {
2056 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2057
2058 /* workaround for gcc bug #37014 */
2059 volatile int tmp_v = abs(cur_vit_mask - bin);
2060
2061 if (tmp_v < 75)
2062 mask_amt = 1;
2063 else
2064 mask_amt = 0;
2065 if (cur_vit_mask < 0)
2066 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2067 else
2068 mask_p[cur_vit_mask / 100] = mask_amt;
2069 }
2070 cur_vit_mask -= 100;
2071 }
2072
2073 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2074 | (mask_m[48] << 26) | (mask_m[49] << 24)
2075 | (mask_m[50] << 22) | (mask_m[51] << 20)
2076 | (mask_m[52] << 18) | (mask_m[53] << 16)
2077 | (mask_m[54] << 14) | (mask_m[55] << 12)
2078 | (mask_m[56] << 10) | (mask_m[57] << 8)
2079 | (mask_m[58] << 6) | (mask_m[59] << 4)
2080 | (mask_m[60] << 2) | (mask_m[61] << 0);
2081 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2082 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2083
2084 tmp_mask = (mask_m[31] << 28)
2085 | (mask_m[32] << 26) | (mask_m[33] << 24)
2086 | (mask_m[34] << 22) | (mask_m[35] << 20)
2087 | (mask_m[36] << 18) | (mask_m[37] << 16)
2088 | (mask_m[48] << 14) | (mask_m[39] << 12)
2089 | (mask_m[40] << 10) | (mask_m[41] << 8)
2090 | (mask_m[42] << 6) | (mask_m[43] << 4)
2091 | (mask_m[44] << 2) | (mask_m[45] << 0);
2092 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2093 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2094
2095 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2096 | (mask_m[18] << 26) | (mask_m[18] << 24)
2097 | (mask_m[20] << 22) | (mask_m[20] << 20)
2098 | (mask_m[22] << 18) | (mask_m[22] << 16)
2099 | (mask_m[24] << 14) | (mask_m[24] << 12)
2100 | (mask_m[25] << 10) | (mask_m[26] << 8)
2101 | (mask_m[27] << 6) | (mask_m[28] << 4)
2102 | (mask_m[29] << 2) | (mask_m[30] << 0);
2103 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2104 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2105
2106 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2107 | (mask_m[2] << 26) | (mask_m[3] << 24)
2108 | (mask_m[4] << 22) | (mask_m[5] << 20)
2109 | (mask_m[6] << 18) | (mask_m[7] << 16)
2110 | (mask_m[8] << 14) | (mask_m[9] << 12)
2111 | (mask_m[10] << 10) | (mask_m[11] << 8)
2112 | (mask_m[12] << 6) | (mask_m[13] << 4)
2113 | (mask_m[14] << 2) | (mask_m[15] << 0);
2114 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2115 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2116
2117 tmp_mask = (mask_p[15] << 28)
2118 | (mask_p[14] << 26) | (mask_p[13] << 24)
2119 | (mask_p[12] << 22) | (mask_p[11] << 20)
2120 | (mask_p[10] << 18) | (mask_p[9] << 16)
2121 | (mask_p[8] << 14) | (mask_p[7] << 12)
2122 | (mask_p[6] << 10) | (mask_p[5] << 8)
2123 | (mask_p[4] << 6) | (mask_p[3] << 4)
2124 | (mask_p[2] << 2) | (mask_p[1] << 0);
2125 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2126 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2127
2128 tmp_mask = (mask_p[30] << 28)
2129 | (mask_p[29] << 26) | (mask_p[28] << 24)
2130 | (mask_p[27] << 22) | (mask_p[26] << 20)
2131 | (mask_p[25] << 18) | (mask_p[24] << 16)
2132 | (mask_p[23] << 14) | (mask_p[22] << 12)
2133 | (mask_p[21] << 10) | (mask_p[20] << 8)
2134 | (mask_p[19] << 6) | (mask_p[18] << 4)
2135 | (mask_p[17] << 2) | (mask_p[16] << 0);
2136 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2137 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2138
2139 tmp_mask = (mask_p[45] << 28)
2140 | (mask_p[44] << 26) | (mask_p[43] << 24)
2141 | (mask_p[42] << 22) | (mask_p[41] << 20)
2142 | (mask_p[40] << 18) | (mask_p[39] << 16)
2143 | (mask_p[38] << 14) | (mask_p[37] << 12)
2144 | (mask_p[36] << 10) | (mask_p[35] << 8)
2145 | (mask_p[34] << 6) | (mask_p[33] << 4)
2146 | (mask_p[32] << 2) | (mask_p[31] << 0);
2147 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2148 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2149
2150 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2151 | (mask_p[59] << 26) | (mask_p[58] << 24)
2152 | (mask_p[57] << 22) | (mask_p[56] << 20)
2153 | (mask_p[55] << 18) | (mask_p[54] << 16)
2154 | (mask_p[53] << 14) | (mask_p[52] << 12)
2155 | (mask_p[51] << 10) | (mask_p[50] << 8)
2156 | (mask_p[49] << 6) | (mask_p[48] << 4)
2157 | (mask_p[47] << 2) | (mask_p[46] << 0);
2158 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2159 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2160 }
2161
2162 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2163 bool bChannelChange)
2164 {
2165 u32 saveLedState;
2166 struct ath_softc *sc = ah->ah_sc;
2167 struct ath9k_channel *curchan = ah->curchan;
2168 u32 saveDefAntenna;
2169 u32 macStaId1;
2170 int i, rx_chainmask, r;
2171
2172 ah->extprotspacing = sc->ht_extprotspacing;
2173 ah->txchainmask = sc->tx_chainmask;
2174 ah->rxchainmask = sc->rx_chainmask;
2175
2176 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2177 return -EIO;
2178
2179 if (curchan)
2180 ath9k_hw_getnf(ah, curchan);
2181
2182 if (bChannelChange &&
2183 (ah->chip_fullsleep != true) &&
2184 (ah->curchan != NULL) &&
2185 (chan->channel != ah->curchan->channel) &&
2186 ((chan->channelFlags & CHANNEL_ALL) ==
2187 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2188 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2189 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2190
2191 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2192 ath9k_hw_loadnf(ah, ah->curchan);
2193 ath9k_hw_start_nfcal(ah);
2194 return 0;
2195 }
2196 }
2197
2198 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2199 if (saveDefAntenna == 0)
2200 saveDefAntenna = 1;
2201
2202 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2203
2204 saveLedState = REG_READ(ah, AR_CFG_LED) &
2205 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2206 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2207
2208 ath9k_hw_mark_phy_inactive(ah);
2209
2210 if (!ath9k_hw_chip_reset(ah, chan)) {
2211 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2212 return -EINVAL;
2213 }
2214
2215 if (AR_SREV_9280_10_OR_LATER(ah))
2216 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2217
2218 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2219 if (r)
2220 return r;
2221
2222 /* Setup MFP options for CCMP */
2223 if (AR_SREV_9280_20_OR_LATER(ah)) {
2224 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2225 * frames when constructing CCMP AAD. */
2226 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2227 0xc7ff);
2228 ah->sw_mgmt_crypto = false;
2229 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2230 /* Disable hardware crypto for management frames */
2231 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2232 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2233 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2234 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2235 ah->sw_mgmt_crypto = true;
2236 } else
2237 ah->sw_mgmt_crypto = true;
2238
2239 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2240 ath9k_hw_set_delta_slope(ah, chan);
2241
2242 if (AR_SREV_9280_10_OR_LATER(ah))
2243 ath9k_hw_9280_spur_mitigate(ah, chan);
2244 else
2245 ath9k_hw_spur_mitigate(ah, chan);
2246
2247 ah->eep_ops->set_board_values(ah, chan);
2248
2249 ath9k_hw_decrease_chain_power(ah, chan);
2250
2251 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2252 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2253 | macStaId1
2254 | AR_STA_ID1_RTS_USE_DEF
2255 | (ah->config.
2256 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2257 | ah->sta_id1_defaults);
2258 ath9k_hw_set_operating_mode(ah, ah->opmode);
2259
2260 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2261 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2262
2263 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2264
2265 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2266 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2267 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2268
2269 REG_WRITE(ah, AR_ISR, ~0);
2270
2271 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2272
2273 if (AR_SREV_9280_10_OR_LATER(ah)) {
2274 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2275 return -EIO;
2276 } else {
2277 if (!(ath9k_hw_set_channel(ah, chan)))
2278 return -EIO;
2279 }
2280
2281 for (i = 0; i < AR_NUM_DCU; i++)
2282 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2283
2284 ah->intr_txqs = 0;
2285 for (i = 0; i < ah->caps.total_queues; i++)
2286 ath9k_hw_resettxqueue(ah, i);
2287
2288 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2289 ath9k_hw_init_qos(ah);
2290
2291 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2292 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2293 ath9k_enable_rfkill(ah);
2294 #endif
2295 ath9k_hw_init_user_settings(ah);
2296
2297 REG_WRITE(ah, AR_STA_ID1,
2298 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2299
2300 ath9k_hw_set_dma(ah);
2301
2302 REG_WRITE(ah, AR_OBS, 8);
2303
2304 if (ah->intr_mitigation) {
2305
2306 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2307 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2308 }
2309
2310 ath9k_hw_init_bb(ah, chan);
2311
2312 if (!ath9k_hw_init_cal(ah, chan))
2313 return -EIO;;
2314
2315 rx_chainmask = ah->rxchainmask;
2316 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2317 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2318 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2319 }
2320
2321 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2322
2323 if (AR_SREV_9100(ah)) {
2324 u32 mask;
2325 mask = REG_READ(ah, AR_CFG);
2326 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2327 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2328 "CFG Byte Swap Set 0x%x\n", mask);
2329 } else {
2330 mask =
2331 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2332 REG_WRITE(ah, AR_CFG, mask);
2333 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2334 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2335 }
2336 } else {
2337 #ifdef __BIG_ENDIAN
2338 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2339 #endif
2340 }
2341
2342 return 0;
2343 }
2344
2345 /************************/
2346 /* Key Cache Management */
2347 /************************/
2348
2349 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2350 {
2351 u32 keyType;
2352
2353 if (entry >= ah->caps.keycache_size) {
2354 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2355 "keychache entry %u out of range\n", entry);
2356 return false;
2357 }
2358
2359 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2360
2361 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2362 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2363 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2364 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2365 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2366 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2367 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2368 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2369
2370 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2371 u16 micentry = entry + 64;
2372
2373 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2374 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2375 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2376 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2377
2378 }
2379
2380 if (ah->curchan == NULL)
2381 return true;
2382
2383 return true;
2384 }
2385
2386 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2387 {
2388 u32 macHi, macLo;
2389
2390 if (entry >= ah->caps.keycache_size) {
2391 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2392 "keychache entry %u out of range\n", entry);
2393 return false;
2394 }
2395
2396 if (mac != NULL) {
2397 macHi = (mac[5] << 8) | mac[4];
2398 macLo = (mac[3] << 24) |
2399 (mac[2] << 16) |
2400 (mac[1] << 8) |
2401 mac[0];
2402 macLo >>= 1;
2403 macLo |= (macHi & 1) << 31;
2404 macHi >>= 1;
2405 } else {
2406 macLo = macHi = 0;
2407 }
2408 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2409 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2410
2411 return true;
2412 }
2413
2414 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2415 const struct ath9k_keyval *k,
2416 const u8 *mac)
2417 {
2418 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2419 u32 key0, key1, key2, key3, key4;
2420 u32 keyType;
2421
2422 if (entry >= pCap->keycache_size) {
2423 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2424 "keycache entry %u out of range\n", entry);
2425 return false;
2426 }
2427
2428 switch (k->kv_type) {
2429 case ATH9K_CIPHER_AES_OCB:
2430 keyType = AR_KEYTABLE_TYPE_AES;
2431 break;
2432 case ATH9K_CIPHER_AES_CCM:
2433 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2434 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2435 "AES-CCM not supported by mac rev 0x%x\n",
2436 ah->hw_version.macRev);
2437 return false;
2438 }
2439 keyType = AR_KEYTABLE_TYPE_CCM;
2440 break;
2441 case ATH9K_CIPHER_TKIP:
2442 keyType = AR_KEYTABLE_TYPE_TKIP;
2443 if (ATH9K_IS_MIC_ENABLED(ah)
2444 && entry + 64 >= pCap->keycache_size) {
2445 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2446 "entry %u inappropriate for TKIP\n", entry);
2447 return false;
2448 }
2449 break;
2450 case ATH9K_CIPHER_WEP:
2451 if (k->kv_len < LEN_WEP40) {
2452 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2453 "WEP key length %u too small\n", k->kv_len);
2454 return false;
2455 }
2456 if (k->kv_len <= LEN_WEP40)
2457 keyType = AR_KEYTABLE_TYPE_40;
2458 else if (k->kv_len <= LEN_WEP104)
2459 keyType = AR_KEYTABLE_TYPE_104;
2460 else
2461 keyType = AR_KEYTABLE_TYPE_128;
2462 break;
2463 case ATH9K_CIPHER_CLR:
2464 keyType = AR_KEYTABLE_TYPE_CLR;
2465 break;
2466 default:
2467 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2468 "cipher %u not supported\n", k->kv_type);
2469 return false;
2470 }
2471
2472 key0 = get_unaligned_le32(k->kv_val + 0);
2473 key1 = get_unaligned_le16(k->kv_val + 4);
2474 key2 = get_unaligned_le32(k->kv_val + 6);
2475 key3 = get_unaligned_le16(k->kv_val + 10);
2476 key4 = get_unaligned_le32(k->kv_val + 12);
2477 if (k->kv_len <= LEN_WEP104)
2478 key4 &= 0xff;
2479
2480 /*
2481 * Note: Key cache registers access special memory area that requires
2482 * two 32-bit writes to actually update the values in the internal
2483 * memory. Consequently, the exact order and pairs used here must be
2484 * maintained.
2485 */
2486
2487 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2488 u16 micentry = entry + 64;
2489
2490 /*
2491 * Write inverted key[47:0] first to avoid Michael MIC errors
2492 * on frames that could be sent or received at the same time.
2493 * The correct key will be written in the end once everything
2494 * else is ready.
2495 */
2496 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2497 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2498
2499 /* Write key[95:48] */
2500 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2501 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2502
2503 /* Write key[127:96] and key type */
2504 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2505 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2506
2507 /* Write MAC address for the entry */
2508 (void) ath9k_hw_keysetmac(ah, entry, mac);
2509
2510 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2511 /*
2512 * TKIP uses two key cache entries:
2513 * Michael MIC TX/RX keys in the same key cache entry
2514 * (idx = main index + 64):
2515 * key0 [31:0] = RX key [31:0]
2516 * key1 [15:0] = TX key [31:16]
2517 * key1 [31:16] = reserved
2518 * key2 [31:0] = RX key [63:32]
2519 * key3 [15:0] = TX key [15:0]
2520 * key3 [31:16] = reserved
2521 * key4 [31:0] = TX key [63:32]
2522 */
2523 u32 mic0, mic1, mic2, mic3, mic4;
2524
2525 mic0 = get_unaligned_le32(k->kv_mic + 0);
2526 mic2 = get_unaligned_le32(k->kv_mic + 4);
2527 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2528 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2529 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2530
2531 /* Write RX[31:0] and TX[31:16] */
2532 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2533 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2534
2535 /* Write RX[63:32] and TX[15:0] */
2536 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2537 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2538
2539 /* Write TX[63:32] and keyType(reserved) */
2540 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2541 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2542 AR_KEYTABLE_TYPE_CLR);
2543
2544 } else {
2545 /*
2546 * TKIP uses four key cache entries (two for group
2547 * keys):
2548 * Michael MIC TX/RX keys are in different key cache
2549 * entries (idx = main index + 64 for TX and
2550 * main index + 32 + 96 for RX):
2551 * key0 [31:0] = TX/RX MIC key [31:0]
2552 * key1 [31:0] = reserved
2553 * key2 [31:0] = TX/RX MIC key [63:32]
2554 * key3 [31:0] = reserved
2555 * key4 [31:0] = reserved
2556 *
2557 * Upper layer code will call this function separately
2558 * for TX and RX keys when these registers offsets are
2559 * used.
2560 */
2561 u32 mic0, mic2;
2562
2563 mic0 = get_unaligned_le32(k->kv_mic + 0);
2564 mic2 = get_unaligned_le32(k->kv_mic + 4);
2565
2566 /* Write MIC key[31:0] */
2567 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2568 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2569
2570 /* Write MIC key[63:32] */
2571 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2572 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2573
2574 /* Write TX[63:32] and keyType(reserved) */
2575 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2576 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2577 AR_KEYTABLE_TYPE_CLR);
2578 }
2579
2580 /* MAC address registers are reserved for the MIC entry */
2581 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2582 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2583
2584 /*
2585 * Write the correct (un-inverted) key[47:0] last to enable
2586 * TKIP now that all other registers are set with correct
2587 * values.
2588 */
2589 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2590 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2591 } else {
2592 /* Write key[47:0] */
2593 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2594 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2595
2596 /* Write key[95:48] */
2597 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2598 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2599
2600 /* Write key[127:96] and key type */
2601 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2602 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2603
2604 /* Write MAC address for the entry */
2605 (void) ath9k_hw_keysetmac(ah, entry, mac);
2606 }
2607
2608 return true;
2609 }
2610
2611 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2612 {
2613 if (entry < ah->caps.keycache_size) {
2614 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2615 if (val & AR_KEYTABLE_VALID)
2616 return true;
2617 }
2618 return false;
2619 }
2620
2621 /******************************/
2622 /* Power Management (Chipset) */
2623 /******************************/
2624
2625 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2626 {
2627 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2628 if (setChip) {
2629 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2630 AR_RTC_FORCE_WAKE_EN);
2631 if (!AR_SREV_9100(ah))
2632 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2633
2634 REG_CLR_BIT(ah, (AR_RTC_RESET),
2635 AR_RTC_RESET_EN);
2636 }
2637 }
2638
2639 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2640 {
2641 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2642 if (setChip) {
2643 struct ath9k_hw_capabilities *pCap = &ah->caps;
2644
2645 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2646 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2647 AR_RTC_FORCE_WAKE_ON_INT);
2648 } else {
2649 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2650 AR_RTC_FORCE_WAKE_EN);
2651 }
2652 }
2653 }
2654
2655 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2656 {
2657 u32 val;
2658 int i;
2659
2660 if (setChip) {
2661 if ((REG_READ(ah, AR_RTC_STATUS) &
2662 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2663 if (ath9k_hw_set_reset_reg(ah,
2664 ATH9K_RESET_POWER_ON) != true) {
2665 return false;
2666 }
2667 }
2668 if (AR_SREV_9100(ah))
2669 REG_SET_BIT(ah, AR_RTC_RESET,
2670 AR_RTC_RESET_EN);
2671
2672 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2673 AR_RTC_FORCE_WAKE_EN);
2674 udelay(50);
2675
2676 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2677 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2678 if (val == AR_RTC_STATUS_ON)
2679 break;
2680 udelay(50);
2681 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2682 AR_RTC_FORCE_WAKE_EN);
2683 }
2684 if (i == 0) {
2685 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2686 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2687 return false;
2688 }
2689 }
2690
2691 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2692
2693 return true;
2694 }
2695
2696 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2697 {
2698 int status = true, setChip = true;
2699 static const char *modes[] = {
2700 "AWAKE",
2701 "FULL-SLEEP",
2702 "NETWORK SLEEP",
2703 "UNDEFINED"
2704 };
2705
2706 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2707 modes[ah->power_mode], modes[mode]);
2708
2709 switch (mode) {
2710 case ATH9K_PM_AWAKE:
2711 status = ath9k_hw_set_power_awake(ah, setChip);
2712 break;
2713 case ATH9K_PM_FULL_SLEEP:
2714 ath9k_set_power_sleep(ah, setChip);
2715 ah->chip_fullsleep = true;
2716 break;
2717 case ATH9K_PM_NETWORK_SLEEP:
2718 ath9k_set_power_network_sleep(ah, setChip);
2719 break;
2720 default:
2721 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2722 "Unknown power mode %u\n", mode);
2723 return false;
2724 }
2725 ah->power_mode = mode;
2726
2727 return status;
2728 }
2729
2730 /*
2731 * Helper for ASPM support.
2732 *
2733 * Disable PLL when in L0s as well as receiver clock when in L1.
2734 * This power saving option must be enabled through the SerDes.
2735 *
2736 * Programming the SerDes must go through the same 288 bit serial shift
2737 * register as the other analog registers. Hence the 9 writes.
2738 */
2739 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2740 {
2741 u8 i;
2742
2743 if (ah->is_pciexpress != true)
2744 return;
2745
2746 /* Do not touch SerDes registers */
2747 if (ah->config.pcie_powersave_enable == 2)
2748 return;
2749
2750 /* Nothing to do on restore for 11N */
2751 if (restore)
2752 return;
2753
2754 if (AR_SREV_9280_20_OR_LATER(ah)) {
2755 /*
2756 * AR9280 2.0 or later chips use SerDes values from the
2757 * initvals.h initialized depending on chipset during
2758 * ath9k_hw_do_attach()
2759 */
2760 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2761 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2762 INI_RA(&ah->iniPcieSerdes, i, 1));
2763 }
2764 } else if (AR_SREV_9280(ah) &&
2765 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2766 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2767 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2768
2769 /* RX shut off when elecidle is asserted */
2770 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2771 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2772 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2773
2774 /* Shut off CLKREQ active in L1 */
2775 if (ah->config.pcie_clock_req)
2776 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2777 else
2778 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2779
2780 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2781 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2782 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2783
2784 /* Load the new settings */
2785 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2786
2787 } else {
2788 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2789 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2790
2791 /* RX shut off when elecidle is asserted */
2792 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2793 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2794 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2795
2796 /*
2797 * Ignore ah->ah_config.pcie_clock_req setting for
2798 * pre-AR9280 11n
2799 */
2800 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2801
2802 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2803 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2805
2806 /* Load the new settings */
2807 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2808 }
2809
2810 udelay(1000);
2811
2812 /* set bit 19 to allow forcing of pcie core into L1 state */
2813 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2814
2815 /* Several PCIe massages to ensure proper behaviour */
2816 if (ah->config.pcie_waen) {
2817 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2818 } else {
2819 if (AR_SREV_9285(ah))
2820 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2821 /*
2822 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2823 * otherwise card may disappear.
2824 */
2825 else if (AR_SREV_9280(ah))
2826 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2827 else
2828 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2829 }
2830 }
2831
2832 /**********************/
2833 /* Interrupt Handling */
2834 /**********************/
2835
2836 bool ath9k_hw_intrpend(struct ath_hw *ah)
2837 {
2838 u32 host_isr;
2839
2840 if (AR_SREV_9100(ah))
2841 return true;
2842
2843 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2844 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2845 return true;
2846
2847 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2848 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2849 && (host_isr != AR_INTR_SPURIOUS))
2850 return true;
2851
2852 return false;
2853 }
2854
2855 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2856 {
2857 u32 isr = 0;
2858 u32 mask2 = 0;
2859 struct ath9k_hw_capabilities *pCap = &ah->caps;
2860 u32 sync_cause = 0;
2861 bool fatal_int = false;
2862
2863 if (!AR_SREV_9100(ah)) {
2864 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2865 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2866 == AR_RTC_STATUS_ON) {
2867 isr = REG_READ(ah, AR_ISR);
2868 }
2869 }
2870
2871 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2872 AR_INTR_SYNC_DEFAULT;
2873
2874 *masked = 0;
2875
2876 if (!isr && !sync_cause)
2877 return false;
2878 } else {
2879 *masked = 0;
2880 isr = REG_READ(ah, AR_ISR);
2881 }
2882
2883 if (isr) {
2884 if (isr & AR_ISR_BCNMISC) {
2885 u32 isr2;
2886 isr2 = REG_READ(ah, AR_ISR_S2);
2887 if (isr2 & AR_ISR_S2_TIM)
2888 mask2 |= ATH9K_INT_TIM;
2889 if (isr2 & AR_ISR_S2_DTIM)
2890 mask2 |= ATH9K_INT_DTIM;
2891 if (isr2 & AR_ISR_S2_DTIMSYNC)
2892 mask2 |= ATH9K_INT_DTIMSYNC;
2893 if (isr2 & (AR_ISR_S2_CABEND))
2894 mask2 |= ATH9K_INT_CABEND;
2895 if (isr2 & AR_ISR_S2_GTT)
2896 mask2 |= ATH9K_INT_GTT;
2897 if (isr2 & AR_ISR_S2_CST)
2898 mask2 |= ATH9K_INT_CST;
2899 if (isr2 & AR_ISR_S2_TSFOOR)
2900 mask2 |= ATH9K_INT_TSFOOR;
2901 }
2902
2903 isr = REG_READ(ah, AR_ISR_RAC);
2904 if (isr == 0xffffffff) {
2905 *masked = 0;
2906 return false;
2907 }
2908
2909 *masked = isr & ATH9K_INT_COMMON;
2910
2911 if (ah->intr_mitigation) {
2912 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2913 *masked |= ATH9K_INT_RX;
2914 }
2915
2916 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2917 *masked |= ATH9K_INT_RX;
2918 if (isr &
2919 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2920 AR_ISR_TXEOL)) {
2921 u32 s0_s, s1_s;
2922
2923 *masked |= ATH9K_INT_TX;
2924
2925 s0_s = REG_READ(ah, AR_ISR_S0_S);
2926 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2927 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2928
2929 s1_s = REG_READ(ah, AR_ISR_S1_S);
2930 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2931 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2932 }
2933
2934 if (isr & AR_ISR_RXORN) {
2935 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2936 "receive FIFO overrun interrupt\n");
2937 }
2938
2939 if (!AR_SREV_9100(ah)) {
2940 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2941 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2942 if (isr5 & AR_ISR_S5_TIM_TIMER)
2943 *masked |= ATH9K_INT_TIM_TIMER;
2944 }
2945 }
2946
2947 *masked |= mask2;
2948 }
2949
2950 if (AR_SREV_9100(ah))
2951 return true;
2952
2953 if (sync_cause) {
2954 fatal_int =
2955 (sync_cause &
2956 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2957 ? true : false;
2958
2959 if (fatal_int) {
2960 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2961 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2962 "received PCI FATAL interrupt\n");
2963 }
2964 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2965 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2966 "received PCI PERR interrupt\n");
2967 }
2968 }
2969 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2970 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2971 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2972 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2973 REG_WRITE(ah, AR_RC, 0);
2974 *masked |= ATH9K_INT_FATAL;
2975 }
2976 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2977 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2978 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2979 }
2980
2981 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2982 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2983 }
2984
2985 return true;
2986 }
2987
2988 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2989 {
2990 return ah->mask_reg;
2991 }
2992
2993 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2994 {
2995 u32 omask = ah->mask_reg;
2996 u32 mask, mask2;
2997 struct ath9k_hw_capabilities *pCap = &ah->caps;
2998
2999 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3000
3001 if (omask & ATH9K_INT_GLOBAL) {
3002 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3003 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3004 (void) REG_READ(ah, AR_IER);
3005 if (!AR_SREV_9100(ah)) {
3006 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3007 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3008
3009 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3010 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3011 }
3012 }
3013
3014 mask = ints & ATH9K_INT_COMMON;
3015 mask2 = 0;
3016
3017 if (ints & ATH9K_INT_TX) {
3018 if (ah->txok_interrupt_mask)
3019 mask |= AR_IMR_TXOK;
3020 if (ah->txdesc_interrupt_mask)
3021 mask |= AR_IMR_TXDESC;
3022 if (ah->txerr_interrupt_mask)
3023 mask |= AR_IMR_TXERR;
3024 if (ah->txeol_interrupt_mask)
3025 mask |= AR_IMR_TXEOL;
3026 }
3027 if (ints & ATH9K_INT_RX) {
3028 mask |= AR_IMR_RXERR;
3029 if (ah->intr_mitigation)
3030 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3031 else
3032 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3033 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3034 mask |= AR_IMR_GENTMR;
3035 }
3036
3037 if (ints & (ATH9K_INT_BMISC)) {
3038 mask |= AR_IMR_BCNMISC;
3039 if (ints & ATH9K_INT_TIM)
3040 mask2 |= AR_IMR_S2_TIM;
3041 if (ints & ATH9K_INT_DTIM)
3042 mask2 |= AR_IMR_S2_DTIM;
3043 if (ints & ATH9K_INT_DTIMSYNC)
3044 mask2 |= AR_IMR_S2_DTIMSYNC;
3045 if (ints & ATH9K_INT_CABEND)
3046 mask2 |= AR_IMR_S2_CABEND;
3047 if (ints & ATH9K_INT_TSFOOR)
3048 mask2 |= AR_IMR_S2_TSFOOR;
3049 }
3050
3051 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3052 mask |= AR_IMR_BCNMISC;
3053 if (ints & ATH9K_INT_GTT)
3054 mask2 |= AR_IMR_S2_GTT;
3055 if (ints & ATH9K_INT_CST)
3056 mask2 |= AR_IMR_S2_CST;
3057 }
3058
3059 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3060 REG_WRITE(ah, AR_IMR, mask);
3061 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3062 AR_IMR_S2_DTIM |
3063 AR_IMR_S2_DTIMSYNC |
3064 AR_IMR_S2_CABEND |
3065 AR_IMR_S2_CABTO |
3066 AR_IMR_S2_TSFOOR |
3067 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3068 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3069 ah->mask_reg = ints;
3070
3071 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3072 if (ints & ATH9K_INT_TIM_TIMER)
3073 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3074 else
3075 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3076 }
3077
3078 if (ints & ATH9K_INT_GLOBAL) {
3079 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3080 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3081 if (!AR_SREV_9100(ah)) {
3082 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3083 AR_INTR_MAC_IRQ);
3084 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3085
3086
3087 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3088 AR_INTR_SYNC_DEFAULT);
3089 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3090 AR_INTR_SYNC_DEFAULT);
3091 }
3092 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3093 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3094 }
3095
3096 return omask;
3097 }
3098
3099 /*******************/
3100 /* Beacon Handling */
3101 /*******************/
3102
3103 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3104 {
3105 int flags = 0;
3106
3107 ah->beacon_interval = beacon_period;
3108
3109 switch (ah->opmode) {
3110 case NL80211_IFTYPE_STATION:
3111 case NL80211_IFTYPE_MONITOR:
3112 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3113 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3114 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3115 flags |= AR_TBTT_TIMER_EN;
3116 break;
3117 case NL80211_IFTYPE_ADHOC:
3118 case NL80211_IFTYPE_MESH_POINT:
3119 REG_SET_BIT(ah, AR_TXCFG,
3120 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3121 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3122 TU_TO_USEC(next_beacon +
3123 (ah->atim_window ? ah->
3124 atim_window : 1)));
3125 flags |= AR_NDP_TIMER_EN;
3126 case NL80211_IFTYPE_AP:
3127 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3128 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3129 TU_TO_USEC(next_beacon -
3130 ah->config.
3131 dma_beacon_response_time));
3132 REG_WRITE(ah, AR_NEXT_SWBA,
3133 TU_TO_USEC(next_beacon -
3134 ah->config.
3135 sw_beacon_response_time));
3136 flags |=
3137 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3138 break;
3139 default:
3140 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3141 "%s: unsupported opmode: %d\n",
3142 __func__, ah->opmode);
3143 return;
3144 break;
3145 }
3146
3147 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3148 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3149 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3150 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3151
3152 beacon_period &= ~ATH9K_BEACON_ENA;
3153 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3154 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3155 ath9k_hw_reset_tsf(ah);
3156 }
3157
3158 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3159 }
3160
3161 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3162 const struct ath9k_beacon_state *bs)
3163 {
3164 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3165 struct ath9k_hw_capabilities *pCap = &ah->caps;
3166
3167 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3168
3169 REG_WRITE(ah, AR_BEACON_PERIOD,
3170 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3171 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3172 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3173
3174 REG_RMW_FIELD(ah, AR_RSSI_THR,
3175 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3176
3177 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3178
3179 if (bs->bs_sleepduration > beaconintval)
3180 beaconintval = bs->bs_sleepduration;
3181
3182 dtimperiod = bs->bs_dtimperiod;
3183 if (bs->bs_sleepduration > dtimperiod)
3184 dtimperiod = bs->bs_sleepduration;
3185
3186 if (beaconintval == dtimperiod)
3187 nextTbtt = bs->bs_nextdtim;
3188 else
3189 nextTbtt = bs->bs_nexttbtt;
3190
3191 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3192 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3193 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3194 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3195
3196 REG_WRITE(ah, AR_NEXT_DTIM,
3197 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3198 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3199
3200 REG_WRITE(ah, AR_SLEEP1,
3201 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3202 | AR_SLEEP1_ASSUME_DTIM);
3203
3204 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3205 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3206 else
3207 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3208
3209 REG_WRITE(ah, AR_SLEEP2,
3210 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3211
3212 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3213 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3214
3215 REG_SET_BIT(ah, AR_TIMER_MODE,
3216 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3217 AR_DTIM_TIMER_EN);
3218
3219 /* TSF Out of Range Threshold */
3220 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3221 }
3222
3223 /*******************/
3224 /* HW Capabilities */
3225 /*******************/
3226
3227 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3228 {
3229 struct ath9k_hw_capabilities *pCap = &ah->caps;
3230 u16 capField = 0, eeval;
3231
3232 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3233 ah->regulatory.current_rd = eeval;
3234
3235 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3236 if (AR_SREV_9285_10_OR_LATER(ah))
3237 eeval |= AR9285_RDEXT_DEFAULT;
3238 ah->regulatory.current_rd_ext = eeval;
3239
3240 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3241
3242 if (ah->opmode != NL80211_IFTYPE_AP &&
3243 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3244 if (ah->regulatory.current_rd == 0x64 ||
3245 ah->regulatory.current_rd == 0x65)
3246 ah->regulatory.current_rd += 5;
3247 else if (ah->regulatory.current_rd == 0x41)
3248 ah->regulatory.current_rd = 0x43;
3249 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3250 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3251 }
3252
3253 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3254 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3255
3256 if (eeval & AR5416_OPFLAGS_11A) {
3257 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3258 if (ah->config.ht_enable) {
3259 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3260 set_bit(ATH9K_MODE_11NA_HT20,
3261 pCap->wireless_modes);
3262 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3263 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3264 pCap->wireless_modes);
3265 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3266 pCap->wireless_modes);
3267 }
3268 }
3269 }
3270
3271 if (eeval & AR5416_OPFLAGS_11G) {
3272 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3273 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3274 if (ah->config.ht_enable) {
3275 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3276 set_bit(ATH9K_MODE_11NG_HT20,
3277 pCap->wireless_modes);
3278 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3279 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3280 pCap->wireless_modes);
3281 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3282 pCap->wireless_modes);
3283 }
3284 }
3285 }
3286
3287 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3288 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3289 !(eeval & AR5416_OPFLAGS_11A))
3290 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3291 else
3292 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3293
3294 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3295 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3296
3297 pCap->low_2ghz_chan = 2312;
3298 pCap->high_2ghz_chan = 2732;
3299
3300 pCap->low_5ghz_chan = 4920;
3301 pCap->high_5ghz_chan = 6100;
3302
3303 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3304 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3305 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3306
3307 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3308 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3309 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3310
3311 if (ah->config.ht_enable)
3312 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3313 else
3314 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3315
3316 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3317 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3318 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3319 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3320
3321 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3322 pCap->total_queues =
3323 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3324 else
3325 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3326
3327 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3328 pCap->keycache_size =
3329 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3330 else
3331 pCap->keycache_size = AR_KEYTABLE_SIZE;
3332
3333 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3334 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3335
3336 if (AR_SREV_9285_10_OR_LATER(ah))
3337 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3338 else if (AR_SREV_9280_10_OR_LATER(ah))
3339 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3340 else
3341 pCap->num_gpio_pins = AR_NUM_GPIO;
3342
3343 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3344 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3345 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3346 } else {
3347 pCap->rts_aggr_limit = (8 * 1024);
3348 }
3349
3350 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3351
3352 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3353 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3354 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3355 ah->rfkill_gpio =
3356 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3357 ah->rfkill_polarity =
3358 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3359
3360 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3361 }
3362 #endif
3363
3364 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3365 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3366 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3367 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3368 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3369 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3370 else
3371 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3372
3373 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3374 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3375 else
3376 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3377
3378 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3379 pCap->reg_cap =
3380 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3381 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3382 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3383 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3384 } else {
3385 pCap->reg_cap =
3386 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3387 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3388 }
3389
3390 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3391
3392 pCap->num_antcfg_5ghz =
3393 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3394 pCap->num_antcfg_2ghz =
3395 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3396
3397 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3398 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3399 ah->btactive_gpio = 6;
3400 ah->wlanactive_gpio = 5;
3401 }
3402 }
3403
3404 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3405 u32 capability, u32 *result)
3406 {
3407 switch (type) {
3408 case ATH9K_CAP_CIPHER:
3409 switch (capability) {
3410 case ATH9K_CIPHER_AES_CCM:
3411 case ATH9K_CIPHER_AES_OCB:
3412 case ATH9K_CIPHER_TKIP:
3413 case ATH9K_CIPHER_WEP:
3414 case ATH9K_CIPHER_MIC:
3415 case ATH9K_CIPHER_CLR:
3416 return true;
3417 default:
3418 return false;
3419 }
3420 case ATH9K_CAP_TKIP_MIC:
3421 switch (capability) {
3422 case 0:
3423 return true;
3424 case 1:
3425 return (ah->sta_id1_defaults &
3426 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3427 false;
3428 }
3429 case ATH9K_CAP_TKIP_SPLIT:
3430 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3431 false : true;
3432 case ATH9K_CAP_DIVERSITY:
3433 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3434 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3435 true : false;
3436 case ATH9K_CAP_MCAST_KEYSRCH:
3437 switch (capability) {
3438 case 0:
3439 return true;
3440 case 1:
3441 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3442 return false;
3443 } else {
3444 return (ah->sta_id1_defaults &
3445 AR_STA_ID1_MCAST_KSRCH) ? true :
3446 false;
3447 }
3448 }
3449 return false;
3450 case ATH9K_CAP_TXPOW:
3451 switch (capability) {
3452 case 0:
3453 return 0;
3454 case 1:
3455 *result = ah->regulatory.power_limit;
3456 return 0;
3457 case 2:
3458 *result = ah->regulatory.max_power_level;
3459 return 0;
3460 case 3:
3461 *result = ah->regulatory.tp_scale;
3462 return 0;
3463 }
3464 return false;
3465 case ATH9K_CAP_DS:
3466 return (AR_SREV_9280_20_OR_LATER(ah) &&
3467 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3468 ? false : true;
3469 default:
3470 return false;
3471 }
3472 }
3473
3474 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3475 u32 capability, u32 setting, int *status)
3476 {
3477 u32 v;
3478
3479 switch (type) {
3480 case ATH9K_CAP_TKIP_MIC:
3481 if (setting)
3482 ah->sta_id1_defaults |=
3483 AR_STA_ID1_CRPT_MIC_ENABLE;
3484 else
3485 ah->sta_id1_defaults &=
3486 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3487 return true;
3488 case ATH9K_CAP_DIVERSITY:
3489 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3490 if (setting)
3491 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3492 else
3493 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3494 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3495 return true;
3496 case ATH9K_CAP_MCAST_KEYSRCH:
3497 if (setting)
3498 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3499 else
3500 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3501 return true;
3502 default:
3503 return false;
3504 }
3505 }
3506
3507 /****************************/
3508 /* GPIO / RFKILL / Antennae */
3509 /****************************/
3510
3511 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3512 u32 gpio, u32 type)
3513 {
3514 int addr;
3515 u32 gpio_shift, tmp;
3516
3517 if (gpio > 11)
3518 addr = AR_GPIO_OUTPUT_MUX3;
3519 else if (gpio > 5)
3520 addr = AR_GPIO_OUTPUT_MUX2;
3521 else
3522 addr = AR_GPIO_OUTPUT_MUX1;
3523
3524 gpio_shift = (gpio % 6) * 5;
3525
3526 if (AR_SREV_9280_20_OR_LATER(ah)
3527 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3528 REG_RMW(ah, addr, (type << gpio_shift),
3529 (0x1f << gpio_shift));
3530 } else {
3531 tmp = REG_READ(ah, addr);
3532 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3533 tmp &= ~(0x1f << gpio_shift);
3534 tmp |= (type << gpio_shift);
3535 REG_WRITE(ah, addr, tmp);
3536 }
3537 }
3538
3539 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3540 {
3541 u32 gpio_shift;
3542
3543 ASSERT(gpio < ah->caps.num_gpio_pins);
3544
3545 gpio_shift = gpio << 1;
3546
3547 REG_RMW(ah,
3548 AR_GPIO_OE_OUT,
3549 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3550 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3551 }
3552
3553 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3554 {
3555 #define MS_REG_READ(x, y) \
3556 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3557
3558 if (gpio >= ah->caps.num_gpio_pins)
3559 return 0xffffffff;
3560
3561 if (AR_SREV_9285_10_OR_LATER(ah))
3562 return MS_REG_READ(AR9285, gpio) != 0;
3563 else if (AR_SREV_9280_10_OR_LATER(ah))
3564 return MS_REG_READ(AR928X, gpio) != 0;
3565 else
3566 return MS_REG_READ(AR, gpio) != 0;
3567 }
3568
3569 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3570 u32 ah_signal_type)
3571 {
3572 u32 gpio_shift;
3573
3574 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3575
3576 gpio_shift = 2 * gpio;
3577
3578 REG_RMW(ah,
3579 AR_GPIO_OE_OUT,
3580 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3581 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3582 }
3583
3584 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3585 {
3586 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3587 AR_GPIO_BIT(gpio));
3588 }
3589
3590 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3591 void ath9k_enable_rfkill(struct ath_hw *ah)
3592 {
3593 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3594 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3595
3596 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3597 AR_GPIO_INPUT_MUX2_RFSILENT);
3598
3599 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3600 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3601 }
3602 #endif
3603
3604 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3605 {
3606 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3607 }
3608
3609 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3610 {
3611 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3612 }
3613
3614 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3615 enum ath9k_ant_setting settings,
3616 struct ath9k_channel *chan,
3617 u8 *tx_chainmask,
3618 u8 *rx_chainmask,
3619 u8 *antenna_cfgd)
3620 {
3621 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3622
3623 if (AR_SREV_9280(ah)) {
3624 if (!tx_chainmask_cfg) {
3625
3626 tx_chainmask_cfg = *tx_chainmask;
3627 rx_chainmask_cfg = *rx_chainmask;
3628 }
3629
3630 switch (settings) {
3631 case ATH9K_ANT_FIXED_A:
3632 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3633 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3634 *antenna_cfgd = true;
3635 break;
3636 case ATH9K_ANT_FIXED_B:
3637 if (ah->caps.tx_chainmask >
3638 ATH9K_ANTENNA1_CHAINMASK) {
3639 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3640 }
3641 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3642 *antenna_cfgd = true;
3643 break;
3644 case ATH9K_ANT_VARIABLE:
3645 *tx_chainmask = tx_chainmask_cfg;
3646 *rx_chainmask = rx_chainmask_cfg;
3647 *antenna_cfgd = true;
3648 break;
3649 default:
3650 break;
3651 }
3652 } else {
3653 ah->diversity_control = settings;
3654 }
3655
3656 return true;
3657 }
3658
3659 /*********************/
3660 /* General Operation */
3661 /*********************/
3662
3663 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3664 {
3665 u32 bits = REG_READ(ah, AR_RX_FILTER);
3666 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3667
3668 if (phybits & AR_PHY_ERR_RADAR)
3669 bits |= ATH9K_RX_FILTER_PHYRADAR;
3670 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3671 bits |= ATH9K_RX_FILTER_PHYERR;
3672
3673 return bits;
3674 }
3675
3676 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3677 {
3678 u32 phybits;
3679
3680 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3681 phybits = 0;
3682 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3683 phybits |= AR_PHY_ERR_RADAR;
3684 if (bits & ATH9K_RX_FILTER_PHYERR)
3685 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3686 REG_WRITE(ah, AR_PHY_ERR, phybits);
3687
3688 if (phybits)
3689 REG_WRITE(ah, AR_RXCFG,
3690 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3691 else
3692 REG_WRITE(ah, AR_RXCFG,
3693 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3694 }
3695
3696 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3697 {
3698 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3699 }
3700
3701 bool ath9k_hw_disable(struct ath_hw *ah)
3702 {
3703 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3704 return false;
3705
3706 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3707 }
3708
3709 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3710 {
3711 struct ath9k_channel *chan = ah->curchan;
3712 struct ieee80211_channel *channel = chan->chan;
3713
3714 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3715
3716 if (ah->eep_ops->set_txpower(ah, chan,
3717 ath9k_regd_get_ctl(ah, chan),
3718 channel->max_antenna_gain * 2,
3719 channel->max_power * 2,
3720 min((u32) MAX_RATE_POWER,
3721 (u32) ah->regulatory.power_limit)) != 0)
3722 return false;
3723
3724 return true;
3725 }
3726
3727 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3728 {
3729 memcpy(ah->macaddr, mac, ETH_ALEN);
3730 }
3731
3732 void ath9k_hw_setopmode(struct ath_hw *ah)
3733 {
3734 ath9k_hw_set_operating_mode(ah, ah->opmode);
3735 }
3736
3737 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3738 {
3739 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3740 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3741 }
3742
3743 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3744 {
3745 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3746 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3747 }
3748
3749 void ath9k_hw_write_associd(struct ath_softc *sc)
3750 {
3751 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3752 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3753 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3754 }
3755
3756 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3757 {
3758 u64 tsf;
3759
3760 tsf = REG_READ(ah, AR_TSF_U32);
3761 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3762
3763 return tsf;
3764 }
3765
3766 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3767 {
3768 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3769 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3770 }
3771
3772 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3773 {
3774 int count;
3775
3776 count = 0;
3777 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3778 count++;
3779 if (count > 10) {
3780 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3781 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3782 break;
3783 }
3784 udelay(10);
3785 }
3786 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3787 }
3788
3789 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3790 {
3791 if (setting)
3792 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3793 else
3794 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3795
3796 return true;
3797 }
3798
3799 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3800 {
3801 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3802 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3803 ah->slottime = (u32) -1;
3804 return false;
3805 } else {
3806 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3807 ah->slottime = us;
3808 return true;
3809 }
3810 }
3811
3812 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3813 {
3814 u32 macmode;
3815
3816 if (mode == ATH9K_HT_MACMODE_2040 &&
3817 !ah->config.cwm_ignore_extcca)
3818 macmode = AR_2040_JOINED_RX_CLEAR;
3819 else
3820 macmode = 0;
3821
3822 REG_WRITE(ah, AR_2040_MODE, macmode);
3823 }
3824
3825 /***************************/
3826 /* Bluetooth Coexistence */
3827 /***************************/
3828
3829 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3830 {
3831 /* connect bt_active to baseband */
3832 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3833 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3834 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3835
3836 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3837 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3838
3839 /* Set input mux for bt_active to gpio pin */
3840 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3841 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3842 ah->btactive_gpio);
3843
3844 /* Configure the desired gpio port for input */
3845 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3846
3847 /* Configure the desired GPIO port for TX_FRAME output */
3848 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3849 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3850 }
CJK support for tty framebuffer vt