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net/macb: better manage tx errors
[linux-2.6/cjktty.git] / drivers / net / ethernet / cadence / macb.c
blobd5b52ff6d586065d672eed2d5ebd6c3cf2091dfa
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_data/macb.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_net.h>
29
30 #include "macb.h"
31
32 #define RX_BUFFER_SIZE 128
33 #define RX_RING_SIZE 512 /* must be power of 2 */
34 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
35
36 /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
37 #define RX_OFFSET 2
38
39 #define TX_RING_SIZE 128 /* must be power of 2 */
40 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
41
42 /* minimum number of free TX descriptors before waking up TX process */
43 #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
44
45 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
46 | MACB_BIT(ISR_ROVR))
47 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
48 | MACB_BIT(ISR_RLE) \
49 | MACB_BIT(TXERR))
50 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
51
52 /*
53 * Graceful stop timeouts in us. We should allow up to
54 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
55 */
56 #define MACB_HALT_TIMEOUT 1230
57
58 /* Ring buffer accessors */
59 static unsigned int macb_tx_ring_wrap(unsigned int index)
60 {
61 return index & (TX_RING_SIZE - 1);
62 }
63
64 static unsigned int macb_tx_ring_avail(struct macb *bp)
65 {
66 return (bp->tx_tail - bp->tx_head) & (TX_RING_SIZE - 1);
67 }
68
69 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
70 {
71 return &bp->tx_ring[macb_tx_ring_wrap(index)];
72 }
73
74 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
75 {
76 return &bp->tx_skb[macb_tx_ring_wrap(index)];
77 }
78
79 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
80 {
81 dma_addr_t offset;
82
83 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
84
85 return bp->tx_ring_dma + offset;
86 }
87
88 static unsigned int macb_rx_ring_wrap(unsigned int index)
89 {
90 return index & (RX_RING_SIZE - 1);
91 }
92
93 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
94 {
95 return &bp->rx_ring[macb_rx_ring_wrap(index)];
96 }
97
98 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
99 {
100 return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index);
101 }
102
103 static void __macb_set_hwaddr(struct macb *bp)
104 {
105 u32 bottom;
106 u16 top;
107
108 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
109 macb_or_gem_writel(bp, SA1B, bottom);
110 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
111 macb_or_gem_writel(bp, SA1T, top);
112 }
113
114 static void __init macb_get_hwaddr(struct macb *bp)
115 {
116 u32 bottom;
117 u16 top;
118 u8 addr[6];
119
120 bottom = macb_or_gem_readl(bp, SA1B);
121 top = macb_or_gem_readl(bp, SA1T);
122
123 addr[0] = bottom & 0xff;
124 addr[1] = (bottom >> 8) & 0xff;
125 addr[2] = (bottom >> 16) & 0xff;
126 addr[3] = (bottom >> 24) & 0xff;
127 addr[4] = top & 0xff;
128 addr[5] = (top >> 8) & 0xff;
129
130 if (is_valid_ether_addr(addr)) {
131 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
132 } else {
133 netdev_info(bp->dev, "invalid hw address, using random\n");
134 eth_hw_addr_random(bp->dev);
135 }
136 }
137
138 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
139 {
140 struct macb *bp = bus->priv;
141 int value;
142
143 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
144 | MACB_BF(RW, MACB_MAN_READ)
145 | MACB_BF(PHYA, mii_id)
146 | MACB_BF(REGA, regnum)
147 | MACB_BF(CODE, MACB_MAN_CODE)));
148
149 /* wait for end of transfer */
150 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
151 cpu_relax();
152
153 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
154
155 return value;
156 }
157
158 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
159 u16 value)
160 {
161 struct macb *bp = bus->priv;
162
163 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
164 | MACB_BF(RW, MACB_MAN_WRITE)
165 | MACB_BF(PHYA, mii_id)
166 | MACB_BF(REGA, regnum)
167 | MACB_BF(CODE, MACB_MAN_CODE)
168 | MACB_BF(DATA, value)));
169
170 /* wait for end of transfer */
171 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
172 cpu_relax();
173
174 return 0;
175 }
176
177 static int macb_mdio_reset(struct mii_bus *bus)
178 {
179 return 0;
180 }
181
182 static void macb_handle_link_change(struct net_device *dev)
183 {
184 struct macb *bp = netdev_priv(dev);
185 struct phy_device *phydev = bp->phy_dev;
186 unsigned long flags;
187
188 int status_change = 0;
189
190 spin_lock_irqsave(&bp->lock, flags);
191
192 if (phydev->link) {
193 if ((bp->speed != phydev->speed) ||
194 (bp->duplex != phydev->duplex)) {
195 u32 reg;
196
197 reg = macb_readl(bp, NCFGR);
198 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
199 if (macb_is_gem(bp))
200 reg &= ~GEM_BIT(GBE);
201
202 if (phydev->duplex)
203 reg |= MACB_BIT(FD);
204 if (phydev->speed == SPEED_100)
205 reg |= MACB_BIT(SPD);
206 if (phydev->speed == SPEED_1000)
207 reg |= GEM_BIT(GBE);
208
209 macb_or_gem_writel(bp, NCFGR, reg);
210
211 bp->speed = phydev->speed;
212 bp->duplex = phydev->duplex;
213 status_change = 1;
214 }
215 }
216
217 if (phydev->link != bp->link) {
218 if (!phydev->link) {
219 bp->speed = 0;
220 bp->duplex = -1;
221 }
222 bp->link = phydev->link;
223
224 status_change = 1;
225 }
226
227 spin_unlock_irqrestore(&bp->lock, flags);
228
229 if (status_change) {
230 if (phydev->link) {
231 netif_carrier_on(dev);
232 netdev_info(dev, "link up (%d/%s)\n",
233 phydev->speed,
234 phydev->duplex == DUPLEX_FULL ?
235 "Full" : "Half");
236 } else {
237 netif_carrier_off(dev);
238 netdev_info(dev, "link down\n");
239 }
240 }
241 }
242
243 /* based on au1000_eth. c*/
244 static int macb_mii_probe(struct net_device *dev)
245 {
246 struct macb *bp = netdev_priv(dev);
247 struct phy_device *phydev;
248 int ret;
249
250 phydev = phy_find_first(bp->mii_bus);
251 if (!phydev) {
252 netdev_err(dev, "no PHY found\n");
253 return -1;
254 }
255
256 /* TODO : add pin_irq */
257
258 /* attach the mac to the phy */
259 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
260 bp->phy_interface);
261 if (ret) {
262 netdev_err(dev, "Could not attach to PHY\n");
263 return ret;
264 }
265
266 /* mask with MAC supported features */
267 if (macb_is_gem(bp))
268 phydev->supported &= PHY_GBIT_FEATURES;
269 else
270 phydev->supported &= PHY_BASIC_FEATURES;
271
272 phydev->advertising = phydev->supported;
273
274 bp->link = 0;
275 bp->speed = 0;
276 bp->duplex = -1;
277 bp->phy_dev = phydev;
278
279 return 0;
280 }
281
282 int macb_mii_init(struct macb *bp)
283 {
284 struct macb_platform_data *pdata;
285 int err = -ENXIO, i;
286
287 /* Enable management port */
288 macb_writel(bp, NCR, MACB_BIT(MPE));
289
290 bp->mii_bus = mdiobus_alloc();
291 if (bp->mii_bus == NULL) {
292 err = -ENOMEM;
293 goto err_out;
294 }
295
296 bp->mii_bus->name = "MACB_mii_bus";
297 bp->mii_bus->read = &macb_mdio_read;
298 bp->mii_bus->write = &macb_mdio_write;
299 bp->mii_bus->reset = &macb_mdio_reset;
300 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
301 bp->pdev->name, bp->pdev->id);
302 bp->mii_bus->priv = bp;
303 bp->mii_bus->parent = &bp->dev->dev;
304 pdata = bp->pdev->dev.platform_data;
305
306 if (pdata)
307 bp->mii_bus->phy_mask = pdata->phy_mask;
308
309 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
310 if (!bp->mii_bus->irq) {
311 err = -ENOMEM;
312 goto err_out_free_mdiobus;
313 }
314
315 for (i = 0; i < PHY_MAX_ADDR; i++)
316 bp->mii_bus->irq[i] = PHY_POLL;
317
318 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
319
320 if (mdiobus_register(bp->mii_bus))
321 goto err_out_free_mdio_irq;
322
323 if (macb_mii_probe(bp->dev) != 0) {
324 goto err_out_unregister_bus;
325 }
326
327 return 0;
328
329 err_out_unregister_bus:
330 mdiobus_unregister(bp->mii_bus);
331 err_out_free_mdio_irq:
332 kfree(bp->mii_bus->irq);
333 err_out_free_mdiobus:
334 mdiobus_free(bp->mii_bus);
335 err_out:
336 return err;
337 }
338 EXPORT_SYMBOL_GPL(macb_mii_init);
339
340 static void macb_update_stats(struct macb *bp)
341 {
342 u32 __iomem *reg = bp->regs + MACB_PFR;
343 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
344 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
345
346 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
347
348 for(; p < end; p++, reg++)
349 *p += __raw_readl(reg);
350 }
351
352 static int macb_halt_tx(struct macb *bp)
353 {
354 unsigned long halt_time, timeout;
355 u32 status;
356
357 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
358
359 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
360 do {
361 halt_time = jiffies;
362 status = macb_readl(bp, TSR);
363 if (!(status & MACB_BIT(TGO)))
364 return 0;
365
366 usleep_range(10, 250);
367 } while (time_before(halt_time, timeout));
368
369 return -ETIMEDOUT;
370 }
371
372 static void macb_tx_error_task(struct work_struct *work)
373 {
374 struct macb *bp = container_of(work, struct macb, tx_error_task);
375 struct macb_tx_skb *tx_skb;
376 struct sk_buff *skb;
377 unsigned int tail;
378
379 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
380 bp->tx_tail, bp->tx_head);
381
382 /* Make sure nobody is trying to queue up new packets */
383 netif_stop_queue(bp->dev);
384
385 /*
386 * Stop transmission now
387 * (in case we have just queued new packets)
388 */
389 if (macb_halt_tx(bp))
390 /* Just complain for now, reinitializing TX path can be good */
391 netdev_err(bp->dev, "BUG: halt tx timed out\n");
392
393 /* No need for the lock here as nobody will interrupt us anymore */
394
395 /*
396 * Treat frames in TX queue including the ones that caused the error.
397 * Free transmit buffers in upper layer.
398 */
399 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
400 struct macb_dma_desc *desc;
401 u32 ctrl;
402
403 desc = macb_tx_desc(bp, tail);
404 ctrl = desc->ctrl;
405 tx_skb = macb_tx_skb(bp, tail);
406 skb = tx_skb->skb;
407
408 if (ctrl & MACB_BIT(TX_USED)) {
409 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
410 macb_tx_ring_wrap(tail), skb->data);
411 bp->stats.tx_packets++;
412 bp->stats.tx_bytes += skb->len;
413 } else {
414 /*
415 * "Buffers exhausted mid-frame" errors may only happen
416 * if the driver is buggy, so complain loudly about those.
417 * Statistics are updated by hardware.
418 */
419 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
420 netdev_err(bp->dev,
421 "BUG: TX buffers exhausted mid-frame\n");
422
423 desc->ctrl = ctrl | MACB_BIT(TX_USED);
424 }
425
426 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
427 DMA_TO_DEVICE);
428 tx_skb->skb = NULL;
429 dev_kfree_skb(skb);
430 }
431
432 /* Make descriptor updates visible to hardware */
433 wmb();
434
435 /* Reinitialize the TX desc queue */
436 macb_writel(bp, TBQP, bp->tx_ring_dma);
437 /* Make TX ring reflect state of hardware */
438 bp->tx_head = bp->tx_tail = 0;
439
440 /* Now we are ready to start transmission again */
441 netif_wake_queue(bp->dev);
442
443 /* Housework before enabling TX IRQ */
444 macb_writel(bp, TSR, macb_readl(bp, TSR));
445 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
446 }
447
448 static void macb_tx_interrupt(struct macb *bp)
449 {
450 unsigned int tail;
451 unsigned int head;
452 u32 status;
453
454 status = macb_readl(bp, TSR);
455 macb_writel(bp, TSR, status);
456
457 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
458 (unsigned long)status);
459
460 head = bp->tx_head;
461 for (tail = bp->tx_tail; tail != head; tail++) {
462 struct macb_tx_skb *tx_skb;
463 struct sk_buff *skb;
464 struct macb_dma_desc *desc;
465 u32 ctrl;
466
467 desc = macb_tx_desc(bp, tail);
468
469 /* Make hw descriptor updates visible to CPU */
470 rmb();
471
472 ctrl = desc->ctrl;
473
474 if (!(ctrl & MACB_BIT(TX_USED)))
475 break;
476
477 tx_skb = macb_tx_skb(bp, tail);
478 skb = tx_skb->skb;
479
480 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
481 macb_tx_ring_wrap(tail), skb->data);
482 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
483 DMA_TO_DEVICE);
484 bp->stats.tx_packets++;
485 bp->stats.tx_bytes += skb->len;
486 tx_skb->skb = NULL;
487 dev_kfree_skb_irq(skb);
488 }
489
490 bp->tx_tail = tail;
491 if (netif_queue_stopped(bp->dev)
492 && macb_tx_ring_avail(bp) > MACB_TX_WAKEUP_THRESH)
493 netif_wake_queue(bp->dev);
494 }
495
496 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
497 unsigned int last_frag)
498 {
499 unsigned int len;
500 unsigned int frag;
501 unsigned int offset = 0;
502 struct sk_buff *skb;
503 struct macb_dma_desc *desc;
504
505 desc = macb_rx_desc(bp, last_frag);
506 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
507
508 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
509 macb_rx_ring_wrap(first_frag),
510 macb_rx_ring_wrap(last_frag), len);
511
512 skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET);
513 if (!skb) {
514 bp->stats.rx_dropped++;
515 for (frag = first_frag; ; frag++) {
516 desc = macb_rx_desc(bp, frag);
517 desc->addr &= ~MACB_BIT(RX_USED);
518 if (frag == last_frag)
519 break;
520 }
521
522 /* Make descriptor updates visible to hardware */
523 wmb();
524
525 return 1;
526 }
527
528 skb_reserve(skb, RX_OFFSET);
529 skb_checksum_none_assert(skb);
530 skb_put(skb, len);
531
532 for (frag = first_frag; ; frag++) {
533 unsigned int frag_len = RX_BUFFER_SIZE;
534
535 if (offset + frag_len > len) {
536 BUG_ON(frag != last_frag);
537 frag_len = len - offset;
538 }
539 skb_copy_to_linear_data_offset(skb, offset,
540 macb_rx_buffer(bp, frag), frag_len);
541 offset += RX_BUFFER_SIZE;
542 desc = macb_rx_desc(bp, frag);
543 desc->addr &= ~MACB_BIT(RX_USED);
544
545 if (frag == last_frag)
546 break;
547 }
548
549 /* Make descriptor updates visible to hardware */
550 wmb();
551
552 skb->protocol = eth_type_trans(skb, bp->dev);
553
554 bp->stats.rx_packets++;
555 bp->stats.rx_bytes += len;
556 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
557 skb->len, skb->csum);
558 netif_receive_skb(skb);
559
560 return 0;
561 }
562
563 /* Mark DMA descriptors from begin up to and not including end as unused */
564 static void discard_partial_frame(struct macb *bp, unsigned int begin,
565 unsigned int end)
566 {
567 unsigned int frag;
568
569 for (frag = begin; frag != end; frag++) {
570 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
571 desc->addr &= ~MACB_BIT(RX_USED);
572 }
573
574 /* Make descriptor updates visible to hardware */
575 wmb();
576
577 /*
578 * When this happens, the hardware stats registers for
579 * whatever caused this is updated, so we don't have to record
580 * anything.
581 */
582 }
583
584 static int macb_rx(struct macb *bp, int budget)
585 {
586 int received = 0;
587 unsigned int tail;
588 int first_frag = -1;
589
590 for (tail = bp->rx_tail; budget > 0; tail++) {
591 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
592 u32 addr, ctrl;
593
594 /* Make hw descriptor updates visible to CPU */
595 rmb();
596
597 addr = desc->addr;
598 ctrl = desc->ctrl;
599
600 if (!(addr & MACB_BIT(RX_USED)))
601 break;
602
603 if (ctrl & MACB_BIT(RX_SOF)) {
604 if (first_frag != -1)
605 discard_partial_frame(bp, first_frag, tail);
606 first_frag = tail;
607 }
608
609 if (ctrl & MACB_BIT(RX_EOF)) {
610 int dropped;
611 BUG_ON(first_frag == -1);
612
613 dropped = macb_rx_frame(bp, first_frag, tail);
614 first_frag = -1;
615 if (!dropped) {
616 received++;
617 budget--;
618 }
619 }
620 }
621
622 if (first_frag != -1)
623 bp->rx_tail = first_frag;
624 else
625 bp->rx_tail = tail;
626
627 return received;
628 }
629
630 static int macb_poll(struct napi_struct *napi, int budget)
631 {
632 struct macb *bp = container_of(napi, struct macb, napi);
633 int work_done;
634 u32 status;
635
636 status = macb_readl(bp, RSR);
637 macb_writel(bp, RSR, status);
638
639 work_done = 0;
640
641 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
642 (unsigned long)status, budget);
643
644 work_done = macb_rx(bp, budget);
645 if (work_done < budget) {
646 napi_complete(napi);
647
648 /*
649 * We've done what we can to clean the buffers. Make sure we
650 * get notified when new packets arrive.
651 */
652 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
653 }
654
655 /* TODO: Handle errors */
656
657 return work_done;
658 }
659
660 static irqreturn_t macb_interrupt(int irq, void *dev_id)
661 {
662 struct net_device *dev = dev_id;
663 struct macb *bp = netdev_priv(dev);
664 u32 status;
665
666 status = macb_readl(bp, ISR);
667
668 if (unlikely(!status))
669 return IRQ_NONE;
670
671 spin_lock(&bp->lock);
672
673 while (status) {
674 /* close possible race with dev_close */
675 if (unlikely(!netif_running(dev))) {
676 macb_writel(bp, IDR, -1);
677 break;
678 }
679
680 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
681
682 if (status & MACB_RX_INT_FLAGS) {
683 /*
684 * There's no point taking any more interrupts
685 * until we have processed the buffers. The
686 * scheduling call may fail if the poll routine
687 * is already scheduled, so disable interrupts
688 * now.
689 */
690 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
691
692 if (napi_schedule_prep(&bp->napi)) {
693 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
694 __napi_schedule(&bp->napi);
695 }
696 }
697
698 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
699 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
700 schedule_work(&bp->tx_error_task);
701 break;
702 }
703
704 if (status & MACB_BIT(TCOMP))
705 macb_tx_interrupt(bp);
706
707 /*
708 * Link change detection isn't possible with RMII, so we'll
709 * add that if/when we get our hands on a full-blown MII PHY.
710 */
711
712 if (status & MACB_BIT(ISR_ROVR)) {
713 /* We missed at least one packet */
714 if (macb_is_gem(bp))
715 bp->hw_stats.gem.rx_overruns++;
716 else
717 bp->hw_stats.macb.rx_overruns++;
718 }
719
720 if (status & MACB_BIT(HRESP)) {
721 /*
722 * TODO: Reset the hardware, and maybe move the
723 * netdev_err to a lower-priority context as well
724 * (work queue?)
725 */
726 netdev_err(dev, "DMA bus error: HRESP not OK\n");
727 }
728
729 status = macb_readl(bp, ISR);
730 }
731
732 spin_unlock(&bp->lock);
733
734 return IRQ_HANDLED;
735 }
736
737 #ifdef CONFIG_NET_POLL_CONTROLLER
738 /*
739 * Polling receive - used by netconsole and other diagnostic tools
740 * to allow network i/o with interrupts disabled.
741 */
742 static void macb_poll_controller(struct net_device *dev)
743 {
744 unsigned long flags;
745
746 local_irq_save(flags);
747 macb_interrupt(dev->irq, dev);
748 local_irq_restore(flags);
749 }
750 #endif
751
752 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
753 {
754 struct macb *bp = netdev_priv(dev);
755 dma_addr_t mapping;
756 unsigned int len, entry;
757 struct macb_dma_desc *desc;
758 struct macb_tx_skb *tx_skb;
759 u32 ctrl;
760 unsigned long flags;
761
762 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
763 netdev_vdbg(bp->dev,
764 "start_xmit: len %u head %p data %p tail %p end %p\n",
765 skb->len, skb->head, skb->data,
766 skb_tail_pointer(skb), skb_end_pointer(skb));
767 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
768 skb->data, 16, true);
769 #endif
770
771 len = skb->len;
772 spin_lock_irqsave(&bp->lock, flags);
773
774 /* This is a hard error, log it. */
775 if (macb_tx_ring_avail(bp) < 1) {
776 netif_stop_queue(dev);
777 spin_unlock_irqrestore(&bp->lock, flags);
778 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
779 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
780 bp->tx_head, bp->tx_tail);
781 return NETDEV_TX_BUSY;
782 }
783
784 entry = macb_tx_ring_wrap(bp->tx_head);
785 bp->tx_head++;
786 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
787 mapping = dma_map_single(&bp->pdev->dev, skb->data,
788 len, DMA_TO_DEVICE);
789
790 tx_skb = &bp->tx_skb[entry];
791 tx_skb->skb = skb;
792 tx_skb->mapping = mapping;
793 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
794 skb->data, (unsigned long)mapping);
795
796 ctrl = MACB_BF(TX_FRMLEN, len);
797 ctrl |= MACB_BIT(TX_LAST);
798 if (entry == (TX_RING_SIZE - 1))
799 ctrl |= MACB_BIT(TX_WRAP);
800
801 desc = &bp->tx_ring[entry];
802 desc->addr = mapping;
803 desc->ctrl = ctrl;
804
805 /* Make newly initialized descriptor visible to hardware */
806 wmb();
807
808 skb_tx_timestamp(skb);
809
810 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
811
812 if (macb_tx_ring_avail(bp) < 1)
813 netif_stop_queue(dev);
814
815 spin_unlock_irqrestore(&bp->lock, flags);
816
817 return NETDEV_TX_OK;
818 }
819
820 static void macb_free_consistent(struct macb *bp)
821 {
822 if (bp->tx_skb) {
823 kfree(bp->tx_skb);
824 bp->tx_skb = NULL;
825 }
826 if (bp->rx_ring) {
827 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
828 bp->rx_ring, bp->rx_ring_dma);
829 bp->rx_ring = NULL;
830 }
831 if (bp->tx_ring) {
832 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
833 bp->tx_ring, bp->tx_ring_dma);
834 bp->tx_ring = NULL;
835 }
836 if (bp->rx_buffers) {
837 dma_free_coherent(&bp->pdev->dev,
838 RX_RING_SIZE * RX_BUFFER_SIZE,
839 bp->rx_buffers, bp->rx_buffers_dma);
840 bp->rx_buffers = NULL;
841 }
842 }
843
844 static int macb_alloc_consistent(struct macb *bp)
845 {
846 int size;
847
848 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
849 bp->tx_skb = kmalloc(size, GFP_KERNEL);
850 if (!bp->tx_skb)
851 goto out_err;
852
853 size = RX_RING_BYTES;
854 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
855 &bp->rx_ring_dma, GFP_KERNEL);
856 if (!bp->rx_ring)
857 goto out_err;
858 netdev_dbg(bp->dev,
859 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
860 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
861
862 size = TX_RING_BYTES;
863 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
864 &bp->tx_ring_dma, GFP_KERNEL);
865 if (!bp->tx_ring)
866 goto out_err;
867 netdev_dbg(bp->dev,
868 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
869 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
870
871 size = RX_RING_SIZE * RX_BUFFER_SIZE;
872 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
873 &bp->rx_buffers_dma, GFP_KERNEL);
874 if (!bp->rx_buffers)
875 goto out_err;
876 netdev_dbg(bp->dev,
877 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
878 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
879
880 return 0;
881
882 out_err:
883 macb_free_consistent(bp);
884 return -ENOMEM;
885 }
886
887 static void macb_init_rings(struct macb *bp)
888 {
889 int i;
890 dma_addr_t addr;
891
892 addr = bp->rx_buffers_dma;
893 for (i = 0; i < RX_RING_SIZE; i++) {
894 bp->rx_ring[i].addr = addr;
895 bp->rx_ring[i].ctrl = 0;
896 addr += RX_BUFFER_SIZE;
897 }
898 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
899
900 for (i = 0; i < TX_RING_SIZE; i++) {
901 bp->tx_ring[i].addr = 0;
902 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
903 }
904 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
905
906 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
907 }
908
909 static void macb_reset_hw(struct macb *bp)
910 {
911 /*
912 * Disable RX and TX (XXX: Should we halt the transmission
913 * more gracefully?)
914 */
915 macb_writel(bp, NCR, 0);
916
917 /* Clear the stats registers (XXX: Update stats first?) */
918 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
919
920 /* Clear all status flags */
921 macb_writel(bp, TSR, -1);
922 macb_writel(bp, RSR, -1);
923
924 /* Disable all interrupts */
925 macb_writel(bp, IDR, -1);
926 macb_readl(bp, ISR);
927 }
928
929 static u32 gem_mdc_clk_div(struct macb *bp)
930 {
931 u32 config;
932 unsigned long pclk_hz = clk_get_rate(bp->pclk);
933
934 if (pclk_hz <= 20000000)
935 config = GEM_BF(CLK, GEM_CLK_DIV8);
936 else if (pclk_hz <= 40000000)
937 config = GEM_BF(CLK, GEM_CLK_DIV16);
938 else if (pclk_hz <= 80000000)
939 config = GEM_BF(CLK, GEM_CLK_DIV32);
940 else if (pclk_hz <= 120000000)
941 config = GEM_BF(CLK, GEM_CLK_DIV48);
942 else if (pclk_hz <= 160000000)
943 config = GEM_BF(CLK, GEM_CLK_DIV64);
944 else
945 config = GEM_BF(CLK, GEM_CLK_DIV96);
946
947 return config;
948 }
949
950 static u32 macb_mdc_clk_div(struct macb *bp)
951 {
952 u32 config;
953 unsigned long pclk_hz;
954
955 if (macb_is_gem(bp))
956 return gem_mdc_clk_div(bp);
957
958 pclk_hz = clk_get_rate(bp->pclk);
959 if (pclk_hz <= 20000000)
960 config = MACB_BF(CLK, MACB_CLK_DIV8);
961 else if (pclk_hz <= 40000000)
962 config = MACB_BF(CLK, MACB_CLK_DIV16);
963 else if (pclk_hz <= 80000000)
964 config = MACB_BF(CLK, MACB_CLK_DIV32);
965 else
966 config = MACB_BF(CLK, MACB_CLK_DIV64);
967
968 return config;
969 }
970
971 /*
972 * Get the DMA bus width field of the network configuration register that we
973 * should program. We find the width from decoding the design configuration
974 * register to find the maximum supported data bus width.
975 */
976 static u32 macb_dbw(struct macb *bp)
977 {
978 if (!macb_is_gem(bp))
979 return 0;
980
981 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
982 case 4:
983 return GEM_BF(DBW, GEM_DBW128);
984 case 2:
985 return GEM_BF(DBW, GEM_DBW64);
986 case 1:
987 default:
988 return GEM_BF(DBW, GEM_DBW32);
989 }
990 }
991
992 /*
993 * Configure the receive DMA engine to use the correct receive buffer size.
994 * This is a configurable parameter for GEM.
995 */
996 static void macb_configure_dma(struct macb *bp)
997 {
998 u32 dmacfg;
999
1000 if (macb_is_gem(bp)) {
1001 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1002 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
1003 gem_writel(bp, DMACFG, dmacfg);
1004 }
1005 }
1006
1007 static void macb_init_hw(struct macb *bp)
1008 {
1009 u32 config;
1010
1011 macb_reset_hw(bp);
1012 __macb_set_hwaddr(bp);
1013
1014 config = macb_mdc_clk_div(bp);
1015 config |= MACB_BIT(PAE); /* PAuse Enable */
1016 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1017 config |= MACB_BIT(BIG); /* Receive oversized frames */
1018 if (bp->dev->flags & IFF_PROMISC)
1019 config |= MACB_BIT(CAF); /* Copy All Frames */
1020 if (!(bp->dev->flags & IFF_BROADCAST))
1021 config |= MACB_BIT(NBC); /* No BroadCast */
1022 config |= macb_dbw(bp);
1023 macb_writel(bp, NCFGR, config);
1024
1025 macb_configure_dma(bp);
1026
1027 /* Initialize TX and RX buffers */
1028 macb_writel(bp, RBQP, bp->rx_ring_dma);
1029 macb_writel(bp, TBQP, bp->tx_ring_dma);
1030
1031 /* Enable TX and RX */
1032 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1033
1034 /* Enable interrupts */
1035 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1036 | MACB_TX_INT_FLAGS
1037 | MACB_BIT(HRESP)));
1038
1039 }
1040
1041 /*
1042 * The hash address register is 64 bits long and takes up two
1043 * locations in the memory map. The least significant bits are stored
1044 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1045 *
1046 * The unicast hash enable and the multicast hash enable bits in the
1047 * network configuration register enable the reception of hash matched
1048 * frames. The destination address is reduced to a 6 bit index into
1049 * the 64 bit hash register using the following hash function. The
1050 * hash function is an exclusive or of every sixth bit of the
1051 * destination address.
1052 *
1053 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1054 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1055 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1056 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1057 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1058 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1059 *
1060 * da[0] represents the least significant bit of the first byte
1061 * received, that is, the multicast/unicast indicator, and da[47]
1062 * represents the most significant bit of the last byte received. If
1063 * the hash index, hi[n], points to a bit that is set in the hash
1064 * register then the frame will be matched according to whether the
1065 * frame is multicast or unicast. A multicast match will be signalled
1066 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1067 * index points to a bit set in the hash register. A unicast match
1068 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1069 * and the hash index points to a bit set in the hash register. To
1070 * receive all multicast frames, the hash register should be set with
1071 * all ones and the multicast hash enable bit should be set in the
1072 * network configuration register.
1073 */
1074
1075 static inline int hash_bit_value(int bitnr, __u8 *addr)
1076 {
1077 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1078 return 1;
1079 return 0;
1080 }
1081
1082 /*
1083 * Return the hash index value for the specified address.
1084 */
1085 static int hash_get_index(__u8 *addr)
1086 {
1087 int i, j, bitval;
1088 int hash_index = 0;
1089
1090 for (j = 0; j < 6; j++) {
1091 for (i = 0, bitval = 0; i < 8; i++)
1092 bitval ^= hash_bit_value(i*6 + j, addr);
1093
1094 hash_index |= (bitval << j);
1095 }
1096
1097 return hash_index;
1098 }
1099
1100 /*
1101 * Add multicast addresses to the internal multicast-hash table.
1102 */
1103 static void macb_sethashtable(struct net_device *dev)
1104 {
1105 struct netdev_hw_addr *ha;
1106 unsigned long mc_filter[2];
1107 unsigned int bitnr;
1108 struct macb *bp = netdev_priv(dev);
1109
1110 mc_filter[0] = mc_filter[1] = 0;
1111
1112 netdev_for_each_mc_addr(ha, dev) {
1113 bitnr = hash_get_index(ha->addr);
1114 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1115 }
1116
1117 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1118 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1119 }
1120
1121 /*
1122 * Enable/Disable promiscuous and multicast modes.
1123 */
1124 void macb_set_rx_mode(struct net_device *dev)
1125 {
1126 unsigned long cfg;
1127 struct macb *bp = netdev_priv(dev);
1128
1129 cfg = macb_readl(bp, NCFGR);
1130
1131 if (dev->flags & IFF_PROMISC)
1132 /* Enable promiscuous mode */
1133 cfg |= MACB_BIT(CAF);
1134 else if (dev->flags & (~IFF_PROMISC))
1135 /* Disable promiscuous mode */
1136 cfg &= ~MACB_BIT(CAF);
1137
1138 if (dev->flags & IFF_ALLMULTI) {
1139 /* Enable all multicast mode */
1140 macb_or_gem_writel(bp, HRB, -1);
1141 macb_or_gem_writel(bp, HRT, -1);
1142 cfg |= MACB_BIT(NCFGR_MTI);
1143 } else if (!netdev_mc_empty(dev)) {
1144 /* Enable specific multicasts */
1145 macb_sethashtable(dev);
1146 cfg |= MACB_BIT(NCFGR_MTI);
1147 } else if (dev->flags & (~IFF_ALLMULTI)) {
1148 /* Disable all multicast mode */
1149 macb_or_gem_writel(bp, HRB, 0);
1150 macb_or_gem_writel(bp, HRT, 0);
1151 cfg &= ~MACB_BIT(NCFGR_MTI);
1152 }
1153
1154 macb_writel(bp, NCFGR, cfg);
1155 }
1156 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1157
1158 static int macb_open(struct net_device *dev)
1159 {
1160 struct macb *bp = netdev_priv(dev);
1161 int err;
1162
1163 netdev_dbg(bp->dev, "open\n");
1164
1165 /* carrier starts down */
1166 netif_carrier_off(dev);
1167
1168 /* if the phy is not yet register, retry later*/
1169 if (!bp->phy_dev)
1170 return -EAGAIN;
1171
1172 if (!is_valid_ether_addr(dev->dev_addr))
1173 return -EADDRNOTAVAIL;
1174
1175 err = macb_alloc_consistent(bp);
1176 if (err) {
1177 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1178 err);
1179 return err;
1180 }
1181
1182 napi_enable(&bp->napi);
1183
1184 macb_init_rings(bp);
1185 macb_init_hw(bp);
1186
1187 /* schedule a link state check */
1188 phy_start(bp->phy_dev);
1189
1190 netif_start_queue(dev);
1191
1192 return 0;
1193 }
1194
1195 static int macb_close(struct net_device *dev)
1196 {
1197 struct macb *bp = netdev_priv(dev);
1198 unsigned long flags;
1199
1200 netif_stop_queue(dev);
1201 napi_disable(&bp->napi);
1202
1203 if (bp->phy_dev)
1204 phy_stop(bp->phy_dev);
1205
1206 spin_lock_irqsave(&bp->lock, flags);
1207 macb_reset_hw(bp);
1208 netif_carrier_off(dev);
1209 spin_unlock_irqrestore(&bp->lock, flags);
1210
1211 macb_free_consistent(bp);
1212
1213 return 0;
1214 }
1215
1216 static void gem_update_stats(struct macb *bp)
1217 {
1218 u32 __iomem *reg = bp->regs + GEM_OTX;
1219 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1220 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1221
1222 for (; p < end; p++, reg++)
1223 *p += __raw_readl(reg);
1224 }
1225
1226 static struct net_device_stats *gem_get_stats(struct macb *bp)
1227 {
1228 struct gem_stats *hwstat = &bp->hw_stats.gem;
1229 struct net_device_stats *nstat = &bp->stats;
1230
1231 gem_update_stats(bp);
1232
1233 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1234 hwstat->rx_alignment_errors +
1235 hwstat->rx_resource_errors +
1236 hwstat->rx_overruns +
1237 hwstat->rx_oversize_frames +
1238 hwstat->rx_jabbers +
1239 hwstat->rx_undersized_frames +
1240 hwstat->rx_length_field_frame_errors);
1241 nstat->tx_errors = (hwstat->tx_late_collisions +
1242 hwstat->tx_excessive_collisions +
1243 hwstat->tx_underrun +
1244 hwstat->tx_carrier_sense_errors);
1245 nstat->multicast = hwstat->rx_multicast_frames;
1246 nstat->collisions = (hwstat->tx_single_collision_frames +
1247 hwstat->tx_multiple_collision_frames +
1248 hwstat->tx_excessive_collisions);
1249 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1250 hwstat->rx_jabbers +
1251 hwstat->rx_undersized_frames +
1252 hwstat->rx_length_field_frame_errors);
1253 nstat->rx_over_errors = hwstat->rx_resource_errors;
1254 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1255 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1256 nstat->rx_fifo_errors = hwstat->rx_overruns;
1257 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1258 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1259 nstat->tx_fifo_errors = hwstat->tx_underrun;
1260
1261 return nstat;
1262 }
1263
1264 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1265 {
1266 struct macb *bp = netdev_priv(dev);
1267 struct net_device_stats *nstat = &bp->stats;
1268 struct macb_stats *hwstat = &bp->hw_stats.macb;
1269
1270 if (macb_is_gem(bp))
1271 return gem_get_stats(bp);
1272
1273 /* read stats from hardware */
1274 macb_update_stats(bp);
1275
1276 /* Convert HW stats into netdevice stats */
1277 nstat->rx_errors = (hwstat->rx_fcs_errors +
1278 hwstat->rx_align_errors +
1279 hwstat->rx_resource_errors +
1280 hwstat->rx_overruns +
1281 hwstat->rx_oversize_pkts +
1282 hwstat->rx_jabbers +
1283 hwstat->rx_undersize_pkts +
1284 hwstat->sqe_test_errors +
1285 hwstat->rx_length_mismatch);
1286 nstat->tx_errors = (hwstat->tx_late_cols +
1287 hwstat->tx_excessive_cols +
1288 hwstat->tx_underruns +
1289 hwstat->tx_carrier_errors);
1290 nstat->collisions = (hwstat->tx_single_cols +
1291 hwstat->tx_multiple_cols +
1292 hwstat->tx_excessive_cols);
1293 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1294 hwstat->rx_jabbers +
1295 hwstat->rx_undersize_pkts +
1296 hwstat->rx_length_mismatch);
1297 nstat->rx_over_errors = hwstat->rx_resource_errors +
1298 hwstat->rx_overruns;
1299 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1300 nstat->rx_frame_errors = hwstat->rx_align_errors;
1301 nstat->rx_fifo_errors = hwstat->rx_overruns;
1302 /* XXX: What does "missed" mean? */
1303 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1304 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1305 nstat->tx_fifo_errors = hwstat->tx_underruns;
1306 /* Don't know about heartbeat or window errors... */
1307
1308 return nstat;
1309 }
1310
1311 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1312 {
1313 struct macb *bp = netdev_priv(dev);
1314 struct phy_device *phydev = bp->phy_dev;
1315
1316 if (!phydev)
1317 return -ENODEV;
1318
1319 return phy_ethtool_gset(phydev, cmd);
1320 }
1321
1322 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1323 {
1324 struct macb *bp = netdev_priv(dev);
1325 struct phy_device *phydev = bp->phy_dev;
1326
1327 if (!phydev)
1328 return -ENODEV;
1329
1330 return phy_ethtool_sset(phydev, cmd);
1331 }
1332
1333 static int macb_get_regs_len(struct net_device *netdev)
1334 {
1335 return MACB_GREGS_NBR * sizeof(u32);
1336 }
1337
1338 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1339 void *p)
1340 {
1341 struct macb *bp = netdev_priv(dev);
1342 unsigned int tail, head;
1343 u32 *regs_buff = p;
1344
1345 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1346 | MACB_GREGS_VERSION;
1347
1348 tail = macb_tx_ring_wrap(bp->tx_tail);
1349 head = macb_tx_ring_wrap(bp->tx_head);
1350
1351 regs_buff[0] = macb_readl(bp, NCR);
1352 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1353 regs_buff[2] = macb_readl(bp, NSR);
1354 regs_buff[3] = macb_readl(bp, TSR);
1355 regs_buff[4] = macb_readl(bp, RBQP);
1356 regs_buff[5] = macb_readl(bp, TBQP);
1357 regs_buff[6] = macb_readl(bp, RSR);
1358 regs_buff[7] = macb_readl(bp, IMR);
1359
1360 regs_buff[8] = tail;
1361 regs_buff[9] = head;
1362 regs_buff[10] = macb_tx_dma(bp, tail);
1363 regs_buff[11] = macb_tx_dma(bp, head);
1364
1365 if (macb_is_gem(bp)) {
1366 regs_buff[12] = gem_readl(bp, USRIO);
1367 regs_buff[13] = gem_readl(bp, DMACFG);
1368 }
1369 }
1370
1371 const struct ethtool_ops macb_ethtool_ops = {
1372 .get_settings = macb_get_settings,
1373 .set_settings = macb_set_settings,
1374 .get_regs_len = macb_get_regs_len,
1375 .get_regs = macb_get_regs,
1376 .get_link = ethtool_op_get_link,
1377 .get_ts_info = ethtool_op_get_ts_info,
1378 };
1379 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1380
1381 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1382 {
1383 struct macb *bp = netdev_priv(dev);
1384 struct phy_device *phydev = bp->phy_dev;
1385
1386 if (!netif_running(dev))
1387 return -EINVAL;
1388
1389 if (!phydev)
1390 return -ENODEV;
1391
1392 return phy_mii_ioctl(phydev, rq, cmd);
1393 }
1394 EXPORT_SYMBOL_GPL(macb_ioctl);
1395
1396 static const struct net_device_ops macb_netdev_ops = {
1397 .ndo_open = macb_open,
1398 .ndo_stop = macb_close,
1399 .ndo_start_xmit = macb_start_xmit,
1400 .ndo_set_rx_mode = macb_set_rx_mode,
1401 .ndo_get_stats = macb_get_stats,
1402 .ndo_do_ioctl = macb_ioctl,
1403 .ndo_validate_addr = eth_validate_addr,
1404 .ndo_change_mtu = eth_change_mtu,
1405 .ndo_set_mac_address = eth_mac_addr,
1406 #ifdef CONFIG_NET_POLL_CONTROLLER
1407 .ndo_poll_controller = macb_poll_controller,
1408 #endif
1409 };
1410
1411 #if defined(CONFIG_OF)
1412 static const struct of_device_id macb_dt_ids[] = {
1413 { .compatible = "cdns,at32ap7000-macb" },
1414 { .compatible = "cdns,at91sam9260-macb" },
1415 { .compatible = "cdns,macb" },
1416 { .compatible = "cdns,pc302-gem" },
1417 { .compatible = "cdns,gem" },
1418 { /* sentinel */ }
1419 };
1420
1421 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1422
1423 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1424 {
1425 struct device_node *np = pdev->dev.of_node;
1426
1427 if (np)
1428 return of_get_phy_mode(np);
1429
1430 return -ENODEV;
1431 }
1432
1433 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1434 {
1435 struct device_node *np = bp->pdev->dev.of_node;
1436 if (np) {
1437 const char *mac = of_get_mac_address(np);
1438 if (mac) {
1439 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1440 return 0;
1441 }
1442 }
1443
1444 return -ENODEV;
1445 }
1446 #else
1447 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1448 {
1449 return -ENODEV;
1450 }
1451 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1452 {
1453 return -ENODEV;
1454 }
1455 #endif
1456
1457 static int __init macb_probe(struct platform_device *pdev)
1458 {
1459 struct macb_platform_data *pdata;
1460 struct resource *regs;
1461 struct net_device *dev;
1462 struct macb *bp;
1463 struct phy_device *phydev;
1464 u32 config;
1465 int err = -ENXIO;
1466
1467 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1468 if (!regs) {
1469 dev_err(&pdev->dev, "no mmio resource defined\n");
1470 goto err_out;
1471 }
1472
1473 err = -ENOMEM;
1474 dev = alloc_etherdev(sizeof(*bp));
1475 if (!dev)
1476 goto err_out;
1477
1478 SET_NETDEV_DEV(dev, &pdev->dev);
1479
1480 /* TODO: Actually, we have some interesting features... */
1481 dev->features |= 0;
1482
1483 bp = netdev_priv(dev);
1484 bp->pdev = pdev;
1485 bp->dev = dev;
1486
1487 spin_lock_init(&bp->lock);
1488 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1489
1490 bp->pclk = clk_get(&pdev->dev, "pclk");
1491 if (IS_ERR(bp->pclk)) {
1492 dev_err(&pdev->dev, "failed to get macb_clk\n");
1493 goto err_out_free_dev;
1494 }
1495 clk_enable(bp->pclk);
1496
1497 bp->hclk = clk_get(&pdev->dev, "hclk");
1498 if (IS_ERR(bp->hclk)) {
1499 dev_err(&pdev->dev, "failed to get hclk\n");
1500 goto err_out_put_pclk;
1501 }
1502 clk_enable(bp->hclk);
1503
1504 bp->regs = ioremap(regs->start, resource_size(regs));
1505 if (!bp->regs) {
1506 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1507 err = -ENOMEM;
1508 goto err_out_disable_clocks;
1509 }
1510
1511 dev->irq = platform_get_irq(pdev, 0);
1512 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1513 if (err) {
1514 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1515 dev->irq, err);
1516 goto err_out_iounmap;
1517 }
1518
1519 dev->netdev_ops = &macb_netdev_ops;
1520 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1521 dev->ethtool_ops = &macb_ethtool_ops;
1522
1523 dev->base_addr = regs->start;
1524
1525 /* Set MII management clock divider */
1526 config = macb_mdc_clk_div(bp);
1527 config |= macb_dbw(bp);
1528 macb_writel(bp, NCFGR, config);
1529
1530 err = macb_get_hwaddr_dt(bp);
1531 if (err < 0)
1532 macb_get_hwaddr(bp);
1533
1534 err = macb_get_phy_mode_dt(pdev);
1535 if (err < 0) {
1536 pdata = pdev->dev.platform_data;
1537 if (pdata && pdata->is_rmii)
1538 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1539 else
1540 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1541 } else {
1542 bp->phy_interface = err;
1543 }
1544
1545 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1546 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1547 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1548 #if defined(CONFIG_ARCH_AT91)
1549 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1550 MACB_BIT(CLKEN)));
1551 #else
1552 macb_or_gem_writel(bp, USRIO, 0);
1553 #endif
1554 else
1555 #if defined(CONFIG_ARCH_AT91)
1556 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1557 #else
1558 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1559 #endif
1560
1561 err = register_netdev(dev);
1562 if (err) {
1563 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1564 goto err_out_free_irq;
1565 }
1566
1567 if (macb_mii_init(bp) != 0) {
1568 goto err_out_unregister_netdev;
1569 }
1570
1571 platform_set_drvdata(pdev, dev);
1572
1573 netif_carrier_off(dev);
1574
1575 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1576 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1577 dev->irq, dev->dev_addr);
1578
1579 phydev = bp->phy_dev;
1580 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1581 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1582
1583 return 0;
1584
1585 err_out_unregister_netdev:
1586 unregister_netdev(dev);
1587 err_out_free_irq:
1588 free_irq(dev->irq, dev);
1589 err_out_iounmap:
1590 iounmap(bp->regs);
1591 err_out_disable_clocks:
1592 clk_disable(bp->hclk);
1593 clk_put(bp->hclk);
1594 clk_disable(bp->pclk);
1595 err_out_put_pclk:
1596 clk_put(bp->pclk);
1597 err_out_free_dev:
1598 free_netdev(dev);
1599 err_out:
1600 platform_set_drvdata(pdev, NULL);
1601 return err;
1602 }
1603
1604 static int __exit macb_remove(struct platform_device *pdev)
1605 {
1606 struct net_device *dev;
1607 struct macb *bp;
1608
1609 dev = platform_get_drvdata(pdev);
1610
1611 if (dev) {
1612 bp = netdev_priv(dev);
1613 if (bp->phy_dev)
1614 phy_disconnect(bp->phy_dev);
1615 mdiobus_unregister(bp->mii_bus);
1616 kfree(bp->mii_bus->irq);
1617 mdiobus_free(bp->mii_bus);
1618 unregister_netdev(dev);
1619 free_irq(dev->irq, dev);
1620 iounmap(bp->regs);
1621 clk_disable(bp->hclk);
1622 clk_put(bp->hclk);
1623 clk_disable(bp->pclk);
1624 clk_put(bp->pclk);
1625 free_netdev(dev);
1626 platform_set_drvdata(pdev, NULL);
1627 }
1628
1629 return 0;
1630 }
1631
1632 #ifdef CONFIG_PM
1633 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1634 {
1635 struct net_device *netdev = platform_get_drvdata(pdev);
1636 struct macb *bp = netdev_priv(netdev);
1637
1638 netif_carrier_off(netdev);
1639 netif_device_detach(netdev);
1640
1641 clk_disable(bp->hclk);
1642 clk_disable(bp->pclk);
1643
1644 return 0;
1645 }
1646
1647 static int macb_resume(struct platform_device *pdev)
1648 {
1649 struct net_device *netdev = platform_get_drvdata(pdev);
1650 struct macb *bp = netdev_priv(netdev);
1651
1652 clk_enable(bp->pclk);
1653 clk_enable(bp->hclk);
1654
1655 netif_device_attach(netdev);
1656
1657 return 0;
1658 }
1659 #else
1660 #define macb_suspend NULL
1661 #define macb_resume NULL
1662 #endif
1663
1664 static struct platform_driver macb_driver = {
1665 .remove = __exit_p(macb_remove),
1666 .suspend = macb_suspend,
1667 .resume = macb_resume,
1668 .driver = {
1669 .name = "macb",
1670 .owner = THIS_MODULE,
1671 .of_match_table = of_match_ptr(macb_dt_ids),
1672 },
1673 };
1674
1675 static int __init macb_init(void)
1676 {
1677 return platform_driver_probe(&macb_driver, macb_probe);
1678 }
1679
1680 static void __exit macb_exit(void)
1681 {
1682 platform_driver_unregister(&macb_driver);
1683 }
1684
1685 module_init(macb_init);
1686 module_exit(macb_exit);
1687
1688 MODULE_LICENSE("GPL");
1689 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1690 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1691 MODULE_ALIAS("platform:macb");
CJK support for tty framebuffer vt