2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
26 #include <asm/break.h>
30 #include <asm/mipsregs.h>
31 #include <asm/mipsmtregs.h>
32 #include <asm/module.h>
33 #include <asm/pgtable.h>
34 #include <asm/ptrace.h>
35 #include <asm/sections.h>
36 #include <asm/system.h>
37 #include <asm/tlbdebug.h>
38 #include <asm/traps.h>
39 #include <asm/uaccess.h>
40 #include <asm/mmu_context.h>
41 #include <asm/watch.h>
42 #include <asm/types.h>
44 extern asmlinkage
void handle_int(void);
45 extern asmlinkage
void handle_tlbm(void);
46 extern asmlinkage
void handle_tlbl(void);
47 extern asmlinkage
void handle_tlbs(void);
48 extern asmlinkage
void handle_adel(void);
49 extern asmlinkage
void handle_ades(void);
50 extern asmlinkage
void handle_ibe(void);
51 extern asmlinkage
void handle_dbe(void);
52 extern asmlinkage
void handle_sys(void);
53 extern asmlinkage
void handle_bp(void);
54 extern asmlinkage
void handle_ri(void);
55 extern asmlinkage
void handle_cpu(void);
56 extern asmlinkage
void handle_ov(void);
57 extern asmlinkage
void handle_tr(void);
58 extern asmlinkage
void handle_fpe(void);
59 extern asmlinkage
void handle_mdmx(void);
60 extern asmlinkage
void handle_watch(void);
61 extern asmlinkage
void handle_mt(void);
62 extern asmlinkage
void handle_dsp(void);
63 extern asmlinkage
void handle_mcheck(void);
64 extern asmlinkage
void handle_reserved(void);
66 extern int fpu_emulator_cop1Handler(struct pt_regs
*xcp
,
67 struct mips_fpu_struct
*ctx
);
69 void (*board_be_init
)(void);
70 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
71 void (*board_nmi_handler_setup
)(void);
72 void (*board_ejtag_handler_setup
)(void);
73 void (*board_bind_eic_interrupt
)(int irq
, int regset
);
76 * These constant is for searching for possible module text segments.
77 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
79 #define MODULE_RANGE (8*1024*1024)
82 * This routine abuses get_user()/put_user() to reference pointers
83 * with at least a bit of error checking ...
85 void show_stack(struct task_struct
*task
, unsigned long *sp
)
87 const int field
= 2 * sizeof(unsigned long);
92 if (task
&& task
!= current
)
93 sp
= (unsigned long *) task
->thread
.reg29
;
95 sp
= (unsigned long *) &sp
;
100 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
101 if (i
&& ((i
% (64 / field
)) == 0))
108 if (__get_user(stackdata
, sp
++)) {
109 printk(" (Bad stack address)");
113 printk(" %0*lx", field
, stackdata
);
119 void show_trace(struct task_struct
*task
, unsigned long *stack
)
121 const int field
= 2 * sizeof(unsigned long);
125 if (task
&& task
!= current
)
126 stack
= (unsigned long *) task
->thread
.reg29
;
128 stack
= (unsigned long *) &stack
;
131 printk("Call Trace:");
132 #ifdef CONFIG_KALLSYMS
135 while (!kstack_end(stack
)) {
137 if (__kernel_text_address(addr
)) {
138 printk(" [<%0*lx>] ", field
, addr
);
139 print_symbol("%s\n", addr
);
146 * The architecture-independent dump_stack generator
148 void dump_stack(void)
152 show_trace(current
, &stack
);
155 EXPORT_SYMBOL(dump_stack
);
157 void show_code(unsigned int *pc
)
163 for(i
= -3 ; i
< 6 ; i
++) {
165 if (__get_user(insn
, pc
+ i
)) {
166 printk(" (Bad address in epc)\n");
169 printk("%c%08x%c", (i
?' ':'<'), insn
, (i
?' ':'>'));
173 void show_regs(struct pt_regs
*regs
)
175 const int field
= 2 * sizeof(unsigned long);
176 unsigned int cause
= regs
->cp0_cause
;
179 printk("Cpu %d\n", smp_processor_id());
182 * Saved main processor registers
184 for (i
= 0; i
< 32; ) {
188 printk(" %0*lx", field
, 0UL);
189 else if (i
== 26 || i
== 27)
190 printk(" %*s", field
, "");
192 printk(" %0*lx", field
, regs
->regs
[i
]);
199 printk("Hi : %0*lx\n", field
, regs
->hi
);
200 printk("Lo : %0*lx\n", field
, regs
->lo
);
203 * Saved cp0 registers
205 printk("epc : %0*lx ", field
, regs
->cp0_epc
);
206 print_symbol("%s ", regs
->cp0_epc
);
207 printk(" %s\n", print_tainted());
208 printk("ra : %0*lx ", field
, regs
->regs
[31]);
209 print_symbol("%s\n", regs
->regs
[31]);
211 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
213 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_I
) {
214 if (regs
->cp0_status
& ST0_KUO
)
216 if (regs
->cp0_status
& ST0_IEO
)
218 if (regs
->cp0_status
& ST0_KUP
)
220 if (regs
->cp0_status
& ST0_IEP
)
222 if (regs
->cp0_status
& ST0_KUC
)
224 if (regs
->cp0_status
& ST0_IEC
)
227 if (regs
->cp0_status
& ST0_KX
)
229 if (regs
->cp0_status
& ST0_SX
)
231 if (regs
->cp0_status
& ST0_UX
)
233 switch (regs
->cp0_status
& ST0_KSU
) {
238 printk("SUPERVISOR ");
247 if (regs
->cp0_status
& ST0_ERL
)
249 if (regs
->cp0_status
& ST0_EXL
)
251 if (regs
->cp0_status
& ST0_IE
)
256 printk("Cause : %08x\n", cause
);
258 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
259 if (1 <= cause
&& cause
<= 5)
260 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
262 printk("PrId : %08x\n", read_c0_prid());
265 void show_registers(struct pt_regs
*regs
)
269 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
270 current
->comm
, current
->pid
, current_thread_info(), current
);
271 show_stack(current
, (long *) regs
->regs
[29]);
272 show_trace(current
, (long *) regs
->regs
[29]);
273 show_code((unsigned int *) regs
->cp0_epc
);
277 static DEFINE_SPINLOCK(die_lock
);
279 NORET_TYPE
void ATTRIB_NORET
die(const char * str
, struct pt_regs
* regs
)
281 static int die_counter
;
282 #ifdef CONFIG_MIPS_MT_SMTC
283 unsigned long dvpret
= dvpe();
284 #endif /* CONFIG_MIPS_MT_SMTC */
287 spin_lock_irq(&die_lock
);
289 #ifdef CONFIG_MIPS_MT_SMTC
290 mips_mt_regdump(dvpret
);
291 #endif /* CONFIG_MIPS_MT_SMTC */
292 printk("%s[#%d]:\n", str
, ++die_counter
);
293 show_registers(regs
);
294 spin_unlock_irq(&die_lock
);
298 extern const struct exception_table_entry __start___dbe_table
[];
299 extern const struct exception_table_entry __stop___dbe_table
[];
301 void __declare_dbe_table(void)
303 __asm__
__volatile__(
304 ".section\t__dbe_table,\"a\"\n\t"
309 /* Given an address, look for it in the exception tables. */
310 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
312 const struct exception_table_entry
*e
;
314 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
316 e
= search_module_dbetables(addr
);
320 asmlinkage
void do_be(struct pt_regs
*regs
)
322 const int field
= 2 * sizeof(unsigned long);
323 const struct exception_table_entry
*fixup
= NULL
;
324 int data
= regs
->cp0_cause
& 4;
325 int action
= MIPS_BE_FATAL
;
327 /* XXX For now. Fixme, this searches the wrong table ... */
328 if (data
&& !user_mode(regs
))
329 fixup
= search_dbe_tables(exception_epc(regs
));
332 action
= MIPS_BE_FIXUP
;
334 if (board_be_handler
)
335 action
= board_be_handler(regs
, fixup
!= 0);
338 case MIPS_BE_DISCARD
:
342 regs
->cp0_epc
= fixup
->nextinsn
;
351 * Assume it would be too dangerous to continue ...
353 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
354 data
? "Data" : "Instruction",
355 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
356 die_if_kernel("Oops", regs
);
357 force_sig(SIGBUS
, current
);
360 static inline int get_insn_opcode(struct pt_regs
*regs
, unsigned int *opcode
)
362 unsigned int __user
*epc
;
364 epc
= (unsigned int __user
*) regs
->cp0_epc
+
365 ((regs
->cp0_cause
& CAUSEF_BD
) != 0);
366 if (!get_user(*opcode
, epc
))
369 force_sig(SIGSEGV
, current
);
377 #define OPCODE 0xfc000000
378 #define BASE 0x03e00000
379 #define RT 0x001f0000
380 #define OFFSET 0x0000ffff
381 #define LL 0xc0000000
382 #define SC 0xe0000000
383 #define SPEC3 0x7c000000
384 #define RD 0x0000f800
385 #define FUNC 0x0000003f
386 #define RDHWR 0x0000003b
389 * The ll_bit is cleared by r*_switch.S
392 unsigned long ll_bit
;
394 static struct task_struct
*ll_task
= NULL
;
396 static inline void simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
398 unsigned long value
, __user
*vaddr
;
403 * analyse the ll instruction that just caused a ri exception
404 * and put the referenced address to addr.
407 /* sign extend offset */
408 offset
= opcode
& OFFSET
;
412 vaddr
= (unsigned long __user
*)
413 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
415 if ((unsigned long)vaddr
& 3) {
419 if (get_user(value
, vaddr
)) {
426 if (ll_task
== NULL
|| ll_task
== current
) {
435 compute_return_epc(regs
);
437 regs
->regs
[(opcode
& RT
) >> 16] = value
;
442 force_sig(signal
, current
);
445 static inline void simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
447 unsigned long __user
*vaddr
;
453 * analyse the sc instruction that just caused a ri exception
454 * and put the referenced address to addr.
457 /* sign extend offset */
458 offset
= opcode
& OFFSET
;
462 vaddr
= (unsigned long __user
*)
463 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
464 reg
= (opcode
& RT
) >> 16;
466 if ((unsigned long)vaddr
& 3) {
473 if (ll_bit
== 0 || ll_task
!= current
) {
474 compute_return_epc(regs
);
482 if (put_user(regs
->regs
[reg
], vaddr
)) {
487 compute_return_epc(regs
);
493 force_sig(signal
, current
);
497 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
498 * opcodes are supposed to result in coprocessor unusable exceptions if
499 * executed on ll/sc-less processors. That's the theory. In practice a
500 * few processors such as NEC's VR4100 throw reserved instruction exceptions
501 * instead, so we're doing the emulation thing in both exception handlers.
503 static inline int simulate_llsc(struct pt_regs
*regs
)
507 if (unlikely(get_insn_opcode(regs
, &opcode
)))
510 if ((opcode
& OPCODE
) == LL
) {
511 simulate_ll(regs
, opcode
);
514 if ((opcode
& OPCODE
) == SC
) {
515 simulate_sc(regs
, opcode
);
519 return -EFAULT
; /* Strange things going on ... */
523 * Simulate trapping 'rdhwr' instructions to provide user accessible
524 * registers not implemented in hardware. The only current use of this
525 * is the thread area pointer.
527 static inline int simulate_rdhwr(struct pt_regs
*regs
)
529 struct thread_info
*ti
= task_thread_info(current
);
532 if (unlikely(get_insn_opcode(regs
, &opcode
)))
535 if (unlikely(compute_return_epc(regs
)))
538 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
539 int rd
= (opcode
& RD
) >> 11;
540 int rt
= (opcode
& RT
) >> 16;
543 regs
->regs
[rt
] = ti
->tp_value
;
554 asmlinkage
void do_ov(struct pt_regs
*regs
)
558 die_if_kernel("Integer overflow", regs
);
560 info
.si_code
= FPE_INTOVF
;
561 info
.si_signo
= SIGFPE
;
563 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
564 force_sig_info(SIGFPE
, &info
, current
);
568 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
570 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
572 if (fcr31
& FPU_CSR_UNI_X
) {
577 #ifdef CONFIG_PREEMPT
578 if (!is_fpu_owner()) {
579 /* We might lose fpu before disabling preempt... */
581 BUG_ON(!used_math());
586 * Unimplemented operation exception. If we've got the full
587 * software emulator on-board, let's use it...
589 * Force FPU to dump state into task/thread context. We're
590 * moving a lot of data here for what is probably a single
591 * instruction, but the alternative is to pre-decode the FP
592 * register operands before invoking the emulator, which seems
593 * a bit extreme for what should be an infrequent event.
596 /* Ensure 'resume' not overwrite saved fp context again. */
601 /* Run the emulator */
602 sig
= fpu_emulator_cop1Handler (regs
, ¤t
->thread
.fpu
);
606 own_fpu(); /* Using the FPU again. */
608 * We can't allow the emulated instruction to leave any of
609 * the cause bit set in $fcr31.
611 current
->thread
.fpu
.fcr31
&= ~FPU_CSR_ALL_X
;
613 /* Restore the hardware register state */
618 /* If something went wrong, signal */
620 force_sig(sig
, current
);
625 force_sig(SIGFPE
, current
);
628 asmlinkage
void do_bp(struct pt_regs
*regs
)
630 unsigned int opcode
, bcode
;
633 die_if_kernel("Break instruction in kernel code", regs
);
635 if (get_insn_opcode(regs
, &opcode
))
639 * There is the ancient bug in the MIPS assemblers that the break
640 * code starts left to bit 16 instead to bit 6 in the opcode.
641 * Gas is bug-compatible, but not always, grrr...
642 * We handle both cases with a simple heuristics. --macro
644 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
645 if (bcode
< (1 << 10))
649 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
650 * insns, even for break codes that indicate arithmetic failures.
652 * But should we continue the brokenness??? --macro
655 case BRK_OVERFLOW
<< 10:
656 case BRK_DIVZERO
<< 10:
657 if (bcode
== (BRK_DIVZERO
<< 10))
658 info
.si_code
= FPE_INTDIV
;
660 info
.si_code
= FPE_INTOVF
;
661 info
.si_signo
= SIGFPE
;
663 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
664 force_sig_info(SIGFPE
, &info
, current
);
667 force_sig(SIGTRAP
, current
);
671 asmlinkage
void do_tr(struct pt_regs
*regs
)
673 unsigned int opcode
, tcode
= 0;
676 die_if_kernel("Trap instruction in kernel code", regs
);
678 if (get_insn_opcode(regs
, &opcode
))
681 /* Immediate versions don't provide a code. */
682 if (!(opcode
& OPCODE
))
683 tcode
= ((opcode
>> 6) & ((1 << 10) - 1));
686 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
687 * insns, even for trap codes that indicate arithmetic failures.
689 * But should we continue the brokenness??? --macro
694 if (tcode
== BRK_DIVZERO
)
695 info
.si_code
= FPE_INTDIV
;
697 info
.si_code
= FPE_INTOVF
;
698 info
.si_signo
= SIGFPE
;
700 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
701 force_sig_info(SIGFPE
, &info
, current
);
704 force_sig(SIGTRAP
, current
);
708 asmlinkage
void do_ri(struct pt_regs
*regs
)
710 die_if_kernel("Reserved instruction in kernel code", regs
);
713 if (!simulate_llsc(regs
))
716 if (!simulate_rdhwr(regs
))
719 force_sig(SIGILL
, current
);
722 asmlinkage
void do_cpu(struct pt_regs
*regs
)
726 die_if_kernel("do_cpu invoked from kernel context!", regs
);
728 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
733 if (!simulate_llsc(regs
))
736 if (!simulate_rdhwr(regs
))
745 if (used_math()) { /* Using the FPU again. */
747 } else { /* First time FPU user. */
755 int sig
= fpu_emulator_cop1Handler(regs
,
756 ¤t
->thread
.fpu
);
758 force_sig(sig
, current
);
759 #ifdef CONFIG_MIPS_MT_FPAFF
762 * MIPS MT processors may have fewer FPU contexts
763 * than CPU threads. If we've emulated more than
764 * some threshold number of instructions, force
765 * migration to a "CPU" that has FP support.
767 if(mt_fpemul_threshold
> 0
768 && ((current
->thread
.emulated_fp
++
769 > mt_fpemul_threshold
))) {
771 * If there's no FPU present, or if the
772 * application has already restricted
773 * the allowed set to exclude any CPUs
774 * with FPUs, we'll skip the procedure.
776 if (cpus_intersects(current
->cpus_allowed
,
781 current
->thread
.user_cpus_allowed
,
783 set_cpus_allowed(current
, tmask
);
784 current
->thread
.mflags
|= MF_FPUBOUND
;
788 #endif /* CONFIG_MIPS_MT_FPAFF */
795 die_if_kernel("do_cpu invoked from kernel context!", regs
);
799 force_sig(SIGILL
, current
);
802 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
804 force_sig(SIGILL
, current
);
807 asmlinkage
void do_watch(struct pt_regs
*regs
)
810 * We use the watch exception where available to detect stack
815 panic("Caught WATCH exception - probably caused by stack overflow.");
818 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
820 const int field
= 2 * sizeof(unsigned long);
821 int multi_match
= regs
->cp0_status
& ST0_TS
;
826 printk("Index : %0x\n", read_c0_index());
827 printk("Pagemask: %0x\n", read_c0_pagemask());
828 printk("EntryHi : %0*lx\n", field
, read_c0_entryhi());
829 printk("EntryLo0: %0*lx\n", field
, read_c0_entrylo0());
830 printk("EntryLo1: %0*lx\n", field
, read_c0_entrylo1());
835 show_code((unsigned int *) regs
->cp0_epc
);
838 * Some chips may have other causes of machine check (e.g. SB1
841 panic("Caught Machine Check exception - %scaused by multiple "
842 "matching entries in the TLB.",
843 (multi_match
) ? "" : "not ");
846 asmlinkage
void do_mt(struct pt_regs
*regs
)
850 subcode
= (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT
)
851 >> VPECONTROL_EXCPT_SHIFT
;
854 printk(KERN_DEBUG
"Thread Underflow\n");
857 printk(KERN_DEBUG
"Thread Overflow\n");
860 printk(KERN_DEBUG
"Invalid YIELD Qualifier\n");
863 printk(KERN_DEBUG
"Gating Storage Exception\n");
866 printk(KERN_DEBUG
"YIELD Scheduler Exception\n");
869 printk(KERN_DEBUG
"Gating Storage Schedulier Exception\n");
872 printk(KERN_DEBUG
"*** UNKNOWN THREAD EXCEPTION %d ***\n",
876 die_if_kernel("MIPS MT Thread exception in kernel", regs
);
878 force_sig(SIGILL
, current
);
882 asmlinkage
void do_dsp(struct pt_regs
*regs
)
885 panic("Unexpected DSP exception\n");
887 force_sig(SIGILL
, current
);
890 asmlinkage
void do_reserved(struct pt_regs
*regs
)
893 * Game over - no way to handle this if it ever occurs. Most probably
894 * caused by a new unknown cpu type or after another deadly
895 * hard/software error.
898 panic("Caught reserved exception %ld - should not happen.",
899 (regs
->cp0_cause
& 0x7f) >> 2);
902 asmlinkage
void do_default_vi(struct pt_regs
*regs
)
905 panic("Caught unexpected vectored interrupt.");
909 * Some MIPS CPUs can enable/disable for cache parity detection, but do
912 static inline void parity_protection_init(void)
914 switch (current_cpu_data
.cputype
) {
918 write_c0_ecc(0x80000000);
919 back_to_back_c0_hazard();
920 /* Set the PE bit (bit 31) in the c0_errctl register. */
921 printk(KERN_INFO
"Cache parity protection %sabled\n",
922 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
926 /* Clear the DE bit (bit 16) in the c0_status register. */
927 printk(KERN_INFO
"Enable cache parity protection for "
928 "MIPS 20KC/25KF CPUs.\n");
929 clear_c0_status(ST0_DE
);
936 asmlinkage
void cache_parity_error(void)
938 const int field
= 2 * sizeof(unsigned long);
939 unsigned int reg_val
;
941 /* For the moment, report the problem and hang. */
942 printk("Cache error exception:\n");
943 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
944 reg_val
= read_c0_cacheerr();
945 printk("c0_cacheerr == %08x\n", reg_val
);
947 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
948 reg_val
& (1<<30) ? "secondary" : "primary",
949 reg_val
& (1<<31) ? "data" : "insn");
950 printk("Error bits: %s%s%s%s%s%s%s\n",
951 reg_val
& (1<<29) ? "ED " : "",
952 reg_val
& (1<<28) ? "ET " : "",
953 reg_val
& (1<<26) ? "EE " : "",
954 reg_val
& (1<<25) ? "EB " : "",
955 reg_val
& (1<<24) ? "EI " : "",
956 reg_val
& (1<<23) ? "E1 " : "",
957 reg_val
& (1<<22) ? "E0 " : "");
958 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
960 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
961 if (reg_val
& (1<<22))
962 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
964 if (reg_val
& (1<<23))
965 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
968 panic("Can't handle the cache error!");
972 * SDBBP EJTAG debug exception handler.
973 * We skip the instruction and return to the next instruction.
975 void ejtag_exception_handler(struct pt_regs
*regs
)
977 const int field
= 2 * sizeof(unsigned long);
978 unsigned long depc
, old_epc
;
981 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
982 depc
= read_c0_depc();
983 debug
= read_c0_debug();
984 printk("c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
985 if (debug
& 0x80000000) {
987 * In branch delay slot.
988 * We cheat a little bit here and use EPC to calculate the
989 * debug return address (DEPC). EPC is restored after the
992 old_epc
= regs
->cp0_epc
;
993 regs
->cp0_epc
= depc
;
994 __compute_return_epc(regs
);
995 depc
= regs
->cp0_epc
;
996 regs
->cp0_epc
= old_epc
;
1002 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
1003 write_c0_debug(debug
| 0x100);
1008 * NMI exception handler.
1010 void nmi_exception_handler(struct pt_regs
*regs
)
1012 #ifdef CONFIG_MIPS_MT_SMTC
1013 unsigned long dvpret
= dvpe();
1015 printk("NMI taken!!!!\n");
1016 mips_mt_regdump(dvpret
);
1019 printk("NMI taken!!!!\n");
1020 #endif /* CONFIG_MIPS_MT_SMTC */
1025 #define VECTORSPACING 0x100 /* for EI/VI mode */
1027 unsigned long ebase
;
1028 unsigned long exception_handlers
[32];
1029 unsigned long vi_handlers
[64];
1032 * As a side effect of the way this is implemented we're limited
1033 * to interrupt handlers in the address range from
1034 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1036 void *set_except_vector(int n
, void *addr
)
1038 unsigned long handler
= (unsigned long) addr
;
1039 unsigned long old_handler
= exception_handlers
[n
];
1041 exception_handlers
[n
] = handler
;
1042 if (n
== 0 && cpu_has_divec
) {
1043 *(volatile u32
*)(ebase
+ 0x200) = 0x08000000 |
1044 (0x03ffffff & (handler
>> 2));
1045 flush_icache_range(ebase
+ 0x200, ebase
+ 0x204);
1047 return (void *)old_handler
;
1050 #ifdef CONFIG_CPU_MIPSR2_SRS
1052 * MIPSR2 shadow register set allocation
1056 static struct shadow_registers
{
1058 * Number of shadow register sets supported
1060 unsigned long sr_supported
;
1062 * Bitmap of allocated shadow registers
1064 unsigned long sr_allocated
;
1067 static void mips_srs_init(void)
1069 shadow_registers
.sr_supported
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1070 printk(KERN_INFO
"%d MIPSR2 register sets available\n",
1071 shadow_registers
.sr_supported
);
1072 shadow_registers
.sr_allocated
= 1; /* Set 0 used by kernel */
1075 int mips_srs_max(void)
1077 return shadow_registers
.sr_supported
;
1080 int mips_srs_alloc(void)
1082 struct shadow_registers
*sr
= &shadow_registers
;
1086 set
= find_first_zero_bit(&sr
->sr_allocated
, sr
->sr_supported
);
1087 if (set
>= sr
->sr_supported
)
1090 if (test_and_set_bit(set
, &sr
->sr_allocated
))
1096 void mips_srs_free(int set
)
1098 struct shadow_registers
*sr
= &shadow_registers
;
1100 clear_bit(set
, &sr
->sr_allocated
);
1103 static void *set_vi_srs_handler(int n
, void *addr
, int srs
)
1105 unsigned long handler
;
1106 unsigned long old_handler
= vi_handlers
[n
];
1110 if (!cpu_has_veic
&& !cpu_has_vint
)
1114 handler
= (unsigned long) do_default_vi
;
1117 handler
= (unsigned long) addr
;
1118 vi_handlers
[n
] = (unsigned long) addr
;
1120 b
= (unsigned char *)(ebase
+ 0x200 + n
*VECTORSPACING
);
1122 if (srs
>= mips_srs_max())
1123 panic("Shadow register set %d not supported", srs
);
1126 if (board_bind_eic_interrupt
)
1127 board_bind_eic_interrupt (n
, srs
);
1128 } else if (cpu_has_vint
) {
1129 /* SRSMap is only defined if shadow sets are implemented */
1130 if (mips_srs_max() > 1)
1131 change_c0_srsmap (0xf << n
*4, srs
<< n
*4);
1136 * If no shadow set is selected then use the default handler
1137 * that does normal register saving and a standard interrupt exit
1140 extern char except_vec_vi
, except_vec_vi_lui
;
1141 extern char except_vec_vi_ori
, except_vec_vi_end
;
1142 #ifdef CONFIG_MIPS_MT_SMTC
1144 * We need to provide the SMTC vectored interrupt handler
1145 * not only with the address of the handler, but with the
1146 * Status.IM bit to be masked before going there.
1148 extern char except_vec_vi_mori
;
1149 const int mori_offset
= &except_vec_vi_mori
- &except_vec_vi
;
1150 #endif /* CONFIG_MIPS_MT_SMTC */
1151 const int handler_len
= &except_vec_vi_end
- &except_vec_vi
;
1152 const int lui_offset
= &except_vec_vi_lui
- &except_vec_vi
;
1153 const int ori_offset
= &except_vec_vi_ori
- &except_vec_vi
;
1155 if (handler_len
> VECTORSPACING
) {
1157 * Sigh... panicing won't help as the console
1158 * is probably not configured :(
1160 panic ("VECTORSPACING too small");
1163 memcpy (b
, &except_vec_vi
, handler_len
);
1164 #ifdef CONFIG_MIPS_MT_SMTC
1166 printk("Vector index %d exceeds SMTC maximum\n", n
);
1167 w
= (u32
*)(b
+ mori_offset
);
1168 *w
= (*w
& 0xffff0000) | (0x100 << n
);
1169 #endif /* CONFIG_MIPS_MT_SMTC */
1170 w
= (u32
*)(b
+ lui_offset
);
1171 *w
= (*w
& 0xffff0000) | (((u32
)handler
>> 16) & 0xffff);
1172 w
= (u32
*)(b
+ ori_offset
);
1173 *w
= (*w
& 0xffff0000) | ((u32
)handler
& 0xffff);
1174 flush_icache_range((unsigned long)b
, (unsigned long)(b
+handler_len
));
1178 * In other cases jump directly to the interrupt handler
1180 * It is the handlers responsibility to save registers if required
1181 * (eg hi/lo) and return from the exception using "eret"
1184 *w
++ = 0x08000000 | (((u32
)handler
>> 2) & 0x03fffff); /* j handler */
1186 flush_icache_range((unsigned long)b
, (unsigned long)(b
+8));
1189 return (void *)old_handler
;
1192 void *set_vi_handler(int n
, void *addr
)
1194 return set_vi_srs_handler(n
, addr
, 0);
1199 static inline void mips_srs_init(void)
1203 #endif /* CONFIG_CPU_MIPSR2_SRS */
1206 * This is used by native signal handling
1208 asmlinkage
int (*save_fp_context
)(struct sigcontext
*sc
);
1209 asmlinkage
int (*restore_fp_context
)(struct sigcontext
*sc
);
1211 extern asmlinkage
int _save_fp_context(struct sigcontext
*sc
);
1212 extern asmlinkage
int _restore_fp_context(struct sigcontext
*sc
);
1214 extern asmlinkage
int fpu_emulator_save_context(struct sigcontext
*sc
);
1215 extern asmlinkage
int fpu_emulator_restore_context(struct sigcontext
*sc
);
1218 static int smp_save_fp_context(struct sigcontext
*sc
)
1221 ? _save_fp_context(sc
)
1222 : fpu_emulator_save_context(sc
);
1225 static int smp_restore_fp_context(struct sigcontext
*sc
)
1228 ? _restore_fp_context(sc
)
1229 : fpu_emulator_restore_context(sc
);
1233 static inline void signal_init(void)
1236 /* For now just do the cpu_has_fpu check when the functions are invoked */
1237 save_fp_context
= smp_save_fp_context
;
1238 restore_fp_context
= smp_restore_fp_context
;
1241 save_fp_context
= _save_fp_context
;
1242 restore_fp_context
= _restore_fp_context
;
1244 save_fp_context
= fpu_emulator_save_context
;
1245 restore_fp_context
= fpu_emulator_restore_context
;
1250 #ifdef CONFIG_MIPS32_COMPAT
1253 * This is used by 32-bit signal stuff on the 64-bit kernel
1255 asmlinkage
int (*save_fp_context32
)(struct sigcontext32
*sc
);
1256 asmlinkage
int (*restore_fp_context32
)(struct sigcontext32
*sc
);
1258 extern asmlinkage
int _save_fp_context32(struct sigcontext32
*sc
);
1259 extern asmlinkage
int _restore_fp_context32(struct sigcontext32
*sc
);
1261 extern asmlinkage
int fpu_emulator_save_context32(struct sigcontext32
*sc
);
1262 extern asmlinkage
int fpu_emulator_restore_context32(struct sigcontext32
*sc
);
1264 static inline void signal32_init(void)
1267 save_fp_context32
= _save_fp_context32
;
1268 restore_fp_context32
= _restore_fp_context32
;
1270 save_fp_context32
= fpu_emulator_save_context32
;
1271 restore_fp_context32
= fpu_emulator_restore_context32
;
1276 extern void cpu_cache_init(void);
1277 extern void tlb_init(void);
1278 extern void flush_tlb_handlers(void);
1280 void __init
per_cpu_trap_init(void)
1282 unsigned int cpu
= smp_processor_id();
1283 unsigned int status_set
= ST0_CU0
;
1284 #ifdef CONFIG_MIPS_MT_SMTC
1285 int secondaryTC
= 0;
1286 int bootTC
= (cpu
== 0);
1289 * Only do per_cpu_trap_init() for first TC of Each VPE.
1290 * Note that this hack assumes that the SMTC init code
1291 * assigns TCs consecutively and in ascending order.
1294 if (((read_c0_tcbind() & TCBIND_CURTC
) != 0) &&
1295 ((read_c0_tcbind() & TCBIND_CURVPE
) == cpu_data
[cpu
- 1].vpe_id
))
1297 #endif /* CONFIG_MIPS_MT_SMTC */
1300 * Disable coprocessors and select 32-bit or 64-bit addressing
1301 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1302 * flag that some firmware may have left set and the TS bit (for
1303 * IP27). Set XX for ISA IV code to work.
1306 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
1308 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_IV
)
1309 status_set
|= ST0_XX
;
1310 change_c0_status(ST0_CU
|ST0_MX
|ST0_RE
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
1314 set_c0_status(ST0_MX
);
1316 #ifdef CONFIG_CPU_MIPSR2
1317 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1320 #ifdef CONFIG_MIPS_MT_SMTC
1322 #endif /* CONFIG_MIPS_MT_SMTC */
1325 * Interrupt handling.
1327 if (cpu_has_veic
|| cpu_has_vint
) {
1328 write_c0_ebase (ebase
);
1329 /* Setting vector spacing enables EI/VI mode */
1330 change_c0_intctl (0x3e0, VECTORSPACING
);
1332 if (cpu_has_divec
) {
1333 if (cpu_has_mipsmt
) {
1334 unsigned int vpflags
= dvpe();
1335 set_c0_cause(CAUSEF_IV
);
1338 set_c0_cause(CAUSEF_IV
);
1340 #ifdef CONFIG_MIPS_MT_SMTC
1342 #endif /* CONFIG_MIPS_MT_SMTC */
1344 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
1345 TLBMISS_HANDLER_SETUP();
1347 atomic_inc(&init_mm
.mm_count
);
1348 current
->active_mm
= &init_mm
;
1349 BUG_ON(current
->mm
);
1350 enter_lazy_tlb(&init_mm
, current
);
1352 #ifdef CONFIG_MIPS_MT_SMTC
1354 #endif /* CONFIG_MIPS_MT_SMTC */
1357 #ifdef CONFIG_MIPS_MT_SMTC
1359 #endif /* CONFIG_MIPS_MT_SMTC */
1362 /* Install CPU exception handler */
1363 void __init
set_handler (unsigned long offset
, void *addr
, unsigned long size
)
1365 memcpy((void *)(ebase
+ offset
), addr
, size
);
1366 flush_icache_range(ebase
+ offset
, ebase
+ offset
+ size
);
1369 /* Install uncached CPU exception handler */
1370 void __init
set_uncached_handler (unsigned long offset
, void *addr
, unsigned long size
)
1373 unsigned long uncached_ebase
= KSEG1ADDR(ebase
);
1376 unsigned long uncached_ebase
= TO_UNCAC(ebase
);
1379 memcpy((void *)(uncached_ebase
+ offset
), addr
, size
);
1382 void __init
trap_init(void)
1384 extern char except_vec3_generic
, except_vec3_r4000
;
1385 extern char except_vec4
;
1388 if (cpu_has_veic
|| cpu_has_vint
)
1389 ebase
= (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING
*64);
1395 per_cpu_trap_init();
1398 * Copy the generic exception handlers to their final destination.
1399 * This will be overriden later as suitable for a particular
1402 set_handler(0x180, &except_vec3_generic
, 0x80);
1405 * Setup default vectors
1407 for (i
= 0; i
<= 31; i
++)
1408 set_except_vector(i
, handle_reserved
);
1411 * Copy the EJTAG debug exception vector handler code to it's final
1414 if (cpu_has_ejtag
&& board_ejtag_handler_setup
)
1415 board_ejtag_handler_setup ();
1418 * Only some CPUs have the watch exceptions.
1421 set_except_vector(23, handle_watch
);
1424 * Initialise interrupt handlers
1426 if (cpu_has_veic
|| cpu_has_vint
) {
1427 int nvec
= cpu_has_veic
? 64 : 8;
1428 for (i
= 0; i
< nvec
; i
++)
1429 set_vi_handler(i
, NULL
);
1431 else if (cpu_has_divec
)
1432 set_handler(0x200, &except_vec4
, 0x8);
1435 * Some CPUs can enable/disable for cache parity detection, but does
1436 * it different ways.
1438 parity_protection_init();
1441 * The Data Bus Errors / Instruction Bus Errors are signaled
1442 * by external hardware. Therefore these two exceptions
1443 * may have board specific handlers.
1448 set_except_vector(0, handle_int
);
1449 set_except_vector(1, handle_tlbm
);
1450 set_except_vector(2, handle_tlbl
);
1451 set_except_vector(3, handle_tlbs
);
1453 set_except_vector(4, handle_adel
);
1454 set_except_vector(5, handle_ades
);
1456 set_except_vector(6, handle_ibe
);
1457 set_except_vector(7, handle_dbe
);
1459 set_except_vector(8, handle_sys
);
1460 set_except_vector(9, handle_bp
);
1461 set_except_vector(10, handle_ri
);
1462 set_except_vector(11, handle_cpu
);
1463 set_except_vector(12, handle_ov
);
1464 set_except_vector(13, handle_tr
);
1466 if (current_cpu_data
.cputype
== CPU_R6000
||
1467 current_cpu_data
.cputype
== CPU_R6000A
) {
1469 * The R6000 is the only R-series CPU that features a machine
1470 * check exception (similar to the R4000 cache error) and
1471 * unaligned ldc1/sdc1 exception. The handlers have not been
1472 * written yet. Well, anyway there is no R6000 machine on the
1473 * current list of targets for Linux/MIPS.
1474 * (Duh, crap, there is someone with a triple R6k machine)
1476 //set_except_vector(14, handle_mc);
1477 //set_except_vector(15, handle_ndc);
1481 if (board_nmi_handler_setup
)
1482 board_nmi_handler_setup();
1484 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
1485 set_except_vector(15, handle_fpe
);
1487 set_except_vector(22, handle_mdmx
);
1490 set_except_vector(24, handle_mcheck
);
1493 set_except_vector(25, handle_mt
);
1496 set_except_vector(26, handle_dsp
);
1499 /* Special exception: R4[04]00 uses also the divec space. */
1500 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_r4000
, 0x100);
1501 else if (cpu_has_4kex
)
1502 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_generic
, 0x80);
1504 memcpy((void *)(CAC_BASE
+ 0x080), &except_vec3_generic
, 0x80);
1507 #ifdef CONFIG_MIPS32_COMPAT
1511 flush_icache_range(ebase
, ebase
+ 0x400);
1512 flush_tlb_handlers();