3 Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan,
4 Jason Lapenta, Scott Smedley
6 This file is part of the DT3155 Device Driver.
8 The DT3155 Device Driver is free software; you can redistribute it
9 and/or modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2 of the
11 License, or (at your option) any later version.
13 The DT3155 Device Driver is distributed in the hope that it will be
14 useful, but WITHOUT ANY WARRANTY; without even the implied warranty
15 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with the DT3155 Device Driver; if not, write to the Free
20 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 Date Programmer Description of changes made
27 -------------------------------------------------------------------
28 24-Jul-2002 SS GPL licence.
32 /* This code is a modified version of examples provided by Data Translations.*/
37 /* macros to access registers */
39 #define WriteMReg(Address, Data) (*((u32 *)(Address)) = Data)
40 #define ReadMReg(Address, Data) (Data = *((u32 *)(Address)))
42 /***************** 32 bit register globals **************/
44 /* offsets for 32-bit memory mapped registers */
46 #define EVEN_DMA_START 0x000
47 #define ODD_DMA_START 0x00C
48 #define EVEN_DMA_STRIDE 0x018
49 #define ODD_DMA_STRIDE 0x024
50 #define EVEN_PIXEL_FMT 0x030
51 #define ODD_PIXEL_FMT 0x034
52 #define FIFO_TRIGGER 0x038
53 #define XFER_MODE 0x03C
55 #define RETRY_WAIT_CNT 0x044
57 #define EVEN_FLD_MASK 0x04C
58 #define ODD_FLD_MASK 0x050
59 #define MASK_LENGTH 0x054
60 #define FIFO_FLAG_CNT 0x058
61 #define IIC_CLK_DUR 0x05C
62 #define IIC_CSR1 0x060
63 #define IIC_CSR2 0x064
64 #define EVEN_DMA_UPPR_LMT 0x08C
65 #define ODD_DMA_UPPR_LMT 0x090
67 #define CLK_DUR_VAL 0x01010101
71 /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/
73 typedef union fifo_trigger_tag
{
83 typedef union xfer_mode_tag
{
94 typedef union csr1_tag
{
115 typedef union retry_wait_cnt_tag
{
123 typedef union int_csr_tag
{
130 u32 FLD_END_EVE_EN
:1;
131 u32 FLD_END_ODD_EN
:1;
137 typedef union mask_length_tag
{
147 typedef union fifo_flag_cnt_tag
{
157 typedef union iic_clk_dur
{
167 typedef union iic_csr1_tag
{
185 /**********************************
188 typedef union iic_csr2_tag
{
200 /* use for both EVEN and ODD DMA UPPER LIMITS */
205 typedef union dma_upper_lmt_tag
{
208 u32 DMA_UPPER_LMT_VAL
:24;
215 * Global declarations of local copies of boards' 32 bit registers
217 extern u32 even_dma_start_r
; /* bit 0 should always be 0 */
218 extern u32 odd_dma_start_r
; /* .. */
219 extern u32 even_dma_stride_r
; /* bits 0&1 should always be 0 */
220 extern u32 odd_dma_stride_r
; /* .. */
221 extern u32 even_pixel_fmt_r
;
222 extern u32 odd_pixel_fmt_r
;
224 extern FIFO_TRIGGER_R fifo_trigger_r
;
225 extern XFER_MODE_R xfer_mode_r
;
226 extern CSR1_R csr1_r
;
227 extern RETRY_WAIT_CNT_R retry_wait_cnt_r
;
228 extern INT_CSR_R int_csr_r
;
230 extern u32 even_fld_mask_r
;
231 extern u32 odd_fld_mask_r
;
233 extern MASK_LENGTH_R mask_length_r
;
234 extern FIFO_FLAG_CNT_R fifo_flag_cnt_r
;
235 extern IIC_CLK_DUR_R iic_clk_dur_r
;
236 extern IIC_CSR1_R iic_csr1_r
;
237 extern IIC_CSR2_R iic_csr2_r
;
238 extern DMA_UPPER_LMT_R even_dma_upper_lmt_r
;
239 extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r
;
243 /***************** 8 bit I2C register globals ***********/
244 #define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/
245 #define EVEN_CSR 0x011
246 #define ODD_CSR 0x012
249 #define X_CLIP_START 0x020
250 #define Y_CLIP_START 0x022
251 #define X_CLIP_END 0x024
252 #define Y_CLIP_END 0x026
253 #define AD_ADDR 0x030
256 #define DIG_OUT 0x040
257 #define PM_LUT_ADDR 0x050
258 #define PM_LUT_DATA 0x051
261 /******** Assignments and Typedefs for 8 bit I2C Registers********************/
263 typedef union i2c_csr2_tag
{
276 typedef union i2c_even_csr_tag
{
286 typedef union i2c_odd_csr_tag
{
296 typedef union i2c_config_tag
{
310 typedef union i2c_ad_cmd_tag
{
311 /* bits can have 3 different meanings depending on value of AD_ADDR */
313 /* Bt252 Command Register if AD_ADDR = 00h */
318 u8 DIGITIZE_CNL_SEL1
:2;
321 /* Bt252 IOUT0 register if AD_ADDR = 01h */
326 /* BT252 IOUT1 register if AD_ADDR = 02h */
333 /***** Global declarations of local copies of boards' 8 bit I2C registers ***/
335 extern I2C_CSR2 i2c_csr2
;
336 extern I2C_EVEN_CSR i2c_even_csr
;
337 extern I2C_ODD_CSR i2c_odd_csr
;
338 extern I2C_CONFIG i2c_config
;
340 extern u8 i2c_x_clip_start
;
341 extern u8 i2c_y_clip_start
;
342 extern u8 i2c_x_clip_end
;
343 extern u8 i2c_y_clip_end
;
344 extern u8 i2c_ad_addr
;
345 extern u8 i2c_ad_lut
;
346 extern I2C_AD_CMD i2c_ad_cmd
;
347 extern u8 i2c_dig_out
;
348 extern u8 i2c_pm_lut_addr
;
349 extern u8 i2c_pm_lut_data
;
351 /* Functions for Global use */
353 /* access 8-bit IIC registers */
355 extern int ReadI2C(u8
*lpReg
, u_short wIregIndex
, u8
*byVal
);
356 extern int WriteI2C(u8
*lpReg
, u_short wIregIndex
, u8 byVal
);