include/asm-powerpc/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4
   5 #include <linux/pci.h>
   6 #include <linux/list.h>
   7 #include <linux/ioport.h>
   8
   9 #ifndef CONFIG_PPC64
  10
  11 struct device_node;
  12 struct pci_controller;
  13
  14 /*
  15  * Structure of a PCI controller (host bridge)
  16  */
  17 struct pci_controller {
  18         struct pci_bus *bus;
  19         char is_dynamic;
  20         void *arch_data;
  21         struct list_head list_node;
  22         struct device *parent;
  23
  24         int first_busno;
  25         int last_busno;
  26         int self_busno;
  27
  28         void __iomem *io_base_virt;
  29         resource_size_t io_base_phys;
  30
  31         /* Some machines (PReP) have a non 1:1 mapping of
  32          * the PCI memory space in the CPU bus space
  33          */
  34         resource_size_t pci_mem_offset;
  35
  36         struct pci_ops *ops;
  37         volatile unsigned int __iomem *cfg_addr;
  38         volatile void __iomem *cfg_data;
  39
  40         /*
  41          * Used for variants of PCI indirect handling and possible quirks:
  42          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  43          *  EXT_REG - provides access to PCI-e extended registers
  44          *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
  45          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  46          *   to determine which bus number to match on when generating type0
  47          *   config cycles
  48          */
  49 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          (0x00000001)
  50 #define PPC_INDIRECT_TYPE_EXT_REG               (0x00000002)
  51 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  (0x00000004)
  52         u32 indirect_type;
  53
  54         /* Currently, we limit ourselves to 1 IO range and 3 mem
  55          * ranges since the common pci_bus structure can't handle more
  56          */
  57         struct resource io_resource;
  58         struct resource mem_resources[3];
  59         int global_number;              /* PCI domain number */
  60 };
  61
  62 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
  63 {
  64         return bus->sysdata;
  65 }
  66
  67 /* These are used for config access before all the PCI probing
  68    has been done. */
  69 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  70                            int where, u8 *val);
  71 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
  72                            int where, u16 *val);
  73 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
  74                             int where, u32 *val);
  75 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  76                             int where, u8 val);
  77 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
  78                             int where, u16 val);
  79 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
  80                              int where, u32 val);
  81
  82 extern void setup_indirect_pci_nomap(struct pci_controller* hose,
  83                                void __iomem *cfg_addr, void __iomem *cfg_data);
  84 extern void setup_indirect_pci(struct pci_controller* hose,
  85                                u32 cfg_addr, u32 cfg_data);
  86 extern void setup_grackle(struct pci_controller *hose);
  87
  88 #else
  89
  90
  91 /*
  92  * This program is free software; you can redistribute it and/or
  93  * modify it under the terms of the GNU General Public License
  94  * as published by the Free Software Foundation; either version
  95  * 2 of the License, or (at your option) any later version.
  96  */
  97
  98 /*
  99  * Structure of a PCI controller (host bridge)
 100  */
 101 struct pci_controller {
 102         struct pci_bus *bus;
 103         char is_dynamic;
 104         int node;
 105         void *arch_data;
 106         struct list_head list_node;
 107         struct device *parent;
 108
 109         int first_busno;
 110         int last_busno;
 111
 112         void __iomem *io_base_virt;
 113         void *io_base_alloc;
 114         resource_size_t io_base_phys;
 115
 116         /* Some machines have a non 1:1 mapping of
 117          * the PCI memory space in the CPU bus space
 118          */
 119         resource_size_t pci_mem_offset;
 120         unsigned long pci_io_size;
 121
 122         struct pci_ops *ops;
 123         volatile unsigned int __iomem *cfg_addr;
 124         volatile void __iomem *cfg_data;
 125
 126         /* Currently, we limit ourselves to 1 IO range and 3 mem
 127          * ranges since the common pci_bus structure can't handle more
 128          */
 129         struct resource io_resource;
 130         struct resource mem_resources[3];
 131         int global_number;
 132         unsigned long buid;
 133         unsigned long dma_window_base_cur;
 134         unsigned long dma_window_size;
 135
 136         void *private_data;
 137 };
 138
 139 /*
 140  * PCI stuff, for nodes representing PCI devices, pointed to
 141  * by device_node->data.
 142  */
 143 struct pci_controller;
 144 struct iommu_table;
 145
 146 struct pci_dn {
 147         int     busno;                  /* pci bus number */
 148         int     bussubno;               /* pci subordinate bus number */
 149         int     devfn;                  /* pci device and function number */
 150         int     class_code;             /* pci device class */
 151
 152         struct  pci_controller *phb;    /* for pci devices */
 153         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 154         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 155         struct  device_node *node;      /* back-pointer to the device_node */
 156
 157         int     pci_ext_config_space;   /* for pci devices */
 158
 159 #ifdef CONFIG_EEH
 160         int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
 161         int     eeh_config_addr;
 162         int     eeh_pe_config_addr; /* new-style partition endpoint address */
 163         int     eeh_check_count;        /* # times driver ignored error */
 164         int     eeh_freeze_count;       /* # times this device froze up. */
 165         int     eeh_false_positives;    /* # times this device reported #ff's */
 166         u32     config_space[16];       /* saved PCI config space */
 167 #endif
 168 };
 169
 170 /* Get the pointer to a device_node's pci_dn */
 171 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 172
 173 struct device_node *fetch_dev_dn(struct pci_dev *dev);
 174
 175 /* Get a device_node from a pci_dev.  This code must be fast except
 176  * in the case where the sysdata is incorrect and needs to be fixed
 177  * up (this will only happen once).
 178  * In this case the sysdata will have been inherited from a PCI host
 179  * bridge or a PCI-PCI bridge further up the tree, so it will point
 180  * to a valid struct pci_dn, just not the one we want.
 181  */
 182 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
 183 {
 184         struct device_node *dn = dev->sysdata;
 185         struct pci_dn *pdn = dn->data;
 186
 187         if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
 188                 return dn;      /* fast path.  sysdata is good */
 189         return fetch_dev_dn(dev);
 190 }
 191
 192 static inline int pci_device_from_OF_node(struct device_node *np,
 193                                           u8 *bus, u8 *devfn)
 194 {
 195         if (!PCI_DN(np))
 196                 return -ENODEV;
 197         *bus = PCI_DN(np)->busno;
 198         *devfn = PCI_DN(np)->devfn;
 199         return 0;
 200 }
 201
 202 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 203 {
 204         if (bus->self)
 205                 return pci_device_to_OF_node(bus->self);
 206         else
 207                 return bus->sysdata; /* Must be root bus (PHB) */
 208 }
 209
 210 /** Find the bus corresponding to the indicated device node */
 211 struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
 212
 213 /** Remove all of the PCI devices under this bus */
 214 void pcibios_remove_pci_devices(struct pci_bus *bus);
 215
 216 /** Discover new pci devices under this bus, and add them */
 217 void pcibios_add_pci_devices(struct pci_bus * bus);
 218 void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
 219
 220 extern int pcibios_remove_root_bus(struct pci_controller *phb);
 221
 222 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
 223 {
 224         struct device_node *busdn = bus->sysdata;
 225
 226         BUG_ON(busdn == NULL);
 227         return PCI_DN(busdn)->phb;
 228 }
 229
 230 extern void pcibios_free_controller(struct pci_controller *phb);
 231
 232 extern void isa_bridge_find_early(struct pci_controller *hose);
 233
 234 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 235 extern int pcibios_map_io_space(struct pci_bus *bus);
 236
 237 /* Return values for ppc_md.pci_probe_mode function */
 238 #define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
 239 #define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
 240 #define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
 241
 242 #ifdef CONFIG_NUMA
 243 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 244 #else
 245 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 246 #endif
 247
 248 #endif /* CONFIG_PPC64 */
 249
 250 /* Get the PCI host controller for an OF device */
 251 extern struct pci_controller*
 252 pci_find_hose_for_OF_device(struct device_node* node);
 253
 254 /* Fill up host controller resources from the OF node */
 255 extern void
 256 pci_process_bridge_OF_ranges(struct pci_controller *hose,
 257                            struct device_node *dev, int primary);
 258
 259 /* Allocate a new PCI host bridge structure */
 260 extern struct pci_controller *
 261 pcibios_alloc_controller(struct device_node *dev);
 262 #ifdef CONFIG_PCI
 263 extern unsigned long pci_address_to_pio(phys_addr_t address);
 264 #else
 265 static inline unsigned long pci_address_to_pio(phys_addr_t address)
 266 {
 267         return (unsigned long)-1;
 268 }
 269 #endif
 270
 271
 272
 273 #endif /* __KERNEL__ */
 274 #endif