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drm/radeon/kms/pm: add support for no display power states
[linux-2.6/cjktty.git] / drivers / gpu / drm / radeon / r600.c
blob08a328c4165a51af1e6be788e0f05c3a4f058794
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include "drmP.h"
33 #include "radeon_drm.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
37 #include "r600d.h"
38 #include "atom.h"
39 #include "avivod.h"
40
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
50
51 /* Firmware Names */
52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
53 MODULE_FIRMWARE("radeon/R600_me.bin");
54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV610_me.bin");
56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV630_me.bin");
58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV620_me.bin");
60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV635_me.bin");
62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV670_me.bin");
64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65 MODULE_FIRMWARE("radeon/RS780_me.bin");
66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV770_me.bin");
68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69 MODULE_FIRMWARE("radeon/RV730_me.bin");
70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
86
87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
88
89 /* r600,rv610,rv630,rv620,rv635,rv670 */
90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
91 void r600_gpu_init(struct radeon_device *rdev);
92 void r600_fini(struct radeon_device *rdev);
93 void r600_irq_disable(struct radeon_device *rdev);
94
95 void r600_get_power_state(struct radeon_device *rdev,
96 enum radeon_pm_action action)
97 {
98 int i;
99
100 rdev->pm.can_upclock = true;
101 rdev->pm.can_downclock = true;
102
103 /* power state array is low to high, default is first */
104 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
105 int min_power_state_index = 0;
106
107 if (rdev->pm.num_power_states > 2)
108 min_power_state_index = 1;
109
110 switch (action) {
111 case PM_ACTION_MINIMUM:
112 rdev->pm.requested_power_state_index = min_power_state_index;
113 rdev->pm.requested_clock_mode_index = 0;
114 rdev->pm.can_downclock = false;
115 break;
116 case PM_ACTION_DOWNCLOCK:
117 if (rdev->pm.current_power_state_index == min_power_state_index) {
118 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
119 rdev->pm.can_downclock = false;
120 } else {
121 if (rdev->pm.active_crtc_count > 1) {
122 for (i = 0; i < rdev->pm.num_power_states; i++) {
123 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
124 continue;
125 else if (i >= rdev->pm.current_power_state_index) {
126 rdev->pm.requested_power_state_index =
127 rdev->pm.current_power_state_index;
128 break;
129 } else {
130 rdev->pm.requested_power_state_index = i;
131 break;
132 }
133 }
134 } else
135 rdev->pm.requested_power_state_index =
136 rdev->pm.current_power_state_index - 1;
137 }
138 rdev->pm.requested_clock_mode_index = 0;
139 /* don't use the power state if crtcs are active and no display flag is set */
140 if ((rdev->pm.active_crtc_count > 0) &&
141 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
142 clock_info[rdev->pm.requested_clock_mode_index].flags &
143 RADEON_PM_MODE_NO_DISPLAY)) {
144 rdev->pm.requested_power_state_index++;
145 }
146 break;
147 case PM_ACTION_UPCLOCK:
148 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
149 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
150 rdev->pm.can_upclock = false;
151 } else {
152 if (rdev->pm.active_crtc_count > 1) {
153 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
154 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
155 continue;
156 else if (i <= rdev->pm.current_power_state_index) {
157 rdev->pm.requested_power_state_index =
158 rdev->pm.current_power_state_index;
159 break;
160 } else {
161 rdev->pm.requested_power_state_index = i;
162 break;
163 }
164 }
165 } else
166 rdev->pm.requested_power_state_index =
167 rdev->pm.current_power_state_index + 1;
168 }
169 rdev->pm.requested_clock_mode_index = 0;
170 break;
171 case PM_ACTION_DEFAULT:
172 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
173 rdev->pm.requested_clock_mode_index = 0;
174 rdev->pm.can_upclock = false;
175 break;
176 case PM_ACTION_NONE:
177 default:
178 DRM_ERROR("Requested mode for not defined action\n");
179 return;
180 }
181 } else {
182 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
183 /* for now just select the first power state and switch between clock modes */
184 /* power state array is low to high, default is first (0) */
185 if (rdev->pm.active_crtc_count > 1) {
186 rdev->pm.requested_power_state_index = -1;
187 /* start at 1 as we don't want the default mode */
188 for (i = 1; i < rdev->pm.num_power_states; i++) {
189 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
190 continue;
191 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
192 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
193 rdev->pm.requested_power_state_index = i;
194 break;
195 }
196 }
197 /* if nothing selected, grab the default state. */
198 if (rdev->pm.requested_power_state_index == -1)
199 rdev->pm.requested_power_state_index = 0;
200 } else
201 rdev->pm.requested_power_state_index = 1;
202
203 switch (action) {
204 case PM_ACTION_MINIMUM:
205 rdev->pm.requested_clock_mode_index = 0;
206 rdev->pm.can_downclock = false;
207 break;
208 case PM_ACTION_DOWNCLOCK:
209 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
210 if (rdev->pm.current_clock_mode_index == 0) {
211 rdev->pm.requested_clock_mode_index = 0;
212 rdev->pm.can_downclock = false;
213 } else
214 rdev->pm.requested_clock_mode_index =
215 rdev->pm.current_clock_mode_index - 1;
216 } else {
217 rdev->pm.requested_clock_mode_index = 0;
218 rdev->pm.can_downclock = false;
219 }
220 /* don't use the power state if crtcs are active and no display flag is set */
221 if ((rdev->pm.active_crtc_count > 0) &&
222 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
223 clock_info[rdev->pm.requested_clock_mode_index].flags &
224 RADEON_PM_MODE_NO_DISPLAY)) {
225 rdev->pm.requested_clock_mode_index++;
226 }
227 break;
228 case PM_ACTION_UPCLOCK:
229 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
230 if (rdev->pm.current_clock_mode_index ==
231 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
232 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
233 rdev->pm.can_upclock = false;
234 } else
235 rdev->pm.requested_clock_mode_index =
236 rdev->pm.current_clock_mode_index + 1;
237 } else {
238 rdev->pm.requested_clock_mode_index =
239 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
240 rdev->pm.can_upclock = false;
241 }
242 break;
243 case PM_ACTION_DEFAULT:
244 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
245 rdev->pm.requested_clock_mode_index = 0;
246 rdev->pm.can_upclock = false;
247 break;
248 case PM_ACTION_NONE:
249 default:
250 DRM_ERROR("Requested mode for not defined action\n");
251 return;
252 }
253 }
254
255 DRM_INFO("Requested: e: %d m: %d p: %d\n",
256 rdev->pm.power_state[rdev->pm.requested_power_state_index].
257 clock_info[rdev->pm.requested_clock_mode_index].sclk,
258 rdev->pm.power_state[rdev->pm.requested_power_state_index].
259 clock_info[rdev->pm.requested_clock_mode_index].mclk,
260 rdev->pm.power_state[rdev->pm.requested_power_state_index].
261 pcie_lanes);
262 }
263
264 void r600_set_power_state(struct radeon_device *rdev, bool static_switch)
265 {
266 u32 sclk, mclk;
267
268 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
269 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
270 return;
271
272 if (radeon_gui_idle(rdev)) {
273 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
274 clock_info[rdev->pm.requested_clock_mode_index].sclk;
275 if (sclk > rdev->clock.default_sclk)
276 sclk = rdev->clock.default_sclk;
277
278 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
279 clock_info[rdev->pm.requested_clock_mode_index].mclk;
280 if (mclk > rdev->clock.default_mclk)
281 mclk = rdev->clock.default_mclk;
282
283 /* voltage, pcie lanes, etc.*/
284 radeon_pm_misc(rdev);
285
286 if (static_switch) {
287 radeon_pm_prepare(rdev);
288 /* set engine clock */
289 if (sclk != rdev->pm.current_sclk) {
290 radeon_set_engine_clock(rdev, sclk);
291 rdev->pm.current_sclk = sclk;
292 DRM_INFO("Setting: e: %d\n", sclk);
293 }
294 /* set memory clock */
295 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
296 radeon_set_memory_clock(rdev, mclk);
297 rdev->pm.current_mclk = mclk;
298 DRM_INFO("Setting: m: %d\n", mclk);
299 }
300 radeon_pm_finish(rdev);
301 } else {
302 radeon_sync_with_vblank(rdev);
303
304 if (!radeon_pm_in_vbl(rdev))
305 return;
306
307 radeon_pm_prepare(rdev);
308 if (sclk != rdev->pm.current_sclk) {
309 radeon_pm_debug_check_in_vbl(rdev, false);
310 radeon_set_engine_clock(rdev, sclk);
311 radeon_pm_debug_check_in_vbl(rdev, true);
312 rdev->pm.current_sclk = sclk;
313 DRM_INFO("Setting: e: %d\n", sclk);
314 }
315
316 /* set memory clock */
317 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
318 radeon_pm_debug_check_in_vbl(rdev, false);
319 radeon_set_memory_clock(rdev, mclk);
320 radeon_pm_debug_check_in_vbl(rdev, true);
321 rdev->pm.current_mclk = mclk;
322 DRM_INFO("Setting: m: %d\n", mclk);
323 }
324 radeon_pm_finish(rdev);
325 }
326
327 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
328 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
329 } else
330 DRM_INFO("GUI not idle!!!\n");
331 }
332
333 void r600_pm_misc(struct radeon_device *rdev)
334 {
335
336 }
337
338 bool r600_gui_idle(struct radeon_device *rdev)
339 {
340 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
341 return false;
342 else
343 return true;
344 }
345
346 /* hpd for digital panel detect/disconnect */
347 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
348 {
349 bool connected = false;
350
351 if (ASIC_IS_DCE3(rdev)) {
352 switch (hpd) {
353 case RADEON_HPD_1:
354 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
355 connected = true;
356 break;
357 case RADEON_HPD_2:
358 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
359 connected = true;
360 break;
361 case RADEON_HPD_3:
362 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
363 connected = true;
364 break;
365 case RADEON_HPD_4:
366 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
367 connected = true;
368 break;
369 /* DCE 3.2 */
370 case RADEON_HPD_5:
371 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
372 connected = true;
373 break;
374 case RADEON_HPD_6:
375 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
376 connected = true;
377 break;
378 default:
379 break;
380 }
381 } else {
382 switch (hpd) {
383 case RADEON_HPD_1:
384 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
385 connected = true;
386 break;
387 case RADEON_HPD_2:
388 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
389 connected = true;
390 break;
391 case RADEON_HPD_3:
392 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
393 connected = true;
394 break;
395 default:
396 break;
397 }
398 }
399 return connected;
400 }
401
402 void r600_hpd_set_polarity(struct radeon_device *rdev,
403 enum radeon_hpd_id hpd)
404 {
405 u32 tmp;
406 bool connected = r600_hpd_sense(rdev, hpd);
407
408 if (ASIC_IS_DCE3(rdev)) {
409 switch (hpd) {
410 case RADEON_HPD_1:
411 tmp = RREG32(DC_HPD1_INT_CONTROL);
412 if (connected)
413 tmp &= ~DC_HPDx_INT_POLARITY;
414 else
415 tmp |= DC_HPDx_INT_POLARITY;
416 WREG32(DC_HPD1_INT_CONTROL, tmp);
417 break;
418 case RADEON_HPD_2:
419 tmp = RREG32(DC_HPD2_INT_CONTROL);
420 if (connected)
421 tmp &= ~DC_HPDx_INT_POLARITY;
422 else
423 tmp |= DC_HPDx_INT_POLARITY;
424 WREG32(DC_HPD2_INT_CONTROL, tmp);
425 break;
426 case RADEON_HPD_3:
427 tmp = RREG32(DC_HPD3_INT_CONTROL);
428 if (connected)
429 tmp &= ~DC_HPDx_INT_POLARITY;
430 else
431 tmp |= DC_HPDx_INT_POLARITY;
432 WREG32(DC_HPD3_INT_CONTROL, tmp);
433 break;
434 case RADEON_HPD_4:
435 tmp = RREG32(DC_HPD4_INT_CONTROL);
436 if (connected)
437 tmp &= ~DC_HPDx_INT_POLARITY;
438 else
439 tmp |= DC_HPDx_INT_POLARITY;
440 WREG32(DC_HPD4_INT_CONTROL, tmp);
441 break;
442 case RADEON_HPD_5:
443 tmp = RREG32(DC_HPD5_INT_CONTROL);
444 if (connected)
445 tmp &= ~DC_HPDx_INT_POLARITY;
446 else
447 tmp |= DC_HPDx_INT_POLARITY;
448 WREG32(DC_HPD5_INT_CONTROL, tmp);
449 break;
450 /* DCE 3.2 */
451 case RADEON_HPD_6:
452 tmp = RREG32(DC_HPD6_INT_CONTROL);
453 if (connected)
454 tmp &= ~DC_HPDx_INT_POLARITY;
455 else
456 tmp |= DC_HPDx_INT_POLARITY;
457 WREG32(DC_HPD6_INT_CONTROL, tmp);
458 break;
459 default:
460 break;
461 }
462 } else {
463 switch (hpd) {
464 case RADEON_HPD_1:
465 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
466 if (connected)
467 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
468 else
469 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
470 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
471 break;
472 case RADEON_HPD_2:
473 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
474 if (connected)
475 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
476 else
477 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
478 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
479 break;
480 case RADEON_HPD_3:
481 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
482 if (connected)
483 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
484 else
485 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
486 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
487 break;
488 default:
489 break;
490 }
491 }
492 }
493
494 void r600_hpd_init(struct radeon_device *rdev)
495 {
496 struct drm_device *dev = rdev->ddev;
497 struct drm_connector *connector;
498
499 if (ASIC_IS_DCE3(rdev)) {
500 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
501 if (ASIC_IS_DCE32(rdev))
502 tmp |= DC_HPDx_EN;
503
504 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
505 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
506 switch (radeon_connector->hpd.hpd) {
507 case RADEON_HPD_1:
508 WREG32(DC_HPD1_CONTROL, tmp);
509 rdev->irq.hpd[0] = true;
510 break;
511 case RADEON_HPD_2:
512 WREG32(DC_HPD2_CONTROL, tmp);
513 rdev->irq.hpd[1] = true;
514 break;
515 case RADEON_HPD_3:
516 WREG32(DC_HPD3_CONTROL, tmp);
517 rdev->irq.hpd[2] = true;
518 break;
519 case RADEON_HPD_4:
520 WREG32(DC_HPD4_CONTROL, tmp);
521 rdev->irq.hpd[3] = true;
522 break;
523 /* DCE 3.2 */
524 case RADEON_HPD_5:
525 WREG32(DC_HPD5_CONTROL, tmp);
526 rdev->irq.hpd[4] = true;
527 break;
528 case RADEON_HPD_6:
529 WREG32(DC_HPD6_CONTROL, tmp);
530 rdev->irq.hpd[5] = true;
531 break;
532 default:
533 break;
534 }
535 }
536 } else {
537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
538 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
539 switch (radeon_connector->hpd.hpd) {
540 case RADEON_HPD_1:
541 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
542 rdev->irq.hpd[0] = true;
543 break;
544 case RADEON_HPD_2:
545 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
546 rdev->irq.hpd[1] = true;
547 break;
548 case RADEON_HPD_3:
549 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
550 rdev->irq.hpd[2] = true;
551 break;
552 default:
553 break;
554 }
555 }
556 }
557 if (rdev->irq.installed)
558 r600_irq_set(rdev);
559 }
560
561 void r600_hpd_fini(struct radeon_device *rdev)
562 {
563 struct drm_device *dev = rdev->ddev;
564 struct drm_connector *connector;
565
566 if (ASIC_IS_DCE3(rdev)) {
567 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
568 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
569 switch (radeon_connector->hpd.hpd) {
570 case RADEON_HPD_1:
571 WREG32(DC_HPD1_CONTROL, 0);
572 rdev->irq.hpd[0] = false;
573 break;
574 case RADEON_HPD_2:
575 WREG32(DC_HPD2_CONTROL, 0);
576 rdev->irq.hpd[1] = false;
577 break;
578 case RADEON_HPD_3:
579 WREG32(DC_HPD3_CONTROL, 0);
580 rdev->irq.hpd[2] = false;
581 break;
582 case RADEON_HPD_4:
583 WREG32(DC_HPD4_CONTROL, 0);
584 rdev->irq.hpd[3] = false;
585 break;
586 /* DCE 3.2 */
587 case RADEON_HPD_5:
588 WREG32(DC_HPD5_CONTROL, 0);
589 rdev->irq.hpd[4] = false;
590 break;
591 case RADEON_HPD_6:
592 WREG32(DC_HPD6_CONTROL, 0);
593 rdev->irq.hpd[5] = false;
594 break;
595 default:
596 break;
597 }
598 }
599 } else {
600 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
601 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
602 switch (radeon_connector->hpd.hpd) {
603 case RADEON_HPD_1:
604 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
605 rdev->irq.hpd[0] = false;
606 break;
607 case RADEON_HPD_2:
608 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
609 rdev->irq.hpd[1] = false;
610 break;
611 case RADEON_HPD_3:
612 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
613 rdev->irq.hpd[2] = false;
614 break;
615 default:
616 break;
617 }
618 }
619 }
620 }
621
622 /*
623 * R600 PCIE GART
624 */
625 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
626 {
627 unsigned i;
628 u32 tmp;
629
630 /* flush hdp cache so updates hit vram */
631 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
632
633 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
634 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
635 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
636 for (i = 0; i < rdev->usec_timeout; i++) {
637 /* read MC_STATUS */
638 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
639 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
640 if (tmp == 2) {
641 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
642 return;
643 }
644 if (tmp) {
645 return;
646 }
647 udelay(1);
648 }
649 }
650
651 int r600_pcie_gart_init(struct radeon_device *rdev)
652 {
653 int r;
654
655 if (rdev->gart.table.vram.robj) {
656 WARN(1, "R600 PCIE GART already initialized.\n");
657 return 0;
658 }
659 /* Initialize common gart structure */
660 r = radeon_gart_init(rdev);
661 if (r)
662 return r;
663 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
664 return radeon_gart_table_vram_alloc(rdev);
665 }
666
667 int r600_pcie_gart_enable(struct radeon_device *rdev)
668 {
669 u32 tmp;
670 int r, i;
671
672 if (rdev->gart.table.vram.robj == NULL) {
673 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
674 return -EINVAL;
675 }
676 r = radeon_gart_table_vram_pin(rdev);
677 if (r)
678 return r;
679 radeon_gart_restore(rdev);
680
681 /* Setup L2 cache */
682 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
683 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
684 EFFECTIVE_L2_QUEUE_SIZE(7));
685 WREG32(VM_L2_CNTL2, 0);
686 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
687 /* Setup TLB control */
688 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
689 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
690 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
691 ENABLE_WAIT_L2_QUERY;
692 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
693 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
694 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
695 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
696 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
697 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
698 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
699 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
700 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
701 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
702 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
703 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
704 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
705 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
706 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
707 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
708 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
709 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
710 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
711 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
712 (u32)(rdev->dummy_page.addr >> 12));
713 for (i = 1; i < 7; i++)
714 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
715
716 r600_pcie_gart_tlb_flush(rdev);
717 rdev->gart.ready = true;
718 return 0;
719 }
720
721 void r600_pcie_gart_disable(struct radeon_device *rdev)
722 {
723 u32 tmp;
724 int i, r;
725
726 /* Disable all tables */
727 for (i = 0; i < 7; i++)
728 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
729
730 /* Disable L2 cache */
731 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
732 EFFECTIVE_L2_QUEUE_SIZE(7));
733 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
734 /* Setup L1 TLB control */
735 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
736 ENABLE_WAIT_L2_QUERY;
737 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
738 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
739 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
740 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
741 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
742 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
743 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
744 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
745 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
746 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
747 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
748 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
749 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
750 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
751 if (rdev->gart.table.vram.robj) {
752 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
753 if (likely(r == 0)) {
754 radeon_bo_kunmap(rdev->gart.table.vram.robj);
755 radeon_bo_unpin(rdev->gart.table.vram.robj);
756 radeon_bo_unreserve(rdev->gart.table.vram.robj);
757 }
758 }
759 }
760
761 void r600_pcie_gart_fini(struct radeon_device *rdev)
762 {
763 radeon_gart_fini(rdev);
764 r600_pcie_gart_disable(rdev);
765 radeon_gart_table_vram_free(rdev);
766 }
767
768 void r600_agp_enable(struct radeon_device *rdev)
769 {
770 u32 tmp;
771 int i;
772
773 /* Setup L2 cache */
774 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
775 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
776 EFFECTIVE_L2_QUEUE_SIZE(7));
777 WREG32(VM_L2_CNTL2, 0);
778 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
779 /* Setup TLB control */
780 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
781 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
782 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
783 ENABLE_WAIT_L2_QUERY;
784 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
785 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
786 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
787 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
788 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
789 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
790 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
791 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
792 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
793 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
794 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
795 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
796 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
797 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
798 for (i = 0; i < 7; i++)
799 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
800 }
801
802 int r600_mc_wait_for_idle(struct radeon_device *rdev)
803 {
804 unsigned i;
805 u32 tmp;
806
807 for (i = 0; i < rdev->usec_timeout; i++) {
808 /* read MC_STATUS */
809 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
810 if (!tmp)
811 return 0;
812 udelay(1);
813 }
814 return -1;
815 }
816
817 static void r600_mc_program(struct radeon_device *rdev)
818 {
819 struct rv515_mc_save save;
820 u32 tmp;
821 int i, j;
822
823 /* Initialize HDP */
824 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
825 WREG32((0x2c14 + j), 0x00000000);
826 WREG32((0x2c18 + j), 0x00000000);
827 WREG32((0x2c1c + j), 0x00000000);
828 WREG32((0x2c20 + j), 0x00000000);
829 WREG32((0x2c24 + j), 0x00000000);
830 }
831 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
832
833 rv515_mc_stop(rdev, &save);
834 if (r600_mc_wait_for_idle(rdev)) {
835 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
836 }
837 /* Lockout access through VGA aperture (doesn't exist before R600) */
838 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
839 /* Update configuration */
840 if (rdev->flags & RADEON_IS_AGP) {
841 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
842 /* VRAM before AGP */
843 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
844 rdev->mc.vram_start >> 12);
845 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
846 rdev->mc.gtt_end >> 12);
847 } else {
848 /* VRAM after AGP */
849 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
850 rdev->mc.gtt_start >> 12);
851 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
852 rdev->mc.vram_end >> 12);
853 }
854 } else {
855 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
856 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
857 }
858 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
859 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
860 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
861 WREG32(MC_VM_FB_LOCATION, tmp);
862 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
863 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
864 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
865 if (rdev->flags & RADEON_IS_AGP) {
866 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
867 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
868 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
869 } else {
870 WREG32(MC_VM_AGP_BASE, 0);
871 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
872 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
873 }
874 if (r600_mc_wait_for_idle(rdev)) {
875 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
876 }
877 rv515_mc_resume(rdev, &save);
878 /* we need to own VRAM, so turn off the VGA renderer here
879 * to stop it overwriting our objects */
880 rv515_vga_render_disable(rdev);
881 }
882
883 /**
884 * r600_vram_gtt_location - try to find VRAM & GTT location
885 * @rdev: radeon device structure holding all necessary informations
886 * @mc: memory controller structure holding memory informations
887 *
888 * Function will place try to place VRAM at same place as in CPU (PCI)
889 * address space as some GPU seems to have issue when we reprogram at
890 * different address space.
891 *
892 * If there is not enough space to fit the unvisible VRAM after the
893 * aperture then we limit the VRAM size to the aperture.
894 *
895 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
896 * them to be in one from GPU point of view so that we can program GPU to
897 * catch access outside them (weird GPU policy see ??).
898 *
899 * This function will never fails, worst case are limiting VRAM or GTT.
900 *
901 * Note: GTT start, end, size should be initialized before calling this
902 * function on AGP platform.
903 */
904 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
905 {
906 u64 size_bf, size_af;
907
908 if (mc->mc_vram_size > 0xE0000000) {
909 /* leave room for at least 512M GTT */
910 dev_warn(rdev->dev, "limiting VRAM\n");
911 mc->real_vram_size = 0xE0000000;
912 mc->mc_vram_size = 0xE0000000;
913 }
914 if (rdev->flags & RADEON_IS_AGP) {
915 size_bf = mc->gtt_start;
916 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
917 if (size_bf > size_af) {
918 if (mc->mc_vram_size > size_bf) {
919 dev_warn(rdev->dev, "limiting VRAM\n");
920 mc->real_vram_size = size_bf;
921 mc->mc_vram_size = size_bf;
922 }
923 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
924 } else {
925 if (mc->mc_vram_size > size_af) {
926 dev_warn(rdev->dev, "limiting VRAM\n");
927 mc->real_vram_size = size_af;
928 mc->mc_vram_size = size_af;
929 }
930 mc->vram_start = mc->gtt_end;
931 }
932 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
933 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
934 mc->mc_vram_size >> 20, mc->vram_start,
935 mc->vram_end, mc->real_vram_size >> 20);
936 } else {
937 u64 base = 0;
938 if (rdev->flags & RADEON_IS_IGP)
939 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
940 radeon_vram_location(rdev, &rdev->mc, base);
941 radeon_gtt_location(rdev, mc);
942 }
943 }
944
945 int r600_mc_init(struct radeon_device *rdev)
946 {
947 u32 tmp;
948 int chansize, numchan;
949
950 /* Get VRAM informations */
951 rdev->mc.vram_is_ddr = true;
952 tmp = RREG32(RAMCFG);
953 if (tmp & CHANSIZE_OVERRIDE) {
954 chansize = 16;
955 } else if (tmp & CHANSIZE_MASK) {
956 chansize = 64;
957 } else {
958 chansize = 32;
959 }
960 tmp = RREG32(CHMAP);
961 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
962 case 0:
963 default:
964 numchan = 1;
965 break;
966 case 1:
967 numchan = 2;
968 break;
969 case 2:
970 numchan = 4;
971 break;
972 case 3:
973 numchan = 8;
974 break;
975 }
976 rdev->mc.vram_width = numchan * chansize;
977 /* Could aper size report 0 ? */
978 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
979 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
980 /* Setup GPU memory space */
981 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
982 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
983 rdev->mc.visible_vram_size = rdev->mc.aper_size;
984 r600_vram_gtt_location(rdev, &rdev->mc);
985
986 if (rdev->flags & RADEON_IS_IGP)
987 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
988 radeon_update_bandwidth_info(rdev);
989 return 0;
990 }
991
992 /* We doesn't check that the GPU really needs a reset we simply do the
993 * reset, it's up to the caller to determine if the GPU needs one. We
994 * might add an helper function to check that.
995 */
996 int r600_gpu_soft_reset(struct radeon_device *rdev)
997 {
998 struct rv515_mc_save save;
999 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1000 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1001 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1002 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1003 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1004 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1005 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1006 S_008010_GUI_ACTIVE(1);
1007 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1008 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1009 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1010 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1011 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1012 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1013 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1014 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1015 u32 tmp;
1016
1017 dev_info(rdev->dev, "GPU softreset \n");
1018 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1019 RREG32(R_008010_GRBM_STATUS));
1020 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1021 RREG32(R_008014_GRBM_STATUS2));
1022 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1023 RREG32(R_000E50_SRBM_STATUS));
1024 rv515_mc_stop(rdev, &save);
1025 if (r600_mc_wait_for_idle(rdev)) {
1026 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1027 }
1028 /* Disable CP parsing/prefetching */
1029 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1030 /* Check if any of the rendering block is busy and reset it */
1031 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1032 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1033 tmp = S_008020_SOFT_RESET_CR(1) |
1034 S_008020_SOFT_RESET_DB(1) |
1035 S_008020_SOFT_RESET_CB(1) |
1036 S_008020_SOFT_RESET_PA(1) |
1037 S_008020_SOFT_RESET_SC(1) |
1038 S_008020_SOFT_RESET_SMX(1) |
1039 S_008020_SOFT_RESET_SPI(1) |
1040 S_008020_SOFT_RESET_SX(1) |
1041 S_008020_SOFT_RESET_SH(1) |
1042 S_008020_SOFT_RESET_TC(1) |
1043 S_008020_SOFT_RESET_TA(1) |
1044 S_008020_SOFT_RESET_VC(1) |
1045 S_008020_SOFT_RESET_VGT(1);
1046 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1047 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1048 RREG32(R_008020_GRBM_SOFT_RESET);
1049 mdelay(15);
1050 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1051 }
1052 /* Reset CP (we always reset CP) */
1053 tmp = S_008020_SOFT_RESET_CP(1);
1054 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1055 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1056 RREG32(R_008020_GRBM_SOFT_RESET);
1057 mdelay(15);
1058 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1059 /* Wait a little for things to settle down */
1060 mdelay(1);
1061 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1062 RREG32(R_008010_GRBM_STATUS));
1063 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1064 RREG32(R_008014_GRBM_STATUS2));
1065 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1066 RREG32(R_000E50_SRBM_STATUS));
1067 rv515_mc_resume(rdev, &save);
1068 return 0;
1069 }
1070
1071 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1072 {
1073 u32 srbm_status;
1074 u32 grbm_status;
1075 u32 grbm_status2;
1076 int r;
1077
1078 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1079 grbm_status = RREG32(R_008010_GRBM_STATUS);
1080 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1081 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1082 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1083 return false;
1084 }
1085 /* force CP activities */
1086 r = radeon_ring_lock(rdev, 2);
1087 if (!r) {
1088 /* PACKET2 NOP */
1089 radeon_ring_write(rdev, 0x80000000);
1090 radeon_ring_write(rdev, 0x80000000);
1091 radeon_ring_unlock_commit(rdev);
1092 }
1093 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1094 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1095 }
1096
1097 int r600_asic_reset(struct radeon_device *rdev)
1098 {
1099 return r600_gpu_soft_reset(rdev);
1100 }
1101
1102 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1103 u32 num_backends,
1104 u32 backend_disable_mask)
1105 {
1106 u32 backend_map = 0;
1107 u32 enabled_backends_mask;
1108 u32 enabled_backends_count;
1109 u32 cur_pipe;
1110 u32 swizzle_pipe[R6XX_MAX_PIPES];
1111 u32 cur_backend;
1112 u32 i;
1113
1114 if (num_tile_pipes > R6XX_MAX_PIPES)
1115 num_tile_pipes = R6XX_MAX_PIPES;
1116 if (num_tile_pipes < 1)
1117 num_tile_pipes = 1;
1118 if (num_backends > R6XX_MAX_BACKENDS)
1119 num_backends = R6XX_MAX_BACKENDS;
1120 if (num_backends < 1)
1121 num_backends = 1;
1122
1123 enabled_backends_mask = 0;
1124 enabled_backends_count = 0;
1125 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1126 if (((backend_disable_mask >> i) & 1) == 0) {
1127 enabled_backends_mask |= (1 << i);
1128 ++enabled_backends_count;
1129 }
1130 if (enabled_backends_count == num_backends)
1131 break;
1132 }
1133
1134 if (enabled_backends_count == 0) {
1135 enabled_backends_mask = 1;
1136 enabled_backends_count = 1;
1137 }
1138
1139 if (enabled_backends_count != num_backends)
1140 num_backends = enabled_backends_count;
1141
1142 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1143 switch (num_tile_pipes) {
1144 case 1:
1145 swizzle_pipe[0] = 0;
1146 break;
1147 case 2:
1148 swizzle_pipe[0] = 0;
1149 swizzle_pipe[1] = 1;
1150 break;
1151 case 3:
1152 swizzle_pipe[0] = 0;
1153 swizzle_pipe[1] = 1;
1154 swizzle_pipe[2] = 2;
1155 break;
1156 case 4:
1157 swizzle_pipe[0] = 0;
1158 swizzle_pipe[1] = 1;
1159 swizzle_pipe[2] = 2;
1160 swizzle_pipe[3] = 3;
1161 break;
1162 case 5:
1163 swizzle_pipe[0] = 0;
1164 swizzle_pipe[1] = 1;
1165 swizzle_pipe[2] = 2;
1166 swizzle_pipe[3] = 3;
1167 swizzle_pipe[4] = 4;
1168 break;
1169 case 6:
1170 swizzle_pipe[0] = 0;
1171 swizzle_pipe[1] = 2;
1172 swizzle_pipe[2] = 4;
1173 swizzle_pipe[3] = 5;
1174 swizzle_pipe[4] = 1;
1175 swizzle_pipe[5] = 3;
1176 break;
1177 case 7:
1178 swizzle_pipe[0] = 0;
1179 swizzle_pipe[1] = 2;
1180 swizzle_pipe[2] = 4;
1181 swizzle_pipe[3] = 6;
1182 swizzle_pipe[4] = 1;
1183 swizzle_pipe[5] = 3;
1184 swizzle_pipe[6] = 5;
1185 break;
1186 case 8:
1187 swizzle_pipe[0] = 0;
1188 swizzle_pipe[1] = 2;
1189 swizzle_pipe[2] = 4;
1190 swizzle_pipe[3] = 6;
1191 swizzle_pipe[4] = 1;
1192 swizzle_pipe[5] = 3;
1193 swizzle_pipe[6] = 5;
1194 swizzle_pipe[7] = 7;
1195 break;
1196 }
1197
1198 cur_backend = 0;
1199 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1200 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1201 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1202
1203 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1204
1205 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1206 }
1207
1208 return backend_map;
1209 }
1210
1211 int r600_count_pipe_bits(uint32_t val)
1212 {
1213 int i, ret = 0;
1214
1215 for (i = 0; i < 32; i++) {
1216 ret += val & 1;
1217 val >>= 1;
1218 }
1219 return ret;
1220 }
1221
1222 void r600_gpu_init(struct radeon_device *rdev)
1223 {
1224 u32 tiling_config;
1225 u32 ramcfg;
1226 u32 backend_map;
1227 u32 cc_rb_backend_disable;
1228 u32 cc_gc_shader_pipe_config;
1229 u32 tmp;
1230 int i, j;
1231 u32 sq_config;
1232 u32 sq_gpr_resource_mgmt_1 = 0;
1233 u32 sq_gpr_resource_mgmt_2 = 0;
1234 u32 sq_thread_resource_mgmt = 0;
1235 u32 sq_stack_resource_mgmt_1 = 0;
1236 u32 sq_stack_resource_mgmt_2 = 0;
1237
1238 /* FIXME: implement */
1239 switch (rdev->family) {
1240 case CHIP_R600:
1241 rdev->config.r600.max_pipes = 4;
1242 rdev->config.r600.max_tile_pipes = 8;
1243 rdev->config.r600.max_simds = 4;
1244 rdev->config.r600.max_backends = 4;
1245 rdev->config.r600.max_gprs = 256;
1246 rdev->config.r600.max_threads = 192;
1247 rdev->config.r600.max_stack_entries = 256;
1248 rdev->config.r600.max_hw_contexts = 8;
1249 rdev->config.r600.max_gs_threads = 16;
1250 rdev->config.r600.sx_max_export_size = 128;
1251 rdev->config.r600.sx_max_export_pos_size = 16;
1252 rdev->config.r600.sx_max_export_smx_size = 128;
1253 rdev->config.r600.sq_num_cf_insts = 2;
1254 break;
1255 case CHIP_RV630:
1256 case CHIP_RV635:
1257 rdev->config.r600.max_pipes = 2;
1258 rdev->config.r600.max_tile_pipes = 2;
1259 rdev->config.r600.max_simds = 3;
1260 rdev->config.r600.max_backends = 1;
1261 rdev->config.r600.max_gprs = 128;
1262 rdev->config.r600.max_threads = 192;
1263 rdev->config.r600.max_stack_entries = 128;
1264 rdev->config.r600.max_hw_contexts = 8;
1265 rdev->config.r600.max_gs_threads = 4;
1266 rdev->config.r600.sx_max_export_size = 128;
1267 rdev->config.r600.sx_max_export_pos_size = 16;
1268 rdev->config.r600.sx_max_export_smx_size = 128;
1269 rdev->config.r600.sq_num_cf_insts = 2;
1270 break;
1271 case CHIP_RV610:
1272 case CHIP_RV620:
1273 case CHIP_RS780:
1274 case CHIP_RS880:
1275 rdev->config.r600.max_pipes = 1;
1276 rdev->config.r600.max_tile_pipes = 1;
1277 rdev->config.r600.max_simds = 2;
1278 rdev->config.r600.max_backends = 1;
1279 rdev->config.r600.max_gprs = 128;
1280 rdev->config.r600.max_threads = 192;
1281 rdev->config.r600.max_stack_entries = 128;
1282 rdev->config.r600.max_hw_contexts = 4;
1283 rdev->config.r600.max_gs_threads = 4;
1284 rdev->config.r600.sx_max_export_size = 128;
1285 rdev->config.r600.sx_max_export_pos_size = 16;
1286 rdev->config.r600.sx_max_export_smx_size = 128;
1287 rdev->config.r600.sq_num_cf_insts = 1;
1288 break;
1289 case CHIP_RV670:
1290 rdev->config.r600.max_pipes = 4;
1291 rdev->config.r600.max_tile_pipes = 4;
1292 rdev->config.r600.max_simds = 4;
1293 rdev->config.r600.max_backends = 4;
1294 rdev->config.r600.max_gprs = 192;
1295 rdev->config.r600.max_threads = 192;
1296 rdev->config.r600.max_stack_entries = 256;
1297 rdev->config.r600.max_hw_contexts = 8;
1298 rdev->config.r600.max_gs_threads = 16;
1299 rdev->config.r600.sx_max_export_size = 128;
1300 rdev->config.r600.sx_max_export_pos_size = 16;
1301 rdev->config.r600.sx_max_export_smx_size = 128;
1302 rdev->config.r600.sq_num_cf_insts = 2;
1303 break;
1304 default:
1305 break;
1306 }
1307
1308 /* Initialize HDP */
1309 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1310 WREG32((0x2c14 + j), 0x00000000);
1311 WREG32((0x2c18 + j), 0x00000000);
1312 WREG32((0x2c1c + j), 0x00000000);
1313 WREG32((0x2c20 + j), 0x00000000);
1314 WREG32((0x2c24 + j), 0x00000000);
1315 }
1316
1317 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1318
1319 /* Setup tiling */
1320 tiling_config = 0;
1321 ramcfg = RREG32(RAMCFG);
1322 switch (rdev->config.r600.max_tile_pipes) {
1323 case 1:
1324 tiling_config |= PIPE_TILING(0);
1325 break;
1326 case 2:
1327 tiling_config |= PIPE_TILING(1);
1328 break;
1329 case 4:
1330 tiling_config |= PIPE_TILING(2);
1331 break;
1332 case 8:
1333 tiling_config |= PIPE_TILING(3);
1334 break;
1335 default:
1336 break;
1337 }
1338 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1339 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1340 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1341 tiling_config |= GROUP_SIZE(0);
1342 rdev->config.r600.tiling_group_size = 256;
1343 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1344 if (tmp > 3) {
1345 tiling_config |= ROW_TILING(3);
1346 tiling_config |= SAMPLE_SPLIT(3);
1347 } else {
1348 tiling_config |= ROW_TILING(tmp);
1349 tiling_config |= SAMPLE_SPLIT(tmp);
1350 }
1351 tiling_config |= BANK_SWAPS(1);
1352
1353 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1354 cc_rb_backend_disable |=
1355 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1356
1357 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1358 cc_gc_shader_pipe_config |=
1359 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1360 cc_gc_shader_pipe_config |=
1361 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1362
1363 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1364 (R6XX_MAX_BACKENDS -
1365 r600_count_pipe_bits((cc_rb_backend_disable &
1366 R6XX_MAX_BACKENDS_MASK) >> 16)),
1367 (cc_rb_backend_disable >> 16));
1368
1369 tiling_config |= BACKEND_MAP(backend_map);
1370 WREG32(GB_TILING_CONFIG, tiling_config);
1371 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1372 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1373
1374 /* Setup pipes */
1375 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1376 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1377 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1378
1379 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1380 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1381 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1382
1383 /* Setup some CP states */
1384 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1385 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1386
1387 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1388 SYNC_WALKER | SYNC_ALIGNER));
1389 /* Setup various GPU states */
1390 if (rdev->family == CHIP_RV670)
1391 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1392
1393 tmp = RREG32(SX_DEBUG_1);
1394 tmp |= SMX_EVENT_RELEASE;
1395 if ((rdev->family > CHIP_R600))
1396 tmp |= ENABLE_NEW_SMX_ADDRESS;
1397 WREG32(SX_DEBUG_1, tmp);
1398
1399 if (((rdev->family) == CHIP_R600) ||
1400 ((rdev->family) == CHIP_RV630) ||
1401 ((rdev->family) == CHIP_RV610) ||
1402 ((rdev->family) == CHIP_RV620) ||
1403 ((rdev->family) == CHIP_RS780) ||
1404 ((rdev->family) == CHIP_RS880)) {
1405 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1406 } else {
1407 WREG32(DB_DEBUG, 0);
1408 }
1409 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1410 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1411
1412 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1413 WREG32(VGT_NUM_INSTANCES, 0);
1414
1415 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1416 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1417
1418 tmp = RREG32(SQ_MS_FIFO_SIZES);
1419 if (((rdev->family) == CHIP_RV610) ||
1420 ((rdev->family) == CHIP_RV620) ||
1421 ((rdev->family) == CHIP_RS780) ||
1422 ((rdev->family) == CHIP_RS880)) {
1423 tmp = (CACHE_FIFO_SIZE(0xa) |
1424 FETCH_FIFO_HIWATER(0xa) |
1425 DONE_FIFO_HIWATER(0xe0) |
1426 ALU_UPDATE_FIFO_HIWATER(0x8));
1427 } else if (((rdev->family) == CHIP_R600) ||
1428 ((rdev->family) == CHIP_RV630)) {
1429 tmp &= ~DONE_FIFO_HIWATER(0xff);
1430 tmp |= DONE_FIFO_HIWATER(0x4);
1431 }
1432 WREG32(SQ_MS_FIFO_SIZES, tmp);
1433
1434 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1435 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1436 */
1437 sq_config = RREG32(SQ_CONFIG);
1438 sq_config &= ~(PS_PRIO(3) |
1439 VS_PRIO(3) |
1440 GS_PRIO(3) |
1441 ES_PRIO(3));
1442 sq_config |= (DX9_CONSTS |
1443 VC_ENABLE |
1444 PS_PRIO(0) |
1445 VS_PRIO(1) |
1446 GS_PRIO(2) |
1447 ES_PRIO(3));
1448
1449 if ((rdev->family) == CHIP_R600) {
1450 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1451 NUM_VS_GPRS(124) |
1452 NUM_CLAUSE_TEMP_GPRS(4));
1453 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1454 NUM_ES_GPRS(0));
1455 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1456 NUM_VS_THREADS(48) |
1457 NUM_GS_THREADS(4) |
1458 NUM_ES_THREADS(4));
1459 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1460 NUM_VS_STACK_ENTRIES(128));
1461 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1462 NUM_ES_STACK_ENTRIES(0));
1463 } else if (((rdev->family) == CHIP_RV610) ||
1464 ((rdev->family) == CHIP_RV620) ||
1465 ((rdev->family) == CHIP_RS780) ||
1466 ((rdev->family) == CHIP_RS880)) {
1467 /* no vertex cache */
1468 sq_config &= ~VC_ENABLE;
1469
1470 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1471 NUM_VS_GPRS(44) |
1472 NUM_CLAUSE_TEMP_GPRS(2));
1473 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1474 NUM_ES_GPRS(17));
1475 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1476 NUM_VS_THREADS(78) |
1477 NUM_GS_THREADS(4) |
1478 NUM_ES_THREADS(31));
1479 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1480 NUM_VS_STACK_ENTRIES(40));
1481 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1482 NUM_ES_STACK_ENTRIES(16));
1483 } else if (((rdev->family) == CHIP_RV630) ||
1484 ((rdev->family) == CHIP_RV635)) {
1485 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1486 NUM_VS_GPRS(44) |
1487 NUM_CLAUSE_TEMP_GPRS(2));
1488 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1489 NUM_ES_GPRS(18));
1490 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1491 NUM_VS_THREADS(78) |
1492 NUM_GS_THREADS(4) |
1493 NUM_ES_THREADS(31));
1494 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1495 NUM_VS_STACK_ENTRIES(40));
1496 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1497 NUM_ES_STACK_ENTRIES(16));
1498 } else if ((rdev->family) == CHIP_RV670) {
1499 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1500 NUM_VS_GPRS(44) |
1501 NUM_CLAUSE_TEMP_GPRS(2));
1502 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1503 NUM_ES_GPRS(17));
1504 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1505 NUM_VS_THREADS(78) |
1506 NUM_GS_THREADS(4) |
1507 NUM_ES_THREADS(31));
1508 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1509 NUM_VS_STACK_ENTRIES(64));
1510 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1511 NUM_ES_STACK_ENTRIES(64));
1512 }
1513
1514 WREG32(SQ_CONFIG, sq_config);
1515 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1516 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1517 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1518 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1519 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1520
1521 if (((rdev->family) == CHIP_RV610) ||
1522 ((rdev->family) == CHIP_RV620) ||
1523 ((rdev->family) == CHIP_RS780) ||
1524 ((rdev->family) == CHIP_RS880)) {
1525 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1526 } else {
1527 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1528 }
1529
1530 /* More default values. 2D/3D driver should adjust as needed */
1531 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1532 S1_X(0x4) | S1_Y(0xc)));
1533 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1534 S1_X(0x2) | S1_Y(0x2) |
1535 S2_X(0xa) | S2_Y(0x6) |
1536 S3_X(0x6) | S3_Y(0xa)));
1537 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1538 S1_X(0x4) | S1_Y(0xc) |
1539 S2_X(0x1) | S2_Y(0x6) |
1540 S3_X(0xa) | S3_Y(0xe)));
1541 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1542 S5_X(0x0) | S5_Y(0x0) |
1543 S6_X(0xb) | S6_Y(0x4) |
1544 S7_X(0x7) | S7_Y(0x8)));
1545
1546 WREG32(VGT_STRMOUT_EN, 0);
1547 tmp = rdev->config.r600.max_pipes * 16;
1548 switch (rdev->family) {
1549 case CHIP_RV610:
1550 case CHIP_RV620:
1551 case CHIP_RS780:
1552 case CHIP_RS880:
1553 tmp += 32;
1554 break;
1555 case CHIP_RV670:
1556 tmp += 128;
1557 break;
1558 default:
1559 break;
1560 }
1561 if (tmp > 256) {
1562 tmp = 256;
1563 }
1564 WREG32(VGT_ES_PER_GS, 128);
1565 WREG32(VGT_GS_PER_ES, tmp);
1566 WREG32(VGT_GS_PER_VS, 2);
1567 WREG32(VGT_GS_VERTEX_REUSE, 16);
1568
1569 /* more default values. 2D/3D driver should adjust as needed */
1570 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1571 WREG32(VGT_STRMOUT_EN, 0);
1572 WREG32(SX_MISC, 0);
1573 WREG32(PA_SC_MODE_CNTL, 0);
1574 WREG32(PA_SC_AA_CONFIG, 0);
1575 WREG32(PA_SC_LINE_STIPPLE, 0);
1576 WREG32(SPI_INPUT_Z, 0);
1577 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1578 WREG32(CB_COLOR7_FRAG, 0);
1579
1580 /* Clear render buffer base addresses */
1581 WREG32(CB_COLOR0_BASE, 0);
1582 WREG32(CB_COLOR1_BASE, 0);
1583 WREG32(CB_COLOR2_BASE, 0);
1584 WREG32(CB_COLOR3_BASE, 0);
1585 WREG32(CB_COLOR4_BASE, 0);
1586 WREG32(CB_COLOR5_BASE, 0);
1587 WREG32(CB_COLOR6_BASE, 0);
1588 WREG32(CB_COLOR7_BASE, 0);
1589 WREG32(CB_COLOR7_FRAG, 0);
1590
1591 switch (rdev->family) {
1592 case CHIP_RV610:
1593 case CHIP_RV620:
1594 case CHIP_RS780:
1595 case CHIP_RS880:
1596 tmp = TC_L2_SIZE(8);
1597 break;
1598 case CHIP_RV630:
1599 case CHIP_RV635:
1600 tmp = TC_L2_SIZE(4);
1601 break;
1602 case CHIP_R600:
1603 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1604 break;
1605 default:
1606 tmp = TC_L2_SIZE(0);
1607 break;
1608 }
1609 WREG32(TC_CNTL, tmp);
1610
1611 tmp = RREG32(HDP_HOST_PATH_CNTL);
1612 WREG32(HDP_HOST_PATH_CNTL, tmp);
1613
1614 tmp = RREG32(ARB_POP);
1615 tmp |= ENABLE_TC128;
1616 WREG32(ARB_POP, tmp);
1617
1618 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1619 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1620 NUM_CLIP_SEQ(3)));
1621 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1622 }
1623
1624
1625 /*
1626 * Indirect registers accessor
1627 */
1628 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1629 {
1630 u32 r;
1631
1632 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1633 (void)RREG32(PCIE_PORT_INDEX);
1634 r = RREG32(PCIE_PORT_DATA);
1635 return r;
1636 }
1637
1638 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1639 {
1640 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1641 (void)RREG32(PCIE_PORT_INDEX);
1642 WREG32(PCIE_PORT_DATA, (v));
1643 (void)RREG32(PCIE_PORT_DATA);
1644 }
1645
1646 /*
1647 * CP & Ring
1648 */
1649 void r600_cp_stop(struct radeon_device *rdev)
1650 {
1651 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1652 }
1653
1654 int r600_init_microcode(struct radeon_device *rdev)
1655 {
1656 struct platform_device *pdev;
1657 const char *chip_name;
1658 const char *rlc_chip_name;
1659 size_t pfp_req_size, me_req_size, rlc_req_size;
1660 char fw_name[30];
1661 int err;
1662
1663 DRM_DEBUG("\n");
1664
1665 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1666 err = IS_ERR(pdev);
1667 if (err) {
1668 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1669 return -EINVAL;
1670 }
1671
1672 switch (rdev->family) {
1673 case CHIP_R600:
1674 chip_name = "R600";
1675 rlc_chip_name = "R600";
1676 break;
1677 case CHIP_RV610:
1678 chip_name = "RV610";
1679 rlc_chip_name = "R600";
1680 break;
1681 case CHIP_RV630:
1682 chip_name = "RV630";
1683 rlc_chip_name = "R600";
1684 break;
1685 case CHIP_RV620:
1686 chip_name = "RV620";
1687 rlc_chip_name = "R600";
1688 break;
1689 case CHIP_RV635:
1690 chip_name = "RV635";
1691 rlc_chip_name = "R600";
1692 break;
1693 case CHIP_RV670:
1694 chip_name = "RV670";
1695 rlc_chip_name = "R600";
1696 break;
1697 case CHIP_RS780:
1698 case CHIP_RS880:
1699 chip_name = "RS780";
1700 rlc_chip_name = "R600";
1701 break;
1702 case CHIP_RV770:
1703 chip_name = "RV770";
1704 rlc_chip_name = "R700";
1705 break;
1706 case CHIP_RV730:
1707 case CHIP_RV740:
1708 chip_name = "RV730";
1709 rlc_chip_name = "R700";
1710 break;
1711 case CHIP_RV710:
1712 chip_name = "RV710";
1713 rlc_chip_name = "R700";
1714 break;
1715 case CHIP_CEDAR:
1716 chip_name = "CEDAR";
1717 rlc_chip_name = "CEDAR";
1718 break;
1719 case CHIP_REDWOOD:
1720 chip_name = "REDWOOD";
1721 rlc_chip_name = "REDWOOD";
1722 break;
1723 case CHIP_JUNIPER:
1724 chip_name = "JUNIPER";
1725 rlc_chip_name = "JUNIPER";
1726 break;
1727 case CHIP_CYPRESS:
1728 case CHIP_HEMLOCK:
1729 chip_name = "CYPRESS";
1730 rlc_chip_name = "CYPRESS";
1731 break;
1732 default: BUG();
1733 }
1734
1735 if (rdev->family >= CHIP_CEDAR) {
1736 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1737 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1738 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1739 } else if (rdev->family >= CHIP_RV770) {
1740 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1741 me_req_size = R700_PM4_UCODE_SIZE * 4;
1742 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1743 } else {
1744 pfp_req_size = PFP_UCODE_SIZE * 4;
1745 me_req_size = PM4_UCODE_SIZE * 12;
1746 rlc_req_size = RLC_UCODE_SIZE * 4;
1747 }
1748
1749 DRM_INFO("Loading %s Microcode\n", chip_name);
1750
1751 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1752 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1753 if (err)
1754 goto out;
1755 if (rdev->pfp_fw->size != pfp_req_size) {
1756 printk(KERN_ERR
1757 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1758 rdev->pfp_fw->size, fw_name);
1759 err = -EINVAL;
1760 goto out;
1761 }
1762
1763 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1764 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1765 if (err)
1766 goto out;
1767 if (rdev->me_fw->size != me_req_size) {
1768 printk(KERN_ERR
1769 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1770 rdev->me_fw->size, fw_name);
1771 err = -EINVAL;
1772 }
1773
1774 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1775 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1776 if (err)
1777 goto out;
1778 if (rdev->rlc_fw->size != rlc_req_size) {
1779 printk(KERN_ERR
1780 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1781 rdev->rlc_fw->size, fw_name);
1782 err = -EINVAL;
1783 }
1784
1785 out:
1786 platform_device_unregister(pdev);
1787
1788 if (err) {
1789 if (err != -EINVAL)
1790 printk(KERN_ERR
1791 "r600_cp: Failed to load firmware \"%s\"\n",
1792 fw_name);
1793 release_firmware(rdev->pfp_fw);
1794 rdev->pfp_fw = NULL;
1795 release_firmware(rdev->me_fw);
1796 rdev->me_fw = NULL;
1797 release_firmware(rdev->rlc_fw);
1798 rdev->rlc_fw = NULL;
1799 }
1800 return err;
1801 }
1802
1803 static int r600_cp_load_microcode(struct radeon_device *rdev)
1804 {
1805 const __be32 *fw_data;
1806 int i;
1807
1808 if (!rdev->me_fw || !rdev->pfp_fw)
1809 return -EINVAL;
1810
1811 r600_cp_stop(rdev);
1812
1813 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1814
1815 /* Reset cp */
1816 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1817 RREG32(GRBM_SOFT_RESET);
1818 mdelay(15);
1819 WREG32(GRBM_SOFT_RESET, 0);
1820
1821 WREG32(CP_ME_RAM_WADDR, 0);
1822
1823 fw_data = (const __be32 *)rdev->me_fw->data;
1824 WREG32(CP_ME_RAM_WADDR, 0);
1825 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1826 WREG32(CP_ME_RAM_DATA,
1827 be32_to_cpup(fw_data++));
1828
1829 fw_data = (const __be32 *)rdev->pfp_fw->data;
1830 WREG32(CP_PFP_UCODE_ADDR, 0);
1831 for (i = 0; i < PFP_UCODE_SIZE; i++)
1832 WREG32(CP_PFP_UCODE_DATA,
1833 be32_to_cpup(fw_data++));
1834
1835 WREG32(CP_PFP_UCODE_ADDR, 0);
1836 WREG32(CP_ME_RAM_WADDR, 0);
1837 WREG32(CP_ME_RAM_RADDR, 0);
1838 return 0;
1839 }
1840
1841 int r600_cp_start(struct radeon_device *rdev)
1842 {
1843 int r;
1844 uint32_t cp_me;
1845
1846 r = radeon_ring_lock(rdev, 7);
1847 if (r) {
1848 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1849 return r;
1850 }
1851 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1852 radeon_ring_write(rdev, 0x1);
1853 if (rdev->family >= CHIP_CEDAR) {
1854 radeon_ring_write(rdev, 0x0);
1855 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1856 } else if (rdev->family >= CHIP_RV770) {
1857 radeon_ring_write(rdev, 0x0);
1858 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1859 } else {
1860 radeon_ring_write(rdev, 0x3);
1861 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1862 }
1863 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1864 radeon_ring_write(rdev, 0);
1865 radeon_ring_write(rdev, 0);
1866 radeon_ring_unlock_commit(rdev);
1867
1868 cp_me = 0xff;
1869 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1870 return 0;
1871 }
1872
1873 int r600_cp_resume(struct radeon_device *rdev)
1874 {
1875 u32 tmp;
1876 u32 rb_bufsz;
1877 int r;
1878
1879 /* Reset cp */
1880 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1881 RREG32(GRBM_SOFT_RESET);
1882 mdelay(15);
1883 WREG32(GRBM_SOFT_RESET, 0);
1884
1885 /* Set ring buffer size */
1886 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1887 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1888 #ifdef __BIG_ENDIAN
1889 tmp |= BUF_SWAP_32BIT;
1890 #endif
1891 WREG32(CP_RB_CNTL, tmp);
1892 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1893
1894 /* Set the write pointer delay */
1895 WREG32(CP_RB_WPTR_DELAY, 0);
1896
1897 /* Initialize the ring buffer's read and write pointers */
1898 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1899 WREG32(CP_RB_RPTR_WR, 0);
1900 WREG32(CP_RB_WPTR, 0);
1901 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1902 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1903 mdelay(1);
1904 WREG32(CP_RB_CNTL, tmp);
1905
1906 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1907 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1908
1909 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1910 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1911
1912 r600_cp_start(rdev);
1913 rdev->cp.ready = true;
1914 r = radeon_ring_test(rdev);
1915 if (r) {
1916 rdev->cp.ready = false;
1917 return r;
1918 }
1919 return 0;
1920 }
1921
1922 void r600_cp_commit(struct radeon_device *rdev)
1923 {
1924 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1925 (void)RREG32(CP_RB_WPTR);
1926 }
1927
1928 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1929 {
1930 u32 rb_bufsz;
1931
1932 /* Align ring size */
1933 rb_bufsz = drm_order(ring_size / 8);
1934 ring_size = (1 << (rb_bufsz + 1)) * 4;
1935 rdev->cp.ring_size = ring_size;
1936 rdev->cp.align_mask = 16 - 1;
1937 }
1938
1939 void r600_cp_fini(struct radeon_device *rdev)
1940 {
1941 r600_cp_stop(rdev);
1942 radeon_ring_fini(rdev);
1943 }
1944
1945
1946 /*
1947 * GPU scratch registers helpers function.
1948 */
1949 void r600_scratch_init(struct radeon_device *rdev)
1950 {
1951 int i;
1952
1953 rdev->scratch.num_reg = 7;
1954 for (i = 0; i < rdev->scratch.num_reg; i++) {
1955 rdev->scratch.free[i] = true;
1956 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1957 }
1958 }
1959
1960 int r600_ring_test(struct radeon_device *rdev)
1961 {
1962 uint32_t scratch;
1963 uint32_t tmp = 0;
1964 unsigned i;
1965 int r;
1966
1967 r = radeon_scratch_get(rdev, &scratch);
1968 if (r) {
1969 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1970 return r;
1971 }
1972 WREG32(scratch, 0xCAFEDEAD);
1973 r = radeon_ring_lock(rdev, 3);
1974 if (r) {
1975 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1976 radeon_scratch_free(rdev, scratch);
1977 return r;
1978 }
1979 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1980 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1981 radeon_ring_write(rdev, 0xDEADBEEF);
1982 radeon_ring_unlock_commit(rdev);
1983 for (i = 0; i < rdev->usec_timeout; i++) {
1984 tmp = RREG32(scratch);
1985 if (tmp == 0xDEADBEEF)
1986 break;
1987 DRM_UDELAY(1);
1988 }
1989 if (i < rdev->usec_timeout) {
1990 DRM_INFO("ring test succeeded in %d usecs\n", i);
1991 } else {
1992 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1993 scratch, tmp);
1994 r = -EINVAL;
1995 }
1996 radeon_scratch_free(rdev, scratch);
1997 return r;
1998 }
1999
2000 void r600_wb_disable(struct radeon_device *rdev)
2001 {
2002 int r;
2003
2004 WREG32(SCRATCH_UMSK, 0);
2005 if (rdev->wb.wb_obj) {
2006 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2007 if (unlikely(r != 0))
2008 return;
2009 radeon_bo_kunmap(rdev->wb.wb_obj);
2010 radeon_bo_unpin(rdev->wb.wb_obj);
2011 radeon_bo_unreserve(rdev->wb.wb_obj);
2012 }
2013 }
2014
2015 void r600_wb_fini(struct radeon_device *rdev)
2016 {
2017 r600_wb_disable(rdev);
2018 if (rdev->wb.wb_obj) {
2019 radeon_bo_unref(&rdev->wb.wb_obj);
2020 rdev->wb.wb = NULL;
2021 rdev->wb.wb_obj = NULL;
2022 }
2023 }
2024
2025 int r600_wb_enable(struct radeon_device *rdev)
2026 {
2027 int r;
2028
2029 if (rdev->wb.wb_obj == NULL) {
2030 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2031 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2032 if (r) {
2033 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2034 return r;
2035 }
2036 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2037 if (unlikely(r != 0)) {
2038 r600_wb_fini(rdev);
2039 return r;
2040 }
2041 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2042 &rdev->wb.gpu_addr);
2043 if (r) {
2044 radeon_bo_unreserve(rdev->wb.wb_obj);
2045 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2046 r600_wb_fini(rdev);
2047 return r;
2048 }
2049 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2050 radeon_bo_unreserve(rdev->wb.wb_obj);
2051 if (r) {
2052 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2053 r600_wb_fini(rdev);
2054 return r;
2055 }
2056 }
2057 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2058 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2059 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2060 WREG32(SCRATCH_UMSK, 0xff);
2061 return 0;
2062 }
2063
2064 void r600_fence_ring_emit(struct radeon_device *rdev,
2065 struct radeon_fence *fence)
2066 {
2067 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
2068
2069 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2070 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2071 /* wait for 3D idle clean */
2072 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2073 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2074 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2075 /* Emit fence sequence & fire IRQ */
2076 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2077 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2078 radeon_ring_write(rdev, fence->seq);
2079 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2080 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2081 radeon_ring_write(rdev, RB_INT_STAT);
2082 }
2083
2084 int r600_copy_blit(struct radeon_device *rdev,
2085 uint64_t src_offset, uint64_t dst_offset,
2086 unsigned num_pages, struct radeon_fence *fence)
2087 {
2088 int r;
2089
2090 mutex_lock(&rdev->r600_blit.mutex);
2091 rdev->r600_blit.vb_ib = NULL;
2092 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2093 if (r) {
2094 if (rdev->r600_blit.vb_ib)
2095 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2096 mutex_unlock(&rdev->r600_blit.mutex);
2097 return r;
2098 }
2099 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2100 r600_blit_done_copy(rdev, fence);
2101 mutex_unlock(&rdev->r600_blit.mutex);
2102 return 0;
2103 }
2104
2105 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2106 uint32_t tiling_flags, uint32_t pitch,
2107 uint32_t offset, uint32_t obj_size)
2108 {
2109 /* FIXME: implement */
2110 return 0;
2111 }
2112
2113 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2114 {
2115 /* FIXME: implement */
2116 }
2117
2118
2119 bool r600_card_posted(struct radeon_device *rdev)
2120 {
2121 uint32_t reg;
2122
2123 /* first check CRTCs */
2124 reg = RREG32(D1CRTC_CONTROL) |
2125 RREG32(D2CRTC_CONTROL);
2126 if (reg & CRTC_EN)
2127 return true;
2128
2129 /* then check MEM_SIZE, in case the crtcs are off */
2130 if (RREG32(CONFIG_MEMSIZE))
2131 return true;
2132
2133 return false;
2134 }
2135
2136 int r600_startup(struct radeon_device *rdev)
2137 {
2138 int r;
2139
2140 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2141 r = r600_init_microcode(rdev);
2142 if (r) {
2143 DRM_ERROR("Failed to load firmware!\n");
2144 return r;
2145 }
2146 }
2147
2148 r600_mc_program(rdev);
2149 if (rdev->flags & RADEON_IS_AGP) {
2150 r600_agp_enable(rdev);
2151 } else {
2152 r = r600_pcie_gart_enable(rdev);
2153 if (r)
2154 return r;
2155 }
2156 r600_gpu_init(rdev);
2157 r = r600_blit_init(rdev);
2158 if (r) {
2159 r600_blit_fini(rdev);
2160 rdev->asic->copy = NULL;
2161 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2162 }
2163 /* pin copy shader into vram */
2164 if (rdev->r600_blit.shader_obj) {
2165 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2166 if (unlikely(r != 0))
2167 return r;
2168 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2169 &rdev->r600_blit.shader_gpu_addr);
2170 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2171 if (r) {
2172 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2173 return r;
2174 }
2175 }
2176 /* Enable IRQ */
2177 r = r600_irq_init(rdev);
2178 if (r) {
2179 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2180 radeon_irq_kms_fini(rdev);
2181 return r;
2182 }
2183 r600_irq_set(rdev);
2184
2185 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2186 if (r)
2187 return r;
2188 r = r600_cp_load_microcode(rdev);
2189 if (r)
2190 return r;
2191 r = r600_cp_resume(rdev);
2192 if (r)
2193 return r;
2194 /* write back buffer are not vital so don't worry about failure */
2195 r600_wb_enable(rdev);
2196 return 0;
2197 }
2198
2199 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2200 {
2201 uint32_t temp;
2202
2203 temp = RREG32(CONFIG_CNTL);
2204 if (state == false) {
2205 temp &= ~(1<<0);
2206 temp |= (1<<1);
2207 } else {
2208 temp &= ~(1<<1);
2209 }
2210 WREG32(CONFIG_CNTL, temp);
2211 }
2212
2213 int r600_resume(struct radeon_device *rdev)
2214 {
2215 int r;
2216
2217 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2218 * posting will perform necessary task to bring back GPU into good
2219 * shape.
2220 */
2221 /* post card */
2222 atom_asic_init(rdev->mode_info.atom_context);
2223 /* Initialize clocks */
2224 r = radeon_clocks_init(rdev);
2225 if (r) {
2226 return r;
2227 }
2228
2229 r = r600_startup(rdev);
2230 if (r) {
2231 DRM_ERROR("r600 startup failed on resume\n");
2232 return r;
2233 }
2234
2235 r = r600_ib_test(rdev);
2236 if (r) {
2237 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2238 return r;
2239 }
2240
2241 r = r600_audio_init(rdev);
2242 if (r) {
2243 DRM_ERROR("radeon: audio resume failed\n");
2244 return r;
2245 }
2246
2247 return r;
2248 }
2249
2250 int r600_suspend(struct radeon_device *rdev)
2251 {
2252 int r;
2253
2254 r600_audio_fini(rdev);
2255 /* FIXME: we should wait for ring to be empty */
2256 r600_cp_stop(rdev);
2257 rdev->cp.ready = false;
2258 r600_irq_suspend(rdev);
2259 r600_wb_disable(rdev);
2260 r600_pcie_gart_disable(rdev);
2261 /* unpin shaders bo */
2262 if (rdev->r600_blit.shader_obj) {
2263 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2264 if (!r) {
2265 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2266 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2267 }
2268 }
2269 return 0;
2270 }
2271
2272 /* Plan is to move initialization in that function and use
2273 * helper function so that radeon_device_init pretty much
2274 * do nothing more than calling asic specific function. This
2275 * should also allow to remove a bunch of callback function
2276 * like vram_info.
2277 */
2278 int r600_init(struct radeon_device *rdev)
2279 {
2280 int r;
2281
2282 r = radeon_dummy_page_init(rdev);
2283 if (r)
2284 return r;
2285 if (r600_debugfs_mc_info_init(rdev)) {
2286 DRM_ERROR("Failed to register debugfs file for mc !\n");
2287 }
2288 /* This don't do much */
2289 r = radeon_gem_init(rdev);
2290 if (r)
2291 return r;
2292 /* Read BIOS */
2293 if (!radeon_get_bios(rdev)) {
2294 if (ASIC_IS_AVIVO(rdev))
2295 return -EINVAL;
2296 }
2297 /* Must be an ATOMBIOS */
2298 if (!rdev->is_atom_bios) {
2299 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2300 return -EINVAL;
2301 }
2302 r = radeon_atombios_init(rdev);
2303 if (r)
2304 return r;
2305 /* Post card if necessary */
2306 if (!r600_card_posted(rdev)) {
2307 if (!rdev->bios) {
2308 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2309 return -EINVAL;
2310 }
2311 DRM_INFO("GPU not posted. posting now...\n");
2312 atom_asic_init(rdev->mode_info.atom_context);
2313 }
2314 /* Initialize scratch registers */
2315 r600_scratch_init(rdev);
2316 /* Initialize surface registers */
2317 radeon_surface_init(rdev);
2318 /* Initialize clocks */
2319 radeon_get_clock_info(rdev->ddev);
2320 r = radeon_clocks_init(rdev);
2321 if (r)
2322 return r;
2323 /* Initialize power management */
2324 radeon_pm_init(rdev);
2325 /* Fence driver */
2326 r = radeon_fence_driver_init(rdev);
2327 if (r)
2328 return r;
2329 if (rdev->flags & RADEON_IS_AGP) {
2330 r = radeon_agp_init(rdev);
2331 if (r)
2332 radeon_agp_disable(rdev);
2333 }
2334 r = r600_mc_init(rdev);
2335 if (r)
2336 return r;
2337 /* Memory manager */
2338 r = radeon_bo_init(rdev);
2339 if (r)
2340 return r;
2341
2342 r = radeon_irq_kms_init(rdev);
2343 if (r)
2344 return r;
2345
2346 rdev->cp.ring_obj = NULL;
2347 r600_ring_init(rdev, 1024 * 1024);
2348
2349 rdev->ih.ring_obj = NULL;
2350 r600_ih_ring_init(rdev, 64 * 1024);
2351
2352 r = r600_pcie_gart_init(rdev);
2353 if (r)
2354 return r;
2355
2356 rdev->accel_working = true;
2357 r = r600_startup(rdev);
2358 if (r) {
2359 dev_err(rdev->dev, "disabling GPU acceleration\n");
2360 r600_cp_fini(rdev);
2361 r600_wb_fini(rdev);
2362 r600_irq_fini(rdev);
2363 radeon_irq_kms_fini(rdev);
2364 r600_pcie_gart_fini(rdev);
2365 rdev->accel_working = false;
2366 }
2367 if (rdev->accel_working) {
2368 r = radeon_ib_pool_init(rdev);
2369 if (r) {
2370 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2371 rdev->accel_working = false;
2372 } else {
2373 r = r600_ib_test(rdev);
2374 if (r) {
2375 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2376 rdev->accel_working = false;
2377 }
2378 }
2379 }
2380
2381 r = r600_audio_init(rdev);
2382 if (r)
2383 return r; /* TODO error handling */
2384 return 0;
2385 }
2386
2387 void r600_fini(struct radeon_device *rdev)
2388 {
2389 radeon_pm_fini(rdev);
2390 r600_audio_fini(rdev);
2391 r600_blit_fini(rdev);
2392 r600_cp_fini(rdev);
2393 r600_wb_fini(rdev);
2394 r600_irq_fini(rdev);
2395 radeon_irq_kms_fini(rdev);
2396 r600_pcie_gart_fini(rdev);
2397 radeon_agp_fini(rdev);
2398 radeon_gem_fini(rdev);
2399 radeon_fence_driver_fini(rdev);
2400 radeon_clocks_fini(rdev);
2401 radeon_bo_fini(rdev);
2402 radeon_atombios_fini(rdev);
2403 kfree(rdev->bios);
2404 rdev->bios = NULL;
2405 radeon_dummy_page_fini(rdev);
2406 }
2407
2408
2409 /*
2410 * CS stuff
2411 */
2412 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2413 {
2414 /* FIXME: implement */
2415 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2416 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2417 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2418 radeon_ring_write(rdev, ib->length_dw);
2419 }
2420
2421 int r600_ib_test(struct radeon_device *rdev)
2422 {
2423 struct radeon_ib *ib;
2424 uint32_t scratch;
2425 uint32_t tmp = 0;
2426 unsigned i;
2427 int r;
2428
2429 r = radeon_scratch_get(rdev, &scratch);
2430 if (r) {
2431 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2432 return r;
2433 }
2434 WREG32(scratch, 0xCAFEDEAD);
2435 r = radeon_ib_get(rdev, &ib);
2436 if (r) {
2437 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2438 return r;
2439 }
2440 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2441 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2442 ib->ptr[2] = 0xDEADBEEF;
2443 ib->ptr[3] = PACKET2(0);
2444 ib->ptr[4] = PACKET2(0);
2445 ib->ptr[5] = PACKET2(0);
2446 ib->ptr[6] = PACKET2(0);
2447 ib->ptr[7] = PACKET2(0);
2448 ib->ptr[8] = PACKET2(0);
2449 ib->ptr[9] = PACKET2(0);
2450 ib->ptr[10] = PACKET2(0);
2451 ib->ptr[11] = PACKET2(0);
2452 ib->ptr[12] = PACKET2(0);
2453 ib->ptr[13] = PACKET2(0);
2454 ib->ptr[14] = PACKET2(0);
2455 ib->ptr[15] = PACKET2(0);
2456 ib->length_dw = 16;
2457 r = radeon_ib_schedule(rdev, ib);
2458 if (r) {
2459 radeon_scratch_free(rdev, scratch);
2460 radeon_ib_free(rdev, &ib);
2461 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2462 return r;
2463 }
2464 r = radeon_fence_wait(ib->fence, false);
2465 if (r) {
2466 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2467 return r;
2468 }
2469 for (i = 0; i < rdev->usec_timeout; i++) {
2470 tmp = RREG32(scratch);
2471 if (tmp == 0xDEADBEEF)
2472 break;
2473 DRM_UDELAY(1);
2474 }
2475 if (i < rdev->usec_timeout) {
2476 DRM_INFO("ib test succeeded in %u usecs\n", i);
2477 } else {
2478 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2479 scratch, tmp);
2480 r = -EINVAL;
2481 }
2482 radeon_scratch_free(rdev, scratch);
2483 radeon_ib_free(rdev, &ib);
2484 return r;
2485 }
2486
2487 /*
2488 * Interrupts
2489 *
2490 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2491 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2492 * writing to the ring and the GPU consuming, the GPU writes to the ring
2493 * and host consumes. As the host irq handler processes interrupts, it
2494 * increments the rptr. When the rptr catches up with the wptr, all the
2495 * current interrupts have been processed.
2496 */
2497
2498 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2499 {
2500 u32 rb_bufsz;
2501
2502 /* Align ring size */
2503 rb_bufsz = drm_order(ring_size / 4);
2504 ring_size = (1 << rb_bufsz) * 4;
2505 rdev->ih.ring_size = ring_size;
2506 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2507 rdev->ih.rptr = 0;
2508 }
2509
2510 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2511 {
2512 int r;
2513
2514 /* Allocate ring buffer */
2515 if (rdev->ih.ring_obj == NULL) {
2516 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2517 true,
2518 RADEON_GEM_DOMAIN_GTT,
2519 &rdev->ih.ring_obj);
2520 if (r) {
2521 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2522 return r;
2523 }
2524 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2525 if (unlikely(r != 0))
2526 return r;
2527 r = radeon_bo_pin(rdev->ih.ring_obj,
2528 RADEON_GEM_DOMAIN_GTT,
2529 &rdev->ih.gpu_addr);
2530 if (r) {
2531 radeon_bo_unreserve(rdev->ih.ring_obj);
2532 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2533 return r;
2534 }
2535 r = radeon_bo_kmap(rdev->ih.ring_obj,
2536 (void **)&rdev->ih.ring);
2537 radeon_bo_unreserve(rdev->ih.ring_obj);
2538 if (r) {
2539 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2540 return r;
2541 }
2542 }
2543 return 0;
2544 }
2545
2546 static void r600_ih_ring_fini(struct radeon_device *rdev)
2547 {
2548 int r;
2549 if (rdev->ih.ring_obj) {
2550 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2551 if (likely(r == 0)) {
2552 radeon_bo_kunmap(rdev->ih.ring_obj);
2553 radeon_bo_unpin(rdev->ih.ring_obj);
2554 radeon_bo_unreserve(rdev->ih.ring_obj);
2555 }
2556 radeon_bo_unref(&rdev->ih.ring_obj);
2557 rdev->ih.ring = NULL;
2558 rdev->ih.ring_obj = NULL;
2559 }
2560 }
2561
2562 void r600_rlc_stop(struct radeon_device *rdev)
2563 {
2564
2565 if ((rdev->family >= CHIP_RV770) &&
2566 (rdev->family <= CHIP_RV740)) {
2567 /* r7xx asics need to soft reset RLC before halting */
2568 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2569 RREG32(SRBM_SOFT_RESET);
2570 udelay(15000);
2571 WREG32(SRBM_SOFT_RESET, 0);
2572 RREG32(SRBM_SOFT_RESET);
2573 }
2574
2575 WREG32(RLC_CNTL, 0);
2576 }
2577
2578 static void r600_rlc_start(struct radeon_device *rdev)
2579 {
2580 WREG32(RLC_CNTL, RLC_ENABLE);
2581 }
2582
2583 static int r600_rlc_init(struct radeon_device *rdev)
2584 {
2585 u32 i;
2586 const __be32 *fw_data;
2587
2588 if (!rdev->rlc_fw)
2589 return -EINVAL;
2590
2591 r600_rlc_stop(rdev);
2592
2593 WREG32(RLC_HB_BASE, 0);
2594 WREG32(RLC_HB_CNTL, 0);
2595 WREG32(RLC_HB_RPTR, 0);
2596 WREG32(RLC_HB_WPTR, 0);
2597 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2598 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2599 WREG32(RLC_MC_CNTL, 0);
2600 WREG32(RLC_UCODE_CNTL, 0);
2601
2602 fw_data = (const __be32 *)rdev->rlc_fw->data;
2603 if (rdev->family >= CHIP_CEDAR) {
2604 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2605 WREG32(RLC_UCODE_ADDR, i);
2606 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2607 }
2608 } else if (rdev->family >= CHIP_RV770) {
2609 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2610 WREG32(RLC_UCODE_ADDR, i);
2611 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2612 }
2613 } else {
2614 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2615 WREG32(RLC_UCODE_ADDR, i);
2616 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2617 }
2618 }
2619 WREG32(RLC_UCODE_ADDR, 0);
2620
2621 r600_rlc_start(rdev);
2622
2623 return 0;
2624 }
2625
2626 static void r600_enable_interrupts(struct radeon_device *rdev)
2627 {
2628 u32 ih_cntl = RREG32(IH_CNTL);
2629 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2630
2631 ih_cntl |= ENABLE_INTR;
2632 ih_rb_cntl |= IH_RB_ENABLE;
2633 WREG32(IH_CNTL, ih_cntl);
2634 WREG32(IH_RB_CNTL, ih_rb_cntl);
2635 rdev->ih.enabled = true;
2636 }
2637
2638 void r600_disable_interrupts(struct radeon_device *rdev)
2639 {
2640 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2641 u32 ih_cntl = RREG32(IH_CNTL);
2642
2643 ih_rb_cntl &= ~IH_RB_ENABLE;
2644 ih_cntl &= ~ENABLE_INTR;
2645 WREG32(IH_RB_CNTL, ih_rb_cntl);
2646 WREG32(IH_CNTL, ih_cntl);
2647 /* set rptr, wptr to 0 */
2648 WREG32(IH_RB_RPTR, 0);
2649 WREG32(IH_RB_WPTR, 0);
2650 rdev->ih.enabled = false;
2651 rdev->ih.wptr = 0;
2652 rdev->ih.rptr = 0;
2653 }
2654
2655 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2656 {
2657 u32 tmp;
2658
2659 WREG32(CP_INT_CNTL, 0);
2660 WREG32(GRBM_INT_CNTL, 0);
2661 WREG32(DxMODE_INT_MASK, 0);
2662 if (ASIC_IS_DCE3(rdev)) {
2663 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2664 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2665 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2666 WREG32(DC_HPD1_INT_CONTROL, tmp);
2667 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2668 WREG32(DC_HPD2_INT_CONTROL, tmp);
2669 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2670 WREG32(DC_HPD3_INT_CONTROL, tmp);
2671 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2672 WREG32(DC_HPD4_INT_CONTROL, tmp);
2673 if (ASIC_IS_DCE32(rdev)) {
2674 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2675 WREG32(DC_HPD5_INT_CONTROL, tmp);
2676 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2677 WREG32(DC_HPD6_INT_CONTROL, tmp);
2678 }
2679 } else {
2680 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2681 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2682 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2683 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2684 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2685 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2686 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2687 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2688 }
2689 }
2690
2691 int r600_irq_init(struct radeon_device *rdev)
2692 {
2693 int ret = 0;
2694 int rb_bufsz;
2695 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2696
2697 /* allocate ring */
2698 ret = r600_ih_ring_alloc(rdev);
2699 if (ret)
2700 return ret;
2701
2702 /* disable irqs */
2703 r600_disable_interrupts(rdev);
2704
2705 /* init rlc */
2706 ret = r600_rlc_init(rdev);
2707 if (ret) {
2708 r600_ih_ring_fini(rdev);
2709 return ret;
2710 }
2711
2712 /* setup interrupt control */
2713 /* set dummy read address to ring address */
2714 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2715 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2716 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2717 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2718 */
2719 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2720 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2721 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2722 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2723
2724 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2725 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2726
2727 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2728 IH_WPTR_OVERFLOW_CLEAR |
2729 (rb_bufsz << 1));
2730 /* WPTR writeback, not yet */
2731 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2732 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2733 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2734
2735 WREG32(IH_RB_CNTL, ih_rb_cntl);
2736
2737 /* set rptr, wptr to 0 */
2738 WREG32(IH_RB_RPTR, 0);
2739 WREG32(IH_RB_WPTR, 0);
2740
2741 /* Default settings for IH_CNTL (disabled at first) */
2742 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2743 /* RPTR_REARM only works if msi's are enabled */
2744 if (rdev->msi_enabled)
2745 ih_cntl |= RPTR_REARM;
2746
2747 #ifdef __BIG_ENDIAN
2748 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2749 #endif
2750 WREG32(IH_CNTL, ih_cntl);
2751
2752 /* force the active interrupt state to all disabled */
2753 if (rdev->family >= CHIP_CEDAR)
2754 evergreen_disable_interrupt_state(rdev);
2755 else
2756 r600_disable_interrupt_state(rdev);
2757
2758 /* enable irqs */
2759 r600_enable_interrupts(rdev);
2760
2761 return ret;
2762 }
2763
2764 void r600_irq_suspend(struct radeon_device *rdev)
2765 {
2766 r600_irq_disable(rdev);
2767 r600_rlc_stop(rdev);
2768 }
2769
2770 void r600_irq_fini(struct radeon_device *rdev)
2771 {
2772 r600_irq_suspend(rdev);
2773 r600_ih_ring_fini(rdev);
2774 }
2775
2776 int r600_irq_set(struct radeon_device *rdev)
2777 {
2778 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2779 u32 mode_int = 0;
2780 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2781 u32 grbm_int_cntl = 0;
2782 u32 hdmi1, hdmi2;
2783
2784 if (!rdev->irq.installed) {
2785 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2786 return -EINVAL;
2787 }
2788 /* don't enable anything if the ih is disabled */
2789 if (!rdev->ih.enabled) {
2790 r600_disable_interrupts(rdev);
2791 /* force the active interrupt state to all disabled */
2792 r600_disable_interrupt_state(rdev);
2793 return 0;
2794 }
2795
2796 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2797 if (ASIC_IS_DCE3(rdev)) {
2798 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2799 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2800 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2801 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2802 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2803 if (ASIC_IS_DCE32(rdev)) {
2804 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2805 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2806 }
2807 } else {
2808 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2809 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2810 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2811 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2812 }
2813
2814 if (rdev->irq.sw_int) {
2815 DRM_DEBUG("r600_irq_set: sw int\n");
2816 cp_int_cntl |= RB_INT_ENABLE;
2817 }
2818 if (rdev->irq.crtc_vblank_int[0]) {
2819 DRM_DEBUG("r600_irq_set: vblank 0\n");
2820 mode_int |= D1MODE_VBLANK_INT_MASK;
2821 }
2822 if (rdev->irq.crtc_vblank_int[1]) {
2823 DRM_DEBUG("r600_irq_set: vblank 1\n");
2824 mode_int |= D2MODE_VBLANK_INT_MASK;
2825 }
2826 if (rdev->irq.hpd[0]) {
2827 DRM_DEBUG("r600_irq_set: hpd 1\n");
2828 hpd1 |= DC_HPDx_INT_EN;
2829 }
2830 if (rdev->irq.hpd[1]) {
2831 DRM_DEBUG("r600_irq_set: hpd 2\n");
2832 hpd2 |= DC_HPDx_INT_EN;
2833 }
2834 if (rdev->irq.hpd[2]) {
2835 DRM_DEBUG("r600_irq_set: hpd 3\n");
2836 hpd3 |= DC_HPDx_INT_EN;
2837 }
2838 if (rdev->irq.hpd[3]) {
2839 DRM_DEBUG("r600_irq_set: hpd 4\n");
2840 hpd4 |= DC_HPDx_INT_EN;
2841 }
2842 if (rdev->irq.hpd[4]) {
2843 DRM_DEBUG("r600_irq_set: hpd 5\n");
2844 hpd5 |= DC_HPDx_INT_EN;
2845 }
2846 if (rdev->irq.hpd[5]) {
2847 DRM_DEBUG("r600_irq_set: hpd 6\n");
2848 hpd6 |= DC_HPDx_INT_EN;
2849 }
2850 if (rdev->irq.hdmi[0]) {
2851 DRM_DEBUG("r600_irq_set: hdmi 1\n");
2852 hdmi1 |= R600_HDMI_INT_EN;
2853 }
2854 if (rdev->irq.hdmi[1]) {
2855 DRM_DEBUG("r600_irq_set: hdmi 2\n");
2856 hdmi2 |= R600_HDMI_INT_EN;
2857 }
2858 if (rdev->irq.gui_idle) {
2859 DRM_DEBUG("gui idle\n");
2860 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2861 }
2862
2863 WREG32(CP_INT_CNTL, cp_int_cntl);
2864 WREG32(DxMODE_INT_MASK, mode_int);
2865 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2866 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
2867 if (ASIC_IS_DCE3(rdev)) {
2868 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
2869 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2870 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2871 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2872 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2873 if (ASIC_IS_DCE32(rdev)) {
2874 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2875 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2876 }
2877 } else {
2878 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
2879 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2880 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2881 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2882 }
2883
2884 return 0;
2885 }
2886
2887 static inline void r600_irq_ack(struct radeon_device *rdev,
2888 u32 *disp_int,
2889 u32 *disp_int_cont,
2890 u32 *disp_int_cont2)
2891 {
2892 u32 tmp;
2893
2894 if (ASIC_IS_DCE3(rdev)) {
2895 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2896 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2897 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2898 } else {
2899 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2900 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2901 *disp_int_cont2 = 0;
2902 }
2903
2904 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2905 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2906 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2907 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2908 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2909 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2910 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2911 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2912 if (*disp_int & DC_HPD1_INTERRUPT) {
2913 if (ASIC_IS_DCE3(rdev)) {
2914 tmp = RREG32(DC_HPD1_INT_CONTROL);
2915 tmp |= DC_HPDx_INT_ACK;
2916 WREG32(DC_HPD1_INT_CONTROL, tmp);
2917 } else {
2918 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2919 tmp |= DC_HPDx_INT_ACK;
2920 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2921 }
2922 }
2923 if (*disp_int & DC_HPD2_INTERRUPT) {
2924 if (ASIC_IS_DCE3(rdev)) {
2925 tmp = RREG32(DC_HPD2_INT_CONTROL);
2926 tmp |= DC_HPDx_INT_ACK;
2927 WREG32(DC_HPD2_INT_CONTROL, tmp);
2928 } else {
2929 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2930 tmp |= DC_HPDx_INT_ACK;
2931 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2932 }
2933 }
2934 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2935 if (ASIC_IS_DCE3(rdev)) {
2936 tmp = RREG32(DC_HPD3_INT_CONTROL);
2937 tmp |= DC_HPDx_INT_ACK;
2938 WREG32(DC_HPD3_INT_CONTROL, tmp);
2939 } else {
2940 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2941 tmp |= DC_HPDx_INT_ACK;
2942 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2943 }
2944 }
2945 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2946 tmp = RREG32(DC_HPD4_INT_CONTROL);
2947 tmp |= DC_HPDx_INT_ACK;
2948 WREG32(DC_HPD4_INT_CONTROL, tmp);
2949 }
2950 if (ASIC_IS_DCE32(rdev)) {
2951 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2952 tmp = RREG32(DC_HPD5_INT_CONTROL);
2953 tmp |= DC_HPDx_INT_ACK;
2954 WREG32(DC_HPD5_INT_CONTROL, tmp);
2955 }
2956 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2957 tmp = RREG32(DC_HPD5_INT_CONTROL);
2958 tmp |= DC_HPDx_INT_ACK;
2959 WREG32(DC_HPD6_INT_CONTROL, tmp);
2960 }
2961 }
2962 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2963 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2964 }
2965 if (ASIC_IS_DCE3(rdev)) {
2966 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2967 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2968 }
2969 } else {
2970 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2971 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2972 }
2973 }
2974 }
2975
2976 void r600_irq_disable(struct radeon_device *rdev)
2977 {
2978 u32 disp_int, disp_int_cont, disp_int_cont2;
2979
2980 r600_disable_interrupts(rdev);
2981 /* Wait and acknowledge irq */
2982 mdelay(1);
2983 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2984 r600_disable_interrupt_state(rdev);
2985 }
2986
2987 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2988 {
2989 u32 wptr, tmp;
2990
2991 /* XXX use writeback */
2992 wptr = RREG32(IH_RB_WPTR);
2993
2994 if (wptr & RB_OVERFLOW) {
2995 /* When a ring buffer overflow happen start parsing interrupt
2996 * from the last not overwritten vector (wptr + 16). Hopefully
2997 * this should allow us to catchup.
2998 */
2999 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3000 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3001 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3002 tmp = RREG32(IH_RB_CNTL);
3003 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3004 WREG32(IH_RB_CNTL, tmp);
3005 }
3006 return (wptr & rdev->ih.ptr_mask);
3007 }
3008
3009 /* r600 IV Ring
3010 * Each IV ring entry is 128 bits:
3011 * [7:0] - interrupt source id
3012 * [31:8] - reserved
3013 * [59:32] - interrupt source data
3014 * [127:60] - reserved
3015 *
3016 * The basic interrupt vector entries
3017 * are decoded as follows:
3018 * src_id src_data description
3019 * 1 0 D1 Vblank
3020 * 1 1 D1 Vline
3021 * 5 0 D2 Vblank
3022 * 5 1 D2 Vline
3023 * 19 0 FP Hot plug detection A
3024 * 19 1 FP Hot plug detection B
3025 * 19 2 DAC A auto-detection
3026 * 19 3 DAC B auto-detection
3027 * 21 4 HDMI block A
3028 * 21 5 HDMI block B
3029 * 176 - CP_INT RB
3030 * 177 - CP_INT IB1
3031 * 178 - CP_INT IB2
3032 * 181 - EOP Interrupt
3033 * 233 - GUI Idle
3034 *
3035 * Note, these are based on r600 and may need to be
3036 * adjusted or added to on newer asics
3037 */
3038
3039 int r600_irq_process(struct radeon_device *rdev)
3040 {
3041 u32 wptr = r600_get_ih_wptr(rdev);
3042 u32 rptr = rdev->ih.rptr;
3043 u32 src_id, src_data;
3044 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3045 unsigned long flags;
3046 bool queue_hotplug = false;
3047
3048 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3049 if (!rdev->ih.enabled)
3050 return IRQ_NONE;
3051
3052 spin_lock_irqsave(&rdev->ih.lock, flags);
3053
3054 if (rptr == wptr) {
3055 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3056 return IRQ_NONE;
3057 }
3058 if (rdev->shutdown) {
3059 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3060 return IRQ_NONE;
3061 }
3062
3063 restart_ih:
3064 /* display interrupts */
3065 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3066
3067 rdev->ih.wptr = wptr;
3068 while (rptr != wptr) {
3069 /* wptr/rptr are in bytes! */
3070 ring_index = rptr / 4;
3071 src_id = rdev->ih.ring[ring_index] & 0xff;
3072 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3073
3074 switch (src_id) {
3075 case 1: /* D1 vblank/vline */
3076 switch (src_data) {
3077 case 0: /* D1 vblank */
3078 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3079 drm_handle_vblank(rdev->ddev, 0);
3080 rdev->pm.vblank_sync = true;
3081 wake_up(&rdev->irq.vblank_queue);
3082 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3083 DRM_DEBUG("IH: D1 vblank\n");
3084 }
3085 break;
3086 case 1: /* D1 vline */
3087 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3088 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3089 DRM_DEBUG("IH: D1 vline\n");
3090 }
3091 break;
3092 default:
3093 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3094 break;
3095 }
3096 break;
3097 case 5: /* D2 vblank/vline */
3098 switch (src_data) {
3099 case 0: /* D2 vblank */
3100 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3101 drm_handle_vblank(rdev->ddev, 1);
3102 rdev->pm.vblank_sync = true;
3103 wake_up(&rdev->irq.vblank_queue);
3104 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3105 DRM_DEBUG("IH: D2 vblank\n");
3106 }
3107 break;
3108 case 1: /* D1 vline */
3109 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3110 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3111 DRM_DEBUG("IH: D2 vline\n");
3112 }
3113 break;
3114 default:
3115 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3116 break;
3117 }
3118 break;
3119 case 19: /* HPD/DAC hotplug */
3120 switch (src_data) {
3121 case 0:
3122 if (disp_int & DC_HPD1_INTERRUPT) {
3123 disp_int &= ~DC_HPD1_INTERRUPT;
3124 queue_hotplug = true;
3125 DRM_DEBUG("IH: HPD1\n");
3126 }
3127 break;
3128 case 1:
3129 if (disp_int & DC_HPD2_INTERRUPT) {
3130 disp_int &= ~DC_HPD2_INTERRUPT;
3131 queue_hotplug = true;
3132 DRM_DEBUG("IH: HPD2\n");
3133 }
3134 break;
3135 case 4:
3136 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3137 disp_int_cont &= ~DC_HPD3_INTERRUPT;
3138 queue_hotplug = true;
3139 DRM_DEBUG("IH: HPD3\n");
3140 }
3141 break;
3142 case 5:
3143 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3144 disp_int_cont &= ~DC_HPD4_INTERRUPT;
3145 queue_hotplug = true;
3146 DRM_DEBUG("IH: HPD4\n");
3147 }
3148 break;
3149 case 10:
3150 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3151 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3152 queue_hotplug = true;
3153 DRM_DEBUG("IH: HPD5\n");
3154 }
3155 break;
3156 case 12:
3157 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3158 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3159 queue_hotplug = true;
3160 DRM_DEBUG("IH: HPD6\n");
3161 }
3162 break;
3163 default:
3164 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3165 break;
3166 }
3167 break;
3168 case 21: /* HDMI */
3169 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3170 r600_audio_schedule_polling(rdev);
3171 break;
3172 case 176: /* CP_INT in ring buffer */
3173 case 177: /* CP_INT in IB1 */
3174 case 178: /* CP_INT in IB2 */
3175 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3176 radeon_fence_process(rdev);
3177 break;
3178 case 181: /* CP EOP event */
3179 DRM_DEBUG("IH: CP EOP\n");
3180 break;
3181 case 233: /* GUI IDLE */
3182 DRM_DEBUG("IH: CP EOP\n");
3183 rdev->pm.gui_idle = true;
3184 wake_up(&rdev->irq.idle_queue);
3185 break;
3186 default:
3187 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3188 break;
3189 }
3190
3191 /* wptr/rptr are in bytes! */
3192 rptr += 16;
3193 rptr &= rdev->ih.ptr_mask;
3194 }
3195 /* make sure wptr hasn't changed while processing */
3196 wptr = r600_get_ih_wptr(rdev);
3197 if (wptr != rdev->ih.wptr)
3198 goto restart_ih;
3199 if (queue_hotplug)
3200 queue_work(rdev->wq, &rdev->hotplug_work);
3201 rdev->ih.rptr = rptr;
3202 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3203 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3204 return IRQ_HANDLED;
3205 }
3206
3207 /*
3208 * Debugfs info
3209 */
3210 #if defined(CONFIG_DEBUG_FS)
3211
3212 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3213 {
3214 struct drm_info_node *node = (struct drm_info_node *) m->private;
3215 struct drm_device *dev = node->minor->dev;
3216 struct radeon_device *rdev = dev->dev_private;
3217 unsigned count, i, j;
3218
3219 radeon_ring_free_size(rdev);
3220 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3221 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3222 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3223 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3224 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3225 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3226 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3227 seq_printf(m, "%u dwords in ring\n", count);
3228 i = rdev->cp.rptr;
3229 for (j = 0; j <= count; j++) {
3230 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3231 i = (i + 1) & rdev->cp.ptr_mask;
3232 }
3233 return 0;
3234 }
3235
3236 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3237 {
3238 struct drm_info_node *node = (struct drm_info_node *) m->private;
3239 struct drm_device *dev = node->minor->dev;
3240 struct radeon_device *rdev = dev->dev_private;
3241
3242 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3243 DREG32_SYS(m, rdev, VM_L2_STATUS);
3244 return 0;
3245 }
3246
3247 static struct drm_info_list r600_mc_info_list[] = {
3248 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3249 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3250 };
3251 #endif
3252
3253 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3254 {
3255 #if defined(CONFIG_DEBUG_FS)
3256 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3257 #else
3258 return 0;
3259 #endif
3260 }
3261
3262 /**
3263 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3264 * rdev: radeon device structure
3265 * bo: buffer object struct which userspace is waiting for idle
3266 *
3267 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3268 * through ring buffer, this leads to corruption in rendering, see
3269 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3270 * directly perform HDP flush by writing register through MMIO.
3271 */
3272 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3273 {
3274 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3275 }
CJK support for tty framebuffer vt