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ixgbe: Define FCoE and Flow director limits much sooner to allow for changes
[linux-2.6/cjktty.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
blob5fd16670482e90dbf336c234c2b2160b4f24775f
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define DRV_VERSION "3.11.33-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
70
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
75 };
76
77 /* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 /* required last entry */
116 {0, }
117 };
118 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
120 #ifdef CONFIG_IXGBE_DCA
121 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
122 void *p);
123 static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127 };
128 #endif
129
130 #ifdef CONFIG_PCI_IOV
131 static unsigned int max_vfs;
132 module_param(max_vfs, uint, 0);
133 MODULE_PARM_DESC(max_vfs,
134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
135 #endif /* CONFIG_PCI_IOV */
136
137 static unsigned int allow_unsupported_sfp;
138 module_param(allow_unsupported_sfp, uint, 0);
139 MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
142 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143 static int debug = -1;
144 module_param(debug, int, 0);
145 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
147 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149 MODULE_LICENSE("GPL");
150 MODULE_VERSION(DRV_VERSION);
151
152 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
153 {
154 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
155 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
156 schedule_work(&adapter->service_task);
157 }
158
159 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
160 {
161 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
162
163 /* flush memory to make sure state is correct before next watchdog */
164 smp_mb__before_clear_bit();
165 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
166 }
167
168 struct ixgbe_reg_info {
169 u32 ofs;
170 char *name;
171 };
172
173 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
174
175 /* General Registers */
176 {IXGBE_CTRL, "CTRL"},
177 {IXGBE_STATUS, "STATUS"},
178 {IXGBE_CTRL_EXT, "CTRL_EXT"},
179
180 /* Interrupt Registers */
181 {IXGBE_EICR, "EICR"},
182
183 /* RX Registers */
184 {IXGBE_SRRCTL(0), "SRRCTL"},
185 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
186 {IXGBE_RDLEN(0), "RDLEN"},
187 {IXGBE_RDH(0), "RDH"},
188 {IXGBE_RDT(0), "RDT"},
189 {IXGBE_RXDCTL(0), "RXDCTL"},
190 {IXGBE_RDBAL(0), "RDBAL"},
191 {IXGBE_RDBAH(0), "RDBAH"},
192
193 /* TX Registers */
194 {IXGBE_TDBAL(0), "TDBAL"},
195 {IXGBE_TDBAH(0), "TDBAH"},
196 {IXGBE_TDLEN(0), "TDLEN"},
197 {IXGBE_TDH(0), "TDH"},
198 {IXGBE_TDT(0), "TDT"},
199 {IXGBE_TXDCTL(0), "TXDCTL"},
200
201 /* List Terminator */
202 {}
203 };
204
205
206 /*
207 * ixgbe_regdump - register printout routine
208 */
209 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
210 {
211 int i = 0, j = 0;
212 char rname[16];
213 u32 regs[64];
214
215 switch (reginfo->ofs) {
216 case IXGBE_SRRCTL(0):
217 for (i = 0; i < 64; i++)
218 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
219 break;
220 case IXGBE_DCA_RXCTRL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
223 break;
224 case IXGBE_RDLEN(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
227 break;
228 case IXGBE_RDH(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
231 break;
232 case IXGBE_RDT(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
235 break;
236 case IXGBE_RXDCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
239 break;
240 case IXGBE_RDBAL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
243 break;
244 case IXGBE_RDBAH(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
247 break;
248 case IXGBE_TDBAL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
251 break;
252 case IXGBE_TDBAH(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
255 break;
256 case IXGBE_TDLEN(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
259 break;
260 case IXGBE_TDH(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
263 break;
264 case IXGBE_TDT(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
267 break;
268 case IXGBE_TXDCTL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
271 break;
272 default:
273 pr_info("%-15s %08x\n", reginfo->name,
274 IXGBE_READ_REG(hw, reginfo->ofs));
275 return;
276 }
277
278 for (i = 0; i < 8; i++) {
279 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
280 pr_err("%-15s", rname);
281 for (j = 0; j < 8; j++)
282 pr_cont(" %08x", regs[i*8+j]);
283 pr_cont("\n");
284 }
285
286 }
287
288 /*
289 * ixgbe_dump - Print registers, tx-rings and rx-rings
290 */
291 static void ixgbe_dump(struct ixgbe_adapter *adapter)
292 {
293 struct net_device *netdev = adapter->netdev;
294 struct ixgbe_hw *hw = &adapter->hw;
295 struct ixgbe_reg_info *reginfo;
296 int n = 0;
297 struct ixgbe_ring *tx_ring;
298 struct ixgbe_tx_buffer *tx_buffer;
299 union ixgbe_adv_tx_desc *tx_desc;
300 struct my_u0 { u64 a; u64 b; } *u0;
301 struct ixgbe_ring *rx_ring;
302 union ixgbe_adv_rx_desc *rx_desc;
303 struct ixgbe_rx_buffer *rx_buffer_info;
304 u32 staterr;
305 int i = 0;
306
307 if (!netif_msg_hw(adapter))
308 return;
309
310 /* Print netdevice Info */
311 if (netdev) {
312 dev_info(&adapter->pdev->dev, "Net device Info\n");
313 pr_info("Device Name state "
314 "trans_start last_rx\n");
315 pr_info("%-15s %016lX %016lX %016lX\n",
316 netdev->name,
317 netdev->state,
318 netdev->trans_start,
319 netdev->last_rx);
320 }
321
322 /* Print Registers */
323 dev_info(&adapter->pdev->dev, "Register Dump\n");
324 pr_info(" Register Name Value\n");
325 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
326 reginfo->name; reginfo++) {
327 ixgbe_regdump(hw, reginfo);
328 }
329
330 /* Print TX Ring Summary */
331 if (!netdev || !netif_running(netdev))
332 goto exit;
333
334 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
335 pr_info(" %s %s %s %s\n",
336 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
337 "leng", "ntw", "timestamp");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * 82598 Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 *
365 * 82598 Advanced Transmit Descriptor (Write-Back Format)
366 * +--------------------------------------------------------------+
367 * 0 | RSV [63:0] |
368 * +--------------------------------------------------------------+
369 * 8 | RSV | STA | NXTSEQ |
370 * +--------------------------------------------------------------+
371 * 63 36 35 32 31 0
372 *
373 * 82599+ Advanced Transmit Descriptor
374 * +--------------------------------------------------------------+
375 * 0 | Buffer Address [63:0] |
376 * +--------------------------------------------------------------+
377 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
378 * +--------------------------------------------------------------+
379 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
380 *
381 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
382 * +--------------------------------------------------------------+
383 * 0 | RSV [63:0] |
384 * +--------------------------------------------------------------+
385 * 8 | RSV | STA | RSV |
386 * +--------------------------------------------------------------+
387 * 63 36 35 32 31 0
388 */
389
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 tx_ring = adapter->tx_ring[n];
392 pr_info("------------------------------------\n");
393 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
394 pr_info("------------------------------------\n");
395 pr_info("%s%s %s %s %s %s\n",
396 "T [desc] [address 63:0 ] ",
397 "[PlPOIdStDDt Ln] [bi->dma ] ",
398 "leng", "ntw", "timestamp", "bi->skb");
399
400 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
401 tx_desc = IXGBE_TX_DESC(tx_ring, i);
402 tx_buffer = &tx_ring->tx_buffer_info[i];
403 u0 = (struct my_u0 *)tx_desc;
404 if (dma_unmap_len(tx_buffer, len) > 0) {
405 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
406 i,
407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
409 (u64)dma_unmap_addr(tx_buffer, dma),
410 dma_unmap_len(tx_buffer, len),
411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
413 tx_buffer->skb);
414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
416 pr_cont(" NTC/U\n");
417 else if (i == tx_ring->next_to_use)
418 pr_cont(" NTU\n");
419 else if (i == tx_ring->next_to_clean)
420 pr_cont(" NTC\n");
421 else
422 pr_cont("\n");
423
424 if (netif_msg_pktdata(adapter) &&
425 tx_buffer->skb)
426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
428 tx_buffer->skb->data,
429 dma_unmap_len(tx_buffer, len),
430 true);
431 }
432 }
433 }
434
435 /* Print RX Rings Summary */
436 rx_ring_summary:
437 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
438 pr_info("Queue [NTU] [NTC]\n");
439 for (n = 0; n < adapter->num_rx_queues; n++) {
440 rx_ring = adapter->rx_ring[n];
441 pr_info("%5d %5X %5X\n",
442 n, rx_ring->next_to_use, rx_ring->next_to_clean);
443 }
444
445 /* Print RX Rings */
446 if (!netif_msg_rx_status(adapter))
447 goto exit;
448
449 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
450
451 /* Receive Descriptor Formats
452 *
453 * 82598 Advanced Receive Descriptor (Read) Format
454 * 63 1 0
455 * +-----------------------------------------------------+
456 * 0 | Packet Buffer Address [63:1] |A0/NSE|
457 * +----------------------------------------------+------+
458 * 8 | Header Buffer Address [63:1] | DD |
459 * +-----------------------------------------------------+
460 *
461 *
462 * 82598 Advanced Receive Descriptor (Write-Back) Format
463 *
464 * 63 48 47 32 31 30 21 20 16 15 4 3 0
465 * +------------------------------------------------------+
466 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
467 * | Packet | IP | | | | Type | Type |
468 * | Checksum | Ident | | | | | |
469 * +------------------------------------------------------+
470 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
471 * +------------------------------------------------------+
472 * 63 48 47 32 31 20 19 0
473 *
474 * 82599+ Advanced Receive Descriptor (Read) Format
475 * 63 1 0
476 * +-----------------------------------------------------+
477 * 0 | Packet Buffer Address [63:1] |A0/NSE|
478 * +----------------------------------------------+------+
479 * 8 | Header Buffer Address [63:1] | DD |
480 * +-----------------------------------------------------+
481 *
482 *
483 * 82599+ Advanced Receive Descriptor (Write-Back) Format
484 *
485 * 63 48 47 32 31 30 21 20 17 16 4 3 0
486 * +------------------------------------------------------+
487 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
488 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
489 * |/ Flow Dir Flt ID | | | | | |
490 * +------------------------------------------------------+
491 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
492 * +------------------------------------------------------+
493 * 63 48 47 32 31 20 19 0
494 */
495
496 for (n = 0; n < adapter->num_rx_queues; n++) {
497 rx_ring = adapter->rx_ring[n];
498 pr_info("------------------------------------\n");
499 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
500 pr_info("------------------------------------\n");
501 pr_info("%s%s%s",
502 "R [desc] [ PktBuf A0] ",
503 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
504 "<-- Adv Rx Read format\n");
505 pr_info("%s%s%s",
506 "RWB[desc] [PcsmIpSHl PtRs] ",
507 "[vl er S cks ln] ---------------- [bi->skb ] ",
508 "<-- Adv Rx Write-Back format\n");
509
510 for (i = 0; i < rx_ring->count; i++) {
511 rx_buffer_info = &rx_ring->rx_buffer_info[i];
512 rx_desc = IXGBE_RX_DESC(rx_ring, i);
513 u0 = (struct my_u0 *)rx_desc;
514 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
515 if (staterr & IXGBE_RXD_STAT_DD) {
516 /* Descriptor Done */
517 pr_info("RWB[0x%03X] %016llX "
518 "%016llX ---------------- %p", i,
519 le64_to_cpu(u0->a),
520 le64_to_cpu(u0->b),
521 rx_buffer_info->skb);
522 } else {
523 pr_info("R [0x%03X] %016llX "
524 "%016llX %016llX %p", i,
525 le64_to_cpu(u0->a),
526 le64_to_cpu(u0->b),
527 (u64)rx_buffer_info->dma,
528 rx_buffer_info->skb);
529
530 if (netif_msg_pktdata(adapter) &&
531 rx_buffer_info->dma) {
532 print_hex_dump(KERN_INFO, "",
533 DUMP_PREFIX_ADDRESS, 16, 1,
534 page_address(rx_buffer_info->page) +
535 rx_buffer_info->page_offset,
536 ixgbe_rx_bufsz(rx_ring), true);
537 }
538 }
539
540 if (i == rx_ring->next_to_use)
541 pr_cont(" NTU\n");
542 else if (i == rx_ring->next_to_clean)
543 pr_cont(" NTC\n");
544 else
545 pr_cont("\n");
546
547 }
548 }
549
550 exit:
551 return;
552 }
553
554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555 {
556 u32 ctrl_ext;
557
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
562 }
563
564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565 {
566 u32 ctrl_ext;
567
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
572 }
573
574 /**
575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
580 *
581 */
582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
583 u8 queue, u8 msix_vector)
584 {
585 u32 ivar, index;
586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 if (direction == -1)
591 direction = 0;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
597 break;
598 case ixgbe_mac_82599EB:
599 case ixgbe_mac_X540:
600 if (direction == -1) {
601 /* other causes */
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
608 break;
609 } else {
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
617 break;
618 }
619 default:
620 break;
621 }
622 }
623
624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
625 u64 qmask)
626 {
627 u32 mask;
628
629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
633 break;
634 case ixgbe_mac_82599EB:
635 case ixgbe_mac_X540:
636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
640 break;
641 default:
642 break;
643 }
644 }
645
646 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
648 {
649 if (tx_buffer->skb) {
650 dev_kfree_skb_any(tx_buffer->skb);
651 if (dma_unmap_len(tx_buffer, len))
652 dma_unmap_single(ring->dev,
653 dma_unmap_addr(tx_buffer, dma),
654 dma_unmap_len(tx_buffer, len),
655 DMA_TO_DEVICE);
656 } else if (dma_unmap_len(tx_buffer, len)) {
657 dma_unmap_page(ring->dev,
658 dma_unmap_addr(tx_buffer, dma),
659 dma_unmap_len(tx_buffer, len),
660 DMA_TO_DEVICE);
661 }
662 tx_buffer->next_to_watch = NULL;
663 tx_buffer->skb = NULL;
664 dma_unmap_len_set(tx_buffer, len, 0);
665 /* tx_buffer must be completely set up in the transmit path */
666 }
667
668 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
669 {
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 int i;
673 u32 data;
674
675 if ((hw->fc.current_mode != ixgbe_fc_full) &&
676 (hw->fc.current_mode != ixgbe_fc_rx_pause))
677 return;
678
679 switch (hw->mac.type) {
680 case ixgbe_mac_82598EB:
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
682 break;
683 default:
684 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
685 }
686 hwstats->lxoffrxc += data;
687
688 /* refill credits (no tx hang) if we received xoff */
689 if (!data)
690 return;
691
692 for (i = 0; i < adapter->num_tx_queues; i++)
693 clear_bit(__IXGBE_HANG_CHECK_ARMED,
694 &adapter->tx_ring[i]->state);
695 }
696
697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698 {
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 xoff[8] = {0};
702 u8 tc;
703 int i;
704 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
705
706 if (adapter->ixgbe_ieee_pfc)
707 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
708
709 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
710 ixgbe_update_xoff_rx_lfc(adapter);
711 return;
712 }
713
714 /* update stats for each tc, only valid with PFC enabled */
715 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
716 u32 pxoffrxc;
717
718 switch (hw->mac.type) {
719 case ixgbe_mac_82598EB:
720 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
721 break;
722 default:
723 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
724 }
725 hwstats->pxoffrxc[i] += pxoffrxc;
726 /* Get the TC for given UP */
727 tc = netdev_get_prio_tc_map(adapter->netdev, i);
728 xoff[tc] += pxoffrxc;
729 }
730
731 /* disarm tx queues that have received xoff frames */
732 for (i = 0; i < adapter->num_tx_queues; i++) {
733 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
734
735 tc = tx_ring->dcb_tc;
736 if (xoff[tc])
737 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
738 }
739 }
740
741 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
742 {
743 return ring->stats.packets;
744 }
745
746 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
747 {
748 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
749 struct ixgbe_hw *hw = &adapter->hw;
750
751 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
752 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
753
754 if (head != tail)
755 return (head < tail) ?
756 tail - head : (tail + ring->count - head);
757
758 return 0;
759 }
760
761 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
762 {
763 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
764 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
765 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
766 bool ret = false;
767
768 clear_check_for_tx_hang(tx_ring);
769
770 /*
771 * Check for a hung queue, but be thorough. This verifies
772 * that a transmit has been completed since the previous
773 * check AND there is at least one packet pending. The
774 * ARMED bit is set to indicate a potential hang. The
775 * bit is cleared if a pause frame is received to remove
776 * false hang detection due to PFC or 802.3x frames. By
777 * requiring this to fail twice we avoid races with
778 * pfc clearing the ARMED bit and conditions where we
779 * run the check_tx_hang logic with a transmit completion
780 * pending but without time to complete it yet.
781 */
782 if ((tx_done_old == tx_done) && tx_pending) {
783 /* make sure it is true for two checks in a row */
784 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
785 &tx_ring->state);
786 } else {
787 /* update completed stats and continue */
788 tx_ring->tx_stats.tx_done_old = tx_done;
789 /* reset the countdown */
790 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
791 }
792
793 return ret;
794 }
795
796 /**
797 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
798 * @adapter: driver private struct
799 **/
800 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
801 {
802
803 /* Do the reset outside of interrupt context */
804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
805 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
806 e_warn(drv, "initiating reset due to tx timeout\n");
807 ixgbe_service_event_schedule(adapter);
808 }
809 }
810
811 /**
812 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
813 * @q_vector: structure containing interrupt and ring information
814 * @tx_ring: tx ring to clean
815 **/
816 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
817 struct ixgbe_ring *tx_ring)
818 {
819 struct ixgbe_adapter *adapter = q_vector->adapter;
820 struct ixgbe_tx_buffer *tx_buffer;
821 union ixgbe_adv_tx_desc *tx_desc;
822 unsigned int total_bytes = 0, total_packets = 0;
823 unsigned int budget = q_vector->tx.work_limit;
824 unsigned int i = tx_ring->next_to_clean;
825
826 if (test_bit(__IXGBE_DOWN, &adapter->state))
827 return true;
828
829 tx_buffer = &tx_ring->tx_buffer_info[i];
830 tx_desc = IXGBE_TX_DESC(tx_ring, i);
831 i -= tx_ring->count;
832
833 do {
834 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
835
836 /* if next_to_watch is not set then there is no work pending */
837 if (!eop_desc)
838 break;
839
840 /* prevent any other reads prior to eop_desc */
841 read_barrier_depends();
842
843 /* if DD is not set pending work has not been completed */
844 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
845 break;
846
847 /* clear next_to_watch to prevent false hangs */
848 tx_buffer->next_to_watch = NULL;
849
850 /* update the statistics for this packet */
851 total_bytes += tx_buffer->bytecount;
852 total_packets += tx_buffer->gso_segs;
853
854 /* free the skb */
855 dev_kfree_skb_any(tx_buffer->skb);
856
857 /* unmap skb header data */
858 dma_unmap_single(tx_ring->dev,
859 dma_unmap_addr(tx_buffer, dma),
860 dma_unmap_len(tx_buffer, len),
861 DMA_TO_DEVICE);
862
863 /* clear tx_buffer data */
864 tx_buffer->skb = NULL;
865 dma_unmap_len_set(tx_buffer, len, 0);
866
867 /* unmap remaining buffers */
868 while (tx_desc != eop_desc) {
869 tx_buffer++;
870 tx_desc++;
871 i++;
872 if (unlikely(!i)) {
873 i -= tx_ring->count;
874 tx_buffer = tx_ring->tx_buffer_info;
875 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
876 }
877
878 /* unmap any remaining paged data */
879 if (dma_unmap_len(tx_buffer, len)) {
880 dma_unmap_page(tx_ring->dev,
881 dma_unmap_addr(tx_buffer, dma),
882 dma_unmap_len(tx_buffer, len),
883 DMA_TO_DEVICE);
884 dma_unmap_len_set(tx_buffer, len, 0);
885 }
886 }
887
888 /* move us one more past the eop_desc for start of next pkt */
889 tx_buffer++;
890 tx_desc++;
891 i++;
892 if (unlikely(!i)) {
893 i -= tx_ring->count;
894 tx_buffer = tx_ring->tx_buffer_info;
895 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
896 }
897
898 /* issue prefetch for next Tx descriptor */
899 prefetch(tx_desc);
900
901 /* update budget accounting */
902 budget--;
903 } while (likely(budget));
904
905 i += tx_ring->count;
906 tx_ring->next_to_clean = i;
907 u64_stats_update_begin(&tx_ring->syncp);
908 tx_ring->stats.bytes += total_bytes;
909 tx_ring->stats.packets += total_packets;
910 u64_stats_update_end(&tx_ring->syncp);
911 q_vector->tx.total_bytes += total_bytes;
912 q_vector->tx.total_packets += total_packets;
913
914 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
915 /* schedule immediate reset if we believe we hung */
916 struct ixgbe_hw *hw = &adapter->hw;
917 e_err(drv, "Detected Tx Unit Hang\n"
918 " Tx Queue <%d>\n"
919 " TDH, TDT <%x>, <%x>\n"
920 " next_to_use <%x>\n"
921 " next_to_clean <%x>\n"
922 "tx_buffer_info[next_to_clean]\n"
923 " time_stamp <%lx>\n"
924 " jiffies <%lx>\n",
925 tx_ring->queue_index,
926 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
927 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
928 tx_ring->next_to_use, i,
929 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
930
931 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
932
933 e_info(probe,
934 "tx hang %d detected on queue %d, resetting adapter\n",
935 adapter->tx_timeout_count + 1, tx_ring->queue_index);
936
937 /* schedule immediate reset if we believe we hung */
938 ixgbe_tx_timeout_reset(adapter);
939
940 /* the adapter is about to reset, no point in enabling stuff */
941 return true;
942 }
943
944 netdev_tx_completed_queue(txring_txq(tx_ring),
945 total_packets, total_bytes);
946
947 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
948 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
949 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
950 /* Make sure that anybody stopping the queue after this
951 * sees the new next_to_clean.
952 */
953 smp_mb();
954 if (__netif_subqueue_stopped(tx_ring->netdev,
955 tx_ring->queue_index)
956 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
957 netif_wake_subqueue(tx_ring->netdev,
958 tx_ring->queue_index);
959 ++tx_ring->tx_stats.restart_queue;
960 }
961 }
962
963 return !!budget;
964 }
965
966 #ifdef CONFIG_IXGBE_DCA
967 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
968 struct ixgbe_ring *tx_ring,
969 int cpu)
970 {
971 struct ixgbe_hw *hw = &adapter->hw;
972 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
973 u16 reg_offset;
974
975 switch (hw->mac.type) {
976 case ixgbe_mac_82598EB:
977 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
978 break;
979 case ixgbe_mac_82599EB:
980 case ixgbe_mac_X540:
981 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
982 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
983 break;
984 default:
985 /* for unknown hardware do not write register */
986 return;
987 }
988
989 /*
990 * We can enable relaxed ordering for reads, but not writes when
991 * DCA is enabled. This is due to a known issue in some chipsets
992 * which will cause the DCA tag to be cleared.
993 */
994 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
995 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
996 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
997
998 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
999 }
1000
1001 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1002 struct ixgbe_ring *rx_ring,
1003 int cpu)
1004 {
1005 struct ixgbe_hw *hw = &adapter->hw;
1006 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1007 u8 reg_idx = rx_ring->reg_idx;
1008
1009
1010 switch (hw->mac.type) {
1011 case ixgbe_mac_82599EB:
1012 case ixgbe_mac_X540:
1013 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1014 break;
1015 default:
1016 break;
1017 }
1018
1019 /*
1020 * We can enable relaxed ordering for reads, but not writes when
1021 * DCA is enabled. This is due to a known issue in some chipsets
1022 * which will cause the DCA tag to be cleared.
1023 */
1024 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1025 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1026
1027 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1028 }
1029
1030 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1031 {
1032 struct ixgbe_adapter *adapter = q_vector->adapter;
1033 struct ixgbe_ring *ring;
1034 int cpu = get_cpu();
1035
1036 if (q_vector->cpu == cpu)
1037 goto out_no_update;
1038
1039 ixgbe_for_each_ring(ring, q_vector->tx)
1040 ixgbe_update_tx_dca(adapter, ring, cpu);
1041
1042 ixgbe_for_each_ring(ring, q_vector->rx)
1043 ixgbe_update_rx_dca(adapter, ring, cpu);
1044
1045 q_vector->cpu = cpu;
1046 out_no_update:
1047 put_cpu();
1048 }
1049
1050 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1051 {
1052 int i;
1053
1054 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1055 return;
1056
1057 /* always use CB2 mode, difference is masked in the CB driver */
1058 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1059
1060 for (i = 0; i < adapter->num_q_vectors; i++) {
1061 adapter->q_vector[i]->cpu = -1;
1062 ixgbe_update_dca(adapter->q_vector[i]);
1063 }
1064 }
1065
1066 static int __ixgbe_notify_dca(struct device *dev, void *data)
1067 {
1068 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1069 unsigned long event = *(unsigned long *)data;
1070
1071 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1072 return 0;
1073
1074 switch (event) {
1075 case DCA_PROVIDER_ADD:
1076 /* if we're already enabled, don't do it again */
1077 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1078 break;
1079 if (dca_add_requester(dev) == 0) {
1080 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1081 ixgbe_setup_dca(adapter);
1082 break;
1083 }
1084 /* Fall Through since DCA is disabled. */
1085 case DCA_PROVIDER_REMOVE:
1086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1087 dca_remove_requester(dev);
1088 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1090 }
1091 break;
1092 }
1093
1094 return 0;
1095 }
1096
1097 #endif /* CONFIG_IXGBE_DCA */
1098 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1101 {
1102 if (ring->netdev->features & NETIF_F_RXHASH)
1103 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1104 }
1105
1106 #ifdef IXGBE_FCOE
1107 /**
1108 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1109 * @ring: structure containing ring specific data
1110 * @rx_desc: advanced rx descriptor
1111 *
1112 * Returns : true if it is FCoE pkt
1113 */
1114 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1115 union ixgbe_adv_rx_desc *rx_desc)
1116 {
1117 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1118
1119 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1120 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1121 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1122 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1123 }
1124
1125 #endif /* IXGBE_FCOE */
1126 /**
1127 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1128 * @ring: structure containing ring specific data
1129 * @rx_desc: current Rx descriptor being processed
1130 * @skb: skb currently being received and modified
1131 **/
1132 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1133 union ixgbe_adv_rx_desc *rx_desc,
1134 struct sk_buff *skb)
1135 {
1136 skb_checksum_none_assert(skb);
1137
1138 /* Rx csum disabled */
1139 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1140 return;
1141
1142 /* if IP and error */
1143 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1144 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1145 ring->rx_stats.csum_err++;
1146 return;
1147 }
1148
1149 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1150 return;
1151
1152 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1153 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1154
1155 /*
1156 * 82599 errata, UDP frames with a 0 checksum can be marked as
1157 * checksum errors.
1158 */
1159 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1160 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1161 return;
1162
1163 ring->rx_stats.csum_err++;
1164 return;
1165 }
1166
1167 /* It must be a TCP or UDP packet with a valid checksum */
1168 skb->ip_summed = CHECKSUM_UNNECESSARY;
1169 }
1170
1171 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1172 {
1173 rx_ring->next_to_use = val;
1174
1175 /* update next to alloc since we have filled the ring */
1176 rx_ring->next_to_alloc = val;
1177 /*
1178 * Force memory writes to complete before letting h/w
1179 * know there are new descriptors to fetch. (Only
1180 * applicable for weak-ordered memory model archs,
1181 * such as IA-64).
1182 */
1183 wmb();
1184 writel(val, rx_ring->tail);
1185 }
1186
1187 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1188 struct ixgbe_rx_buffer *bi)
1189 {
1190 struct page *page = bi->page;
1191 dma_addr_t dma = bi->dma;
1192
1193 /* since we are recycling buffers we should seldom need to alloc */
1194 if (likely(dma))
1195 return true;
1196
1197 /* alloc new page for storage */
1198 if (likely(!page)) {
1199 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1200 bi->skb, ixgbe_rx_pg_order(rx_ring));
1201 if (unlikely(!page)) {
1202 rx_ring->rx_stats.alloc_rx_page_failed++;
1203 return false;
1204 }
1205 bi->page = page;
1206 }
1207
1208 /* map page for use */
1209 dma = dma_map_page(rx_ring->dev, page, 0,
1210 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1211
1212 /*
1213 * if mapping failed free memory back to system since
1214 * there isn't much point in holding memory we can't use
1215 */
1216 if (dma_mapping_error(rx_ring->dev, dma)) {
1217 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1218 bi->page = NULL;
1219
1220 rx_ring->rx_stats.alloc_rx_page_failed++;
1221 return false;
1222 }
1223
1224 bi->dma = dma;
1225 bi->page_offset = 0;
1226
1227 return true;
1228 }
1229
1230 /**
1231 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1232 * @rx_ring: ring to place buffers on
1233 * @cleaned_count: number of buffers to replace
1234 **/
1235 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1236 {
1237 union ixgbe_adv_rx_desc *rx_desc;
1238 struct ixgbe_rx_buffer *bi;
1239 u16 i = rx_ring->next_to_use;
1240
1241 /* nothing to do */
1242 if (!cleaned_count)
1243 return;
1244
1245 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1246 bi = &rx_ring->rx_buffer_info[i];
1247 i -= rx_ring->count;
1248
1249 do {
1250 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1251 break;
1252
1253 /*
1254 * Refresh the desc even if buffer_addrs didn't change
1255 * because each write-back erases this info.
1256 */
1257 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1258
1259 rx_desc++;
1260 bi++;
1261 i++;
1262 if (unlikely(!i)) {
1263 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1264 bi = rx_ring->rx_buffer_info;
1265 i -= rx_ring->count;
1266 }
1267
1268 /* clear the hdr_addr for the next_to_use descriptor */
1269 rx_desc->read.hdr_addr = 0;
1270
1271 cleaned_count--;
1272 } while (cleaned_count);
1273
1274 i += rx_ring->count;
1275
1276 if (rx_ring->next_to_use != i)
1277 ixgbe_release_rx_desc(rx_ring, i);
1278 }
1279
1280 /**
1281 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1282 * @data: pointer to the start of the headers
1283 * @max_len: total length of section to find headers in
1284 *
1285 * This function is meant to determine the length of headers that will
1286 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1287 * motivation of doing this is to only perform one pull for IPv4 TCP
1288 * packets so that we can do basic things like calculating the gso_size
1289 * based on the average data per packet.
1290 **/
1291 static unsigned int ixgbe_get_headlen(unsigned char *data,
1292 unsigned int max_len)
1293 {
1294 union {
1295 unsigned char *network;
1296 /* l2 headers */
1297 struct ethhdr *eth;
1298 struct vlan_hdr *vlan;
1299 /* l3 headers */
1300 struct iphdr *ipv4;
1301 struct ipv6hdr *ipv6;
1302 } hdr;
1303 __be16 protocol;
1304 u8 nexthdr = 0; /* default to not TCP */
1305 u8 hlen;
1306
1307 /* this should never happen, but better safe than sorry */
1308 if (max_len < ETH_HLEN)
1309 return max_len;
1310
1311 /* initialize network frame pointer */
1312 hdr.network = data;
1313
1314 /* set first protocol and move network header forward */
1315 protocol = hdr.eth->h_proto;
1316 hdr.network += ETH_HLEN;
1317
1318 /* handle any vlan tag if present */
1319 if (protocol == __constant_htons(ETH_P_8021Q)) {
1320 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1321 return max_len;
1322
1323 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1324 hdr.network += VLAN_HLEN;
1325 }
1326
1327 /* handle L3 protocols */
1328 if (protocol == __constant_htons(ETH_P_IP)) {
1329 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1330 return max_len;
1331
1332 /* access ihl as a u8 to avoid unaligned access on ia64 */
1333 hlen = (hdr.network[0] & 0x0F) << 2;
1334
1335 /* verify hlen meets minimum size requirements */
1336 if (hlen < sizeof(struct iphdr))
1337 return hdr.network - data;
1338
1339 /* record next protocol if header is present */
1340 if (!hdr.ipv4->frag_off)
1341 nexthdr = hdr.ipv4->protocol;
1342 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1343 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1344 return max_len;
1345
1346 /* record next protocol */
1347 nexthdr = hdr.ipv6->nexthdr;
1348 hlen = sizeof(struct ipv6hdr);
1349 #ifdef IXGBE_FCOE
1350 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1351 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1352 return max_len;
1353 hlen = FCOE_HEADER_LEN;
1354 #endif
1355 } else {
1356 return hdr.network - data;
1357 }
1358
1359 /* relocate pointer to start of L4 header */
1360 hdr.network += hlen;
1361
1362 /* finally sort out TCP/UDP */
1363 if (nexthdr == IPPROTO_TCP) {
1364 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1365 return max_len;
1366
1367 /* access doff as a u8 to avoid unaligned access on ia64 */
1368 hlen = (hdr.network[12] & 0xF0) >> 2;
1369
1370 /* verify hlen meets minimum size requirements */
1371 if (hlen < sizeof(struct tcphdr))
1372 return hdr.network - data;
1373
1374 hdr.network += hlen;
1375 } else if (nexthdr == IPPROTO_UDP) {
1376 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1377 return max_len;
1378
1379 hdr.network += sizeof(struct udphdr);
1380 }
1381
1382 /*
1383 * If everything has gone correctly hdr.network should be the
1384 * data section of the packet and will be the end of the header.
1385 * If not then it probably represents the end of the last recognized
1386 * header.
1387 */
1388 if ((hdr.network - data) < max_len)
1389 return hdr.network - data;
1390 else
1391 return max_len;
1392 }
1393
1394 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1395 struct sk_buff *skb)
1396 {
1397 u16 hdr_len = skb_headlen(skb);
1398
1399 /* set gso_size to avoid messing up TCP MSS */
1400 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1401 IXGBE_CB(skb)->append_cnt);
1402 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1403 }
1404
1405 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1406 struct sk_buff *skb)
1407 {
1408 /* if append_cnt is 0 then frame is not RSC */
1409 if (!IXGBE_CB(skb)->append_cnt)
1410 return;
1411
1412 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1413 rx_ring->rx_stats.rsc_flush++;
1414
1415 ixgbe_set_rsc_gso_size(rx_ring, skb);
1416
1417 /* gso_size is computed using append_cnt so always clear it last */
1418 IXGBE_CB(skb)->append_cnt = 0;
1419 }
1420
1421 /**
1422 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1423 * @rx_ring: rx descriptor ring packet is being transacted on
1424 * @rx_desc: pointer to the EOP Rx descriptor
1425 * @skb: pointer to current skb being populated
1426 *
1427 * This function checks the ring, descriptor, and packet information in
1428 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1429 * other fields within the skb.
1430 **/
1431 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1432 union ixgbe_adv_rx_desc *rx_desc,
1433 struct sk_buff *skb)
1434 {
1435 struct net_device *dev = rx_ring->netdev;
1436
1437 ixgbe_update_rsc_stats(rx_ring, skb);
1438
1439 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1440
1441 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1442
1443 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1444
1445 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1446 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1447 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1448 __vlan_hwaccel_put_tag(skb, vid);
1449 }
1450
1451 skb_record_rx_queue(skb, rx_ring->queue_index);
1452
1453 skb->protocol = eth_type_trans(skb, dev);
1454 }
1455
1456 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1457 struct sk_buff *skb)
1458 {
1459 struct ixgbe_adapter *adapter = q_vector->adapter;
1460
1461 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1462 napi_gro_receive(&q_vector->napi, skb);
1463 else
1464 netif_rx(skb);
1465 }
1466
1467 /**
1468 * ixgbe_is_non_eop - process handling of non-EOP buffers
1469 * @rx_ring: Rx ring being processed
1470 * @rx_desc: Rx descriptor for current buffer
1471 * @skb: Current socket buffer containing buffer in progress
1472 *
1473 * This function updates next to clean. If the buffer is an EOP buffer
1474 * this function exits returning false, otherwise it will place the
1475 * sk_buff in the next buffer to be chained and return true indicating
1476 * that this is in fact a non-EOP buffer.
1477 **/
1478 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1479 union ixgbe_adv_rx_desc *rx_desc,
1480 struct sk_buff *skb)
1481 {
1482 u32 ntc = rx_ring->next_to_clean + 1;
1483
1484 /* fetch, update, and store next to clean */
1485 ntc = (ntc < rx_ring->count) ? ntc : 0;
1486 rx_ring->next_to_clean = ntc;
1487
1488 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1489
1490 /* update RSC append count if present */
1491 if (ring_is_rsc_enabled(rx_ring)) {
1492 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1493 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1494
1495 if (unlikely(rsc_enabled)) {
1496 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1497
1498 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1499 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1500
1501 /* update ntc based on RSC value */
1502 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1503 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1504 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1505 }
1506 }
1507
1508 /* if we are the last buffer then there is nothing else to do */
1509 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1510 return false;
1511
1512 /* place skb in next buffer to be received */
1513 rx_ring->rx_buffer_info[ntc].skb = skb;
1514 rx_ring->rx_stats.non_eop_descs++;
1515
1516 return true;
1517 }
1518
1519 /**
1520 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1521 * @rx_ring: rx descriptor ring packet is being transacted on
1522 * @skb: pointer to current skb being adjusted
1523 *
1524 * This function is an ixgbe specific version of __pskb_pull_tail. The
1525 * main difference between this version and the original function is that
1526 * this function can make several assumptions about the state of things
1527 * that allow for significant optimizations versus the standard function.
1528 * As a result we can do things like drop a frag and maintain an accurate
1529 * truesize for the skb.
1530 */
1531 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1532 struct sk_buff *skb)
1533 {
1534 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1535 unsigned char *va;
1536 unsigned int pull_len;
1537
1538 /*
1539 * it is valid to use page_address instead of kmap since we are
1540 * working with pages allocated out of the lomem pool per
1541 * alloc_page(GFP_ATOMIC)
1542 */
1543 va = skb_frag_address(frag);
1544
1545 /*
1546 * we need the header to contain the greater of either ETH_HLEN or
1547 * 60 bytes if the skb->len is less than 60 for skb_pad.
1548 */
1549 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1550
1551 /* align pull length to size of long to optimize memcpy performance */
1552 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1553
1554 /* update all of the pointers */
1555 skb_frag_size_sub(frag, pull_len);
1556 frag->page_offset += pull_len;
1557 skb->data_len -= pull_len;
1558 skb->tail += pull_len;
1559 }
1560
1561 /**
1562 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1563 * @rx_ring: rx descriptor ring packet is being transacted on
1564 * @skb: pointer to current skb being updated
1565 *
1566 * This function provides a basic DMA sync up for the first fragment of an
1567 * skb. The reason for doing this is that the first fragment cannot be
1568 * unmapped until we have reached the end of packet descriptor for a buffer
1569 * chain.
1570 */
1571 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1572 struct sk_buff *skb)
1573 {
1574 /* if the page was released unmap it, else just sync our portion */
1575 if (unlikely(IXGBE_CB(skb)->page_released)) {
1576 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1577 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1578 IXGBE_CB(skb)->page_released = false;
1579 } else {
1580 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1581
1582 dma_sync_single_range_for_cpu(rx_ring->dev,
1583 IXGBE_CB(skb)->dma,
1584 frag->page_offset,
1585 ixgbe_rx_bufsz(rx_ring),
1586 DMA_FROM_DEVICE);
1587 }
1588 IXGBE_CB(skb)->dma = 0;
1589 }
1590
1591 /**
1592 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1593 * @rx_ring: rx descriptor ring packet is being transacted on
1594 * @rx_desc: pointer to the EOP Rx descriptor
1595 * @skb: pointer to current skb being fixed
1596 *
1597 * Check for corrupted packet headers caused by senders on the local L2
1598 * embedded NIC switch not setting up their Tx Descriptors right. These
1599 * should be very rare.
1600 *
1601 * Also address the case where we are pulling data in on pages only
1602 * and as such no data is present in the skb header.
1603 *
1604 * In addition if skb is not at least 60 bytes we need to pad it so that
1605 * it is large enough to qualify as a valid Ethernet frame.
1606 *
1607 * Returns true if an error was encountered and skb was freed.
1608 **/
1609 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1610 union ixgbe_adv_rx_desc *rx_desc,
1611 struct sk_buff *skb)
1612 {
1613 struct net_device *netdev = rx_ring->netdev;
1614
1615 /* verify that the packet does not have any known errors */
1616 if (unlikely(ixgbe_test_staterr(rx_desc,
1617 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1618 !(netdev->features & NETIF_F_RXALL))) {
1619 dev_kfree_skb_any(skb);
1620 return true;
1621 }
1622
1623 /* place header in linear portion of buffer */
1624 if (skb_is_nonlinear(skb))
1625 ixgbe_pull_tail(rx_ring, skb);
1626
1627 #ifdef IXGBE_FCOE
1628 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1629 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1630 return false;
1631
1632 #endif
1633 /* if skb_pad returns an error the skb was freed */
1634 if (unlikely(skb->len < 60)) {
1635 int pad_len = 60 - skb->len;
1636
1637 if (skb_pad(skb, pad_len))
1638 return true;
1639 __skb_put(skb, pad_len);
1640 }
1641
1642 return false;
1643 }
1644
1645 /**
1646 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1647 * @rx_ring: rx descriptor ring to store buffers on
1648 * @old_buff: donor buffer to have page reused
1649 *
1650 * Synchronizes page for reuse by the adapter
1651 **/
1652 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1653 struct ixgbe_rx_buffer *old_buff)
1654 {
1655 struct ixgbe_rx_buffer *new_buff;
1656 u16 nta = rx_ring->next_to_alloc;
1657
1658 new_buff = &rx_ring->rx_buffer_info[nta];
1659
1660 /* update, and store next to alloc */
1661 nta++;
1662 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1663
1664 /* transfer page from old buffer to new buffer */
1665 new_buff->page = old_buff->page;
1666 new_buff->dma = old_buff->dma;
1667 new_buff->page_offset = old_buff->page_offset;
1668
1669 /* sync the buffer for use by the device */
1670 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1671 new_buff->page_offset,
1672 ixgbe_rx_bufsz(rx_ring),
1673 DMA_FROM_DEVICE);
1674 }
1675
1676 /**
1677 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1678 * @rx_ring: rx descriptor ring to transact packets on
1679 * @rx_buffer: buffer containing page to add
1680 * @rx_desc: descriptor containing length of buffer written by hardware
1681 * @skb: sk_buff to place the data into
1682 *
1683 * This function will add the data contained in rx_buffer->page to the skb.
1684 * This is done either through a direct copy if the data in the buffer is
1685 * less than the skb header size, otherwise it will just attach the page as
1686 * a frag to the skb.
1687 *
1688 * The function will then update the page offset if necessary and return
1689 * true if the buffer can be reused by the adapter.
1690 **/
1691 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1692 struct ixgbe_rx_buffer *rx_buffer,
1693 union ixgbe_adv_rx_desc *rx_desc,
1694 struct sk_buff *skb)
1695 {
1696 struct page *page = rx_buffer->page;
1697 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1698 #if (PAGE_SIZE < 8192)
1699 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1700 #else
1701 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1702 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1703 ixgbe_rx_bufsz(rx_ring);
1704 #endif
1705
1706 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1707 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1708
1709 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1710
1711 /* we can reuse buffer as-is, just make sure it is local */
1712 if (likely(page_to_nid(page) == numa_node_id()))
1713 return true;
1714
1715 /* this page cannot be reused so discard it */
1716 put_page(page);
1717 return false;
1718 }
1719
1720 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1721 rx_buffer->page_offset, size, truesize);
1722
1723 /* avoid re-using remote pages */
1724 if (unlikely(page_to_nid(page) != numa_node_id()))
1725 return false;
1726
1727 #if (PAGE_SIZE < 8192)
1728 /* if we are only owner of page we can reuse it */
1729 if (unlikely(page_count(page) != 1))
1730 return false;
1731
1732 /* flip page offset to other buffer */
1733 rx_buffer->page_offset ^= truesize;
1734
1735 /*
1736 * since we are the only owner of the page and we need to
1737 * increment it, just set the value to 2 in order to avoid
1738 * an unecessary locked operation
1739 */
1740 atomic_set(&page->_count, 2);
1741 #else
1742 /* move offset up to the next cache line */
1743 rx_buffer->page_offset += truesize;
1744
1745 if (rx_buffer->page_offset > last_offset)
1746 return false;
1747
1748 /* bump ref count on page before it is given to the stack */
1749 get_page(page);
1750 #endif
1751
1752 return true;
1753 }
1754
1755 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1756 union ixgbe_adv_rx_desc *rx_desc)
1757 {
1758 struct ixgbe_rx_buffer *rx_buffer;
1759 struct sk_buff *skb;
1760 struct page *page;
1761
1762 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1763 page = rx_buffer->page;
1764 prefetchw(page);
1765
1766 skb = rx_buffer->skb;
1767
1768 if (likely(!skb)) {
1769 void *page_addr = page_address(page) +
1770 rx_buffer->page_offset;
1771
1772 /* prefetch first cache line of first page */
1773 prefetch(page_addr);
1774 #if L1_CACHE_BYTES < 128
1775 prefetch(page_addr + L1_CACHE_BYTES);
1776 #endif
1777
1778 /* allocate a skb to store the frags */
1779 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1780 IXGBE_RX_HDR_SIZE);
1781 if (unlikely(!skb)) {
1782 rx_ring->rx_stats.alloc_rx_buff_failed++;
1783 return NULL;
1784 }
1785
1786 /*
1787 * we will be copying header into skb->data in
1788 * pskb_may_pull so it is in our interest to prefetch
1789 * it now to avoid a possible cache miss
1790 */
1791 prefetchw(skb->data);
1792
1793 /*
1794 * Delay unmapping of the first packet. It carries the
1795 * header information, HW may still access the header
1796 * after the writeback. Only unmap it when EOP is
1797 * reached
1798 */
1799 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1800 goto dma_sync;
1801
1802 IXGBE_CB(skb)->dma = rx_buffer->dma;
1803 } else {
1804 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1805 ixgbe_dma_sync_frag(rx_ring, skb);
1806
1807 dma_sync:
1808 /* we are reusing so sync this buffer for CPU use */
1809 dma_sync_single_range_for_cpu(rx_ring->dev,
1810 rx_buffer->dma,
1811 rx_buffer->page_offset,
1812 ixgbe_rx_bufsz(rx_ring),
1813 DMA_FROM_DEVICE);
1814 }
1815
1816 /* pull page into skb */
1817 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1818 /* hand second half of page back to the ring */
1819 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1820 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1821 /* the page has been released from the ring */
1822 IXGBE_CB(skb)->page_released = true;
1823 } else {
1824 /* we are not reusing the buffer so unmap it */
1825 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1826 ixgbe_rx_pg_size(rx_ring),
1827 DMA_FROM_DEVICE);
1828 }
1829
1830 /* clear contents of buffer_info */
1831 rx_buffer->skb = NULL;
1832 rx_buffer->dma = 0;
1833 rx_buffer->page = NULL;
1834
1835 return skb;
1836 }
1837
1838 /**
1839 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1840 * @q_vector: structure containing interrupt and ring information
1841 * @rx_ring: rx descriptor ring to transact packets on
1842 * @budget: Total limit on number of packets to process
1843 *
1844 * This function provides a "bounce buffer" approach to Rx interrupt
1845 * processing. The advantage to this is that on systems that have
1846 * expensive overhead for IOMMU access this provides a means of avoiding
1847 * it by maintaining the mapping of the page to the syste.
1848 *
1849 * Returns true if all work is completed without reaching budget
1850 **/
1851 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1852 struct ixgbe_ring *rx_ring,
1853 const int budget)
1854 {
1855 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1856 #ifdef IXGBE_FCOE
1857 struct ixgbe_adapter *adapter = q_vector->adapter;
1858 int ddp_bytes;
1859 unsigned int mss = 0;
1860 #endif /* IXGBE_FCOE */
1861 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1862
1863 do {
1864 union ixgbe_adv_rx_desc *rx_desc;
1865 struct sk_buff *skb;
1866
1867 /* return some buffers to hardware, one at a time is too slow */
1868 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1869 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1870 cleaned_count = 0;
1871 }
1872
1873 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1874
1875 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1876 break;
1877
1878 /*
1879 * This memory barrier is needed to keep us from reading
1880 * any other fields out of the rx_desc until we know the
1881 * RXD_STAT_DD bit is set
1882 */
1883 rmb();
1884
1885 /* retrieve a buffer from the ring */
1886 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1887
1888 /* exit if we failed to retrieve a buffer */
1889 if (!skb)
1890 break;
1891
1892 cleaned_count++;
1893
1894 /* place incomplete frames back on ring for completion */
1895 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1896 continue;
1897
1898 /* verify the packet layout is correct */
1899 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1900 continue;
1901
1902 /* probably a little skewed due to removing CRC */
1903 total_rx_bytes += skb->len;
1904
1905 /* populate checksum, timestamp, VLAN, and protocol */
1906 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1907
1908 #ifdef IXGBE_FCOE
1909 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1910 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1911 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1912 /* include DDPed FCoE data */
1913 if (ddp_bytes > 0) {
1914 if (!mss) {
1915 mss = rx_ring->netdev->mtu -
1916 sizeof(struct fcoe_hdr) -
1917 sizeof(struct fc_frame_header) -
1918 sizeof(struct fcoe_crc_eof);
1919 if (mss > 512)
1920 mss &= ~511;
1921 }
1922 total_rx_bytes += ddp_bytes;
1923 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1924 mss);
1925 }
1926 if (!ddp_bytes) {
1927 dev_kfree_skb_any(skb);
1928 continue;
1929 }
1930 }
1931
1932 #endif /* IXGBE_FCOE */
1933 ixgbe_rx_skb(q_vector, skb);
1934
1935 /* update budget accounting */
1936 total_rx_packets++;
1937 } while (likely(total_rx_packets < budget));
1938
1939 u64_stats_update_begin(&rx_ring->syncp);
1940 rx_ring->stats.packets += total_rx_packets;
1941 rx_ring->stats.bytes += total_rx_bytes;
1942 u64_stats_update_end(&rx_ring->syncp);
1943 q_vector->rx.total_packets += total_rx_packets;
1944 q_vector->rx.total_bytes += total_rx_bytes;
1945
1946 if (cleaned_count)
1947 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1948
1949 return (total_rx_packets < budget);
1950 }
1951
1952 /**
1953 * ixgbe_configure_msix - Configure MSI-X hardware
1954 * @adapter: board private structure
1955 *
1956 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1957 * interrupts.
1958 **/
1959 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1960 {
1961 struct ixgbe_q_vector *q_vector;
1962 int v_idx;
1963 u32 mask;
1964
1965 /* Populate MSIX to EITR Select */
1966 if (adapter->num_vfs > 32) {
1967 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1969 }
1970
1971 /*
1972 * Populate the IVAR table and set the ITR values to the
1973 * corresponding register.
1974 */
1975 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1976 struct ixgbe_ring *ring;
1977 q_vector = adapter->q_vector[v_idx];
1978
1979 ixgbe_for_each_ring(ring, q_vector->rx)
1980 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1981
1982 ixgbe_for_each_ring(ring, q_vector->tx)
1983 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1984
1985 ixgbe_write_eitr(q_vector);
1986 }
1987
1988 switch (adapter->hw.mac.type) {
1989 case ixgbe_mac_82598EB:
1990 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1991 v_idx);
1992 break;
1993 case ixgbe_mac_82599EB:
1994 case ixgbe_mac_X540:
1995 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1996 break;
1997 default:
1998 break;
1999 }
2000 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2001
2002 /* set up to autoclear timer, and the vectors */
2003 mask = IXGBE_EIMS_ENABLE_MASK;
2004 mask &= ~(IXGBE_EIMS_OTHER |
2005 IXGBE_EIMS_MAILBOX |
2006 IXGBE_EIMS_LSC);
2007
2008 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2009 }
2010
2011 enum latency_range {
2012 lowest_latency = 0,
2013 low_latency = 1,
2014 bulk_latency = 2,
2015 latency_invalid = 255
2016 };
2017
2018 /**
2019 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2020 * @q_vector: structure containing interrupt and ring information
2021 * @ring_container: structure containing ring performance data
2022 *
2023 * Stores a new ITR value based on packets and byte
2024 * counts during the last interrupt. The advantage of per interrupt
2025 * computation is faster updates and more accurate ITR for the current
2026 * traffic pattern. Constants in this function were computed
2027 * based on theoretical maximum wire speed and thresholds were set based
2028 * on testing data as well as attempting to minimize response time
2029 * while increasing bulk throughput.
2030 * this functionality is controlled by the InterruptThrottleRate module
2031 * parameter (see ixgbe_param.c)
2032 **/
2033 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2034 struct ixgbe_ring_container *ring_container)
2035 {
2036 int bytes = ring_container->total_bytes;
2037 int packets = ring_container->total_packets;
2038 u32 timepassed_us;
2039 u64 bytes_perint;
2040 u8 itr_setting = ring_container->itr;
2041
2042 if (packets == 0)
2043 return;
2044
2045 /* simple throttlerate management
2046 * 0-10MB/s lowest (100000 ints/s)
2047 * 10-20MB/s low (20000 ints/s)
2048 * 20-1249MB/s bulk (8000 ints/s)
2049 */
2050 /* what was last interrupt timeslice? */
2051 timepassed_us = q_vector->itr >> 2;
2052 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2053
2054 switch (itr_setting) {
2055 case lowest_latency:
2056 if (bytes_perint > 10)
2057 itr_setting = low_latency;
2058 break;
2059 case low_latency:
2060 if (bytes_perint > 20)
2061 itr_setting = bulk_latency;
2062 else if (bytes_perint <= 10)
2063 itr_setting = lowest_latency;
2064 break;
2065 case bulk_latency:
2066 if (bytes_perint <= 20)
2067 itr_setting = low_latency;
2068 break;
2069 }
2070
2071 /* clear work counters since we have the values we need */
2072 ring_container->total_bytes = 0;
2073 ring_container->total_packets = 0;
2074
2075 /* write updated itr to ring container */
2076 ring_container->itr = itr_setting;
2077 }
2078
2079 /**
2080 * ixgbe_write_eitr - write EITR register in hardware specific way
2081 * @q_vector: structure containing interrupt and ring information
2082 *
2083 * This function is made to be called by ethtool and by the driver
2084 * when it needs to update EITR registers at runtime. Hardware
2085 * specific quirks/differences are taken care of here.
2086 */
2087 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2088 {
2089 struct ixgbe_adapter *adapter = q_vector->adapter;
2090 struct ixgbe_hw *hw = &adapter->hw;
2091 int v_idx = q_vector->v_idx;
2092 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2093
2094 switch (adapter->hw.mac.type) {
2095 case ixgbe_mac_82598EB:
2096 /* must write high and low 16 bits to reset counter */
2097 itr_reg |= (itr_reg << 16);
2098 break;
2099 case ixgbe_mac_82599EB:
2100 case ixgbe_mac_X540:
2101 /*
2102 * set the WDIS bit to not clear the timer bits and cause an
2103 * immediate assertion of the interrupt
2104 */
2105 itr_reg |= IXGBE_EITR_CNT_WDIS;
2106 break;
2107 default:
2108 break;
2109 }
2110 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2111 }
2112
2113 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2114 {
2115 u32 new_itr = q_vector->itr;
2116 u8 current_itr;
2117
2118 ixgbe_update_itr(q_vector, &q_vector->tx);
2119 ixgbe_update_itr(q_vector, &q_vector->rx);
2120
2121 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2122
2123 switch (current_itr) {
2124 /* counts and packets in update_itr are dependent on these numbers */
2125 case lowest_latency:
2126 new_itr = IXGBE_100K_ITR;
2127 break;
2128 case low_latency:
2129 new_itr = IXGBE_20K_ITR;
2130 break;
2131 case bulk_latency:
2132 new_itr = IXGBE_8K_ITR;
2133 break;
2134 default:
2135 break;
2136 }
2137
2138 if (new_itr != q_vector->itr) {
2139 /* do an exponential smoothing */
2140 new_itr = (10 * new_itr * q_vector->itr) /
2141 ((9 * new_itr) + q_vector->itr);
2142
2143 /* save the algorithm value here */
2144 q_vector->itr = new_itr;
2145
2146 ixgbe_write_eitr(q_vector);
2147 }
2148 }
2149
2150 /**
2151 * ixgbe_check_overtemp_subtask - check for over temperature
2152 * @adapter: pointer to adapter
2153 **/
2154 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2155 {
2156 struct ixgbe_hw *hw = &adapter->hw;
2157 u32 eicr = adapter->interrupt_event;
2158
2159 if (test_bit(__IXGBE_DOWN, &adapter->state))
2160 return;
2161
2162 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2163 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2164 return;
2165
2166 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2167
2168 switch (hw->device_id) {
2169 case IXGBE_DEV_ID_82599_T3_LOM:
2170 /*
2171 * Since the warning interrupt is for both ports
2172 * we don't have to check if:
2173 * - This interrupt wasn't for our port.
2174 * - We may have missed the interrupt so always have to
2175 * check if we got a LSC
2176 */
2177 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2178 !(eicr & IXGBE_EICR_LSC))
2179 return;
2180
2181 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2182 u32 speed;
2183 bool link_up = false;
2184
2185 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2186
2187 if (link_up)
2188 return;
2189 }
2190
2191 /* Check if this is not due to overtemp */
2192 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2193 return;
2194
2195 break;
2196 default:
2197 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2198 return;
2199 break;
2200 }
2201 e_crit(drv,
2202 "Network adapter has been stopped because it has over heated. "
2203 "Restart the computer. If the problem persists, "
2204 "power off the system and replace the adapter\n");
2205
2206 adapter->interrupt_event = 0;
2207 }
2208
2209 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2210 {
2211 struct ixgbe_hw *hw = &adapter->hw;
2212
2213 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2214 (eicr & IXGBE_EICR_GPI_SDP1)) {
2215 e_crit(probe, "Fan has stopped, replace the adapter\n");
2216 /* write to clear the interrupt */
2217 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2218 }
2219 }
2220
2221 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2222 {
2223 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2224 return;
2225
2226 switch (adapter->hw.mac.type) {
2227 case ixgbe_mac_82599EB:
2228 /*
2229 * Need to check link state so complete overtemp check
2230 * on service task
2231 */
2232 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2233 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2234 adapter->interrupt_event = eicr;
2235 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2236 ixgbe_service_event_schedule(adapter);
2237 return;
2238 }
2239 return;
2240 case ixgbe_mac_X540:
2241 if (!(eicr & IXGBE_EICR_TS))
2242 return;
2243 break;
2244 default:
2245 return;
2246 }
2247
2248 e_crit(drv,
2249 "Network adapter has been stopped because it has over heated. "
2250 "Restart the computer. If the problem persists, "
2251 "power off the system and replace the adapter\n");
2252 }
2253
2254 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2255 {
2256 struct ixgbe_hw *hw = &adapter->hw;
2257
2258 if (eicr & IXGBE_EICR_GPI_SDP2) {
2259 /* Clear the interrupt */
2260 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2261 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2262 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2263 ixgbe_service_event_schedule(adapter);
2264 }
2265 }
2266
2267 if (eicr & IXGBE_EICR_GPI_SDP1) {
2268 /* Clear the interrupt */
2269 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2270 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2271 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2272 ixgbe_service_event_schedule(adapter);
2273 }
2274 }
2275 }
2276
2277 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2278 {
2279 struct ixgbe_hw *hw = &adapter->hw;
2280
2281 adapter->lsc_int++;
2282 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2283 adapter->link_check_timeout = jiffies;
2284 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2285 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2286 IXGBE_WRITE_FLUSH(hw);
2287 ixgbe_service_event_schedule(adapter);
2288 }
2289 }
2290
2291 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2292 u64 qmask)
2293 {
2294 u32 mask;
2295 struct ixgbe_hw *hw = &adapter->hw;
2296
2297 switch (hw->mac.type) {
2298 case ixgbe_mac_82598EB:
2299 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2300 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2301 break;
2302 case ixgbe_mac_82599EB:
2303 case ixgbe_mac_X540:
2304 mask = (qmask & 0xFFFFFFFF);
2305 if (mask)
2306 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2307 mask = (qmask >> 32);
2308 if (mask)
2309 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2310 break;
2311 default:
2312 break;
2313 }
2314 /* skip the flush */
2315 }
2316
2317 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2318 u64 qmask)
2319 {
2320 u32 mask;
2321 struct ixgbe_hw *hw = &adapter->hw;
2322
2323 switch (hw->mac.type) {
2324 case ixgbe_mac_82598EB:
2325 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2326 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2327 break;
2328 case ixgbe_mac_82599EB:
2329 case ixgbe_mac_X540:
2330 mask = (qmask & 0xFFFFFFFF);
2331 if (mask)
2332 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2333 mask = (qmask >> 32);
2334 if (mask)
2335 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2336 break;
2337 default:
2338 break;
2339 }
2340 /* skip the flush */
2341 }
2342
2343 /**
2344 * ixgbe_irq_enable - Enable default interrupt generation settings
2345 * @adapter: board private structure
2346 **/
2347 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2348 bool flush)
2349 {
2350 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2351
2352 /* don't reenable LSC while waiting for link */
2353 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2354 mask &= ~IXGBE_EIMS_LSC;
2355
2356 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2357 switch (adapter->hw.mac.type) {
2358 case ixgbe_mac_82599EB:
2359 mask |= IXGBE_EIMS_GPI_SDP0;
2360 break;
2361 case ixgbe_mac_X540:
2362 mask |= IXGBE_EIMS_TS;
2363 break;
2364 default:
2365 break;
2366 }
2367 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2368 mask |= IXGBE_EIMS_GPI_SDP1;
2369 switch (adapter->hw.mac.type) {
2370 case ixgbe_mac_82599EB:
2371 mask |= IXGBE_EIMS_GPI_SDP1;
2372 mask |= IXGBE_EIMS_GPI_SDP2;
2373 case ixgbe_mac_X540:
2374 mask |= IXGBE_EIMS_ECC;
2375 mask |= IXGBE_EIMS_MAILBOX;
2376 break;
2377 default:
2378 break;
2379 }
2380
2381 if (adapter->hw.mac.type == ixgbe_mac_X540)
2382 mask |= IXGBE_EIMS_TIMESYNC;
2383
2384 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2385 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2386 mask |= IXGBE_EIMS_FLOW_DIR;
2387
2388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2389 if (queues)
2390 ixgbe_irq_enable_queues(adapter, ~0);
2391 if (flush)
2392 IXGBE_WRITE_FLUSH(&adapter->hw);
2393 }
2394
2395 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2396 {
2397 struct ixgbe_adapter *adapter = data;
2398 struct ixgbe_hw *hw = &adapter->hw;
2399 u32 eicr;
2400
2401 /*
2402 * Workaround for Silicon errata. Use clear-by-write instead
2403 * of clear-by-read. Reading with EICS will return the
2404 * interrupt causes without clearing, which later be done
2405 * with the write to EICR.
2406 */
2407 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2408 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2409
2410 if (eicr & IXGBE_EICR_LSC)
2411 ixgbe_check_lsc(adapter);
2412
2413 if (eicr & IXGBE_EICR_MAILBOX)
2414 ixgbe_msg_task(adapter);
2415
2416 switch (hw->mac.type) {
2417 case ixgbe_mac_82599EB:
2418 case ixgbe_mac_X540:
2419 if (eicr & IXGBE_EICR_ECC)
2420 e_info(link, "Received unrecoverable ECC Err, please "
2421 "reboot\n");
2422 /* Handle Flow Director Full threshold interrupt */
2423 if (eicr & IXGBE_EICR_FLOW_DIR) {
2424 int reinit_count = 0;
2425 int i;
2426 for (i = 0; i < adapter->num_tx_queues; i++) {
2427 struct ixgbe_ring *ring = adapter->tx_ring[i];
2428 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2429 &ring->state))
2430 reinit_count++;
2431 }
2432 if (reinit_count) {
2433 /* no more flow director interrupts until after init */
2434 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2435 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2436 ixgbe_service_event_schedule(adapter);
2437 }
2438 }
2439 ixgbe_check_sfp_event(adapter, eicr);
2440 ixgbe_check_overtemp_event(adapter, eicr);
2441 break;
2442 default:
2443 break;
2444 }
2445
2446 ixgbe_check_fan_failure(adapter, eicr);
2447
2448 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2449 ixgbe_ptp_check_pps_event(adapter, eicr);
2450
2451 /* re-enable the original interrupt state, no lsc, no queues */
2452 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2453 ixgbe_irq_enable(adapter, false, false);
2454
2455 return IRQ_HANDLED;
2456 }
2457
2458 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2459 {
2460 struct ixgbe_q_vector *q_vector = data;
2461
2462 /* EIAM disabled interrupts (on this vector) for us */
2463
2464 if (q_vector->rx.ring || q_vector->tx.ring)
2465 napi_schedule(&q_vector->napi);
2466
2467 return IRQ_HANDLED;
2468 }
2469
2470 /**
2471 * ixgbe_poll - NAPI Rx polling callback
2472 * @napi: structure for representing this polling device
2473 * @budget: how many packets driver is allowed to clean
2474 *
2475 * This function is used for legacy and MSI, NAPI mode
2476 **/
2477 int ixgbe_poll(struct napi_struct *napi, int budget)
2478 {
2479 struct ixgbe_q_vector *q_vector =
2480 container_of(napi, struct ixgbe_q_vector, napi);
2481 struct ixgbe_adapter *adapter = q_vector->adapter;
2482 struct ixgbe_ring *ring;
2483 int per_ring_budget;
2484 bool clean_complete = true;
2485
2486 #ifdef CONFIG_IXGBE_DCA
2487 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2488 ixgbe_update_dca(q_vector);
2489 #endif
2490
2491 ixgbe_for_each_ring(ring, q_vector->tx)
2492 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2493
2494 /* attempt to distribute budget to each queue fairly, but don't allow
2495 * the budget to go below 1 because we'll exit polling */
2496 if (q_vector->rx.count > 1)
2497 per_ring_budget = max(budget/q_vector->rx.count, 1);
2498 else
2499 per_ring_budget = budget;
2500
2501 ixgbe_for_each_ring(ring, q_vector->rx)
2502 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2503 per_ring_budget);
2504
2505 /* If all work not completed, return budget and keep polling */
2506 if (!clean_complete)
2507 return budget;
2508
2509 /* all work done, exit the polling mode */
2510 napi_complete(napi);
2511 if (adapter->rx_itr_setting & 1)
2512 ixgbe_set_itr(q_vector);
2513 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2514 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2515
2516 return 0;
2517 }
2518
2519 /**
2520 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2521 * @adapter: board private structure
2522 *
2523 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2524 * interrupts from the kernel.
2525 **/
2526 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2527 {
2528 struct net_device *netdev = adapter->netdev;
2529 int vector, err;
2530 int ri = 0, ti = 0;
2531
2532 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2533 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2534 struct msix_entry *entry = &adapter->msix_entries[vector];
2535
2536 if (q_vector->tx.ring && q_vector->rx.ring) {
2537 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2538 "%s-%s-%d", netdev->name, "TxRx", ri++);
2539 ti++;
2540 } else if (q_vector->rx.ring) {
2541 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2542 "%s-%s-%d", netdev->name, "rx", ri++);
2543 } else if (q_vector->tx.ring) {
2544 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2545 "%s-%s-%d", netdev->name, "tx", ti++);
2546 } else {
2547 /* skip this unused q_vector */
2548 continue;
2549 }
2550 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2551 q_vector->name, q_vector);
2552 if (err) {
2553 e_err(probe, "request_irq failed for MSIX interrupt "
2554 "Error: %d\n", err);
2555 goto free_queue_irqs;
2556 }
2557 /* If Flow Director is enabled, set interrupt affinity */
2558 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2559 /* assign the mask for this irq */
2560 irq_set_affinity_hint(entry->vector,
2561 &q_vector->affinity_mask);
2562 }
2563 }
2564
2565 err = request_irq(adapter->msix_entries[vector].vector,
2566 ixgbe_msix_other, 0, netdev->name, adapter);
2567 if (err) {
2568 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2569 goto free_queue_irqs;
2570 }
2571
2572 return 0;
2573
2574 free_queue_irqs:
2575 while (vector) {
2576 vector--;
2577 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2578 NULL);
2579 free_irq(adapter->msix_entries[vector].vector,
2580 adapter->q_vector[vector]);
2581 }
2582 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2583 pci_disable_msix(adapter->pdev);
2584 kfree(adapter->msix_entries);
2585 adapter->msix_entries = NULL;
2586 return err;
2587 }
2588
2589 /**
2590 * ixgbe_intr - legacy mode Interrupt Handler
2591 * @irq: interrupt number
2592 * @data: pointer to a network interface device structure
2593 **/
2594 static irqreturn_t ixgbe_intr(int irq, void *data)
2595 {
2596 struct ixgbe_adapter *adapter = data;
2597 struct ixgbe_hw *hw = &adapter->hw;
2598 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2599 u32 eicr;
2600
2601 /*
2602 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2603 * before the read of EICR.
2604 */
2605 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2606
2607 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2608 * therefore no explicit interrupt disable is necessary */
2609 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2610 if (!eicr) {
2611 /*
2612 * shared interrupt alert!
2613 * make sure interrupts are enabled because the read will
2614 * have disabled interrupts due to EIAM
2615 * finish the workaround of silicon errata on 82598. Unmask
2616 * the interrupt that we masked before the EICR read.
2617 */
2618 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2619 ixgbe_irq_enable(adapter, true, true);
2620 return IRQ_NONE; /* Not our interrupt */
2621 }
2622
2623 if (eicr & IXGBE_EICR_LSC)
2624 ixgbe_check_lsc(adapter);
2625
2626 switch (hw->mac.type) {
2627 case ixgbe_mac_82599EB:
2628 ixgbe_check_sfp_event(adapter, eicr);
2629 /* Fall through */
2630 case ixgbe_mac_X540:
2631 if (eicr & IXGBE_EICR_ECC)
2632 e_info(link, "Received unrecoverable ECC err, please "
2633 "reboot\n");
2634 ixgbe_check_overtemp_event(adapter, eicr);
2635 break;
2636 default:
2637 break;
2638 }
2639
2640 ixgbe_check_fan_failure(adapter, eicr);
2641 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2642 ixgbe_ptp_check_pps_event(adapter, eicr);
2643
2644 /* would disable interrupts here but EIAM disabled it */
2645 napi_schedule(&q_vector->napi);
2646
2647 /*
2648 * re-enable link(maybe) and non-queue interrupts, no flush.
2649 * ixgbe_poll will re-enable the queue interrupts
2650 */
2651 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2652 ixgbe_irq_enable(adapter, false, false);
2653
2654 return IRQ_HANDLED;
2655 }
2656
2657 /**
2658 * ixgbe_request_irq - initialize interrupts
2659 * @adapter: board private structure
2660 *
2661 * Attempts to configure interrupts using the best available
2662 * capabilities of the hardware and kernel.
2663 **/
2664 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2665 {
2666 struct net_device *netdev = adapter->netdev;
2667 int err;
2668
2669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2670 err = ixgbe_request_msix_irqs(adapter);
2671 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2672 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2673 netdev->name, adapter);
2674 else
2675 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2676 netdev->name, adapter);
2677
2678 if (err)
2679 e_err(probe, "request_irq failed, Error %d\n", err);
2680
2681 return err;
2682 }
2683
2684 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2685 {
2686 int vector;
2687
2688 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2689 free_irq(adapter->pdev->irq, adapter);
2690 return;
2691 }
2692
2693 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2694 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2695 struct msix_entry *entry = &adapter->msix_entries[vector];
2696
2697 /* free only the irqs that were actually requested */
2698 if (!q_vector->rx.ring && !q_vector->tx.ring)
2699 continue;
2700
2701 /* clear the affinity_mask in the IRQ descriptor */
2702 irq_set_affinity_hint(entry->vector, NULL);
2703
2704 free_irq(entry->vector, q_vector);
2705 }
2706
2707 free_irq(adapter->msix_entries[vector++].vector, adapter);
2708 }
2709
2710 /**
2711 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2712 * @adapter: board private structure
2713 **/
2714 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2715 {
2716 switch (adapter->hw.mac.type) {
2717 case ixgbe_mac_82598EB:
2718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2719 break;
2720 case ixgbe_mac_82599EB:
2721 case ixgbe_mac_X540:
2722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2725 break;
2726 default:
2727 break;
2728 }
2729 IXGBE_WRITE_FLUSH(&adapter->hw);
2730 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2731 int vector;
2732
2733 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2734 synchronize_irq(adapter->msix_entries[vector].vector);
2735
2736 synchronize_irq(adapter->msix_entries[vector++].vector);
2737 } else {
2738 synchronize_irq(adapter->pdev->irq);
2739 }
2740 }
2741
2742 /**
2743 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2744 *
2745 **/
2746 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2747 {
2748 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2749
2750 ixgbe_write_eitr(q_vector);
2751
2752 ixgbe_set_ivar(adapter, 0, 0, 0);
2753 ixgbe_set_ivar(adapter, 1, 0, 0);
2754
2755 e_info(hw, "Legacy interrupt IVAR setup done\n");
2756 }
2757
2758 /**
2759 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2760 * @adapter: board private structure
2761 * @ring: structure containing ring specific data
2762 *
2763 * Configure the Tx descriptor ring after a reset.
2764 **/
2765 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2766 struct ixgbe_ring *ring)
2767 {
2768 struct ixgbe_hw *hw = &adapter->hw;
2769 u64 tdba = ring->dma;
2770 int wait_loop = 10;
2771 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2772 u8 reg_idx = ring->reg_idx;
2773
2774 /* disable queue to avoid issues while updating state */
2775 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2776 IXGBE_WRITE_FLUSH(hw);
2777
2778 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2779 (tdba & DMA_BIT_MASK(32)));
2780 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2781 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2782 ring->count * sizeof(union ixgbe_adv_tx_desc));
2783 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2784 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2785 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2786
2787 /*
2788 * set WTHRESH to encourage burst writeback, it should not be set
2789 * higher than 1 when ITR is 0 as it could cause false TX hangs
2790 *
2791 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2792 * to or less than the number of on chip descriptors, which is
2793 * currently 40.
2794 */
2795 if (!ring->q_vector || (ring->q_vector->itr < 8))
2796 txdctl |= (1 << 16); /* WTHRESH = 1 */
2797 else
2798 txdctl |= (8 << 16); /* WTHRESH = 8 */
2799
2800 /*
2801 * Setting PTHRESH to 32 both improves performance
2802 * and avoids a TX hang with DFP enabled
2803 */
2804 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2805 32; /* PTHRESH = 32 */
2806
2807 /* reinitialize flowdirector state */
2808 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2809 ring->atr_sample_rate = adapter->atr_sample_rate;
2810 ring->atr_count = 0;
2811 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2812 } else {
2813 ring->atr_sample_rate = 0;
2814 }
2815
2816 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2817
2818 /* enable queue */
2819 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2820
2821 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2822 if (hw->mac.type == ixgbe_mac_82598EB &&
2823 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2824 return;
2825
2826 /* poll to verify queue is enabled */
2827 do {
2828 usleep_range(1000, 2000);
2829 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2830 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2831 if (!wait_loop)
2832 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2833 }
2834
2835 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2836 {
2837 struct ixgbe_hw *hw = &adapter->hw;
2838 u32 rttdcs, mtqc;
2839 u8 tcs = netdev_get_num_tc(adapter->netdev);
2840
2841 if (hw->mac.type == ixgbe_mac_82598EB)
2842 return;
2843
2844 /* disable the arbiter while setting MTQC */
2845 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2846 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2847 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2848
2849 /* set transmit pool layout */
2850 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2851 mtqc = IXGBE_MTQC_VT_ENA;
2852 if (tcs > 4)
2853 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2854 else if (tcs > 1)
2855 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2856 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2857 mtqc |= IXGBE_MTQC_32VF;
2858 else
2859 mtqc |= IXGBE_MTQC_64VF;
2860 } else {
2861 if (tcs > 4)
2862 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2863 else if (tcs > 1)
2864 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2865 else
2866 mtqc = IXGBE_MTQC_64Q_1PB;
2867 }
2868
2869 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2870
2871 /* Enable Security TX Buffer IFG for multiple pb */
2872 if (tcs) {
2873 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2874 sectx |= IXGBE_SECTX_DCB;
2875 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2876 }
2877
2878 /* re-enable the arbiter */
2879 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2880 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2881 }
2882
2883 /**
2884 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2885 * @adapter: board private structure
2886 *
2887 * Configure the Tx unit of the MAC after a reset.
2888 **/
2889 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2890 {
2891 struct ixgbe_hw *hw = &adapter->hw;
2892 u32 dmatxctl;
2893 u32 i;
2894
2895 ixgbe_setup_mtqc(adapter);
2896
2897 if (hw->mac.type != ixgbe_mac_82598EB) {
2898 /* DMATXCTL.EN must be before Tx queues are enabled */
2899 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2900 dmatxctl |= IXGBE_DMATXCTL_TE;
2901 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2902 }
2903
2904 /* Setup the HW Tx Head and Tail descriptor pointers */
2905 for (i = 0; i < adapter->num_tx_queues; i++)
2906 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2907 }
2908
2909 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2910 struct ixgbe_ring *ring)
2911 {
2912 struct ixgbe_hw *hw = &adapter->hw;
2913 u8 reg_idx = ring->reg_idx;
2914 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2915
2916 srrctl |= IXGBE_SRRCTL_DROP_EN;
2917
2918 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2919 }
2920
2921 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2922 struct ixgbe_ring *ring)
2923 {
2924 struct ixgbe_hw *hw = &adapter->hw;
2925 u8 reg_idx = ring->reg_idx;
2926 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2927
2928 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2929
2930 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2931 }
2932
2933 #ifdef CONFIG_IXGBE_DCB
2934 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2935 #else
2936 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2937 #endif
2938 {
2939 int i;
2940 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2941
2942 if (adapter->ixgbe_ieee_pfc)
2943 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2944
2945 /*
2946 * We should set the drop enable bit if:
2947 * SR-IOV is enabled
2948 * or
2949 * Number of Rx queues > 1 and flow control is disabled
2950 *
2951 * This allows us to avoid head of line blocking for security
2952 * and performance reasons.
2953 */
2954 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2955 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2956 for (i = 0; i < adapter->num_rx_queues; i++)
2957 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2958 } else {
2959 for (i = 0; i < adapter->num_rx_queues; i++)
2960 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2961 }
2962 }
2963
2964 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2965
2966 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2967 struct ixgbe_ring *rx_ring)
2968 {
2969 struct ixgbe_hw *hw = &adapter->hw;
2970 u32 srrctl;
2971 u8 reg_idx = rx_ring->reg_idx;
2972
2973 if (hw->mac.type == ixgbe_mac_82598EB) {
2974 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
2975
2976 /*
2977 * if VMDq is not active we must program one srrctl register
2978 * per RSS queue since we have enabled RDRXCTL.MVMEN
2979 */
2980 reg_idx &= mask;
2981 }
2982
2983 /* configure header buffer length, needed for RSC */
2984 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
2985
2986 /* configure the packet buffer length */
2987 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2988
2989 /* configure descriptor type */
2990 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2991
2992 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2993 }
2994
2995 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2996 {
2997 struct ixgbe_hw *hw = &adapter->hw;
2998 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2999 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3000 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3001 u32 mrqc = 0, reta = 0;
3002 u32 rxcsum;
3003 int i, j;
3004 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3005
3006 /*
3007 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3008 * make full use of any rings they may have. We will use the
3009 * PSRTYPE register to control how many rings we use within the PF.
3010 */
3011 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3012 rss_i = 2;
3013
3014 /* Fill out hash function seeds */
3015 for (i = 0; i < 10; i++)
3016 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3017
3018 /* Fill out redirection table */
3019 for (i = 0, j = 0; i < 128; i++, j++) {
3020 if (j == rss_i)
3021 j = 0;
3022 /* reta = 4-byte sliding window of
3023 * 0x00..(indices-1)(indices-1)00..etc. */
3024 reta = (reta << 8) | (j * 0x11);
3025 if ((i & 3) == 3)
3026 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3027 }
3028
3029 /* Disable indicating checksum in descriptor, enables RSS hash */
3030 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3031 rxcsum |= IXGBE_RXCSUM_PCSD;
3032 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3033
3034 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3035 if (adapter->ring_feature[RING_F_RSS].mask)
3036 mrqc = IXGBE_MRQC_RSSEN;
3037 } else {
3038 u8 tcs = netdev_get_num_tc(adapter->netdev);
3039
3040 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3041 if (tcs > 4)
3042 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3043 else if (tcs > 1)
3044 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3045 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3046 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3047 else
3048 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3049 } else {
3050 if (tcs > 4)
3051 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3052 else if (tcs > 1)
3053 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3054 else
3055 mrqc = IXGBE_MRQC_RSSEN;
3056 }
3057 }
3058
3059 /* Perform hash on these packet types */
3060 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3061 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3062 IXGBE_MRQC_RSS_FIELD_IPV6 |
3063 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3064
3065 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3066 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3067 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3068 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3069
3070 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3071 }
3072
3073 /**
3074 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3075 * @adapter: address of board private structure
3076 * @index: index of ring to set
3077 **/
3078 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3079 struct ixgbe_ring *ring)
3080 {
3081 struct ixgbe_hw *hw = &adapter->hw;
3082 u32 rscctrl;
3083 u8 reg_idx = ring->reg_idx;
3084
3085 if (!ring_is_rsc_enabled(ring))
3086 return;
3087
3088 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3089 rscctrl |= IXGBE_RSCCTL_RSCEN;
3090 /*
3091 * we must limit the number of descriptors so that the
3092 * total size of max desc * buf_len is not greater
3093 * than 65536
3094 */
3095 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3096 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3097 }
3098
3099 #define IXGBE_MAX_RX_DESC_POLL 10
3100 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3101 struct ixgbe_ring *ring)
3102 {
3103 struct ixgbe_hw *hw = &adapter->hw;
3104 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3105 u32 rxdctl;
3106 u8 reg_idx = ring->reg_idx;
3107
3108 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3109 if (hw->mac.type == ixgbe_mac_82598EB &&
3110 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3111 return;
3112
3113 do {
3114 usleep_range(1000, 2000);
3115 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3116 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3117
3118 if (!wait_loop) {
3119 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3120 "the polling period\n", reg_idx);
3121 }
3122 }
3123
3124 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3125 struct ixgbe_ring *ring)
3126 {
3127 struct ixgbe_hw *hw = &adapter->hw;
3128 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3129 u32 rxdctl;
3130 u8 reg_idx = ring->reg_idx;
3131
3132 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3133 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3134
3135 /* write value back with RXDCTL.ENABLE bit cleared */
3136 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3137
3138 if (hw->mac.type == ixgbe_mac_82598EB &&
3139 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3140 return;
3141
3142 /* the hardware may take up to 100us to really disable the rx queue */
3143 do {
3144 udelay(10);
3145 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3146 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3147
3148 if (!wait_loop) {
3149 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3150 "the polling period\n", reg_idx);
3151 }
3152 }
3153
3154 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3155 struct ixgbe_ring *ring)
3156 {
3157 struct ixgbe_hw *hw = &adapter->hw;
3158 u64 rdba = ring->dma;
3159 u32 rxdctl;
3160 u8 reg_idx = ring->reg_idx;
3161
3162 /* disable queue to avoid issues while updating state */
3163 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3164 ixgbe_disable_rx_queue(adapter, ring);
3165
3166 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3167 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3168 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3169 ring->count * sizeof(union ixgbe_adv_rx_desc));
3170 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3171 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3172 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3173
3174 ixgbe_configure_srrctl(adapter, ring);
3175 ixgbe_configure_rscctl(adapter, ring);
3176
3177 if (hw->mac.type == ixgbe_mac_82598EB) {
3178 /*
3179 * enable cache line friendly hardware writes:
3180 * PTHRESH=32 descriptors (half the internal cache),
3181 * this also removes ugly rx_no_buffer_count increment
3182 * HTHRESH=4 descriptors (to minimize latency on fetch)
3183 * WTHRESH=8 burst writeback up to two cache lines
3184 */
3185 rxdctl &= ~0x3FFFFF;
3186 rxdctl |= 0x080420;
3187 }
3188
3189 /* enable receive descriptor ring */
3190 rxdctl |= IXGBE_RXDCTL_ENABLE;
3191 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3192
3193 ixgbe_rx_desc_queue_enable(adapter, ring);
3194 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3195 }
3196
3197 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3198 {
3199 struct ixgbe_hw *hw = &adapter->hw;
3200 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3201 int p;
3202
3203 /* PSRTYPE must be initialized in non 82598 adapters */
3204 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3205 IXGBE_PSRTYPE_UDPHDR |
3206 IXGBE_PSRTYPE_IPV4HDR |
3207 IXGBE_PSRTYPE_L2HDR |
3208 IXGBE_PSRTYPE_IPV6HDR;
3209
3210 if (hw->mac.type == ixgbe_mac_82598EB)
3211 return;
3212
3213 if (rss_i > 3)
3214 psrtype |= 2 << 29;
3215 else if (rss_i > 1)
3216 psrtype |= 1 << 29;
3217
3218 for (p = 0; p < adapter->num_rx_pools; p++)
3219 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3220 psrtype);
3221 }
3222
3223 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3224 {
3225 struct ixgbe_hw *hw = &adapter->hw;
3226 u32 reg_offset, vf_shift;
3227 u32 gcr_ext, vmdctl;
3228 int i;
3229
3230 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3231 return;
3232
3233 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3234 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3235 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3236 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3237 vmdctl |= IXGBE_VT_CTL_REPLEN;
3238 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3239
3240 vf_shift = VMDQ_P(0) % 32;
3241 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3242
3243 /* Enable only the PF's pool for Tx/Rx */
3244 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3245 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3246 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3247 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3248 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3249 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3250
3251 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3252 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3253
3254 /*
3255 * Set up VF register offsets for selected VT Mode,
3256 * i.e. 32 or 64 VFs for SR-IOV
3257 */
3258 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3259 case IXGBE_82599_VMDQ_8Q_MASK:
3260 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3261 break;
3262 case IXGBE_82599_VMDQ_4Q_MASK:
3263 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3264 break;
3265 default:
3266 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3267 break;
3268 }
3269
3270 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3271
3272
3273 /* Enable MAC Anti-Spoofing */
3274 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3275 adapter->num_vfs);
3276 /* For VFs that have spoof checking turned off */
3277 for (i = 0; i < adapter->num_vfs; i++) {
3278 if (!adapter->vfinfo[i].spoofchk_enabled)
3279 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3280 }
3281 }
3282
3283 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3284 {
3285 struct ixgbe_hw *hw = &adapter->hw;
3286 struct net_device *netdev = adapter->netdev;
3287 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3288 struct ixgbe_ring *rx_ring;
3289 int i;
3290 u32 mhadd, hlreg0;
3291
3292 #ifdef IXGBE_FCOE
3293 /* adjust max frame to be able to do baby jumbo for FCoE */
3294 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3295 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3296 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3297
3298 #endif /* IXGBE_FCOE */
3299
3300 /* adjust max frame to be at least the size of a standard frame */
3301 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3302 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3303
3304 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3305 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3306 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3307 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3308
3309 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3310 }
3311
3312 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3313 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3314 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3315 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3316
3317 /*
3318 * Setup the HW Rx Head and Tail Descriptor Pointers and
3319 * the Base and Length of the Rx Descriptor Ring
3320 */
3321 for (i = 0; i < adapter->num_rx_queues; i++) {
3322 rx_ring = adapter->rx_ring[i];
3323 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3324 set_ring_rsc_enabled(rx_ring);
3325 else
3326 clear_ring_rsc_enabled(rx_ring);
3327 }
3328 }
3329
3330 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3331 {
3332 struct ixgbe_hw *hw = &adapter->hw;
3333 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3334
3335 switch (hw->mac.type) {
3336 case ixgbe_mac_82598EB:
3337 /*
3338 * For VMDq support of different descriptor types or
3339 * buffer sizes through the use of multiple SRRCTL
3340 * registers, RDRXCTL.MVMEN must be set to 1
3341 *
3342 * also, the manual doesn't mention it clearly but DCA hints
3343 * will only use queue 0's tags unless this bit is set. Side
3344 * effects of setting this bit are only that SRRCTL must be
3345 * fully programmed [0..15]
3346 */
3347 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3348 break;
3349 case ixgbe_mac_82599EB:
3350 case ixgbe_mac_X540:
3351 /* Disable RSC for ACK packets */
3352 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3353 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3354 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3355 /* hardware requires some bits to be set by default */
3356 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3357 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3358 break;
3359 default:
3360 /* We should do nothing since we don't know this hardware */
3361 return;
3362 }
3363
3364 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3365 }
3366
3367 /**
3368 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3369 * @adapter: board private structure
3370 *
3371 * Configure the Rx unit of the MAC after a reset.
3372 **/
3373 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3374 {
3375 struct ixgbe_hw *hw = &adapter->hw;
3376 int i;
3377 u32 rxctrl;
3378
3379 /* disable receives while setting up the descriptors */
3380 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3381 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3382
3383 ixgbe_setup_psrtype(adapter);
3384 ixgbe_setup_rdrxctl(adapter);
3385
3386 /* Program registers for the distribution of queues */
3387 ixgbe_setup_mrqc(adapter);
3388
3389 /* set_rx_buffer_len must be called before ring initialization */
3390 ixgbe_set_rx_buffer_len(adapter);
3391
3392 /*
3393 * Setup the HW Rx Head and Tail Descriptor Pointers and
3394 * the Base and Length of the Rx Descriptor Ring
3395 */
3396 for (i = 0; i < adapter->num_rx_queues; i++)
3397 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3398
3399 /* disable drop enable for 82598 parts */
3400 if (hw->mac.type == ixgbe_mac_82598EB)
3401 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3402
3403 /* enable all receives */
3404 rxctrl |= IXGBE_RXCTRL_RXEN;
3405 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3406 }
3407
3408 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3409 {
3410 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3411 struct ixgbe_hw *hw = &adapter->hw;
3412
3413 /* add VID to filter table */
3414 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3415 set_bit(vid, adapter->active_vlans);
3416
3417 return 0;
3418 }
3419
3420 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3421 {
3422 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3423 struct ixgbe_hw *hw = &adapter->hw;
3424
3425 /* remove VID from filter table */
3426 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3427 clear_bit(vid, adapter->active_vlans);
3428
3429 return 0;
3430 }
3431
3432 /**
3433 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3434 * @adapter: driver data
3435 */
3436 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3437 {
3438 struct ixgbe_hw *hw = &adapter->hw;
3439 u32 vlnctrl;
3440
3441 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3442 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3443 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3444 }
3445
3446 /**
3447 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3448 * @adapter: driver data
3449 */
3450 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3451 {
3452 struct ixgbe_hw *hw = &adapter->hw;
3453 u32 vlnctrl;
3454
3455 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3456 vlnctrl |= IXGBE_VLNCTRL_VFE;
3457 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3458 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3459 }
3460
3461 /**
3462 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3463 * @adapter: driver data
3464 */
3465 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3466 {
3467 struct ixgbe_hw *hw = &adapter->hw;
3468 u32 vlnctrl;
3469 int i, j;
3470
3471 switch (hw->mac.type) {
3472 case ixgbe_mac_82598EB:
3473 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3474 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3475 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3476 break;
3477 case ixgbe_mac_82599EB:
3478 case ixgbe_mac_X540:
3479 for (i = 0; i < adapter->num_rx_queues; i++) {
3480 j = adapter->rx_ring[i]->reg_idx;
3481 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3482 vlnctrl &= ~IXGBE_RXDCTL_VME;
3483 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3484 }
3485 break;
3486 default:
3487 break;
3488 }
3489 }
3490
3491 /**
3492 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3493 * @adapter: driver data
3494 */
3495 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3496 {
3497 struct ixgbe_hw *hw = &adapter->hw;
3498 u32 vlnctrl;
3499 int i, j;
3500
3501 switch (hw->mac.type) {
3502 case ixgbe_mac_82598EB:
3503 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3504 vlnctrl |= IXGBE_VLNCTRL_VME;
3505 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3506 break;
3507 case ixgbe_mac_82599EB:
3508 case ixgbe_mac_X540:
3509 for (i = 0; i < adapter->num_rx_queues; i++) {
3510 j = adapter->rx_ring[i]->reg_idx;
3511 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3512 vlnctrl |= IXGBE_RXDCTL_VME;
3513 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3514 }
3515 break;
3516 default:
3517 break;
3518 }
3519 }
3520
3521 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3522 {
3523 u16 vid;
3524
3525 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3526
3527 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3528 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3529 }
3530
3531 /**
3532 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3533 * @netdev: network interface device structure
3534 *
3535 * Writes unicast address list to the RAR table.
3536 * Returns: -ENOMEM on failure/insufficient address space
3537 * 0 on no addresses written
3538 * X on writing X addresses to the RAR table
3539 **/
3540 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3541 {
3542 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3543 struct ixgbe_hw *hw = &adapter->hw;
3544 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3545 int count = 0;
3546
3547 /* In SR-IOV mode significantly less RAR entries are available */
3548 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3549 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3550
3551 /* return ENOMEM indicating insufficient memory for addresses */
3552 if (netdev_uc_count(netdev) > rar_entries)
3553 return -ENOMEM;
3554
3555 if (!netdev_uc_empty(netdev)) {
3556 struct netdev_hw_addr *ha;
3557 /* return error if we do not support writing to RAR table */
3558 if (!hw->mac.ops.set_rar)
3559 return -ENOMEM;
3560
3561 netdev_for_each_uc_addr(ha, netdev) {
3562 if (!rar_entries)
3563 break;
3564 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3565 VMDQ_P(0), IXGBE_RAH_AV);
3566 count++;
3567 }
3568 }
3569 /* write the addresses in reverse order to avoid write combining */
3570 for (; rar_entries > 0 ; rar_entries--)
3571 hw->mac.ops.clear_rar(hw, rar_entries);
3572
3573 return count;
3574 }
3575
3576 /**
3577 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3578 * @netdev: network interface device structure
3579 *
3580 * The set_rx_method entry point is called whenever the unicast/multicast
3581 * address list or the network interface flags are updated. This routine is
3582 * responsible for configuring the hardware for proper unicast, multicast and
3583 * promiscuous mode.
3584 **/
3585 void ixgbe_set_rx_mode(struct net_device *netdev)
3586 {
3587 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3588 struct ixgbe_hw *hw = &adapter->hw;
3589 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3590 int count;
3591
3592 /* Check for Promiscuous and All Multicast modes */
3593
3594 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3595
3596 /* set all bits that we expect to always be set */
3597 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3598 fctrl |= IXGBE_FCTRL_BAM;
3599 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3600 fctrl |= IXGBE_FCTRL_PMCF;
3601
3602 /* clear the bits we are changing the status of */
3603 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3604
3605 if (netdev->flags & IFF_PROMISC) {
3606 hw->addr_ctrl.user_set_promisc = true;
3607 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3608 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3609 /* don't hardware filter vlans in promisc mode */
3610 ixgbe_vlan_filter_disable(adapter);
3611 } else {
3612 if (netdev->flags & IFF_ALLMULTI) {
3613 fctrl |= IXGBE_FCTRL_MPE;
3614 vmolr |= IXGBE_VMOLR_MPE;
3615 } else {
3616 /*
3617 * Write addresses to the MTA, if the attempt fails
3618 * then we should just turn on promiscuous mode so
3619 * that we can at least receive multicast traffic
3620 */
3621 hw->mac.ops.update_mc_addr_list(hw, netdev);
3622 vmolr |= IXGBE_VMOLR_ROMPE;
3623 }
3624 ixgbe_vlan_filter_enable(adapter);
3625 hw->addr_ctrl.user_set_promisc = false;
3626 }
3627
3628 /*
3629 * Write addresses to available RAR registers, if there is not
3630 * sufficient space to store all the addresses then enable
3631 * unicast promiscuous mode
3632 */
3633 count = ixgbe_write_uc_addr_list(netdev);
3634 if (count < 0) {
3635 fctrl |= IXGBE_FCTRL_UPE;
3636 vmolr |= IXGBE_VMOLR_ROPE;
3637 }
3638
3639 if (adapter->num_vfs)
3640 ixgbe_restore_vf_multicasts(adapter);
3641
3642 if (hw->mac.type != ixgbe_mac_82598EB) {
3643 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3644 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3645 IXGBE_VMOLR_ROPE);
3646 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3647 }
3648
3649 /* This is useful for sniffing bad packets. */
3650 if (adapter->netdev->features & NETIF_F_RXALL) {
3651 /* UPE and MPE will be handled by normal PROMISC logic
3652 * in e1000e_set_rx_mode */
3653 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3654 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3655 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3656
3657 fctrl &= ~(IXGBE_FCTRL_DPF);
3658 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3659 }
3660
3661 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3662
3663 if (netdev->features & NETIF_F_HW_VLAN_RX)
3664 ixgbe_vlan_strip_enable(adapter);
3665 else
3666 ixgbe_vlan_strip_disable(adapter);
3667 }
3668
3669 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3670 {
3671 int q_idx;
3672
3673 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3674 napi_enable(&adapter->q_vector[q_idx]->napi);
3675 }
3676
3677 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3678 {
3679 int q_idx;
3680
3681 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3682 napi_disable(&adapter->q_vector[q_idx]->napi);
3683 }
3684
3685 #ifdef CONFIG_IXGBE_DCB
3686 /**
3687 * ixgbe_configure_dcb - Configure DCB hardware
3688 * @adapter: ixgbe adapter struct
3689 *
3690 * This is called by the driver on open to configure the DCB hardware.
3691 * This is also called by the gennetlink interface when reconfiguring
3692 * the DCB state.
3693 */
3694 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3695 {
3696 struct ixgbe_hw *hw = &adapter->hw;
3697 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3698
3699 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3700 if (hw->mac.type == ixgbe_mac_82598EB)
3701 netif_set_gso_max_size(adapter->netdev, 65536);
3702 return;
3703 }
3704
3705 if (hw->mac.type == ixgbe_mac_82598EB)
3706 netif_set_gso_max_size(adapter->netdev, 32768);
3707
3708 #ifdef IXGBE_FCOE
3709 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3710 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3711 #endif
3712
3713 /* reconfigure the hardware */
3714 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3715 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3716 DCB_TX_CONFIG);
3717 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3718 DCB_RX_CONFIG);
3719 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3720 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3721 ixgbe_dcb_hw_ets(&adapter->hw,
3722 adapter->ixgbe_ieee_ets,
3723 max_frame);
3724 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3725 adapter->ixgbe_ieee_pfc->pfc_en,
3726 adapter->ixgbe_ieee_ets->prio_tc);
3727 }
3728
3729 /* Enable RSS Hash per TC */
3730 if (hw->mac.type != ixgbe_mac_82598EB) {
3731 u32 msb = 0;
3732 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3733
3734 while (rss_i) {
3735 msb++;
3736 rss_i >>= 1;
3737 }
3738
3739 /* write msb to all 8 TCs in one write */
3740 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3741 }
3742 }
3743 #endif
3744
3745 /* Additional bittime to account for IXGBE framing */
3746 #define IXGBE_ETH_FRAMING 20
3747
3748 /**
3749 * ixgbe_hpbthresh - calculate high water mark for flow control
3750 *
3751 * @adapter: board private structure to calculate for
3752 * @pb: packet buffer to calculate
3753 */
3754 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3755 {
3756 struct ixgbe_hw *hw = &adapter->hw;
3757 struct net_device *dev = adapter->netdev;
3758 int link, tc, kb, marker;
3759 u32 dv_id, rx_pba;
3760
3761 /* Calculate max LAN frame size */
3762 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3763
3764 #ifdef IXGBE_FCOE
3765 /* FCoE traffic class uses FCOE jumbo frames */
3766 if ((dev->features & NETIF_F_FCOE_MTU) &&
3767 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3768 (pb == ixgbe_fcoe_get_tc(adapter)))
3769 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3770
3771 #endif
3772 /* Calculate delay value for device */
3773 switch (hw->mac.type) {
3774 case ixgbe_mac_X540:
3775 dv_id = IXGBE_DV_X540(link, tc);
3776 break;
3777 default:
3778 dv_id = IXGBE_DV(link, tc);
3779 break;
3780 }
3781
3782 /* Loopback switch introduces additional latency */
3783 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3784 dv_id += IXGBE_B2BT(tc);
3785
3786 /* Delay value is calculated in bit times convert to KB */
3787 kb = IXGBE_BT2KB(dv_id);
3788 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3789
3790 marker = rx_pba - kb;
3791
3792 /* It is possible that the packet buffer is not large enough
3793 * to provide required headroom. In this case throw an error
3794 * to user and a do the best we can.
3795 */
3796 if (marker < 0) {
3797 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3798 "headroom to support flow control."
3799 "Decrease MTU or number of traffic classes\n", pb);
3800 marker = tc + 1;
3801 }
3802
3803 return marker;
3804 }
3805
3806 /**
3807 * ixgbe_lpbthresh - calculate low water mark for for flow control
3808 *
3809 * @adapter: board private structure to calculate for
3810 * @pb: packet buffer to calculate
3811 */
3812 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3813 {
3814 struct ixgbe_hw *hw = &adapter->hw;
3815 struct net_device *dev = adapter->netdev;
3816 int tc;
3817 u32 dv_id;
3818
3819 /* Calculate max LAN frame size */
3820 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3821
3822 /* Calculate delay value for device */
3823 switch (hw->mac.type) {
3824 case ixgbe_mac_X540:
3825 dv_id = IXGBE_LOW_DV_X540(tc);
3826 break;
3827 default:
3828 dv_id = IXGBE_LOW_DV(tc);
3829 break;
3830 }
3831
3832 /* Delay value is calculated in bit times convert to KB */
3833 return IXGBE_BT2KB(dv_id);
3834 }
3835
3836 /*
3837 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3838 */
3839 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3840 {
3841 struct ixgbe_hw *hw = &adapter->hw;
3842 int num_tc = netdev_get_num_tc(adapter->netdev);
3843 int i;
3844
3845 if (!num_tc)
3846 num_tc = 1;
3847
3848 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3849
3850 for (i = 0; i < num_tc; i++) {
3851 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3852
3853 /* Low water marks must not be larger than high water marks */
3854 if (hw->fc.low_water > hw->fc.high_water[i])
3855 hw->fc.low_water = 0;
3856 }
3857 }
3858
3859 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3860 {
3861 struct ixgbe_hw *hw = &adapter->hw;
3862 int hdrm;
3863 u8 tc = netdev_get_num_tc(adapter->netdev);
3864
3865 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3866 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3867 hdrm = 32 << adapter->fdir_pballoc;
3868 else
3869 hdrm = 0;
3870
3871 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3872 ixgbe_pbthresh_setup(adapter);
3873 }
3874
3875 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3876 {
3877 struct ixgbe_hw *hw = &adapter->hw;
3878 struct hlist_node *node, *node2;
3879 struct ixgbe_fdir_filter *filter;
3880
3881 spin_lock(&adapter->fdir_perfect_lock);
3882
3883 if (!hlist_empty(&adapter->fdir_filter_list))
3884 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3885
3886 hlist_for_each_entry_safe(filter, node, node2,
3887 &adapter->fdir_filter_list, fdir_node) {
3888 ixgbe_fdir_write_perfect_filter_82599(hw,
3889 &filter->filter,
3890 filter->sw_idx,
3891 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3892 IXGBE_FDIR_DROP_QUEUE :
3893 adapter->rx_ring[filter->action]->reg_idx);
3894 }
3895
3896 spin_unlock(&adapter->fdir_perfect_lock);
3897 }
3898
3899 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3900 {
3901 struct ixgbe_hw *hw = &adapter->hw;
3902
3903 ixgbe_configure_pb(adapter);
3904 #ifdef CONFIG_IXGBE_DCB
3905 ixgbe_configure_dcb(adapter);
3906 #endif
3907 /*
3908 * We must restore virtualization before VLANs or else
3909 * the VLVF registers will not be populated
3910 */
3911 ixgbe_configure_virtualization(adapter);
3912
3913 ixgbe_set_rx_mode(adapter->netdev);
3914 ixgbe_restore_vlan(adapter);
3915
3916 switch (hw->mac.type) {
3917 case ixgbe_mac_82599EB:
3918 case ixgbe_mac_X540:
3919 hw->mac.ops.disable_rx_buff(hw);
3920 break;
3921 default:
3922 break;
3923 }
3924
3925 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3926 ixgbe_init_fdir_signature_82599(&adapter->hw,
3927 adapter->fdir_pballoc);
3928 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3929 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3930 adapter->fdir_pballoc);
3931 ixgbe_fdir_filter_restore(adapter);
3932 }
3933
3934 switch (hw->mac.type) {
3935 case ixgbe_mac_82599EB:
3936 case ixgbe_mac_X540:
3937 hw->mac.ops.enable_rx_buff(hw);
3938 break;
3939 default:
3940 break;
3941 }
3942
3943 #ifdef IXGBE_FCOE
3944 /* configure FCoE L2 filters, redirection table, and Rx control */
3945 ixgbe_configure_fcoe(adapter);
3946
3947 #endif /* IXGBE_FCOE */
3948 ixgbe_configure_tx(adapter);
3949 ixgbe_configure_rx(adapter);
3950 }
3951
3952 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3953 {
3954 switch (hw->phy.type) {
3955 case ixgbe_phy_sfp_avago:
3956 case ixgbe_phy_sfp_ftl:
3957 case ixgbe_phy_sfp_intel:
3958 case ixgbe_phy_sfp_unknown:
3959 case ixgbe_phy_sfp_passive_tyco:
3960 case ixgbe_phy_sfp_passive_unknown:
3961 case ixgbe_phy_sfp_active_unknown:
3962 case ixgbe_phy_sfp_ftl_active:
3963 return true;
3964 case ixgbe_phy_nl:
3965 if (hw->mac.type == ixgbe_mac_82598EB)
3966 return true;
3967 default:
3968 return false;
3969 }
3970 }
3971
3972 /**
3973 * ixgbe_sfp_link_config - set up SFP+ link
3974 * @adapter: pointer to private adapter struct
3975 **/
3976 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3977 {
3978 /*
3979 * We are assuming the worst case scenario here, and that
3980 * is that an SFP was inserted/removed after the reset
3981 * but before SFP detection was enabled. As such the best
3982 * solution is to just start searching as soon as we start
3983 */
3984 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3985 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3986
3987 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3988 }
3989
3990 /**
3991 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3992 * @hw: pointer to private hardware struct
3993 *
3994 * Returns 0 on success, negative on failure
3995 **/
3996 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3997 {
3998 u32 speed;
3999 bool autoneg, link_up = false;
4000 u32 ret = IXGBE_ERR_LINK_SETUP;
4001
4002 if (hw->mac.ops.check_link)
4003 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4004
4005 if (ret)
4006 goto link_cfg_out;
4007
4008 speed = hw->phy.autoneg_advertised;
4009 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4010 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4011 &autoneg);
4012 if (ret)
4013 goto link_cfg_out;
4014
4015 if (hw->mac.ops.setup_link)
4016 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4017 link_cfg_out:
4018 return ret;
4019 }
4020
4021 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4022 {
4023 struct ixgbe_hw *hw = &adapter->hw;
4024 u32 gpie = 0;
4025
4026 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4027 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4028 IXGBE_GPIE_OCD;
4029 gpie |= IXGBE_GPIE_EIAME;
4030 /*
4031 * use EIAM to auto-mask when MSI-X interrupt is asserted
4032 * this saves a register write for every interrupt
4033 */
4034 switch (hw->mac.type) {
4035 case ixgbe_mac_82598EB:
4036 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4037 break;
4038 case ixgbe_mac_82599EB:
4039 case ixgbe_mac_X540:
4040 default:
4041 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4042 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4043 break;
4044 }
4045 } else {
4046 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4047 * specifically only auto mask tx and rx interrupts */
4048 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4049 }
4050
4051 /* XXX: to interrupt immediately for EICS writes, enable this */
4052 /* gpie |= IXGBE_GPIE_EIMEN; */
4053
4054 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4055 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4056
4057 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4058 case IXGBE_82599_VMDQ_8Q_MASK:
4059 gpie |= IXGBE_GPIE_VTMODE_16;
4060 break;
4061 case IXGBE_82599_VMDQ_4Q_MASK:
4062 gpie |= IXGBE_GPIE_VTMODE_32;
4063 break;
4064 default:
4065 gpie |= IXGBE_GPIE_VTMODE_64;
4066 break;
4067 }
4068 }
4069
4070 /* Enable Thermal over heat sensor interrupt */
4071 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4072 switch (adapter->hw.mac.type) {
4073 case ixgbe_mac_82599EB:
4074 gpie |= IXGBE_SDP0_GPIEN;
4075 break;
4076 case ixgbe_mac_X540:
4077 gpie |= IXGBE_EIMS_TS;
4078 break;
4079 default:
4080 break;
4081 }
4082 }
4083
4084 /* Enable fan failure interrupt */
4085 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4086 gpie |= IXGBE_SDP1_GPIEN;
4087
4088 if (hw->mac.type == ixgbe_mac_82599EB) {
4089 gpie |= IXGBE_SDP1_GPIEN;
4090 gpie |= IXGBE_SDP2_GPIEN;
4091 }
4092
4093 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4094 }
4095
4096 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4097 {
4098 struct ixgbe_hw *hw = &adapter->hw;
4099 int err;
4100 u32 ctrl_ext;
4101
4102 ixgbe_get_hw_control(adapter);
4103 ixgbe_setup_gpie(adapter);
4104
4105 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4106 ixgbe_configure_msix(adapter);
4107 else
4108 ixgbe_configure_msi_and_legacy(adapter);
4109
4110 /* enable the optics for 82599 SFP+ fiber */
4111 if (hw->mac.ops.enable_tx_laser)
4112 hw->mac.ops.enable_tx_laser(hw);
4113
4114 clear_bit(__IXGBE_DOWN, &adapter->state);
4115 ixgbe_napi_enable_all(adapter);
4116
4117 if (ixgbe_is_sfp(hw)) {
4118 ixgbe_sfp_link_config(adapter);
4119 } else {
4120 err = ixgbe_non_sfp_link_config(hw);
4121 if (err)
4122 e_err(probe, "link_config FAILED %d\n", err);
4123 }
4124
4125 /* clear any pending interrupts, may auto mask */
4126 IXGBE_READ_REG(hw, IXGBE_EICR);
4127 ixgbe_irq_enable(adapter, true, true);
4128
4129 /*
4130 * If this adapter has a fan, check to see if we had a failure
4131 * before we enabled the interrupt.
4132 */
4133 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4134 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4135 if (esdp & IXGBE_ESDP_SDP1)
4136 e_crit(drv, "Fan has stopped, replace the adapter\n");
4137 }
4138
4139 /* enable transmits */
4140 netif_tx_start_all_queues(adapter->netdev);
4141
4142 /* bring the link up in the watchdog, this could race with our first
4143 * link up interrupt but shouldn't be a problem */
4144 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4145 adapter->link_check_timeout = jiffies;
4146 mod_timer(&adapter->service_timer, jiffies);
4147
4148 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4149 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4150 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4151 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4152 }
4153
4154 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4155 {
4156 WARN_ON(in_interrupt());
4157 /* put off any impending NetWatchDogTimeout */
4158 adapter->netdev->trans_start = jiffies;
4159
4160 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4161 usleep_range(1000, 2000);
4162 ixgbe_down(adapter);
4163 /*
4164 * If SR-IOV enabled then wait a bit before bringing the adapter
4165 * back up to give the VFs time to respond to the reset. The
4166 * two second wait is based upon the watchdog timer cycle in
4167 * the VF driver.
4168 */
4169 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4170 msleep(2000);
4171 ixgbe_up(adapter);
4172 clear_bit(__IXGBE_RESETTING, &adapter->state);
4173 }
4174
4175 void ixgbe_up(struct ixgbe_adapter *adapter)
4176 {
4177 /* hardware has been reset, we need to reload some things */
4178 ixgbe_configure(adapter);
4179
4180 ixgbe_up_complete(adapter);
4181 }
4182
4183 void ixgbe_reset(struct ixgbe_adapter *adapter)
4184 {
4185 struct ixgbe_hw *hw = &adapter->hw;
4186 int err;
4187
4188 /* lock SFP init bit to prevent race conditions with the watchdog */
4189 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4190 usleep_range(1000, 2000);
4191
4192 /* clear all SFP and link config related flags while holding SFP_INIT */
4193 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4194 IXGBE_FLAG2_SFP_NEEDS_RESET);
4195 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4196
4197 err = hw->mac.ops.init_hw(hw);
4198 switch (err) {
4199 case 0:
4200 case IXGBE_ERR_SFP_NOT_PRESENT:
4201 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4202 break;
4203 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4204 e_dev_err("master disable timed out\n");
4205 break;
4206 case IXGBE_ERR_EEPROM_VERSION:
4207 /* We are running on a pre-production device, log a warning */
4208 e_dev_warn("This device is a pre-production adapter/LOM. "
4209 "Please be aware there may be issues associated with "
4210 "your hardware. If you are experiencing problems "
4211 "please contact your Intel or hardware "
4212 "representative who provided you with this "
4213 "hardware.\n");
4214 break;
4215 default:
4216 e_dev_err("Hardware Error: %d\n", err);
4217 }
4218
4219 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4220
4221 /* reprogram the RAR[0] in case user changed it. */
4222 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4223
4224 /* update SAN MAC vmdq pool selection */
4225 if (hw->mac.san_mac_rar_index)
4226 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4227
4228 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4229 ixgbe_ptp_reset(adapter);
4230 }
4231
4232 /**
4233 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4234 * @rx_ring: ring to free buffers from
4235 **/
4236 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4237 {
4238 struct device *dev = rx_ring->dev;
4239 unsigned long size;
4240 u16 i;
4241
4242 /* ring already cleared, nothing to do */
4243 if (!rx_ring->rx_buffer_info)
4244 return;
4245
4246 /* Free all the Rx ring sk_buffs */
4247 for (i = 0; i < rx_ring->count; i++) {
4248 struct ixgbe_rx_buffer *rx_buffer;
4249
4250 rx_buffer = &rx_ring->rx_buffer_info[i];
4251 if (rx_buffer->skb) {
4252 struct sk_buff *skb = rx_buffer->skb;
4253 if (IXGBE_CB(skb)->page_released) {
4254 dma_unmap_page(dev,
4255 IXGBE_CB(skb)->dma,
4256 ixgbe_rx_bufsz(rx_ring),
4257 DMA_FROM_DEVICE);
4258 IXGBE_CB(skb)->page_released = false;
4259 }
4260 dev_kfree_skb(skb);
4261 }
4262 rx_buffer->skb = NULL;
4263 if (rx_buffer->dma)
4264 dma_unmap_page(dev, rx_buffer->dma,
4265 ixgbe_rx_pg_size(rx_ring),
4266 DMA_FROM_DEVICE);
4267 rx_buffer->dma = 0;
4268 if (rx_buffer->page)
4269 __free_pages(rx_buffer->page,
4270 ixgbe_rx_pg_order(rx_ring));
4271 rx_buffer->page = NULL;
4272 }
4273
4274 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4275 memset(rx_ring->rx_buffer_info, 0, size);
4276
4277 /* Zero out the descriptor ring */
4278 memset(rx_ring->desc, 0, rx_ring->size);
4279
4280 rx_ring->next_to_alloc = 0;
4281 rx_ring->next_to_clean = 0;
4282 rx_ring->next_to_use = 0;
4283 }
4284
4285 /**
4286 * ixgbe_clean_tx_ring - Free Tx Buffers
4287 * @tx_ring: ring to be cleaned
4288 **/
4289 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4290 {
4291 struct ixgbe_tx_buffer *tx_buffer_info;
4292 unsigned long size;
4293 u16 i;
4294
4295 /* ring already cleared, nothing to do */
4296 if (!tx_ring->tx_buffer_info)
4297 return;
4298
4299 /* Free all the Tx ring sk_buffs */
4300 for (i = 0; i < tx_ring->count; i++) {
4301 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4302 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4303 }
4304
4305 netdev_tx_reset_queue(txring_txq(tx_ring));
4306
4307 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4308 memset(tx_ring->tx_buffer_info, 0, size);
4309
4310 /* Zero out the descriptor ring */
4311 memset(tx_ring->desc, 0, tx_ring->size);
4312
4313 tx_ring->next_to_use = 0;
4314 tx_ring->next_to_clean = 0;
4315 }
4316
4317 /**
4318 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4319 * @adapter: board private structure
4320 **/
4321 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4322 {
4323 int i;
4324
4325 for (i = 0; i < adapter->num_rx_queues; i++)
4326 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4327 }
4328
4329 /**
4330 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4331 * @adapter: board private structure
4332 **/
4333 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4334 {
4335 int i;
4336
4337 for (i = 0; i < adapter->num_tx_queues; i++)
4338 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4339 }
4340
4341 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4342 {
4343 struct hlist_node *node, *node2;
4344 struct ixgbe_fdir_filter *filter;
4345
4346 spin_lock(&adapter->fdir_perfect_lock);
4347
4348 hlist_for_each_entry_safe(filter, node, node2,
4349 &adapter->fdir_filter_list, fdir_node) {
4350 hlist_del(&filter->fdir_node);
4351 kfree(filter);
4352 }
4353 adapter->fdir_filter_count = 0;
4354
4355 spin_unlock(&adapter->fdir_perfect_lock);
4356 }
4357
4358 void ixgbe_down(struct ixgbe_adapter *adapter)
4359 {
4360 struct net_device *netdev = adapter->netdev;
4361 struct ixgbe_hw *hw = &adapter->hw;
4362 u32 rxctrl;
4363 int i;
4364
4365 /* signal that we are down to the interrupt handler */
4366 set_bit(__IXGBE_DOWN, &adapter->state);
4367
4368 /* disable receives */
4369 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4370 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4371
4372 /* disable all enabled rx queues */
4373 for (i = 0; i < adapter->num_rx_queues; i++)
4374 /* this call also flushes the previous write */
4375 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4376
4377 usleep_range(10000, 20000);
4378
4379 netif_tx_stop_all_queues(netdev);
4380
4381 /* call carrier off first to avoid false dev_watchdog timeouts */
4382 netif_carrier_off(netdev);
4383 netif_tx_disable(netdev);
4384
4385 ixgbe_irq_disable(adapter);
4386
4387 ixgbe_napi_disable_all(adapter);
4388
4389 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4390 IXGBE_FLAG2_RESET_REQUESTED);
4391 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4392
4393 del_timer_sync(&adapter->service_timer);
4394
4395 if (adapter->num_vfs) {
4396 /* Clear EITR Select mapping */
4397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4398
4399 /* Mark all the VFs as inactive */
4400 for (i = 0 ; i < adapter->num_vfs; i++)
4401 adapter->vfinfo[i].clear_to_send = false;
4402
4403 /* ping all the active vfs to let them know we are going down */
4404 ixgbe_ping_all_vfs(adapter);
4405
4406 /* Disable all VFTE/VFRE TX/RX */
4407 ixgbe_disable_tx_rx(adapter);
4408 }
4409
4410 /* disable transmits in the hardware now that interrupts are off */
4411 for (i = 0; i < adapter->num_tx_queues; i++) {
4412 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4413 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4414 }
4415
4416 /* Disable the Tx DMA engine on 82599 and X540 */
4417 switch (hw->mac.type) {
4418 case ixgbe_mac_82599EB:
4419 case ixgbe_mac_X540:
4420 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4421 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4422 ~IXGBE_DMATXCTL_TE));
4423 break;
4424 default:
4425 break;
4426 }
4427
4428 if (!pci_channel_offline(adapter->pdev))
4429 ixgbe_reset(adapter);
4430
4431 /* power down the optics for 82599 SFP+ fiber */
4432 if (hw->mac.ops.disable_tx_laser)
4433 hw->mac.ops.disable_tx_laser(hw);
4434
4435 ixgbe_clean_all_tx_rings(adapter);
4436 ixgbe_clean_all_rx_rings(adapter);
4437
4438 #ifdef CONFIG_IXGBE_DCA
4439 /* since we reset the hardware DCA settings were cleared */
4440 ixgbe_setup_dca(adapter);
4441 #endif
4442 }
4443
4444 /**
4445 * ixgbe_tx_timeout - Respond to a Tx Hang
4446 * @netdev: network interface device structure
4447 **/
4448 static void ixgbe_tx_timeout(struct net_device *netdev)
4449 {
4450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4451
4452 /* Do the reset outside of interrupt context */
4453 ixgbe_tx_timeout_reset(adapter);
4454 }
4455
4456 /**
4457 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4458 * @adapter: board private structure to initialize
4459 *
4460 * ixgbe_sw_init initializes the Adapter private data structure.
4461 * Fields are initialized based on PCI device information and
4462 * OS network device settings (MTU size).
4463 **/
4464 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4465 {
4466 struct ixgbe_hw *hw = &adapter->hw;
4467 struct pci_dev *pdev = adapter->pdev;
4468 unsigned int rss, fdir;
4469 u32 fwsm;
4470 #ifdef CONFIG_IXGBE_DCB
4471 int j;
4472 struct tc_configuration *tc;
4473 #endif
4474
4475 /* PCI config space info */
4476
4477 hw->vendor_id = pdev->vendor;
4478 hw->device_id = pdev->device;
4479 hw->revision_id = pdev->revision;
4480 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4481 hw->subsystem_device_id = pdev->subsystem_device;
4482
4483 /* Set common capability flags and settings */
4484 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4485 adapter->ring_feature[RING_F_RSS].limit = rss;
4486 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4487 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4488 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4489 adapter->atr_sample_rate = 20;
4490 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4491 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4492 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4493 #ifdef CONFIG_IXGBE_DCA
4494 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4495 #endif
4496 #ifdef IXGBE_FCOE
4497 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4498 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4499 #ifdef CONFIG_IXGBE_DCB
4500 /* Default traffic class to use for FCoE */
4501 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4502 #endif /* CONFIG_IXGBE_DCB */
4503 #endif /* IXGBE_FCOE */
4504
4505 /* Set MAC specific capability flags and exceptions */
4506 switch (hw->mac.type) {
4507 case ixgbe_mac_82598EB:
4508 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4509 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4510
4511 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4512 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4513
4514 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4515 adapter->ring_feature[RING_F_FDIR].limit = 0;
4516 adapter->atr_sample_rate = 0;
4517 adapter->fdir_pballoc = 0;
4518 #ifdef IXGBE_FCOE
4519 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4520 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4521 #ifdef CONFIG_IXGBE_DCB
4522 adapter->fcoe.up = 0;
4523 #endif /* IXGBE_DCB */
4524 #endif /* IXGBE_FCOE */
4525 break;
4526 case ixgbe_mac_82599EB:
4527 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4528 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4529 break;
4530 case ixgbe_mac_X540:
4531 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4532 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4533 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4534 break;
4535 default:
4536 break;
4537 }
4538
4539 #ifdef IXGBE_FCOE
4540 /* FCoE support exists, always init the FCoE lock */
4541 spin_lock_init(&adapter->fcoe.lock);
4542
4543 #endif
4544 /* n-tuple support exists, always init our spinlock */
4545 spin_lock_init(&adapter->fdir_perfect_lock);
4546
4547 #ifdef CONFIG_IXGBE_DCB
4548 switch (hw->mac.type) {
4549 case ixgbe_mac_X540:
4550 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4551 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4552 break;
4553 default:
4554 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4555 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4556 break;
4557 }
4558
4559 /* Configure DCB traffic classes */
4560 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4561 tc = &adapter->dcb_cfg.tc_config[j];
4562 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4563 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4564 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4565 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4566 tc->dcb_pfc = pfc_disabled;
4567 }
4568
4569 /* Initialize default user to priority mapping, UPx->TC0 */
4570 tc = &adapter->dcb_cfg.tc_config[0];
4571 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4572 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4573
4574 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4575 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4576 adapter->dcb_cfg.pfc_mode_enable = false;
4577 adapter->dcb_set_bitmap = 0x00;
4578 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4579 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4580 sizeof(adapter->temp_dcb_cfg));
4581
4582 #endif
4583
4584 /* default flow control settings */
4585 hw->fc.requested_mode = ixgbe_fc_full;
4586 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4587 ixgbe_pbthresh_setup(adapter);
4588 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4589 hw->fc.send_xon = true;
4590 hw->fc.disable_fc_autoneg =
4591 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4592
4593 #ifdef CONFIG_PCI_IOV
4594 /* assign number of SR-IOV VFs */
4595 if (hw->mac.type != ixgbe_mac_82598EB)
4596 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4597
4598 #endif
4599 /* enable itr by default in dynamic mode */
4600 adapter->rx_itr_setting = 1;
4601 adapter->tx_itr_setting = 1;
4602
4603 /* set default ring sizes */
4604 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4605 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4606
4607 /* set default work limits */
4608 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4609
4610 /* initialize eeprom parameters */
4611 if (ixgbe_init_eeprom_params_generic(hw)) {
4612 e_dev_err("EEPROM initialization failed\n");
4613 return -EIO;
4614 }
4615
4616 set_bit(__IXGBE_DOWN, &adapter->state);
4617
4618 return 0;
4619 }
4620
4621 /**
4622 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4623 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4624 *
4625 * Return 0 on success, negative on failure
4626 **/
4627 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4628 {
4629 struct device *dev = tx_ring->dev;
4630 int orig_node = dev_to_node(dev);
4631 int numa_node = -1;
4632 int size;
4633
4634 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4635
4636 if (tx_ring->q_vector)
4637 numa_node = tx_ring->q_vector->numa_node;
4638
4639 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4640 if (!tx_ring->tx_buffer_info)
4641 tx_ring->tx_buffer_info = vzalloc(size);
4642 if (!tx_ring->tx_buffer_info)
4643 goto err;
4644
4645 /* round up to nearest 4K */
4646 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4647 tx_ring->size = ALIGN(tx_ring->size, 4096);
4648
4649 set_dev_node(dev, numa_node);
4650 tx_ring->desc = dma_alloc_coherent(dev,
4651 tx_ring->size,
4652 &tx_ring->dma,
4653 GFP_KERNEL);
4654 set_dev_node(dev, orig_node);
4655 if (!tx_ring->desc)
4656 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4657 &tx_ring->dma, GFP_KERNEL);
4658 if (!tx_ring->desc)
4659 goto err;
4660
4661 tx_ring->next_to_use = 0;
4662 tx_ring->next_to_clean = 0;
4663 return 0;
4664
4665 err:
4666 vfree(tx_ring->tx_buffer_info);
4667 tx_ring->tx_buffer_info = NULL;
4668 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4669 return -ENOMEM;
4670 }
4671
4672 /**
4673 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4674 * @adapter: board private structure
4675 *
4676 * If this function returns with an error, then it's possible one or
4677 * more of the rings is populated (while the rest are not). It is the
4678 * callers duty to clean those orphaned rings.
4679 *
4680 * Return 0 on success, negative on failure
4681 **/
4682 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4683 {
4684 int i, err = 0;
4685
4686 for (i = 0; i < adapter->num_tx_queues; i++) {
4687 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4688 if (!err)
4689 continue;
4690
4691 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4692 goto err_setup_tx;
4693 }
4694
4695 return 0;
4696 err_setup_tx:
4697 /* rewind the index freeing the rings as we go */
4698 while (i--)
4699 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4700 return err;
4701 }
4702
4703 /**
4704 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4705 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4706 *
4707 * Returns 0 on success, negative on failure
4708 **/
4709 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4710 {
4711 struct device *dev = rx_ring->dev;
4712 int orig_node = dev_to_node(dev);
4713 int numa_node = -1;
4714 int size;
4715
4716 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4717
4718 if (rx_ring->q_vector)
4719 numa_node = rx_ring->q_vector->numa_node;
4720
4721 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4722 if (!rx_ring->rx_buffer_info)
4723 rx_ring->rx_buffer_info = vzalloc(size);
4724 if (!rx_ring->rx_buffer_info)
4725 goto err;
4726
4727 /* Round up to nearest 4K */
4728 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4729 rx_ring->size = ALIGN(rx_ring->size, 4096);
4730
4731 set_dev_node(dev, numa_node);
4732 rx_ring->desc = dma_alloc_coherent(dev,
4733 rx_ring->size,
4734 &rx_ring->dma,
4735 GFP_KERNEL);
4736 set_dev_node(dev, orig_node);
4737 if (!rx_ring->desc)
4738 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4739 &rx_ring->dma, GFP_KERNEL);
4740 if (!rx_ring->desc)
4741 goto err;
4742
4743 rx_ring->next_to_clean = 0;
4744 rx_ring->next_to_use = 0;
4745
4746 return 0;
4747 err:
4748 vfree(rx_ring->rx_buffer_info);
4749 rx_ring->rx_buffer_info = NULL;
4750 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4751 return -ENOMEM;
4752 }
4753
4754 /**
4755 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4756 * @adapter: board private structure
4757 *
4758 * If this function returns with an error, then it's possible one or
4759 * more of the rings is populated (while the rest are not). It is the
4760 * callers duty to clean those orphaned rings.
4761 *
4762 * Return 0 on success, negative on failure
4763 **/
4764 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4765 {
4766 int i, err = 0;
4767
4768 for (i = 0; i < adapter->num_rx_queues; i++) {
4769 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4770 if (!err)
4771 continue;
4772
4773 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4774 goto err_setup_rx;
4775 }
4776
4777 #ifdef IXGBE_FCOE
4778 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4779 if (!err)
4780 #endif
4781 return 0;
4782 err_setup_rx:
4783 /* rewind the index freeing the rings as we go */
4784 while (i--)
4785 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4786 return err;
4787 }
4788
4789 /**
4790 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4791 * @tx_ring: Tx descriptor ring for a specific queue
4792 *
4793 * Free all transmit software resources
4794 **/
4795 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4796 {
4797 ixgbe_clean_tx_ring(tx_ring);
4798
4799 vfree(tx_ring->tx_buffer_info);
4800 tx_ring->tx_buffer_info = NULL;
4801
4802 /* if not set, then don't free */
4803 if (!tx_ring->desc)
4804 return;
4805
4806 dma_free_coherent(tx_ring->dev, tx_ring->size,
4807 tx_ring->desc, tx_ring->dma);
4808
4809 tx_ring->desc = NULL;
4810 }
4811
4812 /**
4813 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4814 * @adapter: board private structure
4815 *
4816 * Free all transmit software resources
4817 **/
4818 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4819 {
4820 int i;
4821
4822 for (i = 0; i < adapter->num_tx_queues; i++)
4823 if (adapter->tx_ring[i]->desc)
4824 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4825 }
4826
4827 /**
4828 * ixgbe_free_rx_resources - Free Rx Resources
4829 * @rx_ring: ring to clean the resources from
4830 *
4831 * Free all receive software resources
4832 **/
4833 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4834 {
4835 ixgbe_clean_rx_ring(rx_ring);
4836
4837 vfree(rx_ring->rx_buffer_info);
4838 rx_ring->rx_buffer_info = NULL;
4839
4840 /* if not set, then don't free */
4841 if (!rx_ring->desc)
4842 return;
4843
4844 dma_free_coherent(rx_ring->dev, rx_ring->size,
4845 rx_ring->desc, rx_ring->dma);
4846
4847 rx_ring->desc = NULL;
4848 }
4849
4850 /**
4851 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4852 * @adapter: board private structure
4853 *
4854 * Free all receive software resources
4855 **/
4856 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4857 {
4858 int i;
4859
4860 #ifdef IXGBE_FCOE
4861 ixgbe_free_fcoe_ddp_resources(adapter);
4862
4863 #endif
4864 for (i = 0; i < adapter->num_rx_queues; i++)
4865 if (adapter->rx_ring[i]->desc)
4866 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4867 }
4868
4869 /**
4870 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4871 * @netdev: network interface device structure
4872 * @new_mtu: new value for maximum frame size
4873 *
4874 * Returns 0 on success, negative on failure
4875 **/
4876 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4877 {
4878 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4879 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4880
4881 /* MTU < 68 is an error and causes problems on some kernels */
4882 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4883 return -EINVAL;
4884
4885 /*
4886 * For 82599EB we cannot allow legacy VFs to enable their receive
4887 * paths when MTU greater than 1500 is configured. So display a
4888 * warning that legacy VFs will be disabled.
4889 */
4890 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4891 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4892 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4893 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4894
4895 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4896
4897 /* must set new MTU before calling down or up */
4898 netdev->mtu = new_mtu;
4899
4900 if (netif_running(netdev))
4901 ixgbe_reinit_locked(adapter);
4902
4903 return 0;
4904 }
4905
4906 /**
4907 * ixgbe_open - Called when a network interface is made active
4908 * @netdev: network interface device structure
4909 *
4910 * Returns 0 on success, negative value on failure
4911 *
4912 * The open entry point is called when a network interface is made
4913 * active by the system (IFF_UP). At this point all resources needed
4914 * for transmit and receive operations are allocated, the interrupt
4915 * handler is registered with the OS, the watchdog timer is started,
4916 * and the stack is notified that the interface is ready.
4917 **/
4918 static int ixgbe_open(struct net_device *netdev)
4919 {
4920 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4921 int err;
4922
4923 /* disallow open during test */
4924 if (test_bit(__IXGBE_TESTING, &adapter->state))
4925 return -EBUSY;
4926
4927 netif_carrier_off(netdev);
4928
4929 /* allocate transmit descriptors */
4930 err = ixgbe_setup_all_tx_resources(adapter);
4931 if (err)
4932 goto err_setup_tx;
4933
4934 /* allocate receive descriptors */
4935 err = ixgbe_setup_all_rx_resources(adapter);
4936 if (err)
4937 goto err_setup_rx;
4938
4939 ixgbe_configure(adapter);
4940
4941 err = ixgbe_request_irq(adapter);
4942 if (err)
4943 goto err_req_irq;
4944
4945 /* Notify the stack of the actual queue counts. */
4946 err = netif_set_real_num_tx_queues(netdev,
4947 adapter->num_rx_pools > 1 ? 1 :
4948 adapter->num_tx_queues);
4949 if (err)
4950 goto err_set_queues;
4951
4952
4953 err = netif_set_real_num_rx_queues(netdev,
4954 adapter->num_rx_pools > 1 ? 1 :
4955 adapter->num_rx_queues);
4956 if (err)
4957 goto err_set_queues;
4958
4959 ixgbe_ptp_init(adapter);
4960
4961 ixgbe_up_complete(adapter);
4962
4963 return 0;
4964
4965 err_set_queues:
4966 ixgbe_free_irq(adapter);
4967 err_req_irq:
4968 ixgbe_free_all_rx_resources(adapter);
4969 err_setup_rx:
4970 ixgbe_free_all_tx_resources(adapter);
4971 err_setup_tx:
4972 ixgbe_reset(adapter);
4973
4974 return err;
4975 }
4976
4977 /**
4978 * ixgbe_close - Disables a network interface
4979 * @netdev: network interface device structure
4980 *
4981 * Returns 0, this is not allowed to fail
4982 *
4983 * The close entry point is called when an interface is de-activated
4984 * by the OS. The hardware is still under the drivers control, but
4985 * needs to be disabled. A global MAC reset is issued to stop the
4986 * hardware, and all transmit and receive resources are freed.
4987 **/
4988 static int ixgbe_close(struct net_device *netdev)
4989 {
4990 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4991
4992 ixgbe_ptp_stop(adapter);
4993
4994 ixgbe_down(adapter);
4995 ixgbe_free_irq(adapter);
4996
4997 ixgbe_fdir_filter_exit(adapter);
4998
4999 ixgbe_free_all_tx_resources(adapter);
5000 ixgbe_free_all_rx_resources(adapter);
5001
5002 ixgbe_release_hw_control(adapter);
5003
5004 return 0;
5005 }
5006
5007 #ifdef CONFIG_PM
5008 static int ixgbe_resume(struct pci_dev *pdev)
5009 {
5010 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5011 struct net_device *netdev = adapter->netdev;
5012 u32 err;
5013
5014 pci_set_power_state(pdev, PCI_D0);
5015 pci_restore_state(pdev);
5016 /*
5017 * pci_restore_state clears dev->state_saved so call
5018 * pci_save_state to restore it.
5019 */
5020 pci_save_state(pdev);
5021
5022 err = pci_enable_device_mem(pdev);
5023 if (err) {
5024 e_dev_err("Cannot enable PCI device from suspend\n");
5025 return err;
5026 }
5027 pci_set_master(pdev);
5028
5029 pci_wake_from_d3(pdev, false);
5030
5031 ixgbe_reset(adapter);
5032
5033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5034
5035 rtnl_lock();
5036 err = ixgbe_init_interrupt_scheme(adapter);
5037 if (!err && netif_running(netdev))
5038 err = ixgbe_open(netdev);
5039
5040 rtnl_unlock();
5041
5042 if (err)
5043 return err;
5044
5045 netif_device_attach(netdev);
5046
5047 return 0;
5048 }
5049 #endif /* CONFIG_PM */
5050
5051 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5052 {
5053 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5054 struct net_device *netdev = adapter->netdev;
5055 struct ixgbe_hw *hw = &adapter->hw;
5056 u32 ctrl, fctrl;
5057 u32 wufc = adapter->wol;
5058 #ifdef CONFIG_PM
5059 int retval = 0;
5060 #endif
5061
5062 netif_device_detach(netdev);
5063
5064 if (netif_running(netdev)) {
5065 rtnl_lock();
5066 ixgbe_down(adapter);
5067 ixgbe_free_irq(adapter);
5068 ixgbe_free_all_tx_resources(adapter);
5069 ixgbe_free_all_rx_resources(adapter);
5070 rtnl_unlock();
5071 }
5072
5073 ixgbe_clear_interrupt_scheme(adapter);
5074
5075 #ifdef CONFIG_PM
5076 retval = pci_save_state(pdev);
5077 if (retval)
5078 return retval;
5079
5080 #endif
5081 if (wufc) {
5082 ixgbe_set_rx_mode(netdev);
5083
5084 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5085 if (hw->mac.ops.enable_tx_laser)
5086 hw->mac.ops.enable_tx_laser(hw);
5087
5088 /* turn on all-multi mode if wake on multicast is enabled */
5089 if (wufc & IXGBE_WUFC_MC) {
5090 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5091 fctrl |= IXGBE_FCTRL_MPE;
5092 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5093 }
5094
5095 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5096 ctrl |= IXGBE_CTRL_GIO_DIS;
5097 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5098
5099 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5100 } else {
5101 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5102 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5103 }
5104
5105 switch (hw->mac.type) {
5106 case ixgbe_mac_82598EB:
5107 pci_wake_from_d3(pdev, false);
5108 break;
5109 case ixgbe_mac_82599EB:
5110 case ixgbe_mac_X540:
5111 pci_wake_from_d3(pdev, !!wufc);
5112 break;
5113 default:
5114 break;
5115 }
5116
5117 *enable_wake = !!wufc;
5118
5119 ixgbe_release_hw_control(adapter);
5120
5121 pci_disable_device(pdev);
5122
5123 return 0;
5124 }
5125
5126 #ifdef CONFIG_PM
5127 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5128 {
5129 int retval;
5130 bool wake;
5131
5132 retval = __ixgbe_shutdown(pdev, &wake);
5133 if (retval)
5134 return retval;
5135
5136 if (wake) {
5137 pci_prepare_to_sleep(pdev);
5138 } else {
5139 pci_wake_from_d3(pdev, false);
5140 pci_set_power_state(pdev, PCI_D3hot);
5141 }
5142
5143 return 0;
5144 }
5145 #endif /* CONFIG_PM */
5146
5147 static void ixgbe_shutdown(struct pci_dev *pdev)
5148 {
5149 bool wake;
5150
5151 __ixgbe_shutdown(pdev, &wake);
5152
5153 if (system_state == SYSTEM_POWER_OFF) {
5154 pci_wake_from_d3(pdev, wake);
5155 pci_set_power_state(pdev, PCI_D3hot);
5156 }
5157 }
5158
5159 /**
5160 * ixgbe_update_stats - Update the board statistics counters.
5161 * @adapter: board private structure
5162 **/
5163 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5164 {
5165 struct net_device *netdev = adapter->netdev;
5166 struct ixgbe_hw *hw = &adapter->hw;
5167 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5168 u64 total_mpc = 0;
5169 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5170 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5171 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5172 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5173
5174 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5175 test_bit(__IXGBE_RESETTING, &adapter->state))
5176 return;
5177
5178 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5179 u64 rsc_count = 0;
5180 u64 rsc_flush = 0;
5181 for (i = 0; i < adapter->num_rx_queues; i++) {
5182 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5183 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5184 }
5185 adapter->rsc_total_count = rsc_count;
5186 adapter->rsc_total_flush = rsc_flush;
5187 }
5188
5189 for (i = 0; i < adapter->num_rx_queues; i++) {
5190 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5191 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5192 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5193 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5194 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5195 bytes += rx_ring->stats.bytes;
5196 packets += rx_ring->stats.packets;
5197 }
5198 adapter->non_eop_descs = non_eop_descs;
5199 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5200 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5201 adapter->hw_csum_rx_error = hw_csum_rx_error;
5202 netdev->stats.rx_bytes = bytes;
5203 netdev->stats.rx_packets = packets;
5204
5205 bytes = 0;
5206 packets = 0;
5207 /* gather some stats to the adapter struct that are per queue */
5208 for (i = 0; i < adapter->num_tx_queues; i++) {
5209 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5210 restart_queue += tx_ring->tx_stats.restart_queue;
5211 tx_busy += tx_ring->tx_stats.tx_busy;
5212 bytes += tx_ring->stats.bytes;
5213 packets += tx_ring->stats.packets;
5214 }
5215 adapter->restart_queue = restart_queue;
5216 adapter->tx_busy = tx_busy;
5217 netdev->stats.tx_bytes = bytes;
5218 netdev->stats.tx_packets = packets;
5219
5220 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5221
5222 /* 8 register reads */
5223 for (i = 0; i < 8; i++) {
5224 /* for packet buffers not used, the register should read 0 */
5225 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5226 missed_rx += mpc;
5227 hwstats->mpc[i] += mpc;
5228 total_mpc += hwstats->mpc[i];
5229 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5230 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5231 switch (hw->mac.type) {
5232 case ixgbe_mac_82598EB:
5233 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5234 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5235 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5236 hwstats->pxonrxc[i] +=
5237 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5238 break;
5239 case ixgbe_mac_82599EB:
5240 case ixgbe_mac_X540:
5241 hwstats->pxonrxc[i] +=
5242 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5243 break;
5244 default:
5245 break;
5246 }
5247 }
5248
5249 /*16 register reads */
5250 for (i = 0; i < 16; i++) {
5251 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5252 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5253 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5254 (hw->mac.type == ixgbe_mac_X540)) {
5255 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5256 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5257 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5258 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5259 }
5260 }
5261
5262 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5263 /* work around hardware counting issue */
5264 hwstats->gprc -= missed_rx;
5265
5266 ixgbe_update_xoff_received(adapter);
5267
5268 /* 82598 hardware only has a 32 bit counter in the high register */
5269 switch (hw->mac.type) {
5270 case ixgbe_mac_82598EB:
5271 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5272 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5273 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5274 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5275 break;
5276 case ixgbe_mac_X540:
5277 /* OS2BMC stats are X540 only*/
5278 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5279 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5280 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5281 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5282 case ixgbe_mac_82599EB:
5283 for (i = 0; i < 16; i++)
5284 adapter->hw_rx_no_dma_resources +=
5285 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5286 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5287 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5288 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5289 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5290 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5291 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5292 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5293 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5294 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5295 #ifdef IXGBE_FCOE
5296 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5297 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5298 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5299 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5300 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5301 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5302 /* Add up per cpu counters for total ddp aloc fail */
5303 if (adapter->fcoe.ddp_pool) {
5304 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5305 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5306 unsigned int cpu;
5307 u64 noddp = 0, noddp_ext_buff = 0;
5308 for_each_possible_cpu(cpu) {
5309 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5310 noddp += ddp_pool->noddp;
5311 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5312 }
5313 hwstats->fcoe_noddp = noddp;
5314 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5315 }
5316 #endif /* IXGBE_FCOE */
5317 break;
5318 default:
5319 break;
5320 }
5321 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5322 hwstats->bprc += bprc;
5323 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5324 if (hw->mac.type == ixgbe_mac_82598EB)
5325 hwstats->mprc -= bprc;
5326 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5327 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5328 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5329 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5330 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5331 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5332 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5333 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5334 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5335 hwstats->lxontxc += lxon;
5336 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5337 hwstats->lxofftxc += lxoff;
5338 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5339 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5340 /*
5341 * 82598 errata - tx of flow control packets is included in tx counters
5342 */
5343 xon_off_tot = lxon + lxoff;
5344 hwstats->gptc -= xon_off_tot;
5345 hwstats->mptc -= xon_off_tot;
5346 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5347 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5348 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5349 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5350 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5351 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5352 hwstats->ptc64 -= xon_off_tot;
5353 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5354 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5355 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5356 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5357 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5358 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5359
5360 /* Fill out the OS statistics structure */
5361 netdev->stats.multicast = hwstats->mprc;
5362
5363 /* Rx Errors */
5364 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5365 netdev->stats.rx_dropped = 0;
5366 netdev->stats.rx_length_errors = hwstats->rlec;
5367 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5368 netdev->stats.rx_missed_errors = total_mpc;
5369 }
5370
5371 /**
5372 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5373 * @adapter: pointer to the device adapter structure
5374 **/
5375 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5376 {
5377 struct ixgbe_hw *hw = &adapter->hw;
5378 int i;
5379
5380 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5381 return;
5382
5383 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5384
5385 /* if interface is down do nothing */
5386 if (test_bit(__IXGBE_DOWN, &adapter->state))
5387 return;
5388
5389 /* do nothing if we are not using signature filters */
5390 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5391 return;
5392
5393 adapter->fdir_overflow++;
5394
5395 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5396 for (i = 0; i < adapter->num_tx_queues; i++)
5397 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5398 &(adapter->tx_ring[i]->state));
5399 /* re-enable flow director interrupts */
5400 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5401 } else {
5402 e_err(probe, "failed to finish FDIR re-initialization, "
5403 "ignored adding FDIR ATR filters\n");
5404 }
5405 }
5406
5407 /**
5408 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5409 * @adapter: pointer to the device adapter structure
5410 *
5411 * This function serves two purposes. First it strobes the interrupt lines
5412 * in order to make certain interrupts are occurring. Secondly it sets the
5413 * bits needed to check for TX hangs. As a result we should immediately
5414 * determine if a hang has occurred.
5415 */
5416 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5417 {
5418 struct ixgbe_hw *hw = &adapter->hw;
5419 u64 eics = 0;
5420 int i;
5421
5422 /* If we're down or resetting, just bail */
5423 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5424 test_bit(__IXGBE_RESETTING, &adapter->state))
5425 return;
5426
5427 /* Force detection of hung controller */
5428 if (netif_carrier_ok(adapter->netdev)) {
5429 for (i = 0; i < adapter->num_tx_queues; i++)
5430 set_check_for_tx_hang(adapter->tx_ring[i]);
5431 }
5432
5433 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5434 /*
5435 * for legacy and MSI interrupts don't set any bits
5436 * that are enabled for EIAM, because this operation
5437 * would set *both* EIMS and EICS for any bit in EIAM
5438 */
5439 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5440 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5441 } else {
5442 /* get one bit for every active tx/rx interrupt vector */
5443 for (i = 0; i < adapter->num_q_vectors; i++) {
5444 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5445 if (qv->rx.ring || qv->tx.ring)
5446 eics |= ((u64)1 << i);
5447 }
5448 }
5449
5450 /* Cause software interrupt to ensure rings are cleaned */
5451 ixgbe_irq_rearm_queues(adapter, eics);
5452
5453 }
5454
5455 /**
5456 * ixgbe_watchdog_update_link - update the link status
5457 * @adapter: pointer to the device adapter structure
5458 * @link_speed: pointer to a u32 to store the link_speed
5459 **/
5460 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5461 {
5462 struct ixgbe_hw *hw = &adapter->hw;
5463 u32 link_speed = adapter->link_speed;
5464 bool link_up = adapter->link_up;
5465 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5466
5467 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5468 return;
5469
5470 if (hw->mac.ops.check_link) {
5471 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5472 } else {
5473 /* always assume link is up, if no check link function */
5474 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5475 link_up = true;
5476 }
5477
5478 if (adapter->ixgbe_ieee_pfc)
5479 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5480
5481 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5482 hw->mac.ops.fc_enable(hw);
5483 ixgbe_set_rx_drop_en(adapter);
5484 }
5485
5486 if (link_up ||
5487 time_after(jiffies, (adapter->link_check_timeout +
5488 IXGBE_TRY_LINK_TIMEOUT))) {
5489 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5490 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5491 IXGBE_WRITE_FLUSH(hw);
5492 }
5493
5494 adapter->link_up = link_up;
5495 adapter->link_speed = link_speed;
5496 }
5497
5498 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5499 {
5500 #ifdef CONFIG_IXGBE_DCB
5501 struct net_device *netdev = adapter->netdev;
5502 struct dcb_app app = {
5503 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5504 .protocol = 0,
5505 };
5506 u8 up = 0;
5507
5508 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5509 up = dcb_ieee_getapp_mask(netdev, &app);
5510
5511 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5512 #endif
5513 }
5514
5515 /**
5516 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5517 * print link up message
5518 * @adapter: pointer to the device adapter structure
5519 **/
5520 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5521 {
5522 struct net_device *netdev = adapter->netdev;
5523 struct ixgbe_hw *hw = &adapter->hw;
5524 u32 link_speed = adapter->link_speed;
5525 bool flow_rx, flow_tx;
5526
5527 /* only continue if link was previously down */
5528 if (netif_carrier_ok(netdev))
5529 return;
5530
5531 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5532
5533 switch (hw->mac.type) {
5534 case ixgbe_mac_82598EB: {
5535 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5536 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5537 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5538 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5539 }
5540 break;
5541 case ixgbe_mac_X540:
5542 case ixgbe_mac_82599EB: {
5543 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5544 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5545 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5546 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5547 }
5548 break;
5549 default:
5550 flow_tx = false;
5551 flow_rx = false;
5552 break;
5553 }
5554
5555 adapter->last_rx_ptp_check = jiffies;
5556
5557 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5558 ixgbe_ptp_start_cyclecounter(adapter);
5559
5560 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5561 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5562 "10 Gbps" :
5563 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5564 "1 Gbps" :
5565 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5566 "100 Mbps" :
5567 "unknown speed"))),
5568 ((flow_rx && flow_tx) ? "RX/TX" :
5569 (flow_rx ? "RX" :
5570 (flow_tx ? "TX" : "None"))));
5571
5572 netif_carrier_on(netdev);
5573 ixgbe_check_vf_rate_limit(adapter);
5574
5575 /* update the default user priority for VFs */
5576 ixgbe_update_default_up(adapter);
5577
5578 /* ping all the active vfs to let them know link has changed */
5579 ixgbe_ping_all_vfs(adapter);
5580 }
5581
5582 /**
5583 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5584 * print link down message
5585 * @adapter: pointer to the adapter structure
5586 **/
5587 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5588 {
5589 struct net_device *netdev = adapter->netdev;
5590 struct ixgbe_hw *hw = &adapter->hw;
5591
5592 adapter->link_up = false;
5593 adapter->link_speed = 0;
5594
5595 /* only continue if link was up previously */
5596 if (!netif_carrier_ok(netdev))
5597 return;
5598
5599 /* poll for SFP+ cable when link is down */
5600 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5601 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5602
5603 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5604 ixgbe_ptp_start_cyclecounter(adapter);
5605
5606 e_info(drv, "NIC Link is Down\n");
5607 netif_carrier_off(netdev);
5608
5609 /* ping all the active vfs to let them know link has changed */
5610 ixgbe_ping_all_vfs(adapter);
5611 }
5612
5613 /**
5614 * ixgbe_watchdog_flush_tx - flush queues on link down
5615 * @adapter: pointer to the device adapter structure
5616 **/
5617 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5618 {
5619 int i;
5620 int some_tx_pending = 0;
5621
5622 if (!netif_carrier_ok(adapter->netdev)) {
5623 for (i = 0; i < adapter->num_tx_queues; i++) {
5624 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5625 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5626 some_tx_pending = 1;
5627 break;
5628 }
5629 }
5630
5631 if (some_tx_pending) {
5632 /* We've lost link, so the controller stops DMA,
5633 * but we've got queued Tx work that's never going
5634 * to get done, so reset controller to flush Tx.
5635 * (Do the reset outside of interrupt context).
5636 */
5637 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5638 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5639 }
5640 }
5641 }
5642
5643 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5644 {
5645 u32 ssvpc;
5646
5647 /* Do not perform spoof check for 82598 or if not in IOV mode */
5648 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5649 adapter->num_vfs == 0)
5650 return;
5651
5652 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5653
5654 /*
5655 * ssvpc register is cleared on read, if zero then no
5656 * spoofed packets in the last interval.
5657 */
5658 if (!ssvpc)
5659 return;
5660
5661 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5662 }
5663
5664 /**
5665 * ixgbe_watchdog_subtask - check and bring link up
5666 * @adapter: pointer to the device adapter structure
5667 **/
5668 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5669 {
5670 /* if interface is down do nothing */
5671 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5672 test_bit(__IXGBE_RESETTING, &adapter->state))
5673 return;
5674
5675 ixgbe_watchdog_update_link(adapter);
5676
5677 if (adapter->link_up)
5678 ixgbe_watchdog_link_is_up(adapter);
5679 else
5680 ixgbe_watchdog_link_is_down(adapter);
5681
5682 ixgbe_spoof_check(adapter);
5683 ixgbe_update_stats(adapter);
5684
5685 ixgbe_watchdog_flush_tx(adapter);
5686 }
5687
5688 /**
5689 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5690 * @adapter: the ixgbe adapter structure
5691 **/
5692 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5693 {
5694 struct ixgbe_hw *hw = &adapter->hw;
5695 s32 err;
5696
5697 /* not searching for SFP so there is nothing to do here */
5698 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5699 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5700 return;
5701
5702 /* someone else is in init, wait until next service event */
5703 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5704 return;
5705
5706 err = hw->phy.ops.identify_sfp(hw);
5707 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5708 goto sfp_out;
5709
5710 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5711 /* If no cable is present, then we need to reset
5712 * the next time we find a good cable. */
5713 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5714 }
5715
5716 /* exit on error */
5717 if (err)
5718 goto sfp_out;
5719
5720 /* exit if reset not needed */
5721 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5722 goto sfp_out;
5723
5724 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5725
5726 /*
5727 * A module may be identified correctly, but the EEPROM may not have
5728 * support for that module. setup_sfp() will fail in that case, so
5729 * we should not allow that module to load.
5730 */
5731 if (hw->mac.type == ixgbe_mac_82598EB)
5732 err = hw->phy.ops.reset(hw);
5733 else
5734 err = hw->mac.ops.setup_sfp(hw);
5735
5736 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5737 goto sfp_out;
5738
5739 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5740 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5741
5742 sfp_out:
5743 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5744
5745 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5746 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5747 e_dev_err("failed to initialize because an unsupported "
5748 "SFP+ module type was detected.\n");
5749 e_dev_err("Reload the driver after installing a "
5750 "supported module.\n");
5751 unregister_netdev(adapter->netdev);
5752 }
5753 }
5754
5755 /**
5756 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5757 * @adapter: the ixgbe adapter structure
5758 **/
5759 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5760 {
5761 struct ixgbe_hw *hw = &adapter->hw;
5762 u32 speed;
5763 bool autoneg = false;
5764
5765 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5766 return;
5767
5768 /* someone else is in init, wait until next service event */
5769 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5770 return;
5771
5772 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5773
5774 speed = hw->phy.autoneg_advertised;
5775 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5776 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
5777 if (hw->mac.ops.setup_link)
5778 hw->mac.ops.setup_link(hw, speed, true);
5779
5780 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5781 adapter->link_check_timeout = jiffies;
5782 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5783 }
5784
5785 #ifdef CONFIG_PCI_IOV
5786 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5787 {
5788 int vf;
5789 struct ixgbe_hw *hw = &adapter->hw;
5790 struct net_device *netdev = adapter->netdev;
5791 u32 gpc;
5792 u32 ciaa, ciad;
5793
5794 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5795 if (gpc) /* If incrementing then no need for the check below */
5796 return;
5797 /*
5798 * Check to see if a bad DMA write target from an errant or
5799 * malicious VF has caused a PCIe error. If so then we can
5800 * issue a VFLR to the offending VF(s) and then resume without
5801 * requesting a full slot reset.
5802 */
5803
5804 for (vf = 0; vf < adapter->num_vfs; vf++) {
5805 ciaa = (vf << 16) | 0x80000000;
5806 /* 32 bit read so align, we really want status at offset 6 */
5807 ciaa |= PCI_COMMAND;
5808 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5809 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5810 ciaa &= 0x7FFFFFFF;
5811 /* disable debug mode asap after reading data */
5812 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5813 /* Get the upper 16 bits which will be the PCI status reg */
5814 ciad >>= 16;
5815 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5816 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5817 /* Issue VFLR */
5818 ciaa = (vf << 16) | 0x80000000;
5819 ciaa |= 0xA8;
5820 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5821 ciad = 0x00008000; /* VFLR */
5822 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5823 ciaa &= 0x7FFFFFFF;
5824 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5825 }
5826 }
5827 }
5828
5829 #endif
5830 /**
5831 * ixgbe_service_timer - Timer Call-back
5832 * @data: pointer to adapter cast into an unsigned long
5833 **/
5834 static void ixgbe_service_timer(unsigned long data)
5835 {
5836 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5837 unsigned long next_event_offset;
5838 bool ready = true;
5839
5840 /* poll faster when waiting for link */
5841 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5842 next_event_offset = HZ / 10;
5843 else
5844 next_event_offset = HZ * 2;
5845
5846 #ifdef CONFIG_PCI_IOV
5847 /*
5848 * don't bother with SR-IOV VF DMA hang check if there are
5849 * no VFs or the link is down
5850 */
5851 if (!adapter->num_vfs ||
5852 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5853 goto normal_timer_service;
5854
5855 /* If we have VFs allocated then we must check for DMA hangs */
5856 ixgbe_check_for_bad_vf(adapter);
5857 next_event_offset = HZ / 50;
5858 adapter->timer_event_accumulator++;
5859
5860 if (adapter->timer_event_accumulator >= 100)
5861 adapter->timer_event_accumulator = 0;
5862 else
5863 ready = false;
5864
5865 normal_timer_service:
5866 #endif
5867 /* Reset the timer */
5868 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5869
5870 if (ready)
5871 ixgbe_service_event_schedule(adapter);
5872 }
5873
5874 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5875 {
5876 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5877 return;
5878
5879 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5880
5881 /* If we're already down or resetting, just bail */
5882 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5883 test_bit(__IXGBE_RESETTING, &adapter->state))
5884 return;
5885
5886 ixgbe_dump(adapter);
5887 netdev_err(adapter->netdev, "Reset adapter\n");
5888 adapter->tx_timeout_count++;
5889
5890 ixgbe_reinit_locked(adapter);
5891 }
5892
5893 /**
5894 * ixgbe_service_task - manages and runs subtasks
5895 * @work: pointer to work_struct containing our data
5896 **/
5897 static void ixgbe_service_task(struct work_struct *work)
5898 {
5899 struct ixgbe_adapter *adapter = container_of(work,
5900 struct ixgbe_adapter,
5901 service_task);
5902 ixgbe_reset_subtask(adapter);
5903 ixgbe_sfp_detection_subtask(adapter);
5904 ixgbe_sfp_link_config_subtask(adapter);
5905 ixgbe_check_overtemp_subtask(adapter);
5906 ixgbe_watchdog_subtask(adapter);
5907 ixgbe_fdir_reinit_subtask(adapter);
5908 ixgbe_check_hang_subtask(adapter);
5909
5910 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5911 ixgbe_ptp_overflow_check(adapter);
5912 ixgbe_ptp_rx_hang(adapter);
5913 }
5914
5915 ixgbe_service_event_complete(adapter);
5916 }
5917
5918 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5919 struct ixgbe_tx_buffer *first,
5920 u8 *hdr_len)
5921 {
5922 struct sk_buff *skb = first->skb;
5923 u32 vlan_macip_lens, type_tucmd;
5924 u32 mss_l4len_idx, l4len;
5925
5926 if (skb->ip_summed != CHECKSUM_PARTIAL)
5927 return 0;
5928
5929 if (!skb_is_gso(skb))
5930 return 0;
5931
5932 if (skb_header_cloned(skb)) {
5933 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5934 if (err)
5935 return err;
5936 }
5937
5938 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5939 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5940
5941 if (first->protocol == __constant_htons(ETH_P_IP)) {
5942 struct iphdr *iph = ip_hdr(skb);
5943 iph->tot_len = 0;
5944 iph->check = 0;
5945 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5946 iph->daddr, 0,
5947 IPPROTO_TCP,
5948 0);
5949 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5950 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5951 IXGBE_TX_FLAGS_CSUM |
5952 IXGBE_TX_FLAGS_IPV4;
5953 } else if (skb_is_gso_v6(skb)) {
5954 ipv6_hdr(skb)->payload_len = 0;
5955 tcp_hdr(skb)->check =
5956 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5957 &ipv6_hdr(skb)->daddr,
5958 0, IPPROTO_TCP, 0);
5959 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5960 IXGBE_TX_FLAGS_CSUM;
5961 }
5962
5963 /* compute header lengths */
5964 l4len = tcp_hdrlen(skb);
5965 *hdr_len = skb_transport_offset(skb) + l4len;
5966
5967 /* update gso size and bytecount with header size */
5968 first->gso_segs = skb_shinfo(skb)->gso_segs;
5969 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5970
5971 /* mss_l4len_id: use 0 as index for TSO */
5972 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5973 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5974
5975 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5976 vlan_macip_lens = skb_network_header_len(skb);
5977 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5978 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5979
5980 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5981 mss_l4len_idx);
5982
5983 return 1;
5984 }
5985
5986 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5987 struct ixgbe_tx_buffer *first)
5988 {
5989 struct sk_buff *skb = first->skb;
5990 u32 vlan_macip_lens = 0;
5991 u32 mss_l4len_idx = 0;
5992 u32 type_tucmd = 0;
5993
5994 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5995 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5996 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
5997 return;
5998 } else {
5999 u8 l4_hdr = 0;
6000 switch (first->protocol) {
6001 case __constant_htons(ETH_P_IP):
6002 vlan_macip_lens |= skb_network_header_len(skb);
6003 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6004 l4_hdr = ip_hdr(skb)->protocol;
6005 break;
6006 case __constant_htons(ETH_P_IPV6):
6007 vlan_macip_lens |= skb_network_header_len(skb);
6008 l4_hdr = ipv6_hdr(skb)->nexthdr;
6009 break;
6010 default:
6011 if (unlikely(net_ratelimit())) {
6012 dev_warn(tx_ring->dev,
6013 "partial checksum but proto=%x!\n",
6014 first->protocol);
6015 }
6016 break;
6017 }
6018
6019 switch (l4_hdr) {
6020 case IPPROTO_TCP:
6021 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6022 mss_l4len_idx = tcp_hdrlen(skb) <<
6023 IXGBE_ADVTXD_L4LEN_SHIFT;
6024 break;
6025 case IPPROTO_SCTP:
6026 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6027 mss_l4len_idx = sizeof(struct sctphdr) <<
6028 IXGBE_ADVTXD_L4LEN_SHIFT;
6029 break;
6030 case IPPROTO_UDP:
6031 mss_l4len_idx = sizeof(struct udphdr) <<
6032 IXGBE_ADVTXD_L4LEN_SHIFT;
6033 break;
6034 default:
6035 if (unlikely(net_ratelimit())) {
6036 dev_warn(tx_ring->dev,
6037 "partial checksum but l4 proto=%x!\n",
6038 l4_hdr);
6039 }
6040 break;
6041 }
6042
6043 /* update TX checksum flag */
6044 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6045 }
6046
6047 /* vlan_macip_lens: MACLEN, VLAN tag */
6048 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6049 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6050
6051 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6052 type_tucmd, mss_l4len_idx);
6053 }
6054
6055 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6056 ((_flag <= _result) ? \
6057 ((u32)(_input & _flag) * (_result / _flag)) : \
6058 ((u32)(_input & _flag) / (_flag / _result)))
6059
6060 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6061 {
6062 /* set type for advanced descriptor with frame checksum insertion */
6063 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6064 IXGBE_ADVTXD_DCMD_DEXT |
6065 IXGBE_ADVTXD_DCMD_IFCS;
6066
6067 /* set HW vlan bit if vlan is present */
6068 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6069 IXGBE_ADVTXD_DCMD_VLE);
6070
6071 /* set segmentation enable bits for TSO/FSO */
6072 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6073 IXGBE_ADVTXD_DCMD_TSE);
6074
6075 /* set timestamp bit if present */
6076 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6077 IXGBE_ADVTXD_MAC_TSTAMP);
6078
6079 /* insert frame checksum */
6080 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6081
6082 return cmd_type;
6083 }
6084
6085 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6086 u32 tx_flags, unsigned int paylen)
6087 {
6088 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6089
6090 /* enable L4 checksum for TSO and TX checksum offload */
6091 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6092 IXGBE_TX_FLAGS_CSUM,
6093 IXGBE_ADVTXD_POPTS_TXSM);
6094
6095 /* enble IPv4 checksum for TSO */
6096 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6097 IXGBE_TX_FLAGS_IPV4,
6098 IXGBE_ADVTXD_POPTS_IXSM);
6099
6100 /*
6101 * Check Context must be set if Tx switch is enabled, which it
6102 * always is for case where virtual functions are running
6103 */
6104 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6105 IXGBE_TX_FLAGS_CC,
6106 IXGBE_ADVTXD_CC);
6107
6108 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6109 }
6110
6111 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6112 IXGBE_TXD_CMD_RS)
6113
6114 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6115 struct ixgbe_tx_buffer *first,
6116 const u8 hdr_len)
6117 {
6118 struct sk_buff *skb = first->skb;
6119 struct ixgbe_tx_buffer *tx_buffer;
6120 union ixgbe_adv_tx_desc *tx_desc;
6121 struct skb_frag_struct *frag;
6122 dma_addr_t dma;
6123 unsigned int data_len, size;
6124 u32 tx_flags = first->tx_flags;
6125 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6126 u16 i = tx_ring->next_to_use;
6127
6128 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6129
6130 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6131
6132 size = skb_headlen(skb);
6133 data_len = skb->data_len;
6134
6135 #ifdef IXGBE_FCOE
6136 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6137 if (data_len < sizeof(struct fcoe_crc_eof)) {
6138 size -= sizeof(struct fcoe_crc_eof) - data_len;
6139 data_len = 0;
6140 } else {
6141 data_len -= sizeof(struct fcoe_crc_eof);
6142 }
6143 }
6144
6145 #endif
6146 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6147
6148 tx_buffer = first;
6149
6150 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6151 if (dma_mapping_error(tx_ring->dev, dma))
6152 goto dma_error;
6153
6154 /* record length, and DMA address */
6155 dma_unmap_len_set(tx_buffer, len, size);
6156 dma_unmap_addr_set(tx_buffer, dma, dma);
6157
6158 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6159
6160 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6161 tx_desc->read.cmd_type_len =
6162 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6163
6164 i++;
6165 tx_desc++;
6166 if (i == tx_ring->count) {
6167 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6168 i = 0;
6169 }
6170 tx_desc->read.olinfo_status = 0;
6171
6172 dma += IXGBE_MAX_DATA_PER_TXD;
6173 size -= IXGBE_MAX_DATA_PER_TXD;
6174
6175 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6176 }
6177
6178 if (likely(!data_len))
6179 break;
6180
6181 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6182
6183 i++;
6184 tx_desc++;
6185 if (i == tx_ring->count) {
6186 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6187 i = 0;
6188 }
6189 tx_desc->read.olinfo_status = 0;
6190
6191 #ifdef IXGBE_FCOE
6192 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6193 #else
6194 size = skb_frag_size(frag);
6195 #endif
6196 data_len -= size;
6197
6198 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6199 DMA_TO_DEVICE);
6200
6201 tx_buffer = &tx_ring->tx_buffer_info[i];
6202 }
6203
6204 /* write last descriptor with RS and EOP bits */
6205 cmd_type |= size | IXGBE_TXD_CMD;
6206 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6207
6208 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6209
6210 /* set the timestamp */
6211 first->time_stamp = jiffies;
6212
6213 /*
6214 * Force memory writes to complete before letting h/w know there
6215 * are new descriptors to fetch. (Only applicable for weak-ordered
6216 * memory model archs, such as IA-64).
6217 *
6218 * We also need this memory barrier to make certain all of the
6219 * status bits have been updated before next_to_watch is written.
6220 */
6221 wmb();
6222
6223 /* set next_to_watch value indicating a packet is present */
6224 first->next_to_watch = tx_desc;
6225
6226 i++;
6227 if (i == tx_ring->count)
6228 i = 0;
6229
6230 tx_ring->next_to_use = i;
6231
6232 /* notify HW of packet */
6233 writel(i, tx_ring->tail);
6234
6235 return;
6236 dma_error:
6237 dev_err(tx_ring->dev, "TX DMA map failed\n");
6238
6239 /* clear dma mappings for failed tx_buffer_info map */
6240 for (;;) {
6241 tx_buffer = &tx_ring->tx_buffer_info[i];
6242 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6243 if (tx_buffer == first)
6244 break;
6245 if (i == 0)
6246 i = tx_ring->count;
6247 i--;
6248 }
6249
6250 tx_ring->next_to_use = i;
6251 }
6252
6253 static void ixgbe_atr(struct ixgbe_ring *ring,
6254 struct ixgbe_tx_buffer *first)
6255 {
6256 struct ixgbe_q_vector *q_vector = ring->q_vector;
6257 union ixgbe_atr_hash_dword input = { .dword = 0 };
6258 union ixgbe_atr_hash_dword common = { .dword = 0 };
6259 union {
6260 unsigned char *network;
6261 struct iphdr *ipv4;
6262 struct ipv6hdr *ipv6;
6263 } hdr;
6264 struct tcphdr *th;
6265 __be16 vlan_id;
6266
6267 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6268 if (!q_vector)
6269 return;
6270
6271 /* do nothing if sampling is disabled */
6272 if (!ring->atr_sample_rate)
6273 return;
6274
6275 ring->atr_count++;
6276
6277 /* snag network header to get L4 type and address */
6278 hdr.network = skb_network_header(first->skb);
6279
6280 /* Currently only IPv4/IPv6 with TCP is supported */
6281 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6282 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6283 (first->protocol != __constant_htons(ETH_P_IP) ||
6284 hdr.ipv4->protocol != IPPROTO_TCP))
6285 return;
6286
6287 th = tcp_hdr(first->skb);
6288
6289 /* skip this packet since it is invalid or the socket is closing */
6290 if (!th || th->fin)
6291 return;
6292
6293 /* sample on all syn packets or once every atr sample count */
6294 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6295 return;
6296
6297 /* reset sample count */
6298 ring->atr_count = 0;
6299
6300 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6301
6302 /*
6303 * src and dst are inverted, think how the receiver sees them
6304 *
6305 * The input is broken into two sections, a non-compressed section
6306 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6307 * is XORed together and stored in the compressed dword.
6308 */
6309 input.formatted.vlan_id = vlan_id;
6310
6311 /*
6312 * since src port and flex bytes occupy the same word XOR them together
6313 * and write the value to source port portion of compressed dword
6314 */
6315 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6316 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6317 else
6318 common.port.src ^= th->dest ^ first->protocol;
6319 common.port.dst ^= th->source;
6320
6321 if (first->protocol == __constant_htons(ETH_P_IP)) {
6322 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6323 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6324 } else {
6325 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6326 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6327 hdr.ipv6->saddr.s6_addr32[1] ^
6328 hdr.ipv6->saddr.s6_addr32[2] ^
6329 hdr.ipv6->saddr.s6_addr32[3] ^
6330 hdr.ipv6->daddr.s6_addr32[0] ^
6331 hdr.ipv6->daddr.s6_addr32[1] ^
6332 hdr.ipv6->daddr.s6_addr32[2] ^
6333 hdr.ipv6->daddr.s6_addr32[3];
6334 }
6335
6336 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6337 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6338 input, common, ring->queue_index);
6339 }
6340
6341 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6342 {
6343 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6344 /* Herbert's original patch had:
6345 * smp_mb__after_netif_stop_queue();
6346 * but since that doesn't exist yet, just open code it. */
6347 smp_mb();
6348
6349 /* We need to check again in a case another CPU has just
6350 * made room available. */
6351 if (likely(ixgbe_desc_unused(tx_ring) < size))
6352 return -EBUSY;
6353
6354 /* A reprieve! - use start_queue because it doesn't call schedule */
6355 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6356 ++tx_ring->tx_stats.restart_queue;
6357 return 0;
6358 }
6359
6360 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6361 {
6362 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6363 return 0;
6364 return __ixgbe_maybe_stop_tx(tx_ring, size);
6365 }
6366
6367 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6368 {
6369 struct ixgbe_adapter *adapter = netdev_priv(dev);
6370 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6371 smp_processor_id();
6372 #ifdef IXGBE_FCOE
6373 __be16 protocol = vlan_get_protocol(skb);
6374
6375 if (((protocol == htons(ETH_P_FCOE)) ||
6376 (protocol == htons(ETH_P_FIP))) &&
6377 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6378 struct ixgbe_ring_feature *f;
6379
6380 f = &adapter->ring_feature[RING_F_FCOE];
6381
6382 while (txq >= f->indices)
6383 txq -= f->indices;
6384 txq += adapter->ring_feature[RING_F_FCOE].offset;
6385
6386 return txq;
6387 }
6388 #endif
6389
6390 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6391 while (unlikely(txq >= dev->real_num_tx_queues))
6392 txq -= dev->real_num_tx_queues;
6393 return txq;
6394 }
6395
6396 return skb_tx_hash(dev, skb);
6397 }
6398
6399 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6400 struct ixgbe_adapter *adapter,
6401 struct ixgbe_ring *tx_ring)
6402 {
6403 struct ixgbe_tx_buffer *first;
6404 int tso;
6405 u32 tx_flags = 0;
6406 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6407 unsigned short f;
6408 #endif
6409 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6410 __be16 protocol = skb->protocol;
6411 u8 hdr_len = 0;
6412
6413 /*
6414 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6415 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6416 * + 2 desc gap to keep tail from touching head,
6417 * + 1 desc for context descriptor,
6418 * otherwise try next time
6419 */
6420 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6421 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6422 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6423 #else
6424 count += skb_shinfo(skb)->nr_frags;
6425 #endif
6426 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6427 tx_ring->tx_stats.tx_busy++;
6428 return NETDEV_TX_BUSY;
6429 }
6430
6431 /* record the location of the first descriptor for this packet */
6432 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6433 first->skb = skb;
6434 first->bytecount = skb->len;
6435 first->gso_segs = 1;
6436
6437 /* if we have a HW VLAN tag being added default to the HW one */
6438 if (vlan_tx_tag_present(skb)) {
6439 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6440 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6441 /* else if it is a SW VLAN check the next protocol and store the tag */
6442 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6443 struct vlan_hdr *vhdr, _vhdr;
6444 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6445 if (!vhdr)
6446 goto out_drop;
6447
6448 protocol = vhdr->h_vlan_encapsulated_proto;
6449 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6450 IXGBE_TX_FLAGS_VLAN_SHIFT;
6451 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6452 }
6453
6454 skb_tx_timestamp(skb);
6455
6456 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6457 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6458 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6459
6460 /* schedule check for Tx timestamp */
6461 adapter->ptp_tx_skb = skb_get(skb);
6462 adapter->ptp_tx_start = jiffies;
6463 schedule_work(&adapter->ptp_tx_work);
6464 }
6465
6466 #ifdef CONFIG_PCI_IOV
6467 /*
6468 * Use the l2switch_enable flag - would be false if the DMA
6469 * Tx switch had been disabled.
6470 */
6471 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6472 tx_flags |= IXGBE_TX_FLAGS_CC;
6473
6474 #endif
6475 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6476 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6477 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6478 (skb->priority != TC_PRIO_CONTROL))) {
6479 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6480 tx_flags |= (skb->priority & 0x7) <<
6481 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6482 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6483 struct vlan_ethhdr *vhdr;
6484 if (skb_header_cloned(skb) &&
6485 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6486 goto out_drop;
6487 vhdr = (struct vlan_ethhdr *)skb->data;
6488 vhdr->h_vlan_TCI = htons(tx_flags >>
6489 IXGBE_TX_FLAGS_VLAN_SHIFT);
6490 } else {
6491 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6492 }
6493 }
6494
6495 /* record initial flags and protocol */
6496 first->tx_flags = tx_flags;
6497 first->protocol = protocol;
6498
6499 #ifdef IXGBE_FCOE
6500 /* setup tx offload for FCoE */
6501 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6502 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6503 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6504 if (tso < 0)
6505 goto out_drop;
6506
6507 goto xmit_fcoe;
6508 }
6509
6510 #endif /* IXGBE_FCOE */
6511 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6512 if (tso < 0)
6513 goto out_drop;
6514 else if (!tso)
6515 ixgbe_tx_csum(tx_ring, first);
6516
6517 /* add the ATR filter if ATR is on */
6518 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6519 ixgbe_atr(tx_ring, first);
6520
6521 #ifdef IXGBE_FCOE
6522 xmit_fcoe:
6523 #endif /* IXGBE_FCOE */
6524 ixgbe_tx_map(tx_ring, first, hdr_len);
6525
6526 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6527
6528 return NETDEV_TX_OK;
6529
6530 out_drop:
6531 dev_kfree_skb_any(first->skb);
6532 first->skb = NULL;
6533
6534 return NETDEV_TX_OK;
6535 }
6536
6537 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6538 struct net_device *netdev)
6539 {
6540 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6541 struct ixgbe_ring *tx_ring;
6542
6543 /*
6544 * The minimum packet size for olinfo paylen is 17 so pad the skb
6545 * in order to meet this minimum size requirement.
6546 */
6547 if (unlikely(skb->len < 17)) {
6548 if (skb_pad(skb, 17 - skb->len))
6549 return NETDEV_TX_OK;
6550 skb->len = 17;
6551 skb_set_tail_pointer(skb, 17);
6552 }
6553
6554 tx_ring = adapter->tx_ring[skb->queue_mapping];
6555 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6556 }
6557
6558 /**
6559 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6560 * @netdev: network interface device structure
6561 * @p: pointer to an address structure
6562 *
6563 * Returns 0 on success, negative on failure
6564 **/
6565 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6566 {
6567 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6568 struct ixgbe_hw *hw = &adapter->hw;
6569 struct sockaddr *addr = p;
6570
6571 if (!is_valid_ether_addr(addr->sa_data))
6572 return -EADDRNOTAVAIL;
6573
6574 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6575 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6576
6577 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6578
6579 return 0;
6580 }
6581
6582 static int
6583 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6584 {
6585 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6586 struct ixgbe_hw *hw = &adapter->hw;
6587 u16 value;
6588 int rc;
6589
6590 if (prtad != hw->phy.mdio.prtad)
6591 return -EINVAL;
6592 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6593 if (!rc)
6594 rc = value;
6595 return rc;
6596 }
6597
6598 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6599 u16 addr, u16 value)
6600 {
6601 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6602 struct ixgbe_hw *hw = &adapter->hw;
6603
6604 if (prtad != hw->phy.mdio.prtad)
6605 return -EINVAL;
6606 return hw->phy.ops.write_reg(hw, addr, devad, value);
6607 }
6608
6609 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6610 {
6611 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6612
6613 switch (cmd) {
6614 case SIOCSHWTSTAMP:
6615 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6616 default:
6617 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6618 }
6619 }
6620
6621 /**
6622 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6623 * netdev->dev_addrs
6624 * @netdev: network interface device structure
6625 *
6626 * Returns non-zero on failure
6627 **/
6628 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6629 {
6630 int err = 0;
6631 struct ixgbe_adapter *adapter = netdev_priv(dev);
6632 struct ixgbe_hw *hw = &adapter->hw;
6633
6634 if (is_valid_ether_addr(hw->mac.san_addr)) {
6635 rtnl_lock();
6636 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6637 rtnl_unlock();
6638
6639 /* update SAN MAC vmdq pool selection */
6640 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6641 }
6642 return err;
6643 }
6644
6645 /**
6646 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6647 * netdev->dev_addrs
6648 * @netdev: network interface device structure
6649 *
6650 * Returns non-zero on failure
6651 **/
6652 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6653 {
6654 int err = 0;
6655 struct ixgbe_adapter *adapter = netdev_priv(dev);
6656 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6657
6658 if (is_valid_ether_addr(mac->san_addr)) {
6659 rtnl_lock();
6660 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6661 rtnl_unlock();
6662 }
6663 return err;
6664 }
6665
6666 #ifdef CONFIG_NET_POLL_CONTROLLER
6667 /*
6668 * Polling 'interrupt' - used by things like netconsole to send skbs
6669 * without having to re-enable interrupts. It's not called while
6670 * the interrupt routine is executing.
6671 */
6672 static void ixgbe_netpoll(struct net_device *netdev)
6673 {
6674 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6675 int i;
6676
6677 /* if interface is down do nothing */
6678 if (test_bit(__IXGBE_DOWN, &adapter->state))
6679 return;
6680
6681 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6682 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6683 for (i = 0; i < adapter->num_q_vectors; i++)
6684 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6685 } else {
6686 ixgbe_intr(adapter->pdev->irq, netdev);
6687 }
6688 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6689 }
6690
6691 #endif
6692 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6693 struct rtnl_link_stats64 *stats)
6694 {
6695 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6696 int i;
6697
6698 rcu_read_lock();
6699 for (i = 0; i < adapter->num_rx_queues; i++) {
6700 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6701 u64 bytes, packets;
6702 unsigned int start;
6703
6704 if (ring) {
6705 do {
6706 start = u64_stats_fetch_begin_bh(&ring->syncp);
6707 packets = ring->stats.packets;
6708 bytes = ring->stats.bytes;
6709 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6710 stats->rx_packets += packets;
6711 stats->rx_bytes += bytes;
6712 }
6713 }
6714
6715 for (i = 0; i < adapter->num_tx_queues; i++) {
6716 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6717 u64 bytes, packets;
6718 unsigned int start;
6719
6720 if (ring) {
6721 do {
6722 start = u64_stats_fetch_begin_bh(&ring->syncp);
6723 packets = ring->stats.packets;
6724 bytes = ring->stats.bytes;
6725 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6726 stats->tx_packets += packets;
6727 stats->tx_bytes += bytes;
6728 }
6729 }
6730 rcu_read_unlock();
6731 /* following stats updated by ixgbe_watchdog_task() */
6732 stats->multicast = netdev->stats.multicast;
6733 stats->rx_errors = netdev->stats.rx_errors;
6734 stats->rx_length_errors = netdev->stats.rx_length_errors;
6735 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6736 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6737 return stats;
6738 }
6739
6740 #ifdef CONFIG_IXGBE_DCB
6741 /**
6742 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6743 * @adapter: pointer to ixgbe_adapter
6744 * @tc: number of traffic classes currently enabled
6745 *
6746 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6747 * 802.1Q priority maps to a packet buffer that exists.
6748 */
6749 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6750 {
6751 struct ixgbe_hw *hw = &adapter->hw;
6752 u32 reg, rsave;
6753 int i;
6754
6755 /* 82598 have a static priority to TC mapping that can not
6756 * be changed so no validation is needed.
6757 */
6758 if (hw->mac.type == ixgbe_mac_82598EB)
6759 return;
6760
6761 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6762 rsave = reg;
6763
6764 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6765 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6766
6767 /* If up2tc is out of bounds default to zero */
6768 if (up2tc > tc)
6769 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6770 }
6771
6772 if (reg != rsave)
6773 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6774
6775 return;
6776 }
6777
6778 /**
6779 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6780 * @adapter: Pointer to adapter struct
6781 *
6782 * Populate the netdev user priority to tc map
6783 */
6784 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6785 {
6786 struct net_device *dev = adapter->netdev;
6787 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6788 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6789 u8 prio;
6790
6791 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6792 u8 tc = 0;
6793
6794 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6795 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6796 else if (ets)
6797 tc = ets->prio_tc[prio];
6798
6799 netdev_set_prio_tc_map(dev, prio, tc);
6800 }
6801 }
6802
6803 /**
6804 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6805 *
6806 * @netdev: net device to configure
6807 * @tc: number of traffic classes to enable
6808 */
6809 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6810 {
6811 struct ixgbe_adapter *adapter = netdev_priv(dev);
6812 struct ixgbe_hw *hw = &adapter->hw;
6813
6814 /* Hardware supports up to 8 traffic classes */
6815 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6816 (hw->mac.type == ixgbe_mac_82598EB &&
6817 tc < MAX_TRAFFIC_CLASS))
6818 return -EINVAL;
6819
6820 /* Hardware has to reinitialize queues and interrupts to
6821 * match packet buffer alignment. Unfortunately, the
6822 * hardware is not flexible enough to do this dynamically.
6823 */
6824 if (netif_running(dev))
6825 ixgbe_close(dev);
6826 ixgbe_clear_interrupt_scheme(adapter);
6827
6828 if (tc) {
6829 netdev_set_num_tc(dev, tc);
6830 ixgbe_set_prio_tc_map(adapter);
6831
6832 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6833
6834 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6835 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6836 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6837 }
6838 } else {
6839 netdev_reset_tc(dev);
6840
6841 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6842 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6843
6844 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6845
6846 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6847 adapter->dcb_cfg.pfc_mode_enable = false;
6848 }
6849
6850 ixgbe_init_interrupt_scheme(adapter);
6851 ixgbe_validate_rtr(adapter, tc);
6852 if (netif_running(dev))
6853 ixgbe_open(dev);
6854
6855 return 0;
6856 }
6857
6858 #endif /* CONFIG_IXGBE_DCB */
6859 #ifdef CONFIG_PCI_IOV
6860 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6861 {
6862 struct net_device *netdev = adapter->netdev;
6863
6864 rtnl_lock();
6865 #ifdef CONFIG_IXGBE_DCB
6866 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
6867 #else
6868 if (netif_running(netdev))
6869 ixgbe_close(netdev);
6870 ixgbe_clear_interrupt_scheme(adapter);
6871 ixgbe_init_interrupt_scheme(adapter);
6872 if (netif_running(netdev))
6873 ixgbe_open(netdev);
6874 #endif
6875 rtnl_unlock();
6876 }
6877
6878 #endif
6879 void ixgbe_do_reset(struct net_device *netdev)
6880 {
6881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6882
6883 if (netif_running(netdev))
6884 ixgbe_reinit_locked(adapter);
6885 else
6886 ixgbe_reset(adapter);
6887 }
6888
6889 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6890 netdev_features_t features)
6891 {
6892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6893
6894 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6895 if (!(features & NETIF_F_RXCSUM))
6896 features &= ~NETIF_F_LRO;
6897
6898 /* Turn off LRO if not RSC capable */
6899 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6900 features &= ~NETIF_F_LRO;
6901
6902 return features;
6903 }
6904
6905 static int ixgbe_set_features(struct net_device *netdev,
6906 netdev_features_t features)
6907 {
6908 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6909 netdev_features_t changed = netdev->features ^ features;
6910 bool need_reset = false;
6911
6912 /* Make sure RSC matches LRO, reset if change */
6913 if (!(features & NETIF_F_LRO)) {
6914 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6915 need_reset = true;
6916 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6917 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6918 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6919 if (adapter->rx_itr_setting == 1 ||
6920 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6921 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6922 need_reset = true;
6923 } else if ((changed ^ features) & NETIF_F_LRO) {
6924 e_info(probe, "rx-usecs set too low, "
6925 "disabling RSC\n");
6926 }
6927 }
6928
6929 /*
6930 * Check if Flow Director n-tuple support was enabled or disabled. If
6931 * the state changed, we need to reset.
6932 */
6933 switch (features & NETIF_F_NTUPLE) {
6934 case NETIF_F_NTUPLE:
6935 /* turn off ATR, enable perfect filters and reset */
6936 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6937 need_reset = true;
6938
6939 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6940 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6941 break;
6942 default:
6943 /* turn off perfect filters, enable ATR and reset */
6944 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6945 need_reset = true;
6946
6947 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6948
6949 /* We cannot enable ATR if SR-IOV is enabled */
6950 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6951 break;
6952
6953 /* We cannot enable ATR if we have 2 or more traffic classes */
6954 if (netdev_get_num_tc(netdev) > 1)
6955 break;
6956
6957 /* We cannot enable ATR if RSS is disabled */
6958 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6959 break;
6960
6961 /* A sample rate of 0 indicates ATR disabled */
6962 if (!adapter->atr_sample_rate)
6963 break;
6964
6965 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6966 break;
6967 }
6968
6969 if (features & NETIF_F_HW_VLAN_RX)
6970 ixgbe_vlan_strip_enable(adapter);
6971 else
6972 ixgbe_vlan_strip_disable(adapter);
6973
6974 if (changed & NETIF_F_RXALL)
6975 need_reset = true;
6976
6977 netdev->features = features;
6978 if (need_reset)
6979 ixgbe_do_reset(netdev);
6980
6981 return 0;
6982 }
6983
6984 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6985 struct net_device *dev,
6986 const unsigned char *addr,
6987 u16 flags)
6988 {
6989 struct ixgbe_adapter *adapter = netdev_priv(dev);
6990 int err;
6991
6992 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6993 return -EOPNOTSUPP;
6994
6995 /* Hardware does not support aging addresses so if a
6996 * ndm_state is given only allow permanent addresses
6997 */
6998 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6999 pr_info("%s: FDB only supports static addresses\n",
7000 ixgbe_driver_name);
7001 return -EINVAL;
7002 }
7003
7004 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7005 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7006
7007 if (netdev_uc_count(dev) < rar_uc_entries)
7008 err = dev_uc_add_excl(dev, addr);
7009 else
7010 err = -ENOMEM;
7011 } else if (is_multicast_ether_addr(addr)) {
7012 err = dev_mc_add_excl(dev, addr);
7013 } else {
7014 err = -EINVAL;
7015 }
7016
7017 /* Only return duplicate errors if NLM_F_EXCL is set */
7018 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7019 err = 0;
7020
7021 return err;
7022 }
7023
7024 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
7025 struct net_device *dev,
7026 const unsigned char *addr)
7027 {
7028 struct ixgbe_adapter *adapter = netdev_priv(dev);
7029 int err = -EOPNOTSUPP;
7030
7031 if (ndm->ndm_state & NUD_PERMANENT) {
7032 pr_info("%s: FDB only supports static addresses\n",
7033 ixgbe_driver_name);
7034 return -EINVAL;
7035 }
7036
7037 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7038 if (is_unicast_ether_addr(addr))
7039 err = dev_uc_del(dev, addr);
7040 else if (is_multicast_ether_addr(addr))
7041 err = dev_mc_del(dev, addr);
7042 else
7043 err = -EINVAL;
7044 }
7045
7046 return err;
7047 }
7048
7049 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7050 struct netlink_callback *cb,
7051 struct net_device *dev,
7052 int idx)
7053 {
7054 struct ixgbe_adapter *adapter = netdev_priv(dev);
7055
7056 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7057 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7058
7059 return idx;
7060 }
7061
7062 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7063 struct nlmsghdr *nlh)
7064 {
7065 struct ixgbe_adapter *adapter = netdev_priv(dev);
7066 struct nlattr *attr, *br_spec;
7067 int rem;
7068
7069 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7070 return -EOPNOTSUPP;
7071
7072 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7073
7074 nla_for_each_nested(attr, br_spec, rem) {
7075 __u16 mode;
7076 u32 reg = 0;
7077
7078 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7079 continue;
7080
7081 mode = nla_get_u16(attr);
7082 if (mode == BRIDGE_MODE_VEPA) {
7083 reg = 0;
7084 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7085 } else if (mode == BRIDGE_MODE_VEB) {
7086 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7087 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7088 } else
7089 return -EINVAL;
7090
7091 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7092
7093 e_info(drv, "enabling bridge mode: %s\n",
7094 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7095 }
7096
7097 return 0;
7098 }
7099
7100 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7101 struct net_device *dev,
7102 u32 filter_mask)
7103 {
7104 struct ixgbe_adapter *adapter = netdev_priv(dev);
7105 u16 mode;
7106
7107 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7108 return 0;
7109
7110 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7111 mode = BRIDGE_MODE_VEB;
7112 else
7113 mode = BRIDGE_MODE_VEPA;
7114
7115 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7116 }
7117
7118 static const struct net_device_ops ixgbe_netdev_ops = {
7119 .ndo_open = ixgbe_open,
7120 .ndo_stop = ixgbe_close,
7121 .ndo_start_xmit = ixgbe_xmit_frame,
7122 .ndo_select_queue = ixgbe_select_queue,
7123 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7124 .ndo_validate_addr = eth_validate_addr,
7125 .ndo_set_mac_address = ixgbe_set_mac,
7126 .ndo_change_mtu = ixgbe_change_mtu,
7127 .ndo_tx_timeout = ixgbe_tx_timeout,
7128 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7129 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7130 .ndo_do_ioctl = ixgbe_ioctl,
7131 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7132 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7133 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7134 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7135 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7136 .ndo_get_stats64 = ixgbe_get_stats64,
7137 #ifdef CONFIG_IXGBE_DCB
7138 .ndo_setup_tc = ixgbe_setup_tc,
7139 #endif
7140 #ifdef CONFIG_NET_POLL_CONTROLLER
7141 .ndo_poll_controller = ixgbe_netpoll,
7142 #endif
7143 #ifdef IXGBE_FCOE
7144 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7145 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7146 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7147 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7148 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7149 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7150 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7151 #endif /* IXGBE_FCOE */
7152 .ndo_set_features = ixgbe_set_features,
7153 .ndo_fix_features = ixgbe_fix_features,
7154 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7155 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7156 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
7157 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7158 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7159 };
7160
7161 /**
7162 * ixgbe_wol_supported - Check whether device supports WoL
7163 * @hw: hw specific details
7164 * @device_id: the device ID
7165 * @subdev_id: the subsystem device ID
7166 *
7167 * This function is used by probe and ethtool to determine
7168 * which devices have WoL support
7169 *
7170 **/
7171 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7172 u16 subdevice_id)
7173 {
7174 struct ixgbe_hw *hw = &adapter->hw;
7175 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7176 int is_wol_supported = 0;
7177
7178 switch (device_id) {
7179 case IXGBE_DEV_ID_82599_SFP:
7180 /* Only these subdevices could supports WOL */
7181 switch (subdevice_id) {
7182 case IXGBE_SUBDEV_ID_82599_560FLR:
7183 /* only support first port */
7184 if (hw->bus.func != 0)
7185 break;
7186 case IXGBE_SUBDEV_ID_82599_SFP:
7187 case IXGBE_SUBDEV_ID_82599_RNDC:
7188 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7189 is_wol_supported = 1;
7190 break;
7191 }
7192 break;
7193 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7194 /* All except this subdevice support WOL */
7195 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7196 is_wol_supported = 1;
7197 break;
7198 case IXGBE_DEV_ID_82599_KX4:
7199 is_wol_supported = 1;
7200 break;
7201 case IXGBE_DEV_ID_X540T:
7202 case IXGBE_DEV_ID_X540T1:
7203 /* check eeprom to see if enabled wol */
7204 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7205 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7206 (hw->bus.func == 0))) {
7207 is_wol_supported = 1;
7208 }
7209 break;
7210 }
7211
7212 return is_wol_supported;
7213 }
7214
7215 /**
7216 * ixgbe_probe - Device Initialization Routine
7217 * @pdev: PCI device information struct
7218 * @ent: entry in ixgbe_pci_tbl
7219 *
7220 * Returns 0 on success, negative on failure
7221 *
7222 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7223 * The OS initialization, configuring of the adapter private structure,
7224 * and a hardware reset occur.
7225 **/
7226 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7227 {
7228 struct net_device *netdev;
7229 struct ixgbe_adapter *adapter = NULL;
7230 struct ixgbe_hw *hw;
7231 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7232 static int cards_found;
7233 int i, err, pci_using_dac;
7234 unsigned int indices = MAX_TX_QUEUES;
7235 u8 part_str[IXGBE_PBANUM_LENGTH];
7236 #ifdef IXGBE_FCOE
7237 u16 device_caps;
7238 #endif
7239 u32 eec;
7240
7241 /* Catch broken hardware that put the wrong VF device ID in
7242 * the PCIe SR-IOV capability.
7243 */
7244 if (pdev->is_virtfn) {
7245 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7246 pci_name(pdev), pdev->vendor, pdev->device);
7247 return -EINVAL;
7248 }
7249
7250 err = pci_enable_device_mem(pdev);
7251 if (err)
7252 return err;
7253
7254 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7255 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7256 pci_using_dac = 1;
7257 } else {
7258 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7259 if (err) {
7260 err = dma_set_coherent_mask(&pdev->dev,
7261 DMA_BIT_MASK(32));
7262 if (err) {
7263 dev_err(&pdev->dev,
7264 "No usable DMA configuration, aborting\n");
7265 goto err_dma;
7266 }
7267 }
7268 pci_using_dac = 0;
7269 }
7270
7271 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7272 IORESOURCE_MEM), ixgbe_driver_name);
7273 if (err) {
7274 dev_err(&pdev->dev,
7275 "pci_request_selected_regions failed 0x%x\n", err);
7276 goto err_pci_reg;
7277 }
7278
7279 pci_enable_pcie_error_reporting(pdev);
7280
7281 pci_set_master(pdev);
7282 pci_save_state(pdev);
7283
7284 if (ii->mac == ixgbe_mac_82598EB) {
7285 #ifdef CONFIG_IXGBE_DCB
7286 /* 8 TC w/ 4 queues per TC */
7287 indices = 4 * MAX_TRAFFIC_CLASS;
7288 #else
7289 indices = IXGBE_MAX_RSS_INDICES;
7290 #endif
7291 }
7292
7293 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7294 if (!netdev) {
7295 err = -ENOMEM;
7296 goto err_alloc_etherdev;
7297 }
7298
7299 SET_NETDEV_DEV(netdev, &pdev->dev);
7300
7301 adapter = netdev_priv(netdev);
7302 pci_set_drvdata(pdev, adapter);
7303
7304 adapter->netdev = netdev;
7305 adapter->pdev = pdev;
7306 hw = &adapter->hw;
7307 hw->back = adapter;
7308 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7309
7310 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7311 pci_resource_len(pdev, 0));
7312 if (!hw->hw_addr) {
7313 err = -EIO;
7314 goto err_ioremap;
7315 }
7316
7317 netdev->netdev_ops = &ixgbe_netdev_ops;
7318 ixgbe_set_ethtool_ops(netdev);
7319 netdev->watchdog_timeo = 5 * HZ;
7320 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7321
7322 adapter->bd_number = cards_found;
7323
7324 /* Setup hw api */
7325 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7326 hw->mac.type = ii->mac;
7327
7328 /* EEPROM */
7329 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7330 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7331 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7332 if (!(eec & (1 << 8)))
7333 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7334
7335 /* PHY */
7336 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7337 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7338 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7339 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7340 hw->phy.mdio.mmds = 0;
7341 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7342 hw->phy.mdio.dev = netdev;
7343 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7344 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7345
7346 ii->get_invariants(hw);
7347
7348 /* setup the private structure */
7349 err = ixgbe_sw_init(adapter);
7350 if (err)
7351 goto err_sw_init;
7352
7353 /* Make it possible the adapter to be woken up via WOL */
7354 switch (adapter->hw.mac.type) {
7355 case ixgbe_mac_82599EB:
7356 case ixgbe_mac_X540:
7357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7358 break;
7359 default:
7360 break;
7361 }
7362
7363 /*
7364 * If there is a fan on this device and it has failed log the
7365 * failure.
7366 */
7367 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7368 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7369 if (esdp & IXGBE_ESDP_SDP1)
7370 e_crit(probe, "Fan has stopped, replace the adapter\n");
7371 }
7372
7373 if (allow_unsupported_sfp)
7374 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7375
7376 /* reset_hw fills in the perm_addr as well */
7377 hw->phy.reset_if_overtemp = true;
7378 err = hw->mac.ops.reset_hw(hw);
7379 hw->phy.reset_if_overtemp = false;
7380 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7381 hw->mac.type == ixgbe_mac_82598EB) {
7382 err = 0;
7383 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7384 e_dev_err("failed to load because an unsupported SFP+ "
7385 "module type was detected.\n");
7386 e_dev_err("Reload the driver after installing a supported "
7387 "module.\n");
7388 goto err_sw_init;
7389 } else if (err) {
7390 e_dev_err("HW Init failed: %d\n", err);
7391 goto err_sw_init;
7392 }
7393
7394 #ifdef CONFIG_PCI_IOV
7395 /* SR-IOV not supported on the 82598 */
7396 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7397 goto skip_sriov;
7398 /* Mailbox */
7399 ixgbe_init_mbx_params_pf(hw);
7400 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7401 ixgbe_enable_sriov(adapter);
7402 pci_sriov_set_totalvfs(pdev, 63);
7403 skip_sriov:
7404
7405 #endif
7406 netdev->features = NETIF_F_SG |
7407 NETIF_F_IP_CSUM |
7408 NETIF_F_IPV6_CSUM |
7409 NETIF_F_HW_VLAN_TX |
7410 NETIF_F_HW_VLAN_RX |
7411 NETIF_F_HW_VLAN_FILTER |
7412 NETIF_F_TSO |
7413 NETIF_F_TSO6 |
7414 NETIF_F_RXHASH |
7415 NETIF_F_RXCSUM;
7416
7417 netdev->hw_features = netdev->features;
7418
7419 switch (adapter->hw.mac.type) {
7420 case ixgbe_mac_82599EB:
7421 case ixgbe_mac_X540:
7422 netdev->features |= NETIF_F_SCTP_CSUM;
7423 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7424 NETIF_F_NTUPLE;
7425 break;
7426 default:
7427 break;
7428 }
7429
7430 netdev->hw_features |= NETIF_F_RXALL;
7431
7432 netdev->vlan_features |= NETIF_F_TSO;
7433 netdev->vlan_features |= NETIF_F_TSO6;
7434 netdev->vlan_features |= NETIF_F_IP_CSUM;
7435 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7436 netdev->vlan_features |= NETIF_F_SG;
7437
7438 netdev->priv_flags |= IFF_UNICAST_FLT;
7439 netdev->priv_flags |= IFF_SUPP_NOFCS;
7440
7441 #ifdef CONFIG_IXGBE_DCB
7442 netdev->dcbnl_ops = &dcbnl_ops;
7443 #endif
7444
7445 #ifdef IXGBE_FCOE
7446 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7447 unsigned int fcoe_l;
7448
7449 if (hw->mac.ops.get_device_caps) {
7450 hw->mac.ops.get_device_caps(hw, &device_caps);
7451 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7452 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7453 }
7454
7455
7456 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7457 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7458
7459 netdev->features |= NETIF_F_FSO |
7460 NETIF_F_FCOE_CRC;
7461
7462 netdev->vlan_features |= NETIF_F_FSO |
7463 NETIF_F_FCOE_CRC |
7464 NETIF_F_FCOE_MTU;
7465 }
7466 #endif /* IXGBE_FCOE */
7467 if (pci_using_dac) {
7468 netdev->features |= NETIF_F_HIGHDMA;
7469 netdev->vlan_features |= NETIF_F_HIGHDMA;
7470 }
7471
7472 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7473 netdev->hw_features |= NETIF_F_LRO;
7474 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7475 netdev->features |= NETIF_F_LRO;
7476
7477 /* make sure the EEPROM is good */
7478 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7479 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7480 err = -EIO;
7481 goto err_sw_init;
7482 }
7483
7484 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7485
7486 if (!is_valid_ether_addr(netdev->dev_addr)) {
7487 e_dev_err("invalid MAC address\n");
7488 err = -EIO;
7489 goto err_sw_init;
7490 }
7491
7492 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7493 (unsigned long) adapter);
7494
7495 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7496 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7497
7498 err = ixgbe_init_interrupt_scheme(adapter);
7499 if (err)
7500 goto err_sw_init;
7501
7502 /* WOL not supported for all devices */
7503 adapter->wol = 0;
7504 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7505 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7506 adapter->wol = IXGBE_WUFC_MAG;
7507
7508 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7509
7510 /* save off EEPROM version number */
7511 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7512 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7513
7514 /* pick up the PCI bus settings for reporting later */
7515 hw->mac.ops.get_bus_info(hw);
7516
7517 /* print bus type/speed/width info */
7518 e_dev_info("(PCI Express:%s:%s) %pM\n",
7519 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7520 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7521 "Unknown"),
7522 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7523 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7524 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7525 "Unknown"),
7526 netdev->dev_addr);
7527
7528 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7529 if (err)
7530 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7531 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7532 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7533 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7534 part_str);
7535 else
7536 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7537 hw->mac.type, hw->phy.type, part_str);
7538
7539 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7540 e_dev_warn("PCI-Express bandwidth available for this card is "
7541 "not sufficient for optimal performance.\n");
7542 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7543 "is required.\n");
7544 }
7545
7546 /* reset the hardware with the new settings */
7547 err = hw->mac.ops.start_hw(hw);
7548 if (err == IXGBE_ERR_EEPROM_VERSION) {
7549 /* We are running on a pre-production device, log a warning */
7550 e_dev_warn("This device is a pre-production adapter/LOM. "
7551 "Please be aware there may be issues associated "
7552 "with your hardware. If you are experiencing "
7553 "problems please contact your Intel or hardware "
7554 "representative who provided you with this "
7555 "hardware.\n");
7556 }
7557 strcpy(netdev->name, "eth%d");
7558 err = register_netdev(netdev);
7559 if (err)
7560 goto err_register;
7561
7562 /* power down the optics for 82599 SFP+ fiber */
7563 if (hw->mac.ops.disable_tx_laser)
7564 hw->mac.ops.disable_tx_laser(hw);
7565
7566 /* carrier off reporting is important to ethtool even BEFORE open */
7567 netif_carrier_off(netdev);
7568
7569 #ifdef CONFIG_IXGBE_DCA
7570 if (dca_add_requester(&pdev->dev) == 0) {
7571 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7572 ixgbe_setup_dca(adapter);
7573 }
7574 #endif
7575 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7576 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7577 for (i = 0; i < adapter->num_vfs; i++)
7578 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7579 }
7580
7581 /* firmware requires driver version to be 0xFFFFFFFF
7582 * since os does not support feature
7583 */
7584 if (hw->mac.ops.set_fw_drv_ver)
7585 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7586 0xFF);
7587
7588 /* add san mac addr to netdev */
7589 ixgbe_add_sanmac_netdev(netdev);
7590
7591 e_dev_info("%s\n", ixgbe_default_device_descr);
7592 cards_found++;
7593
7594 #ifdef CONFIG_IXGBE_HWMON
7595 if (ixgbe_sysfs_init(adapter))
7596 e_err(probe, "failed to allocate sysfs resources\n");
7597 #endif /* CONFIG_IXGBE_HWMON */
7598
7599 #ifdef CONFIG_DEBUG_FS
7600 ixgbe_dbg_adapter_init(adapter);
7601 #endif /* CONFIG_DEBUG_FS */
7602
7603 return 0;
7604
7605 err_register:
7606 ixgbe_release_hw_control(adapter);
7607 ixgbe_clear_interrupt_scheme(adapter);
7608 err_sw_init:
7609 ixgbe_disable_sriov(adapter);
7610 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7611 iounmap(hw->hw_addr);
7612 err_ioremap:
7613 free_netdev(netdev);
7614 err_alloc_etherdev:
7615 pci_release_selected_regions(pdev,
7616 pci_select_bars(pdev, IORESOURCE_MEM));
7617 err_pci_reg:
7618 err_dma:
7619 pci_disable_device(pdev);
7620 return err;
7621 }
7622
7623 /**
7624 * ixgbe_remove - Device Removal Routine
7625 * @pdev: PCI device information struct
7626 *
7627 * ixgbe_remove is called by the PCI subsystem to alert the driver
7628 * that it should release a PCI device. The could be caused by a
7629 * Hot-Plug event, or because the driver is going to be removed from
7630 * memory.
7631 **/
7632 static void ixgbe_remove(struct pci_dev *pdev)
7633 {
7634 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7635 struct net_device *netdev = adapter->netdev;
7636
7637 #ifdef CONFIG_DEBUG_FS
7638 ixgbe_dbg_adapter_exit(adapter);
7639 #endif /*CONFIG_DEBUG_FS */
7640
7641 set_bit(__IXGBE_DOWN, &adapter->state);
7642 cancel_work_sync(&adapter->service_task);
7643
7644
7645 #ifdef CONFIG_IXGBE_DCA
7646 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7647 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7648 dca_remove_requester(&pdev->dev);
7649 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7650 }
7651
7652 #endif
7653 #ifdef CONFIG_IXGBE_HWMON
7654 ixgbe_sysfs_exit(adapter);
7655 #endif /* CONFIG_IXGBE_HWMON */
7656
7657 /* remove the added san mac */
7658 ixgbe_del_sanmac_netdev(netdev);
7659
7660 if (netdev->reg_state == NETREG_REGISTERED)
7661 unregister_netdev(netdev);
7662
7663 #ifdef CONFIG_PCI_IOV
7664 /*
7665 * Only disable SR-IOV on unload if the user specified the now
7666 * deprecated max_vfs module parameter.
7667 */
7668 if (max_vfs)
7669 ixgbe_disable_sriov(adapter);
7670 #endif
7671 ixgbe_clear_interrupt_scheme(adapter);
7672
7673 ixgbe_release_hw_control(adapter);
7674
7675 #ifdef CONFIG_DCB
7676 kfree(adapter->ixgbe_ieee_pfc);
7677 kfree(adapter->ixgbe_ieee_ets);
7678
7679 #endif
7680 iounmap(adapter->hw.hw_addr);
7681 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7682 IORESOURCE_MEM));
7683
7684 e_dev_info("complete\n");
7685
7686 free_netdev(netdev);
7687
7688 pci_disable_pcie_error_reporting(pdev);
7689
7690 pci_disable_device(pdev);
7691 }
7692
7693 /**
7694 * ixgbe_io_error_detected - called when PCI error is detected
7695 * @pdev: Pointer to PCI device
7696 * @state: The current pci connection state
7697 *
7698 * This function is called after a PCI bus error affecting
7699 * this device has been detected.
7700 */
7701 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7702 pci_channel_state_t state)
7703 {
7704 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7705 struct net_device *netdev = adapter->netdev;
7706
7707 #ifdef CONFIG_PCI_IOV
7708 struct pci_dev *bdev, *vfdev;
7709 u32 dw0, dw1, dw2, dw3;
7710 int vf, pos;
7711 u16 req_id, pf_func;
7712
7713 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7714 adapter->num_vfs == 0)
7715 goto skip_bad_vf_detection;
7716
7717 bdev = pdev->bus->self;
7718 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7719 bdev = bdev->bus->self;
7720
7721 if (!bdev)
7722 goto skip_bad_vf_detection;
7723
7724 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7725 if (!pos)
7726 goto skip_bad_vf_detection;
7727
7728 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7729 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7730 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7731 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7732
7733 req_id = dw1 >> 16;
7734 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7735 if (!(req_id & 0x0080))
7736 goto skip_bad_vf_detection;
7737
7738 pf_func = req_id & 0x01;
7739 if ((pf_func & 1) == (pdev->devfn & 1)) {
7740 unsigned int device_id;
7741
7742 vf = (req_id & 0x7F) >> 1;
7743 e_dev_err("VF %d has caused a PCIe error\n", vf);
7744 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7745 "%8.8x\tdw3: %8.8x\n",
7746 dw0, dw1, dw2, dw3);
7747 switch (adapter->hw.mac.type) {
7748 case ixgbe_mac_82599EB:
7749 device_id = IXGBE_82599_VF_DEVICE_ID;
7750 break;
7751 case ixgbe_mac_X540:
7752 device_id = IXGBE_X540_VF_DEVICE_ID;
7753 break;
7754 default:
7755 device_id = 0;
7756 break;
7757 }
7758
7759 /* Find the pci device of the offending VF */
7760 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7761 while (vfdev) {
7762 if (vfdev->devfn == (req_id & 0xFF))
7763 break;
7764 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7765 device_id, vfdev);
7766 }
7767 /*
7768 * There's a slim chance the VF could have been hot plugged,
7769 * so if it is no longer present we don't need to issue the
7770 * VFLR. Just clean up the AER in that case.
7771 */
7772 if (vfdev) {
7773 e_dev_err("Issuing VFLR to VF %d\n", vf);
7774 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7775 /* Free device reference count */
7776 pci_dev_put(vfdev);
7777 }
7778
7779 pci_cleanup_aer_uncorrect_error_status(pdev);
7780 }
7781
7782 /*
7783 * Even though the error may have occurred on the other port
7784 * we still need to increment the vf error reference count for
7785 * both ports because the I/O resume function will be called
7786 * for both of them.
7787 */
7788 adapter->vferr_refcount++;
7789
7790 return PCI_ERS_RESULT_RECOVERED;
7791
7792 skip_bad_vf_detection:
7793 #endif /* CONFIG_PCI_IOV */
7794 netif_device_detach(netdev);
7795
7796 if (state == pci_channel_io_perm_failure)
7797 return PCI_ERS_RESULT_DISCONNECT;
7798
7799 if (netif_running(netdev))
7800 ixgbe_down(adapter);
7801 pci_disable_device(pdev);
7802
7803 /* Request a slot reset. */
7804 return PCI_ERS_RESULT_NEED_RESET;
7805 }
7806
7807 /**
7808 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7809 * @pdev: Pointer to PCI device
7810 *
7811 * Restart the card from scratch, as if from a cold-boot.
7812 */
7813 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7814 {
7815 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7816 pci_ers_result_t result;
7817 int err;
7818
7819 if (pci_enable_device_mem(pdev)) {
7820 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7821 result = PCI_ERS_RESULT_DISCONNECT;
7822 } else {
7823 pci_set_master(pdev);
7824 pci_restore_state(pdev);
7825 pci_save_state(pdev);
7826
7827 pci_wake_from_d3(pdev, false);
7828
7829 ixgbe_reset(adapter);
7830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7831 result = PCI_ERS_RESULT_RECOVERED;
7832 }
7833
7834 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7835 if (err) {
7836 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7837 "failed 0x%0x\n", err);
7838 /* non-fatal, continue */
7839 }
7840
7841 return result;
7842 }
7843
7844 /**
7845 * ixgbe_io_resume - called when traffic can start flowing again.
7846 * @pdev: Pointer to PCI device
7847 *
7848 * This callback is called when the error recovery driver tells us that
7849 * its OK to resume normal operation.
7850 */
7851 static void ixgbe_io_resume(struct pci_dev *pdev)
7852 {
7853 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7854 struct net_device *netdev = adapter->netdev;
7855
7856 #ifdef CONFIG_PCI_IOV
7857 if (adapter->vferr_refcount) {
7858 e_info(drv, "Resuming after VF err\n");
7859 adapter->vferr_refcount--;
7860 return;
7861 }
7862
7863 #endif
7864 if (netif_running(netdev))
7865 ixgbe_up(adapter);
7866
7867 netif_device_attach(netdev);
7868 }
7869
7870 static const struct pci_error_handlers ixgbe_err_handler = {
7871 .error_detected = ixgbe_io_error_detected,
7872 .slot_reset = ixgbe_io_slot_reset,
7873 .resume = ixgbe_io_resume,
7874 };
7875
7876 static struct pci_driver ixgbe_driver = {
7877 .name = ixgbe_driver_name,
7878 .id_table = ixgbe_pci_tbl,
7879 .probe = ixgbe_probe,
7880 .remove = ixgbe_remove,
7881 #ifdef CONFIG_PM
7882 .suspend = ixgbe_suspend,
7883 .resume = ixgbe_resume,
7884 #endif
7885 .shutdown = ixgbe_shutdown,
7886 .sriov_configure = ixgbe_pci_sriov_configure,
7887 .err_handler = &ixgbe_err_handler
7888 };
7889
7890 /**
7891 * ixgbe_init_module - Driver Registration Routine
7892 *
7893 * ixgbe_init_module is the first routine called when the driver is
7894 * loaded. All it does is register with the PCI subsystem.
7895 **/
7896 static int __init ixgbe_init_module(void)
7897 {
7898 int ret;
7899 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7900 pr_info("%s\n", ixgbe_copyright);
7901
7902 #ifdef CONFIG_DEBUG_FS
7903 ixgbe_dbg_init();
7904 #endif /* CONFIG_DEBUG_FS */
7905
7906 #ifdef CONFIG_IXGBE_DCA
7907 dca_register_notify(&dca_notifier);
7908 #endif
7909
7910 ret = pci_register_driver(&ixgbe_driver);
7911 return ret;
7912 }
7913
7914 module_init(ixgbe_init_module);
7915
7916 /**
7917 * ixgbe_exit_module - Driver Exit Cleanup Routine
7918 *
7919 * ixgbe_exit_module is called just before the driver is removed
7920 * from memory.
7921 **/
7922 static void __exit ixgbe_exit_module(void)
7923 {
7924 #ifdef CONFIG_IXGBE_DCA
7925 dca_unregister_notify(&dca_notifier);
7926 #endif
7927 pci_unregister_driver(&ixgbe_driver);
7928
7929 #ifdef CONFIG_DEBUG_FS
7930 ixgbe_dbg_exit();
7931 #endif /* CONFIG_DEBUG_FS */
7932
7933 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7934 }
7935
7936 #ifdef CONFIG_IXGBE_DCA
7937 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7938 void *p)
7939 {
7940 int ret_val;
7941
7942 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7943 __ixgbe_notify_dca);
7944
7945 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7946 }
7947
7948 #endif /* CONFIG_IXGBE_DCA */
7949
7950 module_exit(ixgbe_exit_module);
7951
7952 /* ixgbe_main.c */
CJK support for tty framebuffer vt