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ixgbe: Define FCoE and Flow director limits much sooner to allow for changes
[linux-2.6/cjktty.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82599.c
blob203a00c2433027c19f824bd9ddb84ed6fa0cb5bd
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
42
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
61
62 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
63 {
64 struct ixgbe_mac_info *mac = &hw->mac;
65
66 /* enable the laser control functions for SFP+ fiber */
67 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
68 mac->ops.disable_tx_laser =
69 &ixgbe_disable_tx_laser_multispeed_fiber;
70 mac->ops.enable_tx_laser =
71 &ixgbe_enable_tx_laser_multispeed_fiber;
72 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
73 } else {
74 mac->ops.disable_tx_laser = NULL;
75 mac->ops.enable_tx_laser = NULL;
76 mac->ops.flap_tx_laser = NULL;
77 }
78
79 if (hw->phy.multispeed_fiber) {
80 /* Set up dual speed SFP+ support */
81 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
82 } else {
83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
87 !ixgbe_verify_lesm_fw_enabled_82599(hw))
88 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
89 else
90 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
91 }
92 }
93
94 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
95 {
96 s32 ret_val = 0;
97 u16 list_offset, data_offset, data_value;
98 bool got_lock = false;
99
100 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
101 ixgbe_init_mac_link_ops_82599(hw);
102
103 hw->phy.ops.reset = NULL;
104
105 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
106 &data_offset);
107 if (ret_val != 0)
108 goto setup_sfp_out;
109
110 /* PHY config will finish before releasing the semaphore */
111 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
112 IXGBE_GSSR_MAC_CSR_SM);
113 if (ret_val != 0) {
114 ret_val = IXGBE_ERR_SWFW_SYNC;
115 goto setup_sfp_out;
116 }
117
118 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
119 while (data_value != 0xffff) {
120 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
121 IXGBE_WRITE_FLUSH(hw);
122 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
123 }
124
125 /* Release the semaphore */
126 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
127 /*
128 * Delay obtaining semaphore again to allow FW access,
129 * semaphore_delay is in ms usleep_range needs us.
130 */
131 usleep_range(hw->eeprom.semaphore_delay * 1000,
132 hw->eeprom.semaphore_delay * 2000);
133
134 /* Need SW/FW semaphore around AUTOC writes if LESM on,
135 * likewise reset_pipeline requires lock as it also writes
136 * AUTOC.
137 */
138 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
139 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
140 IXGBE_GSSR_MAC_CSR_SM);
141 if (ret_val)
142 goto setup_sfp_out;
143
144 got_lock = true;
145 }
146
147 /* Restart DSP and set SFI mode */
148 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
149 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
150
151 ret_val = ixgbe_reset_pipeline_82599(hw);
152
153 if (got_lock) {
154 hw->mac.ops.release_swfw_sync(hw,
155 IXGBE_GSSR_MAC_CSR_SM);
156 got_lock = false;
157 }
158
159 if (ret_val) {
160 hw_dbg(hw, " sfp module setup not complete\n");
161 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
162 goto setup_sfp_out;
163 }
164 }
165
166 setup_sfp_out:
167 return ret_val;
168 }
169
170 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
171 {
172 struct ixgbe_mac_info *mac = &hw->mac;
173
174 ixgbe_init_mac_link_ops_82599(hw);
175
176 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
177 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
178 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
179 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
180 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
181 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
182
183 return 0;
184 }
185
186 /**
187 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
188 * @hw: pointer to hardware structure
189 *
190 * Initialize any function pointers that were not able to be
191 * set during get_invariants because the PHY/SFP type was
192 * not known. Perform the SFP init if necessary.
193 *
194 **/
195 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
196 {
197 struct ixgbe_mac_info *mac = &hw->mac;
198 struct ixgbe_phy_info *phy = &hw->phy;
199 s32 ret_val = 0;
200
201 /* Identify the PHY or SFP module */
202 ret_val = phy->ops.identify(hw);
203
204 /* Setup function pointers based on detected SFP module and speeds */
205 ixgbe_init_mac_link_ops_82599(hw);
206
207 /* If copper media, overwrite with copper function pointers */
208 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
209 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
210 mac->ops.get_link_capabilities =
211 &ixgbe_get_copper_link_capabilities_generic;
212 }
213
214 /* Set necessary function pointers based on phy type */
215 switch (hw->phy.type) {
216 case ixgbe_phy_tn:
217 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
218 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
219 phy->ops.get_firmware_version =
220 &ixgbe_get_phy_firmware_version_tnx;
221 break;
222 default:
223 break;
224 }
225
226 return ret_val;
227 }
228
229 /**
230 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
231 * @hw: pointer to hardware structure
232 * @speed: pointer to link speed
233 * @autoneg: true when autoneg or autotry is enabled
234 *
235 * Determines the link capabilities by reading the AUTOC register.
236 **/
237 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
238 ixgbe_link_speed *speed,
239 bool *autoneg)
240 {
241 s32 status = 0;
242 u32 autoc = 0;
243
244 /* Determine 1G link capabilities off of SFP+ type */
245 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
246 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
247 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
248 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
249 *speed = IXGBE_LINK_SPEED_1GB_FULL;
250 *autoneg = true;
251 goto out;
252 }
253
254 /*
255 * Determine link capabilities based on the stored value of AUTOC,
256 * which represents EEPROM defaults. If AUTOC value has not been
257 * stored, use the current register value.
258 */
259 if (hw->mac.orig_link_settings_stored)
260 autoc = hw->mac.orig_autoc;
261 else
262 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
263
264 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
265 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
266 *speed = IXGBE_LINK_SPEED_1GB_FULL;
267 *autoneg = false;
268 break;
269
270 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
271 *speed = IXGBE_LINK_SPEED_10GB_FULL;
272 *autoneg = false;
273 break;
274
275 case IXGBE_AUTOC_LMS_1G_AN:
276 *speed = IXGBE_LINK_SPEED_1GB_FULL;
277 *autoneg = true;
278 break;
279
280 case IXGBE_AUTOC_LMS_10G_SERIAL:
281 *speed = IXGBE_LINK_SPEED_10GB_FULL;
282 *autoneg = false;
283 break;
284
285 case IXGBE_AUTOC_LMS_KX4_KX_KR:
286 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
287 *speed = IXGBE_LINK_SPEED_UNKNOWN;
288 if (autoc & IXGBE_AUTOC_KR_SUPP)
289 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
290 if (autoc & IXGBE_AUTOC_KX4_SUPP)
291 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
292 if (autoc & IXGBE_AUTOC_KX_SUPP)
293 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
294 *autoneg = true;
295 break;
296
297 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
298 *speed = IXGBE_LINK_SPEED_100_FULL;
299 if (autoc & IXGBE_AUTOC_KR_SUPP)
300 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
301 if (autoc & IXGBE_AUTOC_KX4_SUPP)
302 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
303 if (autoc & IXGBE_AUTOC_KX_SUPP)
304 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
305 *autoneg = true;
306 break;
307
308 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
309 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
310 *autoneg = false;
311 break;
312
313 default:
314 status = IXGBE_ERR_LINK_SETUP;
315 goto out;
316 break;
317 }
318
319 if (hw->phy.multispeed_fiber) {
320 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
321 IXGBE_LINK_SPEED_1GB_FULL;
322 *autoneg = true;
323 }
324
325 out:
326 return status;
327 }
328
329 /**
330 * ixgbe_get_media_type_82599 - Get media type
331 * @hw: pointer to hardware structure
332 *
333 * Returns the media type (fiber, copper, backplane)
334 **/
335 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
336 {
337 enum ixgbe_media_type media_type;
338
339 /* Detect if there is a copper PHY attached. */
340 switch (hw->phy.type) {
341 case ixgbe_phy_cu_unknown:
342 case ixgbe_phy_tn:
343 media_type = ixgbe_media_type_copper;
344 goto out;
345 default:
346 break;
347 }
348
349 switch (hw->device_id) {
350 case IXGBE_DEV_ID_82599_KX4:
351 case IXGBE_DEV_ID_82599_KX4_MEZZ:
352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
353 case IXGBE_DEV_ID_82599_KR:
354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
355 case IXGBE_DEV_ID_82599_XAUI_LOM:
356 /* Default device ID is mezzanine card KX/KX4 */
357 media_type = ixgbe_media_type_backplane;
358 break;
359 case IXGBE_DEV_ID_82599_SFP:
360 case IXGBE_DEV_ID_82599_SFP_FCOE:
361 case IXGBE_DEV_ID_82599_SFP_EM:
362 case IXGBE_DEV_ID_82599_SFP_SF2:
363 case IXGBE_DEV_ID_82599_SFP_SF_QP:
364 case IXGBE_DEV_ID_82599EN_SFP:
365 media_type = ixgbe_media_type_fiber;
366 break;
367 case IXGBE_DEV_ID_82599_CX4:
368 media_type = ixgbe_media_type_cx4;
369 break;
370 case IXGBE_DEV_ID_82599_T3_LOM:
371 media_type = ixgbe_media_type_copper;
372 break;
373 case IXGBE_DEV_ID_82599_LS:
374 media_type = ixgbe_media_type_fiber_lco;
375 break;
376 default:
377 media_type = ixgbe_media_type_unknown;
378 break;
379 }
380 out:
381 return media_type;
382 }
383
384 /**
385 * ixgbe_start_mac_link_82599 - Setup MAC link settings
386 * @hw: pointer to hardware structure
387 * @autoneg_wait_to_complete: true when waiting for completion is needed
388 *
389 * Configures link settings based on values in the ixgbe_hw struct.
390 * Restarts the link. Performs autonegotiation if needed.
391 **/
392 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
393 bool autoneg_wait_to_complete)
394 {
395 u32 autoc_reg;
396 u32 links_reg;
397 u32 i;
398 s32 status = 0;
399 bool got_lock = false;
400
401 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
402 status = hw->mac.ops.acquire_swfw_sync(hw,
403 IXGBE_GSSR_MAC_CSR_SM);
404 if (status)
405 goto out;
406
407 got_lock = true;
408 }
409
410 /* Restart link */
411 ixgbe_reset_pipeline_82599(hw);
412
413 if (got_lock)
414 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
415
416 /* Only poll for autoneg to complete if specified to do so */
417 if (autoneg_wait_to_complete) {
418 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
419 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
420 IXGBE_AUTOC_LMS_KX4_KX_KR ||
421 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
422 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
423 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
424 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
425 links_reg = 0; /* Just in case Autoneg time = 0 */
426 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
427 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
428 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
429 break;
430 msleep(100);
431 }
432 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
433 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
434 hw_dbg(hw, "Autoneg did not complete.\n");
435 }
436 }
437 }
438
439 /* Add delay to filter out noises during initial link setup */
440 msleep(50);
441
442 out:
443 return status;
444 }
445
446 /**
447 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
448 * @hw: pointer to hardware structure
449 *
450 * The base drivers may require better control over SFP+ module
451 * PHY states. This includes selectively shutting down the Tx
452 * laser on the PHY, effectively halting physical link.
453 **/
454 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
455 {
456 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
457
458 /* Disable tx laser; allow 100us to go dark per spec */
459 esdp_reg |= IXGBE_ESDP_SDP3;
460 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
461 IXGBE_WRITE_FLUSH(hw);
462 udelay(100);
463 }
464
465 /**
466 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
467 * @hw: pointer to hardware structure
468 *
469 * The base drivers may require better control over SFP+ module
470 * PHY states. This includes selectively turning on the Tx
471 * laser on the PHY, effectively starting physical link.
472 **/
473 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
474 {
475 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
476
477 /* Enable tx laser; allow 100ms to light up */
478 esdp_reg &= ~IXGBE_ESDP_SDP3;
479 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
480 IXGBE_WRITE_FLUSH(hw);
481 msleep(100);
482 }
483
484 /**
485 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
486 * @hw: pointer to hardware structure
487 *
488 * When the driver changes the link speeds that it can support,
489 * it sets autotry_restart to true to indicate that we need to
490 * initiate a new autotry session with the link partner. To do
491 * so, we set the speed then disable and re-enable the tx laser, to
492 * alert the link partner that it also needs to restart autotry on its
493 * end. This is consistent with true clause 37 autoneg, which also
494 * involves a loss of signal.
495 **/
496 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
497 {
498 if (hw->mac.autotry_restart) {
499 ixgbe_disable_tx_laser_multispeed_fiber(hw);
500 ixgbe_enable_tx_laser_multispeed_fiber(hw);
501 hw->mac.autotry_restart = false;
502 }
503 }
504
505 /**
506 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
507 * @hw: pointer to hardware structure
508 * @speed: new link speed
509 * @autoneg_wait_to_complete: true when waiting for completion is needed
510 *
511 * Set the link speed in the AUTOC register and restarts link.
512 **/
513 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
514 ixgbe_link_speed speed,
515 bool autoneg_wait_to_complete)
516 {
517 s32 status = 0;
518 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
519 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
520 u32 speedcnt = 0;
521 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
522 u32 i = 0;
523 bool link_up = false;
524 bool autoneg = false;
525
526 /* Mask off requested but non-supported speeds */
527 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
528 &autoneg);
529 if (status != 0)
530 return status;
531
532 speed &= link_speed;
533
534 /*
535 * Try each speed one by one, highest priority first. We do this in
536 * software because 10gb fiber doesn't support speed autonegotiation.
537 */
538 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
539 speedcnt++;
540 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
541
542 /* If we already have link at this speed, just jump out */
543 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
544 false);
545 if (status != 0)
546 return status;
547
548 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
549 goto out;
550
551 /* Set the module link speed */
552 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
553 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
554 IXGBE_WRITE_FLUSH(hw);
555
556 /* Allow module to change analog characteristics (1G->10G) */
557 msleep(40);
558
559 status = ixgbe_setup_mac_link_82599(hw,
560 IXGBE_LINK_SPEED_10GB_FULL,
561 autoneg_wait_to_complete);
562 if (status != 0)
563 return status;
564
565 /* Flap the tx laser if it has not already been done */
566 hw->mac.ops.flap_tx_laser(hw);
567
568 /*
569 * Wait for the controller to acquire link. Per IEEE 802.3ap,
570 * Section 73.10.2, we may have to wait up to 500ms if KR is
571 * attempted. 82599 uses the same timing for 10g SFI.
572 */
573 for (i = 0; i < 5; i++) {
574 /* Wait for the link partner to also set speed */
575 msleep(100);
576
577 /* If we have link, just jump out */
578 status = hw->mac.ops.check_link(hw, &link_speed,
579 &link_up, false);
580 if (status != 0)
581 return status;
582
583 if (link_up)
584 goto out;
585 }
586 }
587
588 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
589 speedcnt++;
590 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
591 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
592
593 /* If we already have link at this speed, just jump out */
594 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
595 false);
596 if (status != 0)
597 return status;
598
599 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
600 goto out;
601
602 /* Set the module link speed */
603 esdp_reg &= ~IXGBE_ESDP_SDP5;
604 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
605 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
606 IXGBE_WRITE_FLUSH(hw);
607
608 /* Allow module to change analog characteristics (10G->1G) */
609 msleep(40);
610
611 status = ixgbe_setup_mac_link_82599(hw,
612 IXGBE_LINK_SPEED_1GB_FULL,
613 autoneg_wait_to_complete);
614 if (status != 0)
615 return status;
616
617 /* Flap the tx laser if it has not already been done */
618 hw->mac.ops.flap_tx_laser(hw);
619
620 /* Wait for the link partner to also set speed */
621 msleep(100);
622
623 /* If we have link, just jump out */
624 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
625 false);
626 if (status != 0)
627 return status;
628
629 if (link_up)
630 goto out;
631 }
632
633 /*
634 * We didn't get link. Configure back to the highest speed we tried,
635 * (if there was more than one). We call ourselves back with just the
636 * single highest speed that the user requested.
637 */
638 if (speedcnt > 1)
639 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
640 highest_link_speed,
641 autoneg_wait_to_complete);
642
643 out:
644 /* Set autoneg_advertised value based on input link speed */
645 hw->phy.autoneg_advertised = 0;
646
647 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
648 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
649
650 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
651 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
652
653 return status;
654 }
655
656 /**
657 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
658 * @hw: pointer to hardware structure
659 * @speed: new link speed
660 * @autoneg_wait_to_complete: true when waiting for completion is needed
661 *
662 * Implements the Intel SmartSpeed algorithm.
663 **/
664 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
665 ixgbe_link_speed speed,
666 bool autoneg_wait_to_complete)
667 {
668 s32 status = 0;
669 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
670 s32 i, j;
671 bool link_up = false;
672 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
673
674 /* Set autoneg_advertised value based on input link speed */
675 hw->phy.autoneg_advertised = 0;
676
677 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
678 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
679
680 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
681 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
682
683 if (speed & IXGBE_LINK_SPEED_100_FULL)
684 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
685
686 /*
687 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
688 * autoneg advertisement if link is unable to be established at the
689 * highest negotiated rate. This can sometimes happen due to integrity
690 * issues with the physical media connection.
691 */
692
693 /* First, try to get link with full advertisement */
694 hw->phy.smart_speed_active = false;
695 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
696 status = ixgbe_setup_mac_link_82599(hw, speed,
697 autoneg_wait_to_complete);
698 if (status != 0)
699 goto out;
700
701 /*
702 * Wait for the controller to acquire link. Per IEEE 802.3ap,
703 * Section 73.10.2, we may have to wait up to 500ms if KR is
704 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
705 * Table 9 in the AN MAS.
706 */
707 for (i = 0; i < 5; i++) {
708 mdelay(100);
709
710 /* If we have link, just jump out */
711 status = hw->mac.ops.check_link(hw, &link_speed,
712 &link_up, false);
713 if (status != 0)
714 goto out;
715
716 if (link_up)
717 goto out;
718 }
719 }
720
721 /*
722 * We didn't get link. If we advertised KR plus one of KX4/KX
723 * (or BX4/BX), then disable KR and try again.
724 */
725 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
726 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
727 goto out;
728
729 /* Turn SmartSpeed on to disable KR support */
730 hw->phy.smart_speed_active = true;
731 status = ixgbe_setup_mac_link_82599(hw, speed,
732 autoneg_wait_to_complete);
733 if (status != 0)
734 goto out;
735
736 /*
737 * Wait for the controller to acquire link. 600ms will allow for
738 * the AN link_fail_inhibit_timer as well for multiple cycles of
739 * parallel detect, both 10g and 1g. This allows for the maximum
740 * connect attempts as defined in the AN MAS table 73-7.
741 */
742 for (i = 0; i < 6; i++) {
743 mdelay(100);
744
745 /* If we have link, just jump out */
746 status = hw->mac.ops.check_link(hw, &link_speed,
747 &link_up, false);
748 if (status != 0)
749 goto out;
750
751 if (link_up)
752 goto out;
753 }
754
755 /* We didn't get link. Turn SmartSpeed back off. */
756 hw->phy.smart_speed_active = false;
757 status = ixgbe_setup_mac_link_82599(hw, speed,
758 autoneg_wait_to_complete);
759
760 out:
761 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
762 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
763 "the maximum advertised\n");
764 return status;
765 }
766
767 /**
768 * ixgbe_setup_mac_link_82599 - Set MAC link speed
769 * @hw: pointer to hardware structure
770 * @speed: new link speed
771 * @autoneg_wait_to_complete: true when waiting for completion is needed
772 *
773 * Set the link speed in the AUTOC register and restarts link.
774 **/
775 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
776 ixgbe_link_speed speed,
777 bool autoneg_wait_to_complete)
778 {
779 s32 status = 0;
780 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
781 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
782 u32 start_autoc = autoc;
783 u32 orig_autoc = 0;
784 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
785 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
786 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
787 u32 links_reg;
788 u32 i;
789 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
790 bool got_lock = false;
791 bool autoneg = false;
792
793 /* Check to see if speed passed in is supported. */
794 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
795 &autoneg);
796 if (status != 0)
797 goto out;
798
799 speed &= link_capabilities;
800
801 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
802 status = IXGBE_ERR_LINK_SETUP;
803 goto out;
804 }
805
806 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
807 if (hw->mac.orig_link_settings_stored)
808 orig_autoc = hw->mac.orig_autoc;
809 else
810 orig_autoc = autoc;
811
812 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
813 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
814 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
815 /* Set KX4/KX/KR support according to speed requested */
816 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
817 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
818 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
819 autoc |= IXGBE_AUTOC_KX4_SUPP;
820 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
821 (hw->phy.smart_speed_active == false))
822 autoc |= IXGBE_AUTOC_KR_SUPP;
823 }
824 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
825 autoc |= IXGBE_AUTOC_KX_SUPP;
826 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
827 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
828 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
829 /* Switch from 1G SFI to 10G SFI if requested */
830 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
831 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
832 autoc &= ~IXGBE_AUTOC_LMS_MASK;
833 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
834 }
835 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
836 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
837 /* Switch from 10G SFI to 1G SFI if requested */
838 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
839 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
840 autoc &= ~IXGBE_AUTOC_LMS_MASK;
841 if (autoneg)
842 autoc |= IXGBE_AUTOC_LMS_1G_AN;
843 else
844 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
845 }
846 }
847
848 if (autoc != start_autoc) {
849 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
850 * likewise reset_pipeline requires us to hold this lock as
851 * it also writes to AUTOC.
852 */
853 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
854 status = hw->mac.ops.acquire_swfw_sync(hw,
855 IXGBE_GSSR_MAC_CSR_SM);
856 if (status != 0)
857 goto out;
858
859 got_lock = true;
860 }
861
862 /* Restart link */
863 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
864 ixgbe_reset_pipeline_82599(hw);
865
866 if (got_lock)
867 hw->mac.ops.release_swfw_sync(hw,
868 IXGBE_GSSR_MAC_CSR_SM);
869
870 /* Only poll for autoneg to complete if specified to do so */
871 if (autoneg_wait_to_complete) {
872 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
873 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
874 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
875 links_reg = 0; /*Just in case Autoneg time=0*/
876 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
877 links_reg =
878 IXGBE_READ_REG(hw, IXGBE_LINKS);
879 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
880 break;
881 msleep(100);
882 }
883 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
884 status =
885 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
886 hw_dbg(hw, "Autoneg did not "
887 "complete.\n");
888 }
889 }
890 }
891
892 /* Add delay to filter out noises during initial link setup */
893 msleep(50);
894 }
895
896 out:
897 return status;
898 }
899
900 /**
901 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
902 * @hw: pointer to hardware structure
903 * @speed: new link speed
904 * @autoneg_wait_to_complete: true if waiting is needed to complete
905 *
906 * Restarts link on PHY and MAC based on settings passed in.
907 **/
908 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
909 ixgbe_link_speed speed,
910 bool autoneg_wait_to_complete)
911 {
912 s32 status;
913
914 /* Setup the PHY according to input speed */
915 status = hw->phy.ops.setup_link_speed(hw, speed,
916 autoneg_wait_to_complete);
917 /* Set up MAC */
918 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
919
920 return status;
921 }
922
923 /**
924 * ixgbe_reset_hw_82599 - Perform hardware reset
925 * @hw: pointer to hardware structure
926 *
927 * Resets the hardware by resetting the transmit and receive units, masks
928 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
929 * reset.
930 **/
931 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
932 {
933 ixgbe_link_speed link_speed;
934 s32 status;
935 u32 ctrl, i, autoc, autoc2;
936 bool link_up = false;
937
938 /* Call adapter stop to disable tx/rx and clear interrupts */
939 status = hw->mac.ops.stop_adapter(hw);
940 if (status != 0)
941 goto reset_hw_out;
942
943 /* flush pending Tx transactions */
944 ixgbe_clear_tx_pending(hw);
945
946 /* PHY ops must be identified and initialized prior to reset */
947
948 /* Identify PHY and related function pointers */
949 status = hw->phy.ops.init(hw);
950
951 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
952 goto reset_hw_out;
953
954 /* Setup SFP module if there is one present. */
955 if (hw->phy.sfp_setup_needed) {
956 status = hw->mac.ops.setup_sfp(hw);
957 hw->phy.sfp_setup_needed = false;
958 }
959
960 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
961 goto reset_hw_out;
962
963 /* Reset PHY */
964 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
965 hw->phy.ops.reset(hw);
966
967 mac_reset_top:
968 /*
969 * Issue global reset to the MAC. Needs to be SW reset if link is up.
970 * If link reset is used when link is up, it might reset the PHY when
971 * mng is using it. If link is down or the flag to force full link
972 * reset is set, then perform link reset.
973 */
974 ctrl = IXGBE_CTRL_LNK_RST;
975 if (!hw->force_full_reset) {
976 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
977 if (link_up)
978 ctrl = IXGBE_CTRL_RST;
979 }
980
981 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
982 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
983 IXGBE_WRITE_FLUSH(hw);
984
985 /* Poll for reset bit to self-clear indicating reset is complete */
986 for (i = 0; i < 10; i++) {
987 udelay(1);
988 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
989 if (!(ctrl & IXGBE_CTRL_RST_MASK))
990 break;
991 }
992
993 if (ctrl & IXGBE_CTRL_RST_MASK) {
994 status = IXGBE_ERR_RESET_FAILED;
995 hw_dbg(hw, "Reset polling failed to complete.\n");
996 }
997
998 msleep(50);
999
1000 /*
1001 * Double resets are required for recovery from certain error
1002 * conditions. Between resets, it is necessary to stall to allow time
1003 * for any pending HW events to complete.
1004 */
1005 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1006 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1007 goto mac_reset_top;
1008 }
1009
1010 /*
1011 * Store the original AUTOC/AUTOC2 values if they have not been
1012 * stored off yet. Otherwise restore the stored original
1013 * values since the reset operation sets back to defaults.
1014 */
1015 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1016 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1017 if (hw->mac.orig_link_settings_stored == false) {
1018 hw->mac.orig_autoc = autoc;
1019 hw->mac.orig_autoc2 = autoc2;
1020 hw->mac.orig_link_settings_stored = true;
1021 } else {
1022 if (autoc != hw->mac.orig_autoc) {
1023 /* Need SW/FW semaphore around AUTOC writes if LESM is
1024 * on, likewise reset_pipeline requires us to hold
1025 * this lock as it also writes to AUTOC.
1026 */
1027 bool got_lock = false;
1028 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1029 status = hw->mac.ops.acquire_swfw_sync(hw,
1030 IXGBE_GSSR_MAC_CSR_SM);
1031 if (status)
1032 goto reset_hw_out;
1033
1034 got_lock = true;
1035 }
1036
1037 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1038 ixgbe_reset_pipeline_82599(hw);
1039
1040 if (got_lock)
1041 hw->mac.ops.release_swfw_sync(hw,
1042 IXGBE_GSSR_MAC_CSR_SM);
1043 }
1044
1045 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1046 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1047 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1048 autoc2 |= (hw->mac.orig_autoc2 &
1049 IXGBE_AUTOC2_UPPER_MASK);
1050 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1051 }
1052 }
1053
1054 /* Store the permanent mac address */
1055 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1056
1057 /*
1058 * Store MAC address from RAR0, clear receive address registers, and
1059 * clear the multicast table. Also reset num_rar_entries to 128,
1060 * since we modify this value when programming the SAN MAC address.
1061 */
1062 hw->mac.num_rar_entries = 128;
1063 hw->mac.ops.init_rx_addrs(hw);
1064
1065 /* Store the permanent SAN mac address */
1066 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1067
1068 /* Add the SAN MAC address to the RAR only if it's a valid address */
1069 if (is_valid_ether_addr(hw->mac.san_addr)) {
1070 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1071 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1072
1073 /* Save the SAN MAC RAR index */
1074 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1075
1076 /* Reserve the last RAR for the SAN MAC address */
1077 hw->mac.num_rar_entries--;
1078 }
1079
1080 /* Store the alternative WWNN/WWPN prefix */
1081 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1082 &hw->mac.wwpn_prefix);
1083
1084 reset_hw_out:
1085 return status;
1086 }
1087
1088 /**
1089 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1090 * @hw: pointer to hardware structure
1091 **/
1092 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1093 {
1094 int i;
1095 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1096 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1097
1098 /*
1099 * Before starting reinitialization process,
1100 * FDIRCMD.CMD must be zero.
1101 */
1102 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1103 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1104 IXGBE_FDIRCMD_CMD_MASK))
1105 break;
1106 udelay(10);
1107 }
1108 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1109 hw_dbg(hw, "Flow Director previous command isn't complete, "
1110 "aborting table re-initialization.\n");
1111 return IXGBE_ERR_FDIR_REINIT_FAILED;
1112 }
1113
1114 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1115 IXGBE_WRITE_FLUSH(hw);
1116 /*
1117 * 82599 adapters flow director init flow cannot be restarted,
1118 * Workaround 82599 silicon errata by performing the following steps
1119 * before re-writing the FDIRCTRL control register with the same value.
1120 * - write 1 to bit 8 of FDIRCMD register &
1121 * - write 0 to bit 8 of FDIRCMD register
1122 */
1123 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1124 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1125 IXGBE_FDIRCMD_CLEARHT));
1126 IXGBE_WRITE_FLUSH(hw);
1127 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1128 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1129 ~IXGBE_FDIRCMD_CLEARHT));
1130 IXGBE_WRITE_FLUSH(hw);
1131 /*
1132 * Clear FDIR Hash register to clear any leftover hashes
1133 * waiting to be programmed.
1134 */
1135 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1136 IXGBE_WRITE_FLUSH(hw);
1137
1138 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1139 IXGBE_WRITE_FLUSH(hw);
1140
1141 /* Poll init-done after we write FDIRCTRL register */
1142 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1143 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1144 IXGBE_FDIRCTRL_INIT_DONE)
1145 break;
1146 usleep_range(1000, 2000);
1147 }
1148 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1149 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1150 return IXGBE_ERR_FDIR_REINIT_FAILED;
1151 }
1152
1153 /* Clear FDIR statistics registers (read to clear) */
1154 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1155 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1156 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1157 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1158 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1159
1160 return 0;
1161 }
1162
1163 /**
1164 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1165 * @hw: pointer to hardware structure
1166 * @fdirctrl: value to write to flow director control register
1167 **/
1168 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1169 {
1170 int i;
1171
1172 /* Prime the keys for hashing */
1173 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1174 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1175
1176 /*
1177 * Poll init-done after we write the register. Estimated times:
1178 * 10G: PBALLOC = 11b, timing is 60us
1179 * 1G: PBALLOC = 11b, timing is 600us
1180 * 100M: PBALLOC = 11b, timing is 6ms
1181 *
1182 * Multiple these timings by 4 if under full Rx load
1183 *
1184 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1185 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1186 * this might not finish in our poll time, but we can live with that
1187 * for now.
1188 */
1189 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1190 IXGBE_WRITE_FLUSH(hw);
1191 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1192 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1193 IXGBE_FDIRCTRL_INIT_DONE)
1194 break;
1195 usleep_range(1000, 2000);
1196 }
1197
1198 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1199 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1200 }
1201
1202 /**
1203 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1204 * @hw: pointer to hardware structure
1205 * @fdirctrl: value to write to flow director control register, initially
1206 * contains just the value of the Rx packet buffer allocation
1207 **/
1208 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1209 {
1210 /*
1211 * Continue setup of fdirctrl register bits:
1212 * Move the flexible bytes to use the ethertype - shift 6 words
1213 * Set the maximum length per hash bucket to 0xA filters
1214 * Send interrupt when 64 filters are left
1215 */
1216 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1217 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1218 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1219
1220 /* write hashes and fdirctrl register, poll for completion */
1221 ixgbe_fdir_enable_82599(hw, fdirctrl);
1222
1223 return 0;
1224 }
1225
1226 /**
1227 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1228 * @hw: pointer to hardware structure
1229 * @fdirctrl: value to write to flow director control register, initially
1230 * contains just the value of the Rx packet buffer allocation
1231 **/
1232 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1233 {
1234 /*
1235 * Continue setup of fdirctrl register bits:
1236 * Turn perfect match filtering on
1237 * Report hash in RSS field of Rx wb descriptor
1238 * Initialize the drop queue
1239 * Move the flexible bytes to use the ethertype - shift 6 words
1240 * Set the maximum length per hash bucket to 0xA filters
1241 * Send interrupt when 64 (0x4 * 16) filters are left
1242 */
1243 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1244 IXGBE_FDIRCTRL_REPORT_STATUS |
1245 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1246 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1247 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1248 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1249
1250 /* write hashes and fdirctrl register, poll for completion */
1251 ixgbe_fdir_enable_82599(hw, fdirctrl);
1252
1253 return 0;
1254 }
1255
1256 /*
1257 * These defines allow us to quickly generate all of the necessary instructions
1258 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1259 * for values 0 through 15
1260 */
1261 #define IXGBE_ATR_COMMON_HASH_KEY \
1262 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1263 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1264 do { \
1265 u32 n = (_n); \
1266 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1267 common_hash ^= lo_hash_dword >> n; \
1268 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1269 bucket_hash ^= lo_hash_dword >> n; \
1270 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1271 sig_hash ^= lo_hash_dword << (16 - n); \
1272 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1273 common_hash ^= hi_hash_dword >> n; \
1274 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1275 bucket_hash ^= hi_hash_dword >> n; \
1276 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1277 sig_hash ^= hi_hash_dword << (16 - n); \
1278 } while (0);
1279
1280 /**
1281 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1282 * @stream: input bitstream to compute the hash on
1283 *
1284 * This function is almost identical to the function above but contains
1285 * several optomizations such as unwinding all of the loops, letting the
1286 * compiler work out all of the conditional ifs since the keys are static
1287 * defines, and computing two keys at once since the hashed dword stream
1288 * will be the same for both keys.
1289 **/
1290 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1291 union ixgbe_atr_hash_dword common)
1292 {
1293 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1294 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1295
1296 /* record the flow_vm_vlan bits as they are a key part to the hash */
1297 flow_vm_vlan = ntohl(input.dword);
1298
1299 /* generate common hash dword */
1300 hi_hash_dword = ntohl(common.dword);
1301
1302 /* low dword is word swapped version of common */
1303 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1304
1305 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1306 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1307
1308 /* Process bits 0 and 16 */
1309 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1310
1311 /*
1312 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1313 * delay this because bit 0 of the stream should not be processed
1314 * so we do not add the vlan until after bit 0 was processed
1315 */
1316 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1317
1318 /* Process remaining 30 bit of the key */
1319 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1320 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1321 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1322 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1323 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1324 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1325 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1326 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1327 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1328 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1329 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1330 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1331 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1332 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1333 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1334
1335 /* combine common_hash result with signature and bucket hashes */
1336 bucket_hash ^= common_hash;
1337 bucket_hash &= IXGBE_ATR_HASH_MASK;
1338
1339 sig_hash ^= common_hash << 16;
1340 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1341
1342 /* return completed signature hash */
1343 return sig_hash ^ bucket_hash;
1344 }
1345
1346 /**
1347 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1348 * @hw: pointer to hardware structure
1349 * @input: unique input dword
1350 * @common: compressed common input dword
1351 * @queue: queue index to direct traffic to
1352 **/
1353 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1354 union ixgbe_atr_hash_dword input,
1355 union ixgbe_atr_hash_dword common,
1356 u8 queue)
1357 {
1358 u64 fdirhashcmd;
1359 u32 fdircmd;
1360
1361 /*
1362 * Get the flow_type in order to program FDIRCMD properly
1363 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1364 */
1365 switch (input.formatted.flow_type) {
1366 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1367 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1368 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1369 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1370 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1371 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1372 break;
1373 default:
1374 hw_dbg(hw, " Error on flow type input\n");
1375 return IXGBE_ERR_CONFIG;
1376 }
1377
1378 /* configure FDIRCMD register */
1379 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1380 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1381 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1382 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1383
1384 /*
1385 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1386 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1387 */
1388 fdirhashcmd = (u64)fdircmd << 32;
1389 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1390 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1391
1392 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1393
1394 return 0;
1395 }
1396
1397 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1398 do { \
1399 u32 n = (_n); \
1400 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1401 bucket_hash ^= lo_hash_dword >> n; \
1402 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1403 bucket_hash ^= hi_hash_dword >> n; \
1404 } while (0);
1405
1406 /**
1407 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1408 * @atr_input: input bitstream to compute the hash on
1409 * @input_mask: mask for the input bitstream
1410 *
1411 * This function serves two main purposes. First it applys the input_mask
1412 * to the atr_input resulting in a cleaned up atr_input data stream.
1413 * Secondly it computes the hash and stores it in the bkt_hash field at
1414 * the end of the input byte stream. This way it will be available for
1415 * future use without needing to recompute the hash.
1416 **/
1417 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1418 union ixgbe_atr_input *input_mask)
1419 {
1420
1421 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1422 u32 bucket_hash = 0;
1423
1424 /* Apply masks to input data */
1425 input->dword_stream[0] &= input_mask->dword_stream[0];
1426 input->dword_stream[1] &= input_mask->dword_stream[1];
1427 input->dword_stream[2] &= input_mask->dword_stream[2];
1428 input->dword_stream[3] &= input_mask->dword_stream[3];
1429 input->dword_stream[4] &= input_mask->dword_stream[4];
1430 input->dword_stream[5] &= input_mask->dword_stream[5];
1431 input->dword_stream[6] &= input_mask->dword_stream[6];
1432 input->dword_stream[7] &= input_mask->dword_stream[7];
1433 input->dword_stream[8] &= input_mask->dword_stream[8];
1434 input->dword_stream[9] &= input_mask->dword_stream[9];
1435 input->dword_stream[10] &= input_mask->dword_stream[10];
1436
1437 /* record the flow_vm_vlan bits as they are a key part to the hash */
1438 flow_vm_vlan = ntohl(input->dword_stream[0]);
1439
1440 /* generate common hash dword */
1441 hi_hash_dword = ntohl(input->dword_stream[1] ^
1442 input->dword_stream[2] ^
1443 input->dword_stream[3] ^
1444 input->dword_stream[4] ^
1445 input->dword_stream[5] ^
1446 input->dword_stream[6] ^
1447 input->dword_stream[7] ^
1448 input->dword_stream[8] ^
1449 input->dword_stream[9] ^
1450 input->dword_stream[10]);
1451
1452 /* low dword is word swapped version of common */
1453 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1454
1455 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1456 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1457
1458 /* Process bits 0 and 16 */
1459 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1460
1461 /*
1462 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1463 * delay this because bit 0 of the stream should not be processed
1464 * so we do not add the vlan until after bit 0 was processed
1465 */
1466 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1467
1468 /* Process remaining 30 bit of the key */
1469 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1470 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1471 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1472 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1473 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1474 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1475 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1476 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1477 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1478 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1479 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1480 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1481 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1482 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1483 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1484
1485 /*
1486 * Limit hash to 13 bits since max bucket count is 8K.
1487 * Store result at the end of the input stream.
1488 */
1489 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1490 }
1491
1492 /**
1493 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1494 * @input_mask: mask to be bit swapped
1495 *
1496 * The source and destination port masks for flow director are bit swapped
1497 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1498 * generate a correctly swapped value we need to bit swap the mask and that
1499 * is what is accomplished by this function.
1500 **/
1501 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1502 {
1503 u32 mask = ntohs(input_mask->formatted.dst_port);
1504 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1505 mask |= ntohs(input_mask->formatted.src_port);
1506 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1507 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1508 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1509 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1510 }
1511
1512 /*
1513 * These two macros are meant to address the fact that we have registers
1514 * that are either all or in part big-endian. As a result on big-endian
1515 * systems we will end up byte swapping the value to little-endian before
1516 * it is byte swapped again and written to the hardware in the original
1517 * big-endian format.
1518 */
1519 #define IXGBE_STORE_AS_BE32(_value) \
1520 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1521 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1522
1523 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1524 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1525
1526 #define IXGBE_STORE_AS_BE16(_value) \
1527 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1528
1529 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1530 union ixgbe_atr_input *input_mask)
1531 {
1532 /* mask IPv6 since it is currently not supported */
1533 u32 fdirm = IXGBE_FDIRM_DIPv6;
1534 u32 fdirtcpm;
1535
1536 /*
1537 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1538 * are zero, then assume a full mask for that field. Also assume that
1539 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1540 * cannot be masked out in this implementation.
1541 *
1542 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1543 * point in time.
1544 */
1545
1546 /* verify bucket hash is cleared on hash generation */
1547 if (input_mask->formatted.bkt_hash)
1548 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1549
1550 /* Program FDIRM and verify partial masks */
1551 switch (input_mask->formatted.vm_pool & 0x7F) {
1552 case 0x0:
1553 fdirm |= IXGBE_FDIRM_POOL;
1554 case 0x7F:
1555 break;
1556 default:
1557 hw_dbg(hw, " Error on vm pool mask\n");
1558 return IXGBE_ERR_CONFIG;
1559 }
1560
1561 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1562 case 0x0:
1563 fdirm |= IXGBE_FDIRM_L4P;
1564 if (input_mask->formatted.dst_port ||
1565 input_mask->formatted.src_port) {
1566 hw_dbg(hw, " Error on src/dst port mask\n");
1567 return IXGBE_ERR_CONFIG;
1568 }
1569 case IXGBE_ATR_L4TYPE_MASK:
1570 break;
1571 default:
1572 hw_dbg(hw, " Error on flow type mask\n");
1573 return IXGBE_ERR_CONFIG;
1574 }
1575
1576 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1577 case 0x0000:
1578 /* mask VLAN ID, fall through to mask VLAN priority */
1579 fdirm |= IXGBE_FDIRM_VLANID;
1580 case 0x0FFF:
1581 /* mask VLAN priority */
1582 fdirm |= IXGBE_FDIRM_VLANP;
1583 break;
1584 case 0xE000:
1585 /* mask VLAN ID only, fall through */
1586 fdirm |= IXGBE_FDIRM_VLANID;
1587 case 0xEFFF:
1588 /* no VLAN fields masked */
1589 break;
1590 default:
1591 hw_dbg(hw, " Error on VLAN mask\n");
1592 return IXGBE_ERR_CONFIG;
1593 }
1594
1595 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1596 case 0x0000:
1597 /* Mask Flex Bytes, fall through */
1598 fdirm |= IXGBE_FDIRM_FLEX;
1599 case 0xFFFF:
1600 break;
1601 default:
1602 hw_dbg(hw, " Error on flexible byte mask\n");
1603 return IXGBE_ERR_CONFIG;
1604 }
1605
1606 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1607 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1608
1609 /* store the TCP/UDP port masks, bit reversed from port layout */
1610 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1611
1612 /* write both the same so that UDP and TCP use the same mask */
1613 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1614 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1615
1616 /* store source and destination IP masks (big-enian) */
1617 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1618 ~input_mask->formatted.src_ip[0]);
1619 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1620 ~input_mask->formatted.dst_ip[0]);
1621
1622 return 0;
1623 }
1624
1625 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1626 union ixgbe_atr_input *input,
1627 u16 soft_id, u8 queue)
1628 {
1629 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1630
1631 /* currently IPv6 is not supported, must be programmed with 0 */
1632 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1633 input->formatted.src_ip[0]);
1634 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1635 input->formatted.src_ip[1]);
1636 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1637 input->formatted.src_ip[2]);
1638
1639 /* record the source address (big-endian) */
1640 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1641
1642 /* record the first 32 bits of the destination address (big-endian) */
1643 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1644
1645 /* record source and destination port (little-endian)*/
1646 fdirport = ntohs(input->formatted.dst_port);
1647 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1648 fdirport |= ntohs(input->formatted.src_port);
1649 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1650
1651 /* record vlan (little-endian) and flex_bytes(big-endian) */
1652 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1653 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1654 fdirvlan |= ntohs(input->formatted.vlan_id);
1655 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1656
1657 /* configure FDIRHASH register */
1658 fdirhash = input->formatted.bkt_hash;
1659 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1660 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1661
1662 /*
1663 * flush all previous writes to make certain registers are
1664 * programmed prior to issuing the command
1665 */
1666 IXGBE_WRITE_FLUSH(hw);
1667
1668 /* configure FDIRCMD register */
1669 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1670 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1671 if (queue == IXGBE_FDIR_DROP_QUEUE)
1672 fdircmd |= IXGBE_FDIRCMD_DROP;
1673 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1674 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1675 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1676
1677 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1678
1679 return 0;
1680 }
1681
1682 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1683 union ixgbe_atr_input *input,
1684 u16 soft_id)
1685 {
1686 u32 fdirhash;
1687 u32 fdircmd = 0;
1688 u32 retry_count;
1689 s32 err = 0;
1690
1691 /* configure FDIRHASH register */
1692 fdirhash = input->formatted.bkt_hash;
1693 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1694 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1695
1696 /* flush hash to HW */
1697 IXGBE_WRITE_FLUSH(hw);
1698
1699 /* Query if filter is present */
1700 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1701
1702 for (retry_count = 10; retry_count; retry_count--) {
1703 /* allow 10us for query to process */
1704 udelay(10);
1705 /* verify query completed successfully */
1706 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1707 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1708 break;
1709 }
1710
1711 if (!retry_count)
1712 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1713
1714 /* if filter exists in hardware then remove it */
1715 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1716 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1717 IXGBE_WRITE_FLUSH(hw);
1718 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1719 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1720 }
1721
1722 return err;
1723 }
1724
1725 /**
1726 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1727 * @hw: pointer to hardware structure
1728 * @reg: analog register to read
1729 * @val: read value
1730 *
1731 * Performs read operation to Omer analog register specified.
1732 **/
1733 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1734 {
1735 u32 core_ctl;
1736
1737 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1738 (reg << 8));
1739 IXGBE_WRITE_FLUSH(hw);
1740 udelay(10);
1741 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1742 *val = (u8)core_ctl;
1743
1744 return 0;
1745 }
1746
1747 /**
1748 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1749 * @hw: pointer to hardware structure
1750 * @reg: atlas register to write
1751 * @val: value to write
1752 *
1753 * Performs write operation to Omer analog register specified.
1754 **/
1755 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1756 {
1757 u32 core_ctl;
1758
1759 core_ctl = (reg << 8) | val;
1760 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1761 IXGBE_WRITE_FLUSH(hw);
1762 udelay(10);
1763
1764 return 0;
1765 }
1766
1767 /**
1768 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1769 * @hw: pointer to hardware structure
1770 *
1771 * Starts the hardware using the generic start_hw function
1772 * and the generation start_hw function.
1773 * Then performs revision-specific operations, if any.
1774 **/
1775 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1776 {
1777 s32 ret_val = 0;
1778
1779 ret_val = ixgbe_start_hw_generic(hw);
1780 if (ret_val != 0)
1781 goto out;
1782
1783 ret_val = ixgbe_start_hw_gen2(hw);
1784 if (ret_val != 0)
1785 goto out;
1786
1787 /* We need to run link autotry after the driver loads */
1788 hw->mac.autotry_restart = true;
1789 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1790
1791 if (ret_val == 0)
1792 ret_val = ixgbe_verify_fw_version_82599(hw);
1793 out:
1794 return ret_val;
1795 }
1796
1797 /**
1798 * ixgbe_identify_phy_82599 - Get physical layer module
1799 * @hw: pointer to hardware structure
1800 *
1801 * Determines the physical layer module found on the current adapter.
1802 * If PHY already detected, maintains current PHY type in hw struct,
1803 * otherwise executes the PHY detection routine.
1804 **/
1805 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1806 {
1807 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1808
1809 /* Detect PHY if not unknown - returns success if already detected. */
1810 status = ixgbe_identify_phy_generic(hw);
1811 if (status != 0) {
1812 /* 82599 10GBASE-T requires an external PHY */
1813 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1814 goto out;
1815 else
1816 status = ixgbe_identify_sfp_module_generic(hw);
1817 }
1818
1819 /* Set PHY type none if no PHY detected */
1820 if (hw->phy.type == ixgbe_phy_unknown) {
1821 hw->phy.type = ixgbe_phy_none;
1822 status = 0;
1823 }
1824
1825 /* Return error if SFP module has been detected but is not supported */
1826 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1827 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1828
1829 out:
1830 return status;
1831 }
1832
1833 /**
1834 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1835 * @hw: pointer to hardware structure
1836 *
1837 * Determines physical layer capabilities of the current configuration.
1838 **/
1839 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1840 {
1841 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1842 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1843 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1844 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1845 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1846 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1847 u16 ext_ability = 0;
1848 u8 comp_codes_10g = 0;
1849 u8 comp_codes_1g = 0;
1850
1851 hw->phy.ops.identify(hw);
1852
1853 switch (hw->phy.type) {
1854 case ixgbe_phy_tn:
1855 case ixgbe_phy_cu_unknown:
1856 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1857 &ext_ability);
1858 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1859 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1860 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1861 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1862 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1863 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1864 goto out;
1865 default:
1866 break;
1867 }
1868
1869 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1870 case IXGBE_AUTOC_LMS_1G_AN:
1871 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1872 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1873 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1874 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1875 goto out;
1876 } else
1877 /* SFI mode so read SFP module */
1878 goto sfp_check;
1879 break;
1880 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1881 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1882 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1883 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1884 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1885 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1886 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1887 goto out;
1888 break;
1889 case IXGBE_AUTOC_LMS_10G_SERIAL:
1890 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1891 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1892 goto out;
1893 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1894 goto sfp_check;
1895 break;
1896 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1897 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1898 if (autoc & IXGBE_AUTOC_KX_SUPP)
1899 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1900 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1901 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1902 if (autoc & IXGBE_AUTOC_KR_SUPP)
1903 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1904 goto out;
1905 break;
1906 default:
1907 goto out;
1908 break;
1909 }
1910
1911 sfp_check:
1912 /* SFP check must be done last since DA modules are sometimes used to
1913 * test KR mode - we need to id KR mode correctly before SFP module.
1914 * Call identify_sfp because the pluggable module may have changed */
1915 hw->phy.ops.identify_sfp(hw);
1916 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1917 goto out;
1918
1919 switch (hw->phy.type) {
1920 case ixgbe_phy_sfp_passive_tyco:
1921 case ixgbe_phy_sfp_passive_unknown:
1922 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1923 break;
1924 case ixgbe_phy_sfp_ftl_active:
1925 case ixgbe_phy_sfp_active_unknown:
1926 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1927 break;
1928 case ixgbe_phy_sfp_avago:
1929 case ixgbe_phy_sfp_ftl:
1930 case ixgbe_phy_sfp_intel:
1931 case ixgbe_phy_sfp_unknown:
1932 hw->phy.ops.read_i2c_eeprom(hw,
1933 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1934 hw->phy.ops.read_i2c_eeprom(hw,
1935 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1936 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1937 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1938 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1939 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1940 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1941 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1942 break;
1943 default:
1944 break;
1945 }
1946
1947 out:
1948 return physical_layer;
1949 }
1950
1951 /**
1952 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1953 * @hw: pointer to hardware structure
1954 * @regval: register value to write to RXCTRL
1955 *
1956 * Enables the Rx DMA unit for 82599
1957 **/
1958 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1959 {
1960 /*
1961 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1962 * If traffic is incoming before we enable the Rx unit, it could hang
1963 * the Rx DMA unit. Therefore, make sure the security engine is
1964 * completely disabled prior to enabling the Rx unit.
1965 */
1966 hw->mac.ops.disable_rx_buff(hw);
1967
1968 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1969
1970 hw->mac.ops.enable_rx_buff(hw);
1971
1972 return 0;
1973 }
1974
1975 /**
1976 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1977 * @hw: pointer to hardware structure
1978 *
1979 * Verifies that installed the firmware version is 0.6 or higher
1980 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1981 *
1982 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1983 * if the FW version is not supported.
1984 **/
1985 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1986 {
1987 s32 status = IXGBE_ERR_EEPROM_VERSION;
1988 u16 fw_offset, fw_ptp_cfg_offset;
1989 u16 fw_version = 0;
1990
1991 /* firmware check is only necessary for SFI devices */
1992 if (hw->phy.media_type != ixgbe_media_type_fiber) {
1993 status = 0;
1994 goto fw_version_out;
1995 }
1996
1997 /* get the offset to the Firmware Module block */
1998 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1999
2000 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2001 goto fw_version_out;
2002
2003 /* get the offset to the Pass Through Patch Configuration block */
2004 hw->eeprom.ops.read(hw, (fw_offset +
2005 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2006 &fw_ptp_cfg_offset);
2007
2008 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2009 goto fw_version_out;
2010
2011 /* get the firmware version */
2012 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2013 IXGBE_FW_PATCH_VERSION_4),
2014 &fw_version);
2015
2016 if (fw_version > 0x5)
2017 status = 0;
2018
2019 fw_version_out:
2020 return status;
2021 }
2022
2023 /**
2024 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2025 * @hw: pointer to hardware structure
2026 *
2027 * Returns true if the LESM FW module is present and enabled. Otherwise
2028 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2029 **/
2030 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2031 {
2032 bool lesm_enabled = false;
2033 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2034 s32 status;
2035
2036 /* get the offset to the Firmware Module block */
2037 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2038
2039 if ((status != 0) ||
2040 (fw_offset == 0) || (fw_offset == 0xFFFF))
2041 goto out;
2042
2043 /* get the offset to the LESM Parameters block */
2044 status = hw->eeprom.ops.read(hw, (fw_offset +
2045 IXGBE_FW_LESM_PARAMETERS_PTR),
2046 &fw_lesm_param_offset);
2047
2048 if ((status != 0) ||
2049 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2050 goto out;
2051
2052 /* get the lesm state word */
2053 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2054 IXGBE_FW_LESM_STATE_1),
2055 &fw_lesm_state);
2056
2057 if ((status == 0) &&
2058 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2059 lesm_enabled = true;
2060
2061 out:
2062 return lesm_enabled;
2063 }
2064
2065 /**
2066 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2067 * fastest available method
2068 *
2069 * @hw: pointer to hardware structure
2070 * @offset: offset of word in EEPROM to read
2071 * @words: number of words
2072 * @data: word(s) read from the EEPROM
2073 *
2074 * Retrieves 16 bit word(s) read from EEPROM
2075 **/
2076 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2077 u16 words, u16 *data)
2078 {
2079 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2080 s32 ret_val = IXGBE_ERR_CONFIG;
2081
2082 /*
2083 * If EEPROM is detected and can be addressed using 14 bits,
2084 * use EERD otherwise use bit bang
2085 */
2086 if ((eeprom->type == ixgbe_eeprom_spi) &&
2087 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2088 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2089 data);
2090 else
2091 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2092 words,
2093 data);
2094
2095 return ret_val;
2096 }
2097
2098 /**
2099 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2100 * fastest available method
2101 *
2102 * @hw: pointer to hardware structure
2103 * @offset: offset of word in the EEPROM to read
2104 * @data: word read from the EEPROM
2105 *
2106 * Reads a 16 bit word from the EEPROM
2107 **/
2108 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2109 u16 offset, u16 *data)
2110 {
2111 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2112 s32 ret_val = IXGBE_ERR_CONFIG;
2113
2114 /*
2115 * If EEPROM is detected and can be addressed using 14 bits,
2116 * use EERD otherwise use bit bang
2117 */
2118 if ((eeprom->type == ixgbe_eeprom_spi) &&
2119 (offset <= IXGBE_EERD_MAX_ADDR))
2120 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2121 else
2122 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2123
2124 return ret_val;
2125 }
2126
2127 /**
2128 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2129 *
2130 * @hw: pointer to hardware structure
2131 *
2132 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2133 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2134 * to AUTOC, so this function assumes the semaphore is held.
2135 **/
2136 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2137 {
2138 s32 i, autoc_reg, ret_val;
2139 s32 anlp1_reg = 0;
2140
2141 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2142 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2143
2144 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2145 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2146
2147 /* Wait for AN to leave state 0 */
2148 for (i = 0; i < 10; i++) {
2149 usleep_range(4000, 8000);
2150 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2151 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2152 break;
2153 }
2154
2155 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2156 hw_dbg(hw, "auto negotiation not completed\n");
2157 ret_val = IXGBE_ERR_RESET_FAILED;
2158 goto reset_pipeline_out;
2159 }
2160
2161 ret_val = 0;
2162
2163 reset_pipeline_out:
2164 /* Write AUTOC register with original LMS field and Restart_AN */
2165 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2166 IXGBE_WRITE_FLUSH(hw);
2167
2168 return ret_val;
2169 }
2170
2171 static struct ixgbe_mac_operations mac_ops_82599 = {
2172 .init_hw = &ixgbe_init_hw_generic,
2173 .reset_hw = &ixgbe_reset_hw_82599,
2174 .start_hw = &ixgbe_start_hw_82599,
2175 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2176 .get_media_type = &ixgbe_get_media_type_82599,
2177 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2178 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2179 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2180 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2181 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2182 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2183 .get_device_caps = &ixgbe_get_device_caps_generic,
2184 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2185 .stop_adapter = &ixgbe_stop_adapter_generic,
2186 .get_bus_info = &ixgbe_get_bus_info_generic,
2187 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2188 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2189 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2190 .setup_link = &ixgbe_setup_mac_link_82599,
2191 .set_rxpba = &ixgbe_set_rxpba_generic,
2192 .check_link = &ixgbe_check_mac_link_generic,
2193 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2194 .led_on = &ixgbe_led_on_generic,
2195 .led_off = &ixgbe_led_off_generic,
2196 .blink_led_start = &ixgbe_blink_led_start_generic,
2197 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2198 .set_rar = &ixgbe_set_rar_generic,
2199 .clear_rar = &ixgbe_clear_rar_generic,
2200 .set_vmdq = &ixgbe_set_vmdq_generic,
2201 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2202 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2203 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2204 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2205 .enable_mc = &ixgbe_enable_mc_generic,
2206 .disable_mc = &ixgbe_disable_mc_generic,
2207 .clear_vfta = &ixgbe_clear_vfta_generic,
2208 .set_vfta = &ixgbe_set_vfta_generic,
2209 .fc_enable = &ixgbe_fc_enable_generic,
2210 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2211 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2212 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2213 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2214 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2215 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2216 .release_swfw_sync = &ixgbe_release_swfw_sync,
2217 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2218 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2219
2220 };
2221
2222 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2223 .init_params = &ixgbe_init_eeprom_params_generic,
2224 .read = &ixgbe_read_eeprom_82599,
2225 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2226 .write = &ixgbe_write_eeprom_generic,
2227 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2228 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2229 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2230 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2231 };
2232
2233 static struct ixgbe_phy_operations phy_ops_82599 = {
2234 .identify = &ixgbe_identify_phy_82599,
2235 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2236 .init = &ixgbe_init_phy_ops_82599,
2237 .reset = &ixgbe_reset_phy_generic,
2238 .read_reg = &ixgbe_read_phy_reg_generic,
2239 .write_reg = &ixgbe_write_phy_reg_generic,
2240 .setup_link = &ixgbe_setup_phy_link_generic,
2241 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2242 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2243 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2244 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2245 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2246 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2247 .check_overtemp = &ixgbe_tn_check_overtemp,
2248 };
2249
2250 struct ixgbe_info ixgbe_82599_info = {
2251 .mac = ixgbe_mac_82599EB,
2252 .get_invariants = &ixgbe_get_invariants_82599,
2253 .mac_ops = &mac_ops_82599,
2254 .eeprom_ops = &eeprom_ops_82599,
2255 .phy_ops = &phy_ops_82599,
2256 .mbx_ops = &mbx_ops_generic,
2257 };
CJK support for tty framebuffer vt