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net/macb: ethtool interface: add register dump feature
[linux-2.6/cjktty.git] / drivers / net / ethernet / cadence / macb.c
blob78488b4c6fb2fb600944c056b5a1197769bcb234
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_data/macb.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_net.h>
29
30 #include "macb.h"
31
32 #define RX_BUFFER_SIZE 128
33 #define RX_RING_SIZE 512 /* must be power of 2 */
34 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
35
36 /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
37 #define RX_OFFSET 2
38
39 #define TX_RING_SIZE 128 /* must be power of 2 */
40 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
41
42 /* minimum number of free TX descriptors before waking up TX process */
43 #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
44
45 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
46 | MACB_BIT(ISR_ROVR))
47
48 /* Ring buffer accessors */
49 static unsigned int macb_tx_ring_wrap(unsigned int index)
50 {
51 return index & (TX_RING_SIZE - 1);
52 }
53
54 static unsigned int macb_tx_ring_avail(struct macb *bp)
55 {
56 return (bp->tx_tail - bp->tx_head) & (TX_RING_SIZE - 1);
57 }
58
59 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
60 {
61 return &bp->tx_ring[macb_tx_ring_wrap(index)];
62 }
63
64 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
65 {
66 return &bp->tx_skb[macb_tx_ring_wrap(index)];
67 }
68
69 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
70 {
71 dma_addr_t offset;
72
73 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
74
75 return bp->tx_ring_dma + offset;
76 }
77
78 static unsigned int macb_rx_ring_wrap(unsigned int index)
79 {
80 return index & (RX_RING_SIZE - 1);
81 }
82
83 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
84 {
85 return &bp->rx_ring[macb_rx_ring_wrap(index)];
86 }
87
88 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
89 {
90 return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index);
91 }
92
93 static void __macb_set_hwaddr(struct macb *bp)
94 {
95 u32 bottom;
96 u16 top;
97
98 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
99 macb_or_gem_writel(bp, SA1B, bottom);
100 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
101 macb_or_gem_writel(bp, SA1T, top);
102 }
103
104 static void __init macb_get_hwaddr(struct macb *bp)
105 {
106 u32 bottom;
107 u16 top;
108 u8 addr[6];
109
110 bottom = macb_or_gem_readl(bp, SA1B);
111 top = macb_or_gem_readl(bp, SA1T);
112
113 addr[0] = bottom & 0xff;
114 addr[1] = (bottom >> 8) & 0xff;
115 addr[2] = (bottom >> 16) & 0xff;
116 addr[3] = (bottom >> 24) & 0xff;
117 addr[4] = top & 0xff;
118 addr[5] = (top >> 8) & 0xff;
119
120 if (is_valid_ether_addr(addr)) {
121 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
122 } else {
123 netdev_info(bp->dev, "invalid hw address, using random\n");
124 eth_hw_addr_random(bp->dev);
125 }
126 }
127
128 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
129 {
130 struct macb *bp = bus->priv;
131 int value;
132
133 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
134 | MACB_BF(RW, MACB_MAN_READ)
135 | MACB_BF(PHYA, mii_id)
136 | MACB_BF(REGA, regnum)
137 | MACB_BF(CODE, MACB_MAN_CODE)));
138
139 /* wait for end of transfer */
140 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
141 cpu_relax();
142
143 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
144
145 return value;
146 }
147
148 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
149 u16 value)
150 {
151 struct macb *bp = bus->priv;
152
153 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
154 | MACB_BF(RW, MACB_MAN_WRITE)
155 | MACB_BF(PHYA, mii_id)
156 | MACB_BF(REGA, regnum)
157 | MACB_BF(CODE, MACB_MAN_CODE)
158 | MACB_BF(DATA, value)));
159
160 /* wait for end of transfer */
161 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
162 cpu_relax();
163
164 return 0;
165 }
166
167 static int macb_mdio_reset(struct mii_bus *bus)
168 {
169 return 0;
170 }
171
172 static void macb_handle_link_change(struct net_device *dev)
173 {
174 struct macb *bp = netdev_priv(dev);
175 struct phy_device *phydev = bp->phy_dev;
176 unsigned long flags;
177
178 int status_change = 0;
179
180 spin_lock_irqsave(&bp->lock, flags);
181
182 if (phydev->link) {
183 if ((bp->speed != phydev->speed) ||
184 (bp->duplex != phydev->duplex)) {
185 u32 reg;
186
187 reg = macb_readl(bp, NCFGR);
188 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
189 if (macb_is_gem(bp))
190 reg &= ~GEM_BIT(GBE);
191
192 if (phydev->duplex)
193 reg |= MACB_BIT(FD);
194 if (phydev->speed == SPEED_100)
195 reg |= MACB_BIT(SPD);
196 if (phydev->speed == SPEED_1000)
197 reg |= GEM_BIT(GBE);
198
199 macb_or_gem_writel(bp, NCFGR, reg);
200
201 bp->speed = phydev->speed;
202 bp->duplex = phydev->duplex;
203 status_change = 1;
204 }
205 }
206
207 if (phydev->link != bp->link) {
208 if (!phydev->link) {
209 bp->speed = 0;
210 bp->duplex = -1;
211 }
212 bp->link = phydev->link;
213
214 status_change = 1;
215 }
216
217 spin_unlock_irqrestore(&bp->lock, flags);
218
219 if (status_change) {
220 if (phydev->link) {
221 netif_carrier_on(dev);
222 netdev_info(dev, "link up (%d/%s)\n",
223 phydev->speed,
224 phydev->duplex == DUPLEX_FULL ?
225 "Full" : "Half");
226 } else {
227 netif_carrier_off(dev);
228 netdev_info(dev, "link down\n");
229 }
230 }
231 }
232
233 /* based on au1000_eth. c*/
234 static int macb_mii_probe(struct net_device *dev)
235 {
236 struct macb *bp = netdev_priv(dev);
237 struct phy_device *phydev;
238 int ret;
239
240 phydev = phy_find_first(bp->mii_bus);
241 if (!phydev) {
242 netdev_err(dev, "no PHY found\n");
243 return -1;
244 }
245
246 /* TODO : add pin_irq */
247
248 /* attach the mac to the phy */
249 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
250 bp->phy_interface);
251 if (ret) {
252 netdev_err(dev, "Could not attach to PHY\n");
253 return ret;
254 }
255
256 /* mask with MAC supported features */
257 if (macb_is_gem(bp))
258 phydev->supported &= PHY_GBIT_FEATURES;
259 else
260 phydev->supported &= PHY_BASIC_FEATURES;
261
262 phydev->advertising = phydev->supported;
263
264 bp->link = 0;
265 bp->speed = 0;
266 bp->duplex = -1;
267 bp->phy_dev = phydev;
268
269 return 0;
270 }
271
272 int macb_mii_init(struct macb *bp)
273 {
274 struct macb_platform_data *pdata;
275 int err = -ENXIO, i;
276
277 /* Enable management port */
278 macb_writel(bp, NCR, MACB_BIT(MPE));
279
280 bp->mii_bus = mdiobus_alloc();
281 if (bp->mii_bus == NULL) {
282 err = -ENOMEM;
283 goto err_out;
284 }
285
286 bp->mii_bus->name = "MACB_mii_bus";
287 bp->mii_bus->read = &macb_mdio_read;
288 bp->mii_bus->write = &macb_mdio_write;
289 bp->mii_bus->reset = &macb_mdio_reset;
290 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
291 bp->pdev->name, bp->pdev->id);
292 bp->mii_bus->priv = bp;
293 bp->mii_bus->parent = &bp->dev->dev;
294 pdata = bp->pdev->dev.platform_data;
295
296 if (pdata)
297 bp->mii_bus->phy_mask = pdata->phy_mask;
298
299 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
300 if (!bp->mii_bus->irq) {
301 err = -ENOMEM;
302 goto err_out_free_mdiobus;
303 }
304
305 for (i = 0; i < PHY_MAX_ADDR; i++)
306 bp->mii_bus->irq[i] = PHY_POLL;
307
308 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
309
310 if (mdiobus_register(bp->mii_bus))
311 goto err_out_free_mdio_irq;
312
313 if (macb_mii_probe(bp->dev) != 0) {
314 goto err_out_unregister_bus;
315 }
316
317 return 0;
318
319 err_out_unregister_bus:
320 mdiobus_unregister(bp->mii_bus);
321 err_out_free_mdio_irq:
322 kfree(bp->mii_bus->irq);
323 err_out_free_mdiobus:
324 mdiobus_free(bp->mii_bus);
325 err_out:
326 return err;
327 }
328 EXPORT_SYMBOL_GPL(macb_mii_init);
329
330 static void macb_update_stats(struct macb *bp)
331 {
332 u32 __iomem *reg = bp->regs + MACB_PFR;
333 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
334 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
335
336 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
337
338 for(; p < end; p++, reg++)
339 *p += __raw_readl(reg);
340 }
341
342 static void macb_tx(struct macb *bp)
343 {
344 unsigned int tail;
345 unsigned int head;
346 u32 status;
347
348 status = macb_readl(bp, TSR);
349 macb_writel(bp, TSR, status);
350
351 netdev_vdbg(bp->dev, "macb_tx status = 0x%03lx\n", (unsigned long)status);
352
353 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
354 int i;
355 netdev_err(bp->dev, "TX %s, resetting buffers\n",
356 status & MACB_BIT(UND) ?
357 "underrun" : "retry limit exceeded");
358
359 /* Transfer ongoing, disable transmitter, to avoid confusion */
360 if (status & MACB_BIT(TGO))
361 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
362
363 head = bp->tx_head;
364
365 /*Mark all the buffer as used to avoid sending a lost buffer*/
366 for (i = 0; i < TX_RING_SIZE; i++)
367 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
368
369 /* Add wrap bit */
370 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
371
372 /* free transmit buffer in upper layer*/
373 for (tail = bp->tx_tail; tail != head; tail++) {
374 struct macb_tx_skb *tx_skb;
375 struct sk_buff *skb;
376
377 rmb();
378
379 tx_skb = macb_tx_skb(bp, tail);
380 skb = tx_skb->skb;
381
382 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
383 skb->len, DMA_TO_DEVICE);
384 tx_skb->skb = NULL;
385 dev_kfree_skb_irq(skb);
386 }
387
388 bp->tx_head = bp->tx_tail = 0;
389
390 /* Enable the transmitter again */
391 if (status & MACB_BIT(TGO))
392 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
393 }
394
395 if (!(status & MACB_BIT(COMP)))
396 /*
397 * This may happen when a buffer becomes complete
398 * between reading the ISR and scanning the
399 * descriptors. Nothing to worry about.
400 */
401 return;
402
403 head = bp->tx_head;
404 for (tail = bp->tx_tail; tail != head; tail++) {
405 struct macb_tx_skb *tx_skb;
406 struct sk_buff *skb;
407 struct macb_dma_desc *desc;
408 u32 ctrl;
409
410 desc = macb_tx_desc(bp, tail);
411
412 /* Make hw descriptor updates visible to CPU */
413 rmb();
414
415 ctrl = desc->ctrl;
416
417 if (!(ctrl & MACB_BIT(TX_USED)))
418 break;
419
420 tx_skb = macb_tx_skb(bp, tail);
421 skb = tx_skb->skb;
422
423 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
424 macb_tx_ring_wrap(tail), skb->data);
425 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
426 DMA_TO_DEVICE);
427 bp->stats.tx_packets++;
428 bp->stats.tx_bytes += skb->len;
429 tx_skb->skb = NULL;
430 dev_kfree_skb_irq(skb);
431 }
432
433 bp->tx_tail = tail;
434 if (netif_queue_stopped(bp->dev)
435 && macb_tx_ring_avail(bp) > MACB_TX_WAKEUP_THRESH)
436 netif_wake_queue(bp->dev);
437 }
438
439 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
440 unsigned int last_frag)
441 {
442 unsigned int len;
443 unsigned int frag;
444 unsigned int offset = 0;
445 struct sk_buff *skb;
446 struct macb_dma_desc *desc;
447
448 desc = macb_rx_desc(bp, last_frag);
449 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
450
451 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
452 macb_rx_ring_wrap(first_frag),
453 macb_rx_ring_wrap(last_frag), len);
454
455 skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET);
456 if (!skb) {
457 bp->stats.rx_dropped++;
458 for (frag = first_frag; ; frag++) {
459 desc = macb_rx_desc(bp, frag);
460 desc->addr &= ~MACB_BIT(RX_USED);
461 if (frag == last_frag)
462 break;
463 }
464
465 /* Make descriptor updates visible to hardware */
466 wmb();
467
468 return 1;
469 }
470
471 skb_reserve(skb, RX_OFFSET);
472 skb_checksum_none_assert(skb);
473 skb_put(skb, len);
474
475 for (frag = first_frag; ; frag++) {
476 unsigned int frag_len = RX_BUFFER_SIZE;
477
478 if (offset + frag_len > len) {
479 BUG_ON(frag != last_frag);
480 frag_len = len - offset;
481 }
482 skb_copy_to_linear_data_offset(skb, offset,
483 macb_rx_buffer(bp, frag), frag_len);
484 offset += RX_BUFFER_SIZE;
485 desc = macb_rx_desc(bp, frag);
486 desc->addr &= ~MACB_BIT(RX_USED);
487
488 if (frag == last_frag)
489 break;
490 }
491
492 /* Make descriptor updates visible to hardware */
493 wmb();
494
495 skb->protocol = eth_type_trans(skb, bp->dev);
496
497 bp->stats.rx_packets++;
498 bp->stats.rx_bytes += len;
499 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
500 skb->len, skb->csum);
501 netif_receive_skb(skb);
502
503 return 0;
504 }
505
506 /* Mark DMA descriptors from begin up to and not including end as unused */
507 static void discard_partial_frame(struct macb *bp, unsigned int begin,
508 unsigned int end)
509 {
510 unsigned int frag;
511
512 for (frag = begin; frag != end; frag++) {
513 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
514 desc->addr &= ~MACB_BIT(RX_USED);
515 }
516
517 /* Make descriptor updates visible to hardware */
518 wmb();
519
520 /*
521 * When this happens, the hardware stats registers for
522 * whatever caused this is updated, so we don't have to record
523 * anything.
524 */
525 }
526
527 static int macb_rx(struct macb *bp, int budget)
528 {
529 int received = 0;
530 unsigned int tail;
531 int first_frag = -1;
532
533 for (tail = bp->rx_tail; budget > 0; tail++) {
534 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
535 u32 addr, ctrl;
536
537 /* Make hw descriptor updates visible to CPU */
538 rmb();
539
540 addr = desc->addr;
541 ctrl = desc->ctrl;
542
543 if (!(addr & MACB_BIT(RX_USED)))
544 break;
545
546 if (ctrl & MACB_BIT(RX_SOF)) {
547 if (first_frag != -1)
548 discard_partial_frame(bp, first_frag, tail);
549 first_frag = tail;
550 }
551
552 if (ctrl & MACB_BIT(RX_EOF)) {
553 int dropped;
554 BUG_ON(first_frag == -1);
555
556 dropped = macb_rx_frame(bp, first_frag, tail);
557 first_frag = -1;
558 if (!dropped) {
559 received++;
560 budget--;
561 }
562 }
563 }
564
565 if (first_frag != -1)
566 bp->rx_tail = first_frag;
567 else
568 bp->rx_tail = tail;
569
570 return received;
571 }
572
573 static int macb_poll(struct napi_struct *napi, int budget)
574 {
575 struct macb *bp = container_of(napi, struct macb, napi);
576 int work_done;
577 u32 status;
578
579 status = macb_readl(bp, RSR);
580 macb_writel(bp, RSR, status);
581
582 work_done = 0;
583
584 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
585 (unsigned long)status, budget);
586
587 work_done = macb_rx(bp, budget);
588 if (work_done < budget) {
589 napi_complete(napi);
590
591 /*
592 * We've done what we can to clean the buffers. Make sure we
593 * get notified when new packets arrive.
594 */
595 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
596 }
597
598 /* TODO: Handle errors */
599
600 return work_done;
601 }
602
603 static irqreturn_t macb_interrupt(int irq, void *dev_id)
604 {
605 struct net_device *dev = dev_id;
606 struct macb *bp = netdev_priv(dev);
607 u32 status;
608
609 status = macb_readl(bp, ISR);
610
611 if (unlikely(!status))
612 return IRQ_NONE;
613
614 spin_lock(&bp->lock);
615
616 while (status) {
617 /* close possible race with dev_close */
618 if (unlikely(!netif_running(dev))) {
619 macb_writel(bp, IDR, -1);
620 break;
621 }
622
623 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
624
625 if (status & MACB_RX_INT_FLAGS) {
626 /*
627 * There's no point taking any more interrupts
628 * until we have processed the buffers. The
629 * scheduling call may fail if the poll routine
630 * is already scheduled, so disable interrupts
631 * now.
632 */
633 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
634
635 if (napi_schedule_prep(&bp->napi)) {
636 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
637 __napi_schedule(&bp->napi);
638 }
639 }
640
641 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
642 MACB_BIT(ISR_RLE)))
643 macb_tx(bp);
644
645 /*
646 * Link change detection isn't possible with RMII, so we'll
647 * add that if/when we get our hands on a full-blown MII PHY.
648 */
649
650 if (status & MACB_BIT(ISR_ROVR)) {
651 /* We missed at least one packet */
652 if (macb_is_gem(bp))
653 bp->hw_stats.gem.rx_overruns++;
654 else
655 bp->hw_stats.macb.rx_overruns++;
656 }
657
658 if (status & MACB_BIT(HRESP)) {
659 /*
660 * TODO: Reset the hardware, and maybe move the
661 * netdev_err to a lower-priority context as well
662 * (work queue?)
663 */
664 netdev_err(dev, "DMA bus error: HRESP not OK\n");
665 }
666
667 status = macb_readl(bp, ISR);
668 }
669
670 spin_unlock(&bp->lock);
671
672 return IRQ_HANDLED;
673 }
674
675 #ifdef CONFIG_NET_POLL_CONTROLLER
676 /*
677 * Polling receive - used by netconsole and other diagnostic tools
678 * to allow network i/o with interrupts disabled.
679 */
680 static void macb_poll_controller(struct net_device *dev)
681 {
682 unsigned long flags;
683
684 local_irq_save(flags);
685 macb_interrupt(dev->irq, dev);
686 local_irq_restore(flags);
687 }
688 #endif
689
690 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
691 {
692 struct macb *bp = netdev_priv(dev);
693 dma_addr_t mapping;
694 unsigned int len, entry;
695 struct macb_dma_desc *desc;
696 struct macb_tx_skb *tx_skb;
697 u32 ctrl;
698 unsigned long flags;
699
700 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
701 netdev_vdbg(bp->dev,
702 "start_xmit: len %u head %p data %p tail %p end %p\n",
703 skb->len, skb->head, skb->data,
704 skb_tail_pointer(skb), skb_end_pointer(skb));
705 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
706 skb->data, 16, true);
707 #endif
708
709 len = skb->len;
710 spin_lock_irqsave(&bp->lock, flags);
711
712 /* This is a hard error, log it. */
713 if (macb_tx_ring_avail(bp) < 1) {
714 netif_stop_queue(dev);
715 spin_unlock_irqrestore(&bp->lock, flags);
716 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
717 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
718 bp->tx_head, bp->tx_tail);
719 return NETDEV_TX_BUSY;
720 }
721
722 entry = macb_tx_ring_wrap(bp->tx_head);
723 bp->tx_head++;
724 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
725 mapping = dma_map_single(&bp->pdev->dev, skb->data,
726 len, DMA_TO_DEVICE);
727
728 tx_skb = &bp->tx_skb[entry];
729 tx_skb->skb = skb;
730 tx_skb->mapping = mapping;
731 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
732 skb->data, (unsigned long)mapping);
733
734 ctrl = MACB_BF(TX_FRMLEN, len);
735 ctrl |= MACB_BIT(TX_LAST);
736 if (entry == (TX_RING_SIZE - 1))
737 ctrl |= MACB_BIT(TX_WRAP);
738
739 desc = &bp->tx_ring[entry];
740 desc->addr = mapping;
741 desc->ctrl = ctrl;
742
743 /* Make newly initialized descriptor visible to hardware */
744 wmb();
745
746 skb_tx_timestamp(skb);
747
748 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
749
750 if (macb_tx_ring_avail(bp) < 1)
751 netif_stop_queue(dev);
752
753 spin_unlock_irqrestore(&bp->lock, flags);
754
755 return NETDEV_TX_OK;
756 }
757
758 static void macb_free_consistent(struct macb *bp)
759 {
760 if (bp->tx_skb) {
761 kfree(bp->tx_skb);
762 bp->tx_skb = NULL;
763 }
764 if (bp->rx_ring) {
765 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
766 bp->rx_ring, bp->rx_ring_dma);
767 bp->rx_ring = NULL;
768 }
769 if (bp->tx_ring) {
770 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
771 bp->tx_ring, bp->tx_ring_dma);
772 bp->tx_ring = NULL;
773 }
774 if (bp->rx_buffers) {
775 dma_free_coherent(&bp->pdev->dev,
776 RX_RING_SIZE * RX_BUFFER_SIZE,
777 bp->rx_buffers, bp->rx_buffers_dma);
778 bp->rx_buffers = NULL;
779 }
780 }
781
782 static int macb_alloc_consistent(struct macb *bp)
783 {
784 int size;
785
786 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
787 bp->tx_skb = kmalloc(size, GFP_KERNEL);
788 if (!bp->tx_skb)
789 goto out_err;
790
791 size = RX_RING_BYTES;
792 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
793 &bp->rx_ring_dma, GFP_KERNEL);
794 if (!bp->rx_ring)
795 goto out_err;
796 netdev_dbg(bp->dev,
797 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
798 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
799
800 size = TX_RING_BYTES;
801 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
802 &bp->tx_ring_dma, GFP_KERNEL);
803 if (!bp->tx_ring)
804 goto out_err;
805 netdev_dbg(bp->dev,
806 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
807 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
808
809 size = RX_RING_SIZE * RX_BUFFER_SIZE;
810 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
811 &bp->rx_buffers_dma, GFP_KERNEL);
812 if (!bp->rx_buffers)
813 goto out_err;
814 netdev_dbg(bp->dev,
815 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
816 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
817
818 return 0;
819
820 out_err:
821 macb_free_consistent(bp);
822 return -ENOMEM;
823 }
824
825 static void macb_init_rings(struct macb *bp)
826 {
827 int i;
828 dma_addr_t addr;
829
830 addr = bp->rx_buffers_dma;
831 for (i = 0; i < RX_RING_SIZE; i++) {
832 bp->rx_ring[i].addr = addr;
833 bp->rx_ring[i].ctrl = 0;
834 addr += RX_BUFFER_SIZE;
835 }
836 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
837
838 for (i = 0; i < TX_RING_SIZE; i++) {
839 bp->tx_ring[i].addr = 0;
840 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
841 }
842 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
843
844 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
845 }
846
847 static void macb_reset_hw(struct macb *bp)
848 {
849 /*
850 * Disable RX and TX (XXX: Should we halt the transmission
851 * more gracefully?)
852 */
853 macb_writel(bp, NCR, 0);
854
855 /* Clear the stats registers (XXX: Update stats first?) */
856 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
857
858 /* Clear all status flags */
859 macb_writel(bp, TSR, -1);
860 macb_writel(bp, RSR, -1);
861
862 /* Disable all interrupts */
863 macb_writel(bp, IDR, -1);
864 macb_readl(bp, ISR);
865 }
866
867 static u32 gem_mdc_clk_div(struct macb *bp)
868 {
869 u32 config;
870 unsigned long pclk_hz = clk_get_rate(bp->pclk);
871
872 if (pclk_hz <= 20000000)
873 config = GEM_BF(CLK, GEM_CLK_DIV8);
874 else if (pclk_hz <= 40000000)
875 config = GEM_BF(CLK, GEM_CLK_DIV16);
876 else if (pclk_hz <= 80000000)
877 config = GEM_BF(CLK, GEM_CLK_DIV32);
878 else if (pclk_hz <= 120000000)
879 config = GEM_BF(CLK, GEM_CLK_DIV48);
880 else if (pclk_hz <= 160000000)
881 config = GEM_BF(CLK, GEM_CLK_DIV64);
882 else
883 config = GEM_BF(CLK, GEM_CLK_DIV96);
884
885 return config;
886 }
887
888 static u32 macb_mdc_clk_div(struct macb *bp)
889 {
890 u32 config;
891 unsigned long pclk_hz;
892
893 if (macb_is_gem(bp))
894 return gem_mdc_clk_div(bp);
895
896 pclk_hz = clk_get_rate(bp->pclk);
897 if (pclk_hz <= 20000000)
898 config = MACB_BF(CLK, MACB_CLK_DIV8);
899 else if (pclk_hz <= 40000000)
900 config = MACB_BF(CLK, MACB_CLK_DIV16);
901 else if (pclk_hz <= 80000000)
902 config = MACB_BF(CLK, MACB_CLK_DIV32);
903 else
904 config = MACB_BF(CLK, MACB_CLK_DIV64);
905
906 return config;
907 }
908
909 /*
910 * Get the DMA bus width field of the network configuration register that we
911 * should program. We find the width from decoding the design configuration
912 * register to find the maximum supported data bus width.
913 */
914 static u32 macb_dbw(struct macb *bp)
915 {
916 if (!macb_is_gem(bp))
917 return 0;
918
919 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
920 case 4:
921 return GEM_BF(DBW, GEM_DBW128);
922 case 2:
923 return GEM_BF(DBW, GEM_DBW64);
924 case 1:
925 default:
926 return GEM_BF(DBW, GEM_DBW32);
927 }
928 }
929
930 /*
931 * Configure the receive DMA engine to use the correct receive buffer size.
932 * This is a configurable parameter for GEM.
933 */
934 static void macb_configure_dma(struct macb *bp)
935 {
936 u32 dmacfg;
937
938 if (macb_is_gem(bp)) {
939 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
940 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
941 gem_writel(bp, DMACFG, dmacfg);
942 }
943 }
944
945 static void macb_init_hw(struct macb *bp)
946 {
947 u32 config;
948
949 macb_reset_hw(bp);
950 __macb_set_hwaddr(bp);
951
952 config = macb_mdc_clk_div(bp);
953 config |= MACB_BIT(PAE); /* PAuse Enable */
954 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
955 config |= MACB_BIT(BIG); /* Receive oversized frames */
956 if (bp->dev->flags & IFF_PROMISC)
957 config |= MACB_BIT(CAF); /* Copy All Frames */
958 if (!(bp->dev->flags & IFF_BROADCAST))
959 config |= MACB_BIT(NBC); /* No BroadCast */
960 config |= macb_dbw(bp);
961 macb_writel(bp, NCFGR, config);
962
963 macb_configure_dma(bp);
964
965 /* Initialize TX and RX buffers */
966 macb_writel(bp, RBQP, bp->rx_ring_dma);
967 macb_writel(bp, TBQP, bp->tx_ring_dma);
968
969 /* Enable TX and RX */
970 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
971
972 /* Enable interrupts */
973 macb_writel(bp, IER, (MACB_BIT(RCOMP)
974 | MACB_BIT(RXUBR)
975 | MACB_BIT(ISR_TUND)
976 | MACB_BIT(ISR_RLE)
977 | MACB_BIT(TXERR)
978 | MACB_BIT(TCOMP)
979 | MACB_BIT(ISR_ROVR)
980 | MACB_BIT(HRESP)));
981
982 }
983
984 /*
985 * The hash address register is 64 bits long and takes up two
986 * locations in the memory map. The least significant bits are stored
987 * in EMAC_HSL and the most significant bits in EMAC_HSH.
988 *
989 * The unicast hash enable and the multicast hash enable bits in the
990 * network configuration register enable the reception of hash matched
991 * frames. The destination address is reduced to a 6 bit index into
992 * the 64 bit hash register using the following hash function. The
993 * hash function is an exclusive or of every sixth bit of the
994 * destination address.
995 *
996 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
997 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
998 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
999 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1000 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1001 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1002 *
1003 * da[0] represents the least significant bit of the first byte
1004 * received, that is, the multicast/unicast indicator, and da[47]
1005 * represents the most significant bit of the last byte received. If
1006 * the hash index, hi[n], points to a bit that is set in the hash
1007 * register then the frame will be matched according to whether the
1008 * frame is multicast or unicast. A multicast match will be signalled
1009 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1010 * index points to a bit set in the hash register. A unicast match
1011 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1012 * and the hash index points to a bit set in the hash register. To
1013 * receive all multicast frames, the hash register should be set with
1014 * all ones and the multicast hash enable bit should be set in the
1015 * network configuration register.
1016 */
1017
1018 static inline int hash_bit_value(int bitnr, __u8 *addr)
1019 {
1020 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1021 return 1;
1022 return 0;
1023 }
1024
1025 /*
1026 * Return the hash index value for the specified address.
1027 */
1028 static int hash_get_index(__u8 *addr)
1029 {
1030 int i, j, bitval;
1031 int hash_index = 0;
1032
1033 for (j = 0; j < 6; j++) {
1034 for (i = 0, bitval = 0; i < 8; i++)
1035 bitval ^= hash_bit_value(i*6 + j, addr);
1036
1037 hash_index |= (bitval << j);
1038 }
1039
1040 return hash_index;
1041 }
1042
1043 /*
1044 * Add multicast addresses to the internal multicast-hash table.
1045 */
1046 static void macb_sethashtable(struct net_device *dev)
1047 {
1048 struct netdev_hw_addr *ha;
1049 unsigned long mc_filter[2];
1050 unsigned int bitnr;
1051 struct macb *bp = netdev_priv(dev);
1052
1053 mc_filter[0] = mc_filter[1] = 0;
1054
1055 netdev_for_each_mc_addr(ha, dev) {
1056 bitnr = hash_get_index(ha->addr);
1057 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1058 }
1059
1060 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1061 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1062 }
1063
1064 /*
1065 * Enable/Disable promiscuous and multicast modes.
1066 */
1067 void macb_set_rx_mode(struct net_device *dev)
1068 {
1069 unsigned long cfg;
1070 struct macb *bp = netdev_priv(dev);
1071
1072 cfg = macb_readl(bp, NCFGR);
1073
1074 if (dev->flags & IFF_PROMISC)
1075 /* Enable promiscuous mode */
1076 cfg |= MACB_BIT(CAF);
1077 else if (dev->flags & (~IFF_PROMISC))
1078 /* Disable promiscuous mode */
1079 cfg &= ~MACB_BIT(CAF);
1080
1081 if (dev->flags & IFF_ALLMULTI) {
1082 /* Enable all multicast mode */
1083 macb_or_gem_writel(bp, HRB, -1);
1084 macb_or_gem_writel(bp, HRT, -1);
1085 cfg |= MACB_BIT(NCFGR_MTI);
1086 } else if (!netdev_mc_empty(dev)) {
1087 /* Enable specific multicasts */
1088 macb_sethashtable(dev);
1089 cfg |= MACB_BIT(NCFGR_MTI);
1090 } else if (dev->flags & (~IFF_ALLMULTI)) {
1091 /* Disable all multicast mode */
1092 macb_or_gem_writel(bp, HRB, 0);
1093 macb_or_gem_writel(bp, HRT, 0);
1094 cfg &= ~MACB_BIT(NCFGR_MTI);
1095 }
1096
1097 macb_writel(bp, NCFGR, cfg);
1098 }
1099 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1100
1101 static int macb_open(struct net_device *dev)
1102 {
1103 struct macb *bp = netdev_priv(dev);
1104 int err;
1105
1106 netdev_dbg(bp->dev, "open\n");
1107
1108 /* carrier starts down */
1109 netif_carrier_off(dev);
1110
1111 /* if the phy is not yet register, retry later*/
1112 if (!bp->phy_dev)
1113 return -EAGAIN;
1114
1115 if (!is_valid_ether_addr(dev->dev_addr))
1116 return -EADDRNOTAVAIL;
1117
1118 err = macb_alloc_consistent(bp);
1119 if (err) {
1120 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1121 err);
1122 return err;
1123 }
1124
1125 napi_enable(&bp->napi);
1126
1127 macb_init_rings(bp);
1128 macb_init_hw(bp);
1129
1130 /* schedule a link state check */
1131 phy_start(bp->phy_dev);
1132
1133 netif_start_queue(dev);
1134
1135 return 0;
1136 }
1137
1138 static int macb_close(struct net_device *dev)
1139 {
1140 struct macb *bp = netdev_priv(dev);
1141 unsigned long flags;
1142
1143 netif_stop_queue(dev);
1144 napi_disable(&bp->napi);
1145
1146 if (bp->phy_dev)
1147 phy_stop(bp->phy_dev);
1148
1149 spin_lock_irqsave(&bp->lock, flags);
1150 macb_reset_hw(bp);
1151 netif_carrier_off(dev);
1152 spin_unlock_irqrestore(&bp->lock, flags);
1153
1154 macb_free_consistent(bp);
1155
1156 return 0;
1157 }
1158
1159 static void gem_update_stats(struct macb *bp)
1160 {
1161 u32 __iomem *reg = bp->regs + GEM_OTX;
1162 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1163 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1164
1165 for (; p < end; p++, reg++)
1166 *p += __raw_readl(reg);
1167 }
1168
1169 static struct net_device_stats *gem_get_stats(struct macb *bp)
1170 {
1171 struct gem_stats *hwstat = &bp->hw_stats.gem;
1172 struct net_device_stats *nstat = &bp->stats;
1173
1174 gem_update_stats(bp);
1175
1176 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1177 hwstat->rx_alignment_errors +
1178 hwstat->rx_resource_errors +
1179 hwstat->rx_overruns +
1180 hwstat->rx_oversize_frames +
1181 hwstat->rx_jabbers +
1182 hwstat->rx_undersized_frames +
1183 hwstat->rx_length_field_frame_errors);
1184 nstat->tx_errors = (hwstat->tx_late_collisions +
1185 hwstat->tx_excessive_collisions +
1186 hwstat->tx_underrun +
1187 hwstat->tx_carrier_sense_errors);
1188 nstat->multicast = hwstat->rx_multicast_frames;
1189 nstat->collisions = (hwstat->tx_single_collision_frames +
1190 hwstat->tx_multiple_collision_frames +
1191 hwstat->tx_excessive_collisions);
1192 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1193 hwstat->rx_jabbers +
1194 hwstat->rx_undersized_frames +
1195 hwstat->rx_length_field_frame_errors);
1196 nstat->rx_over_errors = hwstat->rx_resource_errors;
1197 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1198 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1199 nstat->rx_fifo_errors = hwstat->rx_overruns;
1200 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1201 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1202 nstat->tx_fifo_errors = hwstat->tx_underrun;
1203
1204 return nstat;
1205 }
1206
1207 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1208 {
1209 struct macb *bp = netdev_priv(dev);
1210 struct net_device_stats *nstat = &bp->stats;
1211 struct macb_stats *hwstat = &bp->hw_stats.macb;
1212
1213 if (macb_is_gem(bp))
1214 return gem_get_stats(bp);
1215
1216 /* read stats from hardware */
1217 macb_update_stats(bp);
1218
1219 /* Convert HW stats into netdevice stats */
1220 nstat->rx_errors = (hwstat->rx_fcs_errors +
1221 hwstat->rx_align_errors +
1222 hwstat->rx_resource_errors +
1223 hwstat->rx_overruns +
1224 hwstat->rx_oversize_pkts +
1225 hwstat->rx_jabbers +
1226 hwstat->rx_undersize_pkts +
1227 hwstat->sqe_test_errors +
1228 hwstat->rx_length_mismatch);
1229 nstat->tx_errors = (hwstat->tx_late_cols +
1230 hwstat->tx_excessive_cols +
1231 hwstat->tx_underruns +
1232 hwstat->tx_carrier_errors);
1233 nstat->collisions = (hwstat->tx_single_cols +
1234 hwstat->tx_multiple_cols +
1235 hwstat->tx_excessive_cols);
1236 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1237 hwstat->rx_jabbers +
1238 hwstat->rx_undersize_pkts +
1239 hwstat->rx_length_mismatch);
1240 nstat->rx_over_errors = hwstat->rx_resource_errors +
1241 hwstat->rx_overruns;
1242 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1243 nstat->rx_frame_errors = hwstat->rx_align_errors;
1244 nstat->rx_fifo_errors = hwstat->rx_overruns;
1245 /* XXX: What does "missed" mean? */
1246 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1247 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1248 nstat->tx_fifo_errors = hwstat->tx_underruns;
1249 /* Don't know about heartbeat or window errors... */
1250
1251 return nstat;
1252 }
1253
1254 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1255 {
1256 struct macb *bp = netdev_priv(dev);
1257 struct phy_device *phydev = bp->phy_dev;
1258
1259 if (!phydev)
1260 return -ENODEV;
1261
1262 return phy_ethtool_gset(phydev, cmd);
1263 }
1264
1265 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1266 {
1267 struct macb *bp = netdev_priv(dev);
1268 struct phy_device *phydev = bp->phy_dev;
1269
1270 if (!phydev)
1271 return -ENODEV;
1272
1273 return phy_ethtool_sset(phydev, cmd);
1274 }
1275
1276 static int macb_get_regs_len(struct net_device *netdev)
1277 {
1278 return MACB_GREGS_NBR * sizeof(u32);
1279 }
1280
1281 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1282 void *p)
1283 {
1284 struct macb *bp = netdev_priv(dev);
1285 unsigned int tail, head;
1286 u32 *regs_buff = p;
1287
1288 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1289 | MACB_GREGS_VERSION;
1290
1291 tail = macb_tx_ring_wrap(bp->tx_tail);
1292 head = macb_tx_ring_wrap(bp->tx_head);
1293
1294 regs_buff[0] = macb_readl(bp, NCR);
1295 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1296 regs_buff[2] = macb_readl(bp, NSR);
1297 regs_buff[3] = macb_readl(bp, TSR);
1298 regs_buff[4] = macb_readl(bp, RBQP);
1299 regs_buff[5] = macb_readl(bp, TBQP);
1300 regs_buff[6] = macb_readl(bp, RSR);
1301 regs_buff[7] = macb_readl(bp, IMR);
1302
1303 regs_buff[8] = tail;
1304 regs_buff[9] = head;
1305 regs_buff[10] = macb_tx_dma(bp, tail);
1306 regs_buff[11] = macb_tx_dma(bp, head);
1307
1308 if (macb_is_gem(bp)) {
1309 regs_buff[12] = gem_readl(bp, USRIO);
1310 regs_buff[13] = gem_readl(bp, DMACFG);
1311 }
1312 }
1313
1314 const struct ethtool_ops macb_ethtool_ops = {
1315 .get_settings = macb_get_settings,
1316 .set_settings = macb_set_settings,
1317 .get_regs_len = macb_get_regs_len,
1318 .get_regs = macb_get_regs,
1319 .get_link = ethtool_op_get_link,
1320 .get_ts_info = ethtool_op_get_ts_info,
1321 };
1322 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1323
1324 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1325 {
1326 struct macb *bp = netdev_priv(dev);
1327 struct phy_device *phydev = bp->phy_dev;
1328
1329 if (!netif_running(dev))
1330 return -EINVAL;
1331
1332 if (!phydev)
1333 return -ENODEV;
1334
1335 return phy_mii_ioctl(phydev, rq, cmd);
1336 }
1337 EXPORT_SYMBOL_GPL(macb_ioctl);
1338
1339 static const struct net_device_ops macb_netdev_ops = {
1340 .ndo_open = macb_open,
1341 .ndo_stop = macb_close,
1342 .ndo_start_xmit = macb_start_xmit,
1343 .ndo_set_rx_mode = macb_set_rx_mode,
1344 .ndo_get_stats = macb_get_stats,
1345 .ndo_do_ioctl = macb_ioctl,
1346 .ndo_validate_addr = eth_validate_addr,
1347 .ndo_change_mtu = eth_change_mtu,
1348 .ndo_set_mac_address = eth_mac_addr,
1349 #ifdef CONFIG_NET_POLL_CONTROLLER
1350 .ndo_poll_controller = macb_poll_controller,
1351 #endif
1352 };
1353
1354 #if defined(CONFIG_OF)
1355 static const struct of_device_id macb_dt_ids[] = {
1356 { .compatible = "cdns,at32ap7000-macb" },
1357 { .compatible = "cdns,at91sam9260-macb" },
1358 { .compatible = "cdns,macb" },
1359 { .compatible = "cdns,pc302-gem" },
1360 { .compatible = "cdns,gem" },
1361 { /* sentinel */ }
1362 };
1363
1364 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1365
1366 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1367 {
1368 struct device_node *np = pdev->dev.of_node;
1369
1370 if (np)
1371 return of_get_phy_mode(np);
1372
1373 return -ENODEV;
1374 }
1375
1376 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1377 {
1378 struct device_node *np = bp->pdev->dev.of_node;
1379 if (np) {
1380 const char *mac = of_get_mac_address(np);
1381 if (mac) {
1382 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1383 return 0;
1384 }
1385 }
1386
1387 return -ENODEV;
1388 }
1389 #else
1390 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1391 {
1392 return -ENODEV;
1393 }
1394 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1395 {
1396 return -ENODEV;
1397 }
1398 #endif
1399
1400 static int __init macb_probe(struct platform_device *pdev)
1401 {
1402 struct macb_platform_data *pdata;
1403 struct resource *regs;
1404 struct net_device *dev;
1405 struct macb *bp;
1406 struct phy_device *phydev;
1407 u32 config;
1408 int err = -ENXIO;
1409
1410 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1411 if (!regs) {
1412 dev_err(&pdev->dev, "no mmio resource defined\n");
1413 goto err_out;
1414 }
1415
1416 err = -ENOMEM;
1417 dev = alloc_etherdev(sizeof(*bp));
1418 if (!dev)
1419 goto err_out;
1420
1421 SET_NETDEV_DEV(dev, &pdev->dev);
1422
1423 /* TODO: Actually, we have some interesting features... */
1424 dev->features |= 0;
1425
1426 bp = netdev_priv(dev);
1427 bp->pdev = pdev;
1428 bp->dev = dev;
1429
1430 spin_lock_init(&bp->lock);
1431
1432 bp->pclk = clk_get(&pdev->dev, "pclk");
1433 if (IS_ERR(bp->pclk)) {
1434 dev_err(&pdev->dev, "failed to get macb_clk\n");
1435 goto err_out_free_dev;
1436 }
1437 clk_enable(bp->pclk);
1438
1439 bp->hclk = clk_get(&pdev->dev, "hclk");
1440 if (IS_ERR(bp->hclk)) {
1441 dev_err(&pdev->dev, "failed to get hclk\n");
1442 goto err_out_put_pclk;
1443 }
1444 clk_enable(bp->hclk);
1445
1446 bp->regs = ioremap(regs->start, resource_size(regs));
1447 if (!bp->regs) {
1448 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1449 err = -ENOMEM;
1450 goto err_out_disable_clocks;
1451 }
1452
1453 dev->irq = platform_get_irq(pdev, 0);
1454 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1455 if (err) {
1456 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1457 dev->irq, err);
1458 goto err_out_iounmap;
1459 }
1460
1461 dev->netdev_ops = &macb_netdev_ops;
1462 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1463 dev->ethtool_ops = &macb_ethtool_ops;
1464
1465 dev->base_addr = regs->start;
1466
1467 /* Set MII management clock divider */
1468 config = macb_mdc_clk_div(bp);
1469 config |= macb_dbw(bp);
1470 macb_writel(bp, NCFGR, config);
1471
1472 err = macb_get_hwaddr_dt(bp);
1473 if (err < 0)
1474 macb_get_hwaddr(bp);
1475
1476 err = macb_get_phy_mode_dt(pdev);
1477 if (err < 0) {
1478 pdata = pdev->dev.platform_data;
1479 if (pdata && pdata->is_rmii)
1480 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1481 else
1482 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1483 } else {
1484 bp->phy_interface = err;
1485 }
1486
1487 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1488 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1489 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1490 #if defined(CONFIG_ARCH_AT91)
1491 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1492 MACB_BIT(CLKEN)));
1493 #else
1494 macb_or_gem_writel(bp, USRIO, 0);
1495 #endif
1496 else
1497 #if defined(CONFIG_ARCH_AT91)
1498 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1499 #else
1500 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1501 #endif
1502
1503 err = register_netdev(dev);
1504 if (err) {
1505 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1506 goto err_out_free_irq;
1507 }
1508
1509 if (macb_mii_init(bp) != 0) {
1510 goto err_out_unregister_netdev;
1511 }
1512
1513 platform_set_drvdata(pdev, dev);
1514
1515 netif_carrier_off(dev);
1516
1517 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1518 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1519 dev->irq, dev->dev_addr);
1520
1521 phydev = bp->phy_dev;
1522 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1523 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1524
1525 return 0;
1526
1527 err_out_unregister_netdev:
1528 unregister_netdev(dev);
1529 err_out_free_irq:
1530 free_irq(dev->irq, dev);
1531 err_out_iounmap:
1532 iounmap(bp->regs);
1533 err_out_disable_clocks:
1534 clk_disable(bp->hclk);
1535 clk_put(bp->hclk);
1536 clk_disable(bp->pclk);
1537 err_out_put_pclk:
1538 clk_put(bp->pclk);
1539 err_out_free_dev:
1540 free_netdev(dev);
1541 err_out:
1542 platform_set_drvdata(pdev, NULL);
1543 return err;
1544 }
1545
1546 static int __exit macb_remove(struct platform_device *pdev)
1547 {
1548 struct net_device *dev;
1549 struct macb *bp;
1550
1551 dev = platform_get_drvdata(pdev);
1552
1553 if (dev) {
1554 bp = netdev_priv(dev);
1555 if (bp->phy_dev)
1556 phy_disconnect(bp->phy_dev);
1557 mdiobus_unregister(bp->mii_bus);
1558 kfree(bp->mii_bus->irq);
1559 mdiobus_free(bp->mii_bus);
1560 unregister_netdev(dev);
1561 free_irq(dev->irq, dev);
1562 iounmap(bp->regs);
1563 clk_disable(bp->hclk);
1564 clk_put(bp->hclk);
1565 clk_disable(bp->pclk);
1566 clk_put(bp->pclk);
1567 free_netdev(dev);
1568 platform_set_drvdata(pdev, NULL);
1569 }
1570
1571 return 0;
1572 }
1573
1574 #ifdef CONFIG_PM
1575 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1576 {
1577 struct net_device *netdev = platform_get_drvdata(pdev);
1578 struct macb *bp = netdev_priv(netdev);
1579
1580 netif_carrier_off(netdev);
1581 netif_device_detach(netdev);
1582
1583 clk_disable(bp->hclk);
1584 clk_disable(bp->pclk);
1585
1586 return 0;
1587 }
1588
1589 static int macb_resume(struct platform_device *pdev)
1590 {
1591 struct net_device *netdev = platform_get_drvdata(pdev);
1592 struct macb *bp = netdev_priv(netdev);
1593
1594 clk_enable(bp->pclk);
1595 clk_enable(bp->hclk);
1596
1597 netif_device_attach(netdev);
1598
1599 return 0;
1600 }
1601 #else
1602 #define macb_suspend NULL
1603 #define macb_resume NULL
1604 #endif
1605
1606 static struct platform_driver macb_driver = {
1607 .remove = __exit_p(macb_remove),
1608 .suspend = macb_suspend,
1609 .resume = macb_resume,
1610 .driver = {
1611 .name = "macb",
1612 .owner = THIS_MODULE,
1613 .of_match_table = of_match_ptr(macb_dt_ids),
1614 },
1615 };
1616
1617 static int __init macb_init(void)
1618 {
1619 return platform_driver_probe(&macb_driver, macb_probe);
1620 }
1621
1622 static void __exit macb_exit(void)
1623 {
1624 platform_driver_unregister(&macb_driver);
1625 }
1626
1627 module_init(macb_init);
1628 module_exit(macb_exit);
1629
1630 MODULE_LICENSE("GPL");
1631 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1632 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1633 MODULE_ALIAS("platform:macb");
CJK support for tty framebuffer vt