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USB: asix: Detect internal PHY and enable/use accordingly
[linux-2.6/cjktty.git] / drivers / usb / net / asix.c
blob896449f0cf85b7a2f15b7ec1ece5df065319a447
1 /*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 // #define DEBUG // error path messages, extra info
24 // #define VERBOSE // more; success messages
25
26 #include <linux/module.h>
27 #include <linux/kmod.h>
28 #include <linux/sched.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/workqueue.h>
34 #include <linux/mii.h>
35 #include <linux/usb.h>
36 #include <linux/crc32.h>
37
38 #include "usbnet.h"
39
40 #define DRIVER_VERSION "14-Jun-2006"
41 static const char driver_name [] = "asix";
42
43 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
44
45 #define AX_CMD_SET_SW_MII 0x06
46 #define AX_CMD_READ_MII_REG 0x07
47 #define AX_CMD_WRITE_MII_REG 0x08
48 #define AX_CMD_SET_HW_MII 0x0a
49 #define AX_CMD_READ_EEPROM 0x0b
50 #define AX_CMD_WRITE_EEPROM 0x0c
51 #define AX_CMD_WRITE_ENABLE 0x0d
52 #define AX_CMD_WRITE_DISABLE 0x0e
53 #define AX_CMD_READ_RX_CTL 0x0f
54 #define AX_CMD_WRITE_RX_CTL 0x10
55 #define AX_CMD_READ_IPG012 0x11
56 #define AX_CMD_WRITE_IPG0 0x12
57 #define AX_CMD_WRITE_IPG1 0x13
58 #define AX_CMD_READ_NODE_ID 0x13
59 #define AX_CMD_WRITE_IPG2 0x14
60 #define AX_CMD_WRITE_MULTI_FILTER 0x16
61 #define AX88172_CMD_READ_NODE_ID 0x17
62 #define AX_CMD_READ_PHY_ID 0x19
63 #define AX_CMD_READ_MEDIUM_STATUS 0x1a
64 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
65 #define AX_CMD_READ_MONITOR_MODE 0x1c
66 #define AX_CMD_WRITE_MONITOR_MODE 0x1d
67 #define AX_CMD_READ_GPIOS 0x1e
68 #define AX_CMD_WRITE_GPIOS 0x1f
69 #define AX_CMD_SW_RESET 0x20
70 #define AX_CMD_SW_PHY_STATUS 0x21
71 #define AX_CMD_SW_PHY_SELECT 0x22
72
73 #define AX_MONITOR_MODE 0x01
74 #define AX_MONITOR_LINK 0x02
75 #define AX_MONITOR_MAGIC 0x04
76 #define AX_MONITOR_HSFS 0x10
77
78 /* AX88172 Medium Status Register values */
79 #define AX88172_MEDIUM_FD 0x02
80 #define AX88172_MEDIUM_TX 0x04
81 #define AX88172_MEDIUM_FC 0x10
82 #define AX88172_MEDIUM_DEFAULT \
83 ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
84
85 #define AX_MCAST_FILTER_SIZE 8
86 #define AX_MAX_MCAST 64
87
88 #define AX_SWRESET_CLEAR 0x00
89 #define AX_SWRESET_RR 0x01
90 #define AX_SWRESET_RT 0x02
91 #define AX_SWRESET_PRTE 0x04
92 #define AX_SWRESET_PRL 0x08
93 #define AX_SWRESET_BZ 0x10
94 #define AX_SWRESET_IPRL 0x20
95 #define AX_SWRESET_IPPD 0x40
96
97 #define AX88772_IPG0_DEFAULT 0x15
98 #define AX88772_IPG1_DEFAULT 0x0c
99 #define AX88772_IPG2_DEFAULT 0x12
100
101 /* AX88772 & AX88178 Medium Mode Register */
102 #define AX_MEDIUM_PF 0x0080
103 #define AX_MEDIUM_JFE 0x0040
104 #define AX_MEDIUM_TFC 0x0020
105 #define AX_MEDIUM_RFC 0x0010
106 #define AX_MEDIUM_ENCK 0x0008
107 #define AX_MEDIUM_AC 0x0004
108 #define AX_MEDIUM_FD 0x0002
109 #define AX_MEDIUM_GM 0x0001
110 #define AX_MEDIUM_SM 0x1000
111 #define AX_MEDIUM_SBP 0x0800
112 #define AX_MEDIUM_PS 0x0200
113 #define AX_MEDIUM_RE 0x0100
114
115 #define AX88178_MEDIUM_DEFAULT \
116 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
117 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
118 AX_MEDIUM_RE )
119
120 #define AX88772_MEDIUM_DEFAULT \
121 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
122 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
123 AX_MEDIUM_AC | AX_MEDIUM_RE )
124
125 /* AX88772 & AX88178 RX_CTL values */
126 #define AX_RX_CTL_SO 0x0080
127 #define AX_RX_CTL_AP 0x0020
128 #define AX_RX_CTL_AM 0x0010
129 #define AX_RX_CTL_AB 0x0008
130 #define AX_RX_CTL_SEP 0x0004
131 #define AX_RX_CTL_AMALL 0x0002
132 #define AX_RX_CTL_PRO 0x0001
133 #define AX_RX_CTL_MFB_2048 0x0000
134 #define AX_RX_CTL_MFB_4096 0x0100
135 #define AX_RX_CTL_MFB_8192 0x0200
136 #define AX_RX_CTL_MFB_16384 0x0300
137
138 #define AX_DEFAULT_RX_CTL \
139 (AX_RX_CTL_SO | AX_RX_CTL_AB )
140
141 /* GPIO 0 .. 2 toggles */
142 #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */
143 #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */
144 #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */
145 #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */
146 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
147 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
148 #define AX_GPIO_RESERVED 0x40 /* Reserved */
149 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
150
151 #define AX_EEPROM_MAGIC 0xdeadbeef
152 #define AX88172_EEPROM_LEN 0x40
153 #define AX88772_EEPROM_LEN 0xff
154
155 #define PHY_MODE_MARVELL 0x0000
156 #define MII_MARVELL_LED_CTRL 0x0018
157 #define MII_MARVELL_STATUS 0x001b
158 #define MII_MARVELL_CTRL 0x0014
159
160 #define MARVELL_LED_MANUAL 0x0019
161
162 #define MARVELL_STATUS_HWCFG 0x0004
163
164 #define MARVELL_CTRL_TXDELAY 0x0002
165 #define MARVELL_CTRL_RXDELAY 0x0080
166
167 /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
168 struct asix_data {
169 u8 multi_filter[AX_MCAST_FILTER_SIZE];
170 u8 phymode;
171 u8 ledmode;
172 u8 eeprom_len;
173 };
174
175 struct ax88172_int_data {
176 u16 res1;
177 u8 link;
178 u16 res2;
179 u8 status;
180 u16 res3;
181 } __attribute__ ((packed));
182
183 static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
184 u16 size, void *data)
185 {
186 devdbg(dev,"asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d",
187 cmd, value, index, size);
188 return usb_control_msg(
189 dev->udev,
190 usb_rcvctrlpipe(dev->udev, 0),
191 cmd,
192 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
193 value,
194 index,
195 data,
196 size,
197 USB_CTRL_GET_TIMEOUT);
198 }
199
200 static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
201 u16 size, void *data)
202 {
203 devdbg(dev,"asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d",
204 cmd, value, index, size);
205 return usb_control_msg(
206 dev->udev,
207 usb_sndctrlpipe(dev->udev, 0),
208 cmd,
209 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
210 value,
211 index,
212 data,
213 size,
214 USB_CTRL_SET_TIMEOUT);
215 }
216
217 static void asix_async_cmd_callback(struct urb *urb)
218 {
219 struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context;
220
221 if (urb->status < 0)
222 printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d",
223 urb->status);
224
225 kfree(req);
226 usb_free_urb(urb);
227 }
228
229 static void
230 asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index,
231 u16 size, void *data)
232 {
233 struct usb_ctrlrequest *req;
234 int status;
235 struct urb *urb;
236
237 devdbg(dev,"asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d",
238 cmd, value, index, size);
239 if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) {
240 deverr(dev, "Error allocating URB in write_cmd_async!");
241 return;
242 }
243
244 if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) {
245 deverr(dev, "Failed to allocate memory for control request");
246 usb_free_urb(urb);
247 return;
248 }
249
250 req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
251 req->bRequest = cmd;
252 req->wValue = cpu_to_le16(value);
253 req->wIndex = cpu_to_le16(index);
254 req->wLength = cpu_to_le16(size);
255
256 usb_fill_control_urb(urb, dev->udev,
257 usb_sndctrlpipe(dev->udev, 0),
258 (void *)req, data, size,
259 asix_async_cmd_callback, req);
260
261 if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
262 deverr(dev, "Error submitting the control message: status=%d",
263 status);
264 kfree(req);
265 usb_free_urb(urb);
266 }
267 }
268
269 static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
270 {
271 u8 *head;
272 u32 header;
273 char *packet;
274 struct sk_buff *ax_skb;
275 u16 size;
276
277 head = (u8 *) skb->data;
278 memcpy(&header, head, sizeof(header));
279 le32_to_cpus(&header);
280 packet = head + sizeof(header);
281
282 skb_pull(skb, 4);
283
284 while (skb->len > 0) {
285 if ((short)(header & 0x0000ffff) !=
286 ~((short)((header & 0xffff0000) >> 16))) {
287 deverr(dev,"asix_rx_fixup() Bad Header Length");
288 }
289 /* get the packet length */
290 size = (u16) (header & 0x0000ffff);
291
292 if ((skb->len) - ((size + 1) & 0xfffe) == 0)
293 return 2;
294 if (size > ETH_FRAME_LEN) {
295 deverr(dev,"asix_rx_fixup() Bad RX Length %d", size);
296 return 0;
297 }
298 ax_skb = skb_clone(skb, GFP_ATOMIC);
299 if (ax_skb) {
300 ax_skb->len = size;
301 ax_skb->data = packet;
302 ax_skb->tail = packet + size;
303 usbnet_skb_return(dev, ax_skb);
304 } else {
305 return 0;
306 }
307
308 skb_pull(skb, (size + 1) & 0xfffe);
309
310 if (skb->len == 0)
311 break;
312
313 head = (u8 *) skb->data;
314 memcpy(&header, head, sizeof(header));
315 le32_to_cpus(&header);
316 packet = head + sizeof(header);
317 skb_pull(skb, 4);
318 }
319
320 if (skb->len < 0) {
321 deverr(dev,"asix_rx_fixup() Bad SKB Length %d", skb->len);
322 return 0;
323 }
324 return 1;
325 }
326
327 static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
328 gfp_t flags)
329 {
330 int padlen;
331 int headroom = skb_headroom(skb);
332 int tailroom = skb_tailroom(skb);
333 u32 packet_len;
334 u32 padbytes = 0xffff0000;
335
336 padlen = ((skb->len + 4) % 512) ? 0 : 4;
337
338 if ((!skb_cloned(skb))
339 && ((headroom + tailroom) >= (4 + padlen))) {
340 if ((headroom < 4) || (tailroom < padlen)) {
341 skb->data = memmove(skb->head + 4, skb->data, skb->len);
342 skb->tail = skb->data + skb->len;
343 }
344 } else {
345 struct sk_buff *skb2;
346 skb2 = skb_copy_expand(skb, 4, padlen, flags);
347 dev_kfree_skb_any(skb);
348 skb = skb2;
349 if (!skb)
350 return NULL;
351 }
352
353 skb_push(skb, 4);
354 packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4);
355 memcpy(skb->data, &packet_len, sizeof(packet_len));
356
357 if ((skb->len % 512) == 0) {
358 memcpy( skb->tail, &padbytes, sizeof(padbytes));
359 skb_put(skb, sizeof(padbytes));
360 }
361 return skb;
362 }
363
364 static void asix_status(struct usbnet *dev, struct urb *urb)
365 {
366 struct ax88172_int_data *event;
367 int link;
368
369 if (urb->actual_length < 8)
370 return;
371
372 event = urb->transfer_buffer;
373 link = event->link & 0x01;
374 if (netif_carrier_ok(dev->net) != link) {
375 if (link) {
376 netif_carrier_on(dev->net);
377 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
378 } else
379 netif_carrier_off(dev->net);
380 devdbg(dev, "Link Status is: %d", link);
381 }
382 }
383
384 static inline int asix_set_sw_mii(struct usbnet *dev)
385 {
386 int ret;
387 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
388 if (ret < 0)
389 deverr(dev, "Failed to enable software MII access");
390 return ret;
391 }
392
393 static inline int asix_set_hw_mii(struct usbnet *dev)
394 {
395 int ret;
396 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
397 if (ret < 0)
398 deverr(dev, "Failed to enable hardware MII access");
399 return ret;
400 }
401
402 static inline int asix_get_phy_addr(struct usbnet *dev)
403 {
404 int ret = 0;
405 void *buf;
406
407 devdbg(dev, "asix_get_phy_addr()");
408
409 buf = kmalloc(2, GFP_KERNEL);
410 if (!buf)
411 goto out1;
412
413 if ((ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID,
414 0, 0, 2, buf)) < 2) {
415 deverr(dev, "Error reading PHYID register: %02x", ret);
416 goto out2;
417 }
418 devdbg(dev, "asix_get_phy_addr() returning 0x%04x", *((u16 *)buf));
419 ret = *((u8 *)buf + 1);
420 out2:
421 kfree(buf);
422 out1:
423 return ret;
424 }
425
426 static int asix_sw_reset(struct usbnet *dev, u8 flags)
427 {
428 int ret;
429
430 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
431 if (ret < 0)
432 deverr(dev,"Failed to send software reset: %02x", ret);
433
434 return ret;
435 }
436
437 static u16 asix_read_rx_ctl(struct usbnet *dev)
438 {
439 u16 ret = 0;
440 void *buf;
441
442 buf = kmalloc(2, GFP_KERNEL);
443 if (!buf)
444 goto out1;
445
446 if ((ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL,
447 0, 0, 2, buf)) < 2) {
448 deverr(dev, "Error reading RX_CTL register: %02x", ret);
449 goto out2;
450 }
451 ret = le16_to_cpu(*((u16 *)buf));
452 out2:
453 kfree(buf);
454 out1:
455 return ret;
456 }
457
458 static int asix_write_rx_ctl(struct usbnet *dev, u16 mode)
459 {
460 int ret;
461
462 devdbg(dev,"asix_write_rx_ctl() - mode = 0x%04x", mode);
463 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
464 if (ret < 0)
465 deverr(dev, "Failed to write RX_CTL mode to 0x%04x: %02x",
466 mode, ret);
467
468 return ret;
469 }
470
471 static u16 asix_read_medium_status(struct usbnet *dev)
472 {
473 u16 ret = 0;
474 void *buf;
475
476 buf = kmalloc(2, GFP_KERNEL);
477 if (!buf)
478 goto out1;
479
480 if ((ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS,
481 0, 0, 2, buf)) < 2) {
482 deverr(dev, "Error reading Medium Status register: %02x", ret);
483 goto out2;
484 }
485 ret = le16_to_cpu(*((u16 *)buf));
486 out2:
487 kfree(buf);
488 out1:
489 return ret;
490 }
491
492 static int asix_write_medium_mode(struct usbnet *dev, u16 mode)
493 {
494 int ret;
495
496 devdbg(dev,"asix_write_medium_mode() - mode = 0x%04x", mode);
497 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL);
498 if (ret < 0)
499 deverr(dev, "Failed to write Medium Mode mode to 0x%04x: %02x",
500 mode, ret);
501
502 return ret;
503 }
504
505 static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep)
506 {
507 int ret;
508
509 devdbg(dev,"asix_write_gpio() - value = 0x%04x", value);
510 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
511 if (ret < 0)
512 deverr(dev, "Failed to write GPIO value 0x%04x: %02x",
513 value, ret);
514
515 if (sleep)
516 msleep(sleep);
517
518 return ret;
519 }
520
521 /*
522 * AX88772 & AX88178 have a 16-bit RX_CTL value
523 */
524 static void asix_set_multicast(struct net_device *net)
525 {
526 struct usbnet *dev = netdev_priv(net);
527 struct asix_data *data = (struct asix_data *)&dev->data;
528 u16 rx_ctl = AX_DEFAULT_RX_CTL;
529
530 if (net->flags & IFF_PROMISC) {
531 rx_ctl |= AX_RX_CTL_PRO;
532 } else if (net->flags & IFF_ALLMULTI
533 || net->mc_count > AX_MAX_MCAST) {
534 rx_ctl |= AX_RX_CTL_AMALL;
535 } else if (net->mc_count == 0) {
536 /* just broadcast and directed */
537 } else {
538 /* We use the 20 byte dev->data
539 * for our 8 byte filter buffer
540 * to avoid allocating memory that
541 * is tricky to free later */
542 struct dev_mc_list *mc_list = net->mc_list;
543 u32 crc_bits;
544 int i;
545
546 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
547
548 /* Build the multicast hash filter. */
549 for (i = 0; i < net->mc_count; i++) {
550 crc_bits =
551 ether_crc(ETH_ALEN,
552 mc_list->dmi_addr) >> 26;
553 data->multi_filter[crc_bits >> 3] |=
554 1 << (crc_bits & 7);
555 mc_list = mc_list->next;
556 }
557
558 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
559 AX_MCAST_FILTER_SIZE, data->multi_filter);
560
561 rx_ctl |= AX_RX_CTL_AM;
562 }
563
564 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
565 }
566
567 static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc)
568 {
569 struct usbnet *dev = netdev_priv(netdev);
570 u16 res;
571
572 mutex_lock(&dev->phy_mutex);
573 asix_set_sw_mii(dev);
574 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id,
575 (__u16)loc, 2, (u16 *)&res);
576 asix_set_hw_mii(dev);
577 mutex_unlock(&dev->phy_mutex);
578
579 devdbg(dev, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x", phy_id, loc, le16_to_cpu(res & 0xffff));
580
581 return le16_to_cpu(res & 0xffff);
582 }
583
584 static void
585 asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val)
586 {
587 struct usbnet *dev = netdev_priv(netdev);
588 u16 res = cpu_to_le16(val);
589
590 devdbg(dev, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x", phy_id, loc, val);
591 mutex_lock(&dev->phy_mutex);
592 asix_set_sw_mii(dev);
593 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id,
594 (__u16)loc, 2, (u16 *)&res);
595 asix_set_hw_mii(dev);
596 mutex_unlock(&dev->phy_mutex);
597 }
598
599 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
600 static u32 asix_get_phyid(struct usbnet *dev)
601 {
602 int phy_reg;
603 u32 phy_id;
604
605 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
606 if (phy_reg < 0)
607 return 0;
608
609 phy_id = (phy_reg & 0xffff) << 16;
610
611 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
612 if (phy_reg < 0)
613 return 0;
614
615 phy_id |= (phy_reg & 0xffff);
616
617 return phy_id;
618 }
619
620 static void
621 asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
622 {
623 struct usbnet *dev = netdev_priv(net);
624 u8 opt;
625
626 if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) {
627 wolinfo->supported = 0;
628 wolinfo->wolopts = 0;
629 return;
630 }
631 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
632 wolinfo->wolopts = 0;
633 if (opt & AX_MONITOR_MODE) {
634 if (opt & AX_MONITOR_LINK)
635 wolinfo->wolopts |= WAKE_PHY;
636 if (opt & AX_MONITOR_MAGIC)
637 wolinfo->wolopts |= WAKE_MAGIC;
638 }
639 }
640
641 static int
642 asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
643 {
644 struct usbnet *dev = netdev_priv(net);
645 u8 opt = 0;
646 u8 buf[1];
647
648 if (wolinfo->wolopts & WAKE_PHY)
649 opt |= AX_MONITOR_LINK;
650 if (wolinfo->wolopts & WAKE_MAGIC)
651 opt |= AX_MONITOR_MAGIC;
652 if (opt != 0)
653 opt |= AX_MONITOR_MODE;
654
655 if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE,
656 opt, 0, 0, &buf) < 0)
657 return -EINVAL;
658
659 return 0;
660 }
661
662 static int asix_get_eeprom_len(struct net_device *net)
663 {
664 struct usbnet *dev = netdev_priv(net);
665 struct asix_data *data = (struct asix_data *)&dev->data;
666
667 return data->eeprom_len;
668 }
669
670 static int asix_get_eeprom(struct net_device *net,
671 struct ethtool_eeprom *eeprom, u8 *data)
672 {
673 struct usbnet *dev = netdev_priv(net);
674 u16 *ebuf = (u16 *)data;
675 int i;
676
677 /* Crude hack to ensure that we don't overwrite memory
678 * if an odd length is supplied
679 */
680 if (eeprom->len % 2)
681 return -EINVAL;
682
683 eeprom->magic = AX_EEPROM_MAGIC;
684
685 /* ax8817x returns 2 bytes from eeprom on read */
686 for (i=0; i < eeprom->len / 2; i++) {
687 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
688 eeprom->offset + i, 0, 2, &ebuf[i]) < 0)
689 return -EINVAL;
690 }
691 return 0;
692 }
693
694 static void asix_get_drvinfo (struct net_device *net,
695 struct ethtool_drvinfo *info)
696 {
697 struct usbnet *dev = netdev_priv(net);
698 struct asix_data *data = (struct asix_data *)&dev->data;
699
700 /* Inherit standard device info */
701 usbnet_get_drvinfo(net, info);
702 strncpy (info->driver, driver_name, sizeof info->driver);
703 strncpy (info->version, DRIVER_VERSION, sizeof info->version);
704 info->eedump_len = data->eeprom_len;
705 }
706
707 static u32 asix_get_link(struct net_device *net)
708 {
709 struct usbnet *dev = netdev_priv(net);
710
711 return mii_link_ok(&dev->mii);
712 }
713
714 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
715 {
716 struct usbnet *dev = netdev_priv(net);
717
718 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
719 }
720
721 /* We need to override some ethtool_ops so we require our
722 own structure so we don't interfere with other usbnet
723 devices that may be connected at the same time. */
724 static struct ethtool_ops ax88172_ethtool_ops = {
725 .get_drvinfo = asix_get_drvinfo,
726 .get_link = asix_get_link,
727 .get_msglevel = usbnet_get_msglevel,
728 .set_msglevel = usbnet_set_msglevel,
729 .get_wol = asix_get_wol,
730 .set_wol = asix_set_wol,
731 .get_eeprom_len = asix_get_eeprom_len,
732 .get_eeprom = asix_get_eeprom,
733 .get_settings = usbnet_get_settings,
734 .set_settings = usbnet_set_settings,
735 .nway_reset = usbnet_nway_reset,
736 };
737
738 static void ax88172_set_multicast(struct net_device *net)
739 {
740 struct usbnet *dev = netdev_priv(net);
741 struct asix_data *data = (struct asix_data *)&dev->data;
742 u8 rx_ctl = 0x8c;
743
744 if (net->flags & IFF_PROMISC) {
745 rx_ctl |= 0x01;
746 } else if (net->flags & IFF_ALLMULTI
747 || net->mc_count > AX_MAX_MCAST) {
748 rx_ctl |= 0x02;
749 } else if (net->mc_count == 0) {
750 /* just broadcast and directed */
751 } else {
752 /* We use the 20 byte dev->data
753 * for our 8 byte filter buffer
754 * to avoid allocating memory that
755 * is tricky to free later */
756 struct dev_mc_list *mc_list = net->mc_list;
757 u32 crc_bits;
758 int i;
759
760 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
761
762 /* Build the multicast hash filter. */
763 for (i = 0; i < net->mc_count; i++) {
764 crc_bits =
765 ether_crc(ETH_ALEN,
766 mc_list->dmi_addr) >> 26;
767 data->multi_filter[crc_bits >> 3] |=
768 1 << (crc_bits & 7);
769 mc_list = mc_list->next;
770 }
771
772 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
773 AX_MCAST_FILTER_SIZE, data->multi_filter);
774
775 rx_ctl |= 0x10;
776 }
777
778 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
779 }
780
781 static int ax88172_link_reset(struct usbnet *dev)
782 {
783 u8 mode;
784 struct ethtool_cmd ecmd;
785
786 mii_check_media(&dev->mii, 1, 1);
787 mii_ethtool_gset(&dev->mii, &ecmd);
788 mode = AX88172_MEDIUM_DEFAULT;
789
790 if (ecmd.duplex != DUPLEX_FULL)
791 mode |= ~AX88172_MEDIUM_FD;
792
793 devdbg(dev, "ax88172_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode);
794
795 asix_write_medium_mode(dev, mode);
796
797 return 0;
798 }
799
800 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
801 {
802 int ret = 0;
803 void *buf;
804 int i;
805 unsigned long gpio_bits = dev->driver_info->data;
806 struct asix_data *data = (struct asix_data *)&dev->data;
807
808 data->eeprom_len = AX88172_EEPROM_LEN;
809
810 usbnet_get_endpoints(dev,intf);
811
812 buf = kmalloc(ETH_ALEN, GFP_KERNEL);
813 if(!buf) {
814 ret = -ENOMEM;
815 goto out1;
816 }
817
818 /* Toggle the GPIOs in a manufacturer/model specific way */
819 for (i = 2; i >= 0; i--) {
820 if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
821 (gpio_bits >> (i * 8)) & 0xff, 0, 0,
822 buf)) < 0)
823 goto out2;
824 msleep(5);
825 }
826
827 if ((ret = asix_write_rx_ctl(dev, 0x80)) < 0)
828 goto out2;
829
830 /* Get the MAC address */
831 memset(buf, 0, ETH_ALEN);
832 if ((ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
833 0, 0, 6, buf)) < 0) {
834 dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
835 goto out2;
836 }
837 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
838
839 /* Initialize MII structure */
840 dev->mii.dev = dev->net;
841 dev->mii.mdio_read = asix_mdio_read;
842 dev->mii.mdio_write = asix_mdio_write;
843 dev->mii.phy_id_mask = 0x3f;
844 dev->mii.reg_num_mask = 0x1f;
845 dev->mii.phy_id = asix_get_phy_addr(dev);
846 dev->net->do_ioctl = asix_ioctl;
847
848 dev->net->set_multicast_list = ax88172_set_multicast;
849 dev->net->ethtool_ops = &ax88172_ethtool_ops;
850
851 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
852 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
853 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
854 mii_nway_restart(&dev->mii);
855
856 return 0;
857 out2:
858 kfree(buf);
859 out1:
860 return ret;
861 }
862
863 static struct ethtool_ops ax88772_ethtool_ops = {
864 .get_drvinfo = asix_get_drvinfo,
865 .get_link = asix_get_link,
866 .get_msglevel = usbnet_get_msglevel,
867 .set_msglevel = usbnet_set_msglevel,
868 .get_wol = asix_get_wol,
869 .set_wol = asix_set_wol,
870 .get_eeprom_len = asix_get_eeprom_len,
871 .get_eeprom = asix_get_eeprom,
872 .get_settings = usbnet_get_settings,
873 .set_settings = usbnet_set_settings,
874 .nway_reset = usbnet_nway_reset,
875 };
876
877 static int ax88772_link_reset(struct usbnet *dev)
878 {
879 u16 mode;
880 struct ethtool_cmd ecmd;
881
882 mii_check_media(&dev->mii, 1, 1);
883 mii_ethtool_gset(&dev->mii, &ecmd);
884 mode = AX88772_MEDIUM_DEFAULT;
885
886 if (ecmd.speed != SPEED_100)
887 mode &= ~AX_MEDIUM_PS;
888
889 if (ecmd.duplex != DUPLEX_FULL)
890 mode &= ~AX_MEDIUM_FD;
891
892 devdbg(dev, "ax88772_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode);
893
894 asix_write_medium_mode(dev, mode);
895
896 return 0;
897 }
898
899 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
900 {
901 int ret, embd_phy;
902 void *buf;
903 u16 rx_ctl;
904 struct asix_data *data = (struct asix_data *)&dev->data;
905 u32 phyid;
906
907 data->eeprom_len = AX88772_EEPROM_LEN;
908
909 usbnet_get_endpoints(dev,intf);
910
911 buf = kmalloc(6, GFP_KERNEL);
912 if(!buf) {
913 dbg ("Cannot allocate memory for buffer");
914 ret = -ENOMEM;
915 goto out1;
916 }
917
918 if ((ret = asix_write_gpio(dev,
919 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5)) < 0)
920 goto out2;
921
922 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
923 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
924 if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
925 embd_phy, 0, 0, buf)) < 0) {
926 dbg("Select PHY #1 failed: %d", ret);
927 goto out2;
928 }
929
930 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL)) < 0)
931 goto out2;
932
933 msleep(150);
934 if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0)
935 goto out2;
936
937 msleep(150);
938 if (embd_phy) {
939 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL)) < 0)
940 goto out2;
941 }
942 else {
943 if ((ret = asix_sw_reset(dev, AX_SWRESET_PRTE)) < 0)
944 goto out2;
945 }
946
947 msleep(150);
948 rx_ctl = asix_read_rx_ctl(dev);
949 dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
950 if ((ret = asix_write_rx_ctl(dev, 0x0000)) < 0)
951 goto out2;
952
953 rx_ctl = asix_read_rx_ctl(dev);
954 dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
955
956 /* Get the MAC address */
957 memset(buf, 0, ETH_ALEN);
958 if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
959 0, 0, ETH_ALEN, buf)) < 0) {
960 dbg("Failed to read MAC address: %d", ret);
961 goto out2;
962 }
963 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
964
965 /* Initialize MII structure */
966 dev->mii.dev = dev->net;
967 dev->mii.mdio_read = asix_mdio_read;
968 dev->mii.mdio_write = asix_mdio_write;
969 dev->mii.phy_id_mask = 0x1f;
970 dev->mii.reg_num_mask = 0x1f;
971 dev->net->do_ioctl = asix_ioctl;
972 dev->mii.phy_id = asix_get_phy_addr(dev);
973
974 phyid = asix_get_phyid(dev);
975 dbg("PHYID=0x%08x", phyid);
976
977 if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0)
978 goto out2;
979
980 msleep(150);
981
982 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0)
983 goto out2;
984
985 msleep(150);
986
987 dev->net->set_multicast_list = asix_set_multicast;
988 dev->net->ethtool_ops = &ax88772_ethtool_ops;
989
990 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
991 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
992 ADVERTISE_ALL | ADVERTISE_CSMA);
993 mii_nway_restart(&dev->mii);
994
995 if ((ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT)) < 0)
996 goto out2;
997
998 if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
999 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
1000 AX88772_IPG2_DEFAULT, 0, buf)) < 0) {
1001 dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
1002 goto out2;
1003 }
1004
1005 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
1006 if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0)
1007 goto out2;
1008
1009 rx_ctl = asix_read_rx_ctl(dev);
1010 dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
1011
1012 rx_ctl = asix_read_medium_status(dev);
1013 dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
1014
1015 kfree(buf);
1016
1017 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1018 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1019 /* hard_mtu is still the default - the device does not support
1020 jumbo eth frames */
1021 dev->rx_urb_size = 2048;
1022 }
1023
1024 return 0;
1025
1026 out2:
1027 kfree(buf);
1028 out1:
1029 return ret;
1030 }
1031
1032 static struct ethtool_ops ax88178_ethtool_ops = {
1033 .get_drvinfo = asix_get_drvinfo,
1034 .get_link = asix_get_link,
1035 .get_msglevel = usbnet_get_msglevel,
1036 .set_msglevel = usbnet_set_msglevel,
1037 .get_wol = asix_get_wol,
1038 .set_wol = asix_set_wol,
1039 .get_eeprom_len = asix_get_eeprom_len,
1040 .get_eeprom = asix_get_eeprom,
1041 .get_settings = usbnet_get_settings,
1042 .set_settings = usbnet_set_settings,
1043 .nway_reset = usbnet_nway_reset,
1044 };
1045
1046 static int marvell_phy_init(struct usbnet *dev)
1047 {
1048 struct asix_data *data = (struct asix_data *)&dev->data;
1049 u16 reg;
1050
1051 devdbg(dev,"marvell_phy_init()");
1052
1053 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
1054 devdbg(dev,"MII_MARVELL_STATUS = 0x%04x", reg);
1055
1056 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
1057 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
1058
1059 if (data->ledmode) {
1060 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1061 MII_MARVELL_LED_CTRL);
1062 devdbg(dev,"MII_MARVELL_LED_CTRL (1) = 0x%04x", reg);
1063
1064 reg &= 0xf8ff;
1065 reg |= (1 + 0x0100);
1066 asix_mdio_write(dev->net, dev->mii.phy_id,
1067 MII_MARVELL_LED_CTRL, reg);
1068
1069 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1070 MII_MARVELL_LED_CTRL);
1071 devdbg(dev,"MII_MARVELL_LED_CTRL (2) = 0x%04x", reg);
1072 reg &= 0xfc0f;
1073 }
1074
1075 return 0;
1076 }
1077
1078 static int marvell_led_status(struct usbnet *dev, u16 speed)
1079 {
1080 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
1081
1082 devdbg(dev, "marvell_led_status() read 0x%04x", reg);
1083
1084 /* Clear out the center LED bits - 0x03F0 */
1085 reg &= 0xfc0f;
1086
1087 switch (speed) {
1088 case SPEED_1000:
1089 reg |= 0x03e0;
1090 break;
1091 case SPEED_100:
1092 reg |= 0x03b0;
1093 break;
1094 default:
1095 reg |= 0x02f0;
1096 }
1097
1098 devdbg(dev, "marvell_led_status() writing 0x%04x", reg);
1099 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
1100
1101 return 0;
1102 }
1103
1104 static int ax88178_link_reset(struct usbnet *dev)
1105 {
1106 u16 mode;
1107 struct ethtool_cmd ecmd;
1108 struct asix_data *data = (struct asix_data *)&dev->data;
1109
1110 devdbg(dev,"ax88178_link_reset()");
1111
1112 mii_check_media(&dev->mii, 1, 1);
1113 mii_ethtool_gset(&dev->mii, &ecmd);
1114 mode = AX88178_MEDIUM_DEFAULT;
1115
1116 if (ecmd.speed == SPEED_1000)
1117 mode |= AX_MEDIUM_GM | AX_MEDIUM_ENCK;
1118 else if (ecmd.speed == SPEED_100)
1119 mode |= AX_MEDIUM_PS;
1120 else
1121 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1122
1123 if (ecmd.duplex == DUPLEX_FULL)
1124 mode |= AX_MEDIUM_FD;
1125 else
1126 mode &= ~AX_MEDIUM_FD;
1127
1128 devdbg(dev, "ax88178_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode);
1129
1130 asix_write_medium_mode(dev, mode);
1131
1132 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1133 marvell_led_status(dev, ecmd.speed);
1134
1135 return 0;
1136 }
1137
1138 static void ax88178_set_mfb(struct usbnet *dev)
1139 {
1140 u16 mfb = AX_RX_CTL_MFB_16384;
1141 u16 rxctl;
1142 u16 medium;
1143 int old_rx_urb_size = dev->rx_urb_size;
1144
1145 if (dev->hard_mtu < 2048) {
1146 dev->rx_urb_size = 2048;
1147 mfb = AX_RX_CTL_MFB_2048;
1148 } else if (dev->hard_mtu < 4096) {
1149 dev->rx_urb_size = 4096;
1150 mfb = AX_RX_CTL_MFB_4096;
1151 } else if (dev->hard_mtu < 8192) {
1152 dev->rx_urb_size = 8192;
1153 mfb = AX_RX_CTL_MFB_8192;
1154 } else if (dev->hard_mtu < 16384) {
1155 dev->rx_urb_size = 16384;
1156 mfb = AX_RX_CTL_MFB_16384;
1157 }
1158
1159 rxctl = asix_read_rx_ctl(dev);
1160 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
1161
1162 medium = asix_read_medium_status(dev);
1163 if (dev->net->mtu > 1500)
1164 medium |= AX_MEDIUM_JFE;
1165 else
1166 medium &= ~AX_MEDIUM_JFE;
1167 asix_write_medium_mode(dev, medium);
1168
1169 if (dev->rx_urb_size > old_rx_urb_size)
1170 usbnet_unlink_rx_urbs(dev);
1171 }
1172
1173 static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1174 {
1175 struct usbnet *dev = netdev_priv(net);
1176 int ll_mtu = new_mtu + net->hard_header_len + 4;
1177
1178 devdbg(dev, "ax88178_change_mtu() new_mtu=%d", new_mtu);
1179
1180 if (new_mtu <= 0 || ll_mtu > 16384)
1181 return -EINVAL;
1182
1183 if ((ll_mtu % dev->maxpacket) == 0)
1184 return -EDOM;
1185
1186 net->mtu = new_mtu;
1187 dev->hard_mtu = net->mtu + net->hard_header_len;
1188 ax88178_set_mfb(dev);
1189
1190 return 0;
1191 }
1192
1193 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1194 {
1195 struct asix_data *data = (struct asix_data *)&dev->data;
1196 int ret;
1197 void *buf;
1198 u16 eeprom;
1199 int gpio0 = 0;
1200 u32 phyid;
1201
1202 usbnet_get_endpoints(dev,intf);
1203
1204 buf = kmalloc(6, GFP_KERNEL);
1205 if(!buf) {
1206 dbg ("Cannot allocate memory for buffer");
1207 ret = -ENOMEM;
1208 goto out1;
1209 }
1210
1211 eeprom = 0;
1212 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &eeprom);
1213 dbg("GPIO Status: 0x%04x", eeprom);
1214
1215 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
1216 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
1217 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
1218
1219 dbg("EEPROM index 0x17 is 0x%04x", eeprom);
1220
1221 if (eeprom == 0xffff) {
1222 data->phymode = PHY_MODE_MARVELL;
1223 data->ledmode = 0;
1224 gpio0 = 1;
1225 } else {
1226 data->phymode = eeprom & 7;
1227 data->ledmode = eeprom >> 8;
1228 gpio0 = (eeprom & 0x80) ? 0 : 1;
1229 }
1230 dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
1231
1232 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
1233 if ((eeprom >> 8) != 1) {
1234 asix_write_gpio(dev, 0x003c, 30);
1235 asix_write_gpio(dev, 0x001c, 300);
1236 asix_write_gpio(dev, 0x003c, 30);
1237 } else {
1238 dbg("gpio phymode == 1 path");
1239 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
1240 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
1241 }
1242
1243 asix_sw_reset(dev, 0);
1244 msleep(150);
1245
1246 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
1247 msleep(150);
1248
1249 asix_write_rx_ctl(dev, 0);
1250
1251 /* Get the MAC address */
1252 memset(buf, 0, ETH_ALEN);
1253 if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
1254 0, 0, ETH_ALEN, buf)) < 0) {
1255 dbg("Failed to read MAC address: %d", ret);
1256 goto out2;
1257 }
1258 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
1259
1260 /* Initialize MII structure */
1261 dev->mii.dev = dev->net;
1262 dev->mii.mdio_read = asix_mdio_read;
1263 dev->mii.mdio_write = asix_mdio_write;
1264 dev->mii.phy_id_mask = 0x1f;
1265 dev->mii.reg_num_mask = 0xff;
1266 dev->mii.supports_gmii = 1;
1267 dev->net->do_ioctl = asix_ioctl;
1268 dev->mii.phy_id = asix_get_phy_addr(dev);
1269 dev->net->set_multicast_list = asix_set_multicast;
1270 dev->net->ethtool_ops = &ax88178_ethtool_ops;
1271 dev->net->change_mtu = &ax88178_change_mtu;
1272
1273 phyid = asix_get_phyid(dev);
1274 dbg("PHYID=0x%08x", phyid);
1275
1276 if (data->phymode == PHY_MODE_MARVELL) {
1277 marvell_phy_init(dev);
1278 msleep(60);
1279 }
1280
1281 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
1282 BMCR_RESET | BMCR_ANENABLE);
1283 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1284 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1285 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1286 ADVERTISE_1000FULL);
1287
1288 mii_nway_restart(&dev->mii);
1289
1290 if ((ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT)) < 0)
1291 goto out2;
1292
1293 if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0)
1294 goto out2;
1295
1296 kfree(buf);
1297
1298 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1299 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1300 /* hard_mtu is still the default - the device does not support
1301 jumbo eth frames */
1302 dev->rx_urb_size = 2048;
1303 }
1304
1305 return 0;
1306
1307 out2:
1308 kfree(buf);
1309 out1:
1310 return ret;
1311 }
1312
1313 static const struct driver_info ax8817x_info = {
1314 .description = "ASIX AX8817x USB 2.0 Ethernet",
1315 .bind = ax88172_bind,
1316 .status = asix_status,
1317 .link_reset = ax88172_link_reset,
1318 .reset = ax88172_link_reset,
1319 .flags = FLAG_ETHER,
1320 .data = 0x00130103,
1321 };
1322
1323 static const struct driver_info dlink_dub_e100_info = {
1324 .description = "DLink DUB-E100 USB Ethernet",
1325 .bind = ax88172_bind,
1326 .status = asix_status,
1327 .link_reset = ax88172_link_reset,
1328 .reset = ax88172_link_reset,
1329 .flags = FLAG_ETHER,
1330 .data = 0x009f9d9f,
1331 };
1332
1333 static const struct driver_info netgear_fa120_info = {
1334 .description = "Netgear FA-120 USB Ethernet",
1335 .bind = ax88172_bind,
1336 .status = asix_status,
1337 .link_reset = ax88172_link_reset,
1338 .reset = ax88172_link_reset,
1339 .flags = FLAG_ETHER,
1340 .data = 0x00130103,
1341 };
1342
1343 static const struct driver_info hawking_uf200_info = {
1344 .description = "Hawking UF200 USB Ethernet",
1345 .bind = ax88172_bind,
1346 .status = asix_status,
1347 .link_reset = ax88172_link_reset,
1348 .reset = ax88172_link_reset,
1349 .flags = FLAG_ETHER,
1350 .data = 0x001f1d1f,
1351 };
1352
1353 static const struct driver_info ax88772_info = {
1354 .description = "ASIX AX88772 USB 2.0 Ethernet",
1355 .bind = ax88772_bind,
1356 .status = asix_status,
1357 .link_reset = ax88772_link_reset,
1358 .reset = ax88772_link_reset,
1359 .flags = FLAG_ETHER | FLAG_FRAMING_AX,
1360 .rx_fixup = asix_rx_fixup,
1361 .tx_fixup = asix_tx_fixup,
1362 };
1363
1364 static const struct driver_info ax88178_info = {
1365 .description = "ASIX AX88178 USB 2.0 Ethernet",
1366 .bind = ax88178_bind,
1367 .status = asix_status,
1368 .link_reset = ax88178_link_reset,
1369 .reset = ax88178_link_reset,
1370 .flags = FLAG_ETHER | FLAG_FRAMING_AX,
1371 .rx_fixup = asix_rx_fixup,
1372 .tx_fixup = asix_tx_fixup,
1373 };
1374
1375 static const struct usb_device_id products [] = {
1376 {
1377 // Linksys USB200M
1378 USB_DEVICE (0x077b, 0x2226),
1379 .driver_info = (unsigned long) &ax8817x_info,
1380 }, {
1381 // Netgear FA120
1382 USB_DEVICE (0x0846, 0x1040),
1383 .driver_info = (unsigned long) &netgear_fa120_info,
1384 }, {
1385 // DLink DUB-E100
1386 USB_DEVICE (0x2001, 0x1a00),
1387 .driver_info = (unsigned long) &dlink_dub_e100_info,
1388 }, {
1389 // Intellinet, ST Lab USB Ethernet
1390 USB_DEVICE (0x0b95, 0x1720),
1391 .driver_info = (unsigned long) &ax8817x_info,
1392 }, {
1393 // Hawking UF200, TrendNet TU2-ET100
1394 USB_DEVICE (0x07b8, 0x420a),
1395 .driver_info = (unsigned long) &hawking_uf200_info,
1396 }, {
1397 // Billionton Systems, USB2AR
1398 USB_DEVICE (0x08dd, 0x90ff),
1399 .driver_info = (unsigned long) &ax8817x_info,
1400 }, {
1401 // ATEN UC210T
1402 USB_DEVICE (0x0557, 0x2009),
1403 .driver_info = (unsigned long) &ax8817x_info,
1404 }, {
1405 // Buffalo LUA-U2-KTX
1406 USB_DEVICE (0x0411, 0x003d),
1407 .driver_info = (unsigned long) &ax8817x_info,
1408 }, {
1409 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1410 USB_DEVICE (0x6189, 0x182d),
1411 .driver_info = (unsigned long) &ax8817x_info,
1412 }, {
1413 // corega FEther USB2-TX
1414 USB_DEVICE (0x07aa, 0x0017),
1415 .driver_info = (unsigned long) &ax8817x_info,
1416 }, {
1417 // Surecom EP-1427X-2
1418 USB_DEVICE (0x1189, 0x0893),
1419 .driver_info = (unsigned long) &ax8817x_info,
1420 }, {
1421 // goodway corp usb gwusb2e
1422 USB_DEVICE (0x1631, 0x6200),
1423 .driver_info = (unsigned long) &ax8817x_info,
1424 }, {
1425 // ASIX AX88772 10/100
1426 USB_DEVICE (0x0b95, 0x7720),
1427 .driver_info = (unsigned long) &ax88772_info,
1428 }, {
1429 // ASIX AX88178 10/100/1000
1430 USB_DEVICE (0x0b95, 0x1780),
1431 .driver_info = (unsigned long) &ax88178_info,
1432 }, {
1433 // Linksys USB200M Rev 2
1434 USB_DEVICE (0x13b1, 0x0018),
1435 .driver_info = (unsigned long) &ax88772_info,
1436 }, {
1437 // 0Q0 cable ethernet
1438 USB_DEVICE (0x1557, 0x7720),
1439 .driver_info = (unsigned long) &ax88772_info,
1440 }, {
1441 // DLink DUB-E100 H/W Ver B1
1442 USB_DEVICE (0x07d1, 0x3c05),
1443 .driver_info = (unsigned long) &ax88772_info,
1444 }, {
1445 // DLink DUB-E100 H/W Ver B1 Alternate
1446 USB_DEVICE (0x2001, 0x3c05),
1447 .driver_info = (unsigned long) &ax88772_info,
1448 }, {
1449 // Linksys USB1000
1450 USB_DEVICE (0x1737, 0x0039),
1451 .driver_info = (unsigned long) &ax88178_info,
1452 },
1453 { }, // END
1454 };
1455 MODULE_DEVICE_TABLE(usb, products);
1456
1457 static struct usb_driver asix_driver = {
1458 .name = "asix",
1459 .id_table = products,
1460 .probe = usbnet_probe,
1461 .suspend = usbnet_suspend,
1462 .resume = usbnet_resume,
1463 .disconnect = usbnet_disconnect,
1464 };
1465
1466 static int __init asix_init(void)
1467 {
1468 return usb_register(&asix_driver);
1469 }
1470 module_init(asix_init);
1471
1472 static void __exit asix_exit(void)
1473 {
1474 usb_deregister(&asix_driver);
1475 }
1476 module_exit(asix_exit);
1477
1478 MODULE_AUTHOR("David Hollis");
1479 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1480 MODULE_LICENSE("GPL");
1481
CJK support for tty framebuffer vt