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net/macb: tx status is more than 8 bits now
[linux-2.6/cjktty.git] / drivers / net / ethernet / cadence / macb.c
blobcd6d431ff2b47441a810c431ecab6b1682dc37d5
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_data/macb.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_net.h>
29
30 #include "macb.h"
31
32 #define RX_BUFFER_SIZE 128
33 #define RX_RING_SIZE 512
34 #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
35
36 /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
37 #define RX_OFFSET 2
38
39 #define TX_RING_SIZE 128
40 #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
41 #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
42
43 #define TX_RING_GAP(bp) \
44 (TX_RING_SIZE - (bp)->tx_pending)
45 #define TX_BUFFS_AVAIL(bp) \
46 (((bp)->tx_tail <= (bp)->tx_head) ? \
47 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
48 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
49 #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
50
51 #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
52
53 /* minimum number of free TX descriptors before waking up TX process */
54 #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
55
56 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
57 | MACB_BIT(ISR_ROVR))
58
59 static void __macb_set_hwaddr(struct macb *bp)
60 {
61 u32 bottom;
62 u16 top;
63
64 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
65 macb_or_gem_writel(bp, SA1B, bottom);
66 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
67 macb_or_gem_writel(bp, SA1T, top);
68 }
69
70 static void __init macb_get_hwaddr(struct macb *bp)
71 {
72 u32 bottom;
73 u16 top;
74 u8 addr[6];
75
76 bottom = macb_or_gem_readl(bp, SA1B);
77 top = macb_or_gem_readl(bp, SA1T);
78
79 addr[0] = bottom & 0xff;
80 addr[1] = (bottom >> 8) & 0xff;
81 addr[2] = (bottom >> 16) & 0xff;
82 addr[3] = (bottom >> 24) & 0xff;
83 addr[4] = top & 0xff;
84 addr[5] = (top >> 8) & 0xff;
85
86 if (is_valid_ether_addr(addr)) {
87 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
88 } else {
89 netdev_info(bp->dev, "invalid hw address, using random\n");
90 eth_hw_addr_random(bp->dev);
91 }
92 }
93
94 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
95 {
96 struct macb *bp = bus->priv;
97 int value;
98
99 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
100 | MACB_BF(RW, MACB_MAN_READ)
101 | MACB_BF(PHYA, mii_id)
102 | MACB_BF(REGA, regnum)
103 | MACB_BF(CODE, MACB_MAN_CODE)));
104
105 /* wait for end of transfer */
106 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
107 cpu_relax();
108
109 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
110
111 return value;
112 }
113
114 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
115 u16 value)
116 {
117 struct macb *bp = bus->priv;
118
119 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
120 | MACB_BF(RW, MACB_MAN_WRITE)
121 | MACB_BF(PHYA, mii_id)
122 | MACB_BF(REGA, regnum)
123 | MACB_BF(CODE, MACB_MAN_CODE)
124 | MACB_BF(DATA, value)));
125
126 /* wait for end of transfer */
127 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
128 cpu_relax();
129
130 return 0;
131 }
132
133 static int macb_mdio_reset(struct mii_bus *bus)
134 {
135 return 0;
136 }
137
138 static void macb_handle_link_change(struct net_device *dev)
139 {
140 struct macb *bp = netdev_priv(dev);
141 struct phy_device *phydev = bp->phy_dev;
142 unsigned long flags;
143
144 int status_change = 0;
145
146 spin_lock_irqsave(&bp->lock, flags);
147
148 if (phydev->link) {
149 if ((bp->speed != phydev->speed) ||
150 (bp->duplex != phydev->duplex)) {
151 u32 reg;
152
153 reg = macb_readl(bp, NCFGR);
154 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
155 if (macb_is_gem(bp))
156 reg &= ~GEM_BIT(GBE);
157
158 if (phydev->duplex)
159 reg |= MACB_BIT(FD);
160 if (phydev->speed == SPEED_100)
161 reg |= MACB_BIT(SPD);
162 if (phydev->speed == SPEED_1000)
163 reg |= GEM_BIT(GBE);
164
165 macb_or_gem_writel(bp, NCFGR, reg);
166
167 bp->speed = phydev->speed;
168 bp->duplex = phydev->duplex;
169 status_change = 1;
170 }
171 }
172
173 if (phydev->link != bp->link) {
174 if (!phydev->link) {
175 bp->speed = 0;
176 bp->duplex = -1;
177 }
178 bp->link = phydev->link;
179
180 status_change = 1;
181 }
182
183 spin_unlock_irqrestore(&bp->lock, flags);
184
185 if (status_change) {
186 if (phydev->link) {
187 netif_carrier_on(dev);
188 netdev_info(dev, "link up (%d/%s)\n",
189 phydev->speed,
190 phydev->duplex == DUPLEX_FULL ?
191 "Full" : "Half");
192 } else {
193 netif_carrier_off(dev);
194 netdev_info(dev, "link down\n");
195 }
196 }
197 }
198
199 /* based on au1000_eth. c*/
200 static int macb_mii_probe(struct net_device *dev)
201 {
202 struct macb *bp = netdev_priv(dev);
203 struct phy_device *phydev;
204 int ret;
205
206 phydev = phy_find_first(bp->mii_bus);
207 if (!phydev) {
208 netdev_err(dev, "no PHY found\n");
209 return -1;
210 }
211
212 /* TODO : add pin_irq */
213
214 /* attach the mac to the phy */
215 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
216 bp->phy_interface);
217 if (ret) {
218 netdev_err(dev, "Could not attach to PHY\n");
219 return ret;
220 }
221
222 /* mask with MAC supported features */
223 if (macb_is_gem(bp))
224 phydev->supported &= PHY_GBIT_FEATURES;
225 else
226 phydev->supported &= PHY_BASIC_FEATURES;
227
228 phydev->advertising = phydev->supported;
229
230 bp->link = 0;
231 bp->speed = 0;
232 bp->duplex = -1;
233 bp->phy_dev = phydev;
234
235 return 0;
236 }
237
238 int macb_mii_init(struct macb *bp)
239 {
240 struct macb_platform_data *pdata;
241 int err = -ENXIO, i;
242
243 /* Enable management port */
244 macb_writel(bp, NCR, MACB_BIT(MPE));
245
246 bp->mii_bus = mdiobus_alloc();
247 if (bp->mii_bus == NULL) {
248 err = -ENOMEM;
249 goto err_out;
250 }
251
252 bp->mii_bus->name = "MACB_mii_bus";
253 bp->mii_bus->read = &macb_mdio_read;
254 bp->mii_bus->write = &macb_mdio_write;
255 bp->mii_bus->reset = &macb_mdio_reset;
256 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
257 bp->pdev->name, bp->pdev->id);
258 bp->mii_bus->priv = bp;
259 bp->mii_bus->parent = &bp->dev->dev;
260 pdata = bp->pdev->dev.platform_data;
261
262 if (pdata)
263 bp->mii_bus->phy_mask = pdata->phy_mask;
264
265 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
266 if (!bp->mii_bus->irq) {
267 err = -ENOMEM;
268 goto err_out_free_mdiobus;
269 }
270
271 for (i = 0; i < PHY_MAX_ADDR; i++)
272 bp->mii_bus->irq[i] = PHY_POLL;
273
274 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
275
276 if (mdiobus_register(bp->mii_bus))
277 goto err_out_free_mdio_irq;
278
279 if (macb_mii_probe(bp->dev) != 0) {
280 goto err_out_unregister_bus;
281 }
282
283 return 0;
284
285 err_out_unregister_bus:
286 mdiobus_unregister(bp->mii_bus);
287 err_out_free_mdio_irq:
288 kfree(bp->mii_bus->irq);
289 err_out_free_mdiobus:
290 mdiobus_free(bp->mii_bus);
291 err_out:
292 return err;
293 }
294 EXPORT_SYMBOL_GPL(macb_mii_init);
295
296 static void macb_update_stats(struct macb *bp)
297 {
298 u32 __iomem *reg = bp->regs + MACB_PFR;
299 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
300 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
301
302 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
303
304 for(; p < end; p++, reg++)
305 *p += __raw_readl(reg);
306 }
307
308 static void macb_tx(struct macb *bp)
309 {
310 unsigned int tail;
311 unsigned int head;
312 u32 status;
313
314 status = macb_readl(bp, TSR);
315 macb_writel(bp, TSR, status);
316
317 netdev_vdbg(bp->dev, "macb_tx status = 0x%03lx\n", (unsigned long)status);
318
319 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
320 int i;
321 netdev_err(bp->dev, "TX %s, resetting buffers\n",
322 status & MACB_BIT(UND) ?
323 "underrun" : "retry limit exceeded");
324
325 /* Transfer ongoing, disable transmitter, to avoid confusion */
326 if (status & MACB_BIT(TGO))
327 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
328
329 head = bp->tx_head;
330
331 /*Mark all the buffer as used to avoid sending a lost buffer*/
332 for (i = 0; i < TX_RING_SIZE; i++)
333 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
334
335 /* Add wrap bit */
336 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
337
338 /* free transmit buffer in upper layer*/
339 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
340 struct ring_info *rp = &bp->tx_skb[tail];
341 struct sk_buff *skb = rp->skb;
342
343 BUG_ON(skb == NULL);
344
345 rmb();
346
347 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
348 DMA_TO_DEVICE);
349 rp->skb = NULL;
350 dev_kfree_skb_irq(skb);
351 }
352
353 bp->tx_head = bp->tx_tail = 0;
354
355 /* Enable the transmitter again */
356 if (status & MACB_BIT(TGO))
357 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
358 }
359
360 if (!(status & MACB_BIT(COMP)))
361 /*
362 * This may happen when a buffer becomes complete
363 * between reading the ISR and scanning the
364 * descriptors. Nothing to worry about.
365 */
366 return;
367
368 head = bp->tx_head;
369 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
370 struct ring_info *rp = &bp->tx_skb[tail];
371 struct sk_buff *skb = rp->skb;
372 u32 bufstat;
373
374 BUG_ON(skb == NULL);
375
376 /* Make hw descriptor updates visible to CPU */
377 rmb();
378
379 bufstat = bp->tx_ring[tail].ctrl;
380
381 if (!(bufstat & MACB_BIT(TX_USED)))
382 break;
383
384 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
385 tail, skb->data);
386 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
387 DMA_TO_DEVICE);
388 bp->stats.tx_packets++;
389 bp->stats.tx_bytes += skb->len;
390 rp->skb = NULL;
391 dev_kfree_skb_irq(skb);
392 }
393
394 bp->tx_tail = tail;
395 if (netif_queue_stopped(bp->dev) &&
396 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
397 netif_wake_queue(bp->dev);
398 }
399
400 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
401 unsigned int last_frag)
402 {
403 unsigned int len;
404 unsigned int frag;
405 unsigned int offset = 0;
406 struct sk_buff *skb;
407
408 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
409
410 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
411 first_frag, last_frag, len);
412
413 skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET);
414 if (!skb) {
415 bp->stats.rx_dropped++;
416 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
417 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
418 if (frag == last_frag)
419 break;
420 }
421
422 /* Make descriptor updates visible to hardware */
423 wmb();
424
425 return 1;
426 }
427
428 skb_reserve(skb, RX_OFFSET);
429 skb_checksum_none_assert(skb);
430 skb_put(skb, len);
431
432 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
433 unsigned int frag_len = RX_BUFFER_SIZE;
434
435 if (offset + frag_len > len) {
436 BUG_ON(frag != last_frag);
437 frag_len = len - offset;
438 }
439 skb_copy_to_linear_data_offset(skb, offset,
440 (bp->rx_buffers +
441 (RX_BUFFER_SIZE * frag)),
442 frag_len);
443 offset += RX_BUFFER_SIZE;
444 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
445
446 if (frag == last_frag)
447 break;
448 }
449
450 /* Make descriptor updates visible to hardware */
451 wmb();
452
453 skb->protocol = eth_type_trans(skb, bp->dev);
454
455 bp->stats.rx_packets++;
456 bp->stats.rx_bytes += len;
457 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
458 skb->len, skb->csum);
459 netif_receive_skb(skb);
460
461 return 0;
462 }
463
464 /* Mark DMA descriptors from begin up to and not including end as unused */
465 static void discard_partial_frame(struct macb *bp, unsigned int begin,
466 unsigned int end)
467 {
468 unsigned int frag;
469
470 for (frag = begin; frag != end; frag = NEXT_RX(frag))
471 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
472
473 /* Make descriptor updates visible to hardware */
474 wmb();
475
476 /*
477 * When this happens, the hardware stats registers for
478 * whatever caused this is updated, so we don't have to record
479 * anything.
480 */
481 }
482
483 static int macb_rx(struct macb *bp, int budget)
484 {
485 int received = 0;
486 unsigned int tail = bp->rx_tail;
487 int first_frag = -1;
488
489 for (; budget > 0; tail = NEXT_RX(tail)) {
490 u32 addr, ctrl;
491
492 /* Make hw descriptor updates visible to CPU */
493 rmb();
494
495 addr = bp->rx_ring[tail].addr;
496 ctrl = bp->rx_ring[tail].ctrl;
497
498 if (!(addr & MACB_BIT(RX_USED)))
499 break;
500
501 if (ctrl & MACB_BIT(RX_SOF)) {
502 if (first_frag != -1)
503 discard_partial_frame(bp, first_frag, tail);
504 first_frag = tail;
505 }
506
507 if (ctrl & MACB_BIT(RX_EOF)) {
508 int dropped;
509 BUG_ON(first_frag == -1);
510
511 dropped = macb_rx_frame(bp, first_frag, tail);
512 first_frag = -1;
513 if (!dropped) {
514 received++;
515 budget--;
516 }
517 }
518 }
519
520 if (first_frag != -1)
521 bp->rx_tail = first_frag;
522 else
523 bp->rx_tail = tail;
524
525 return received;
526 }
527
528 static int macb_poll(struct napi_struct *napi, int budget)
529 {
530 struct macb *bp = container_of(napi, struct macb, napi);
531 int work_done;
532 u32 status;
533
534 status = macb_readl(bp, RSR);
535 macb_writel(bp, RSR, status);
536
537 work_done = 0;
538
539 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
540 (unsigned long)status, budget);
541
542 work_done = macb_rx(bp, budget);
543 if (work_done < budget) {
544 napi_complete(napi);
545
546 /*
547 * We've done what we can to clean the buffers. Make sure we
548 * get notified when new packets arrive.
549 */
550 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
551 }
552
553 /* TODO: Handle errors */
554
555 return work_done;
556 }
557
558 static irqreturn_t macb_interrupt(int irq, void *dev_id)
559 {
560 struct net_device *dev = dev_id;
561 struct macb *bp = netdev_priv(dev);
562 u32 status;
563
564 status = macb_readl(bp, ISR);
565
566 if (unlikely(!status))
567 return IRQ_NONE;
568
569 spin_lock(&bp->lock);
570
571 while (status) {
572 /* close possible race with dev_close */
573 if (unlikely(!netif_running(dev))) {
574 macb_writel(bp, IDR, -1);
575 break;
576 }
577
578 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
579
580 if (status & MACB_RX_INT_FLAGS) {
581 /*
582 * There's no point taking any more interrupts
583 * until we have processed the buffers. The
584 * scheduling call may fail if the poll routine
585 * is already scheduled, so disable interrupts
586 * now.
587 */
588 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
589
590 if (napi_schedule_prep(&bp->napi)) {
591 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
592 __napi_schedule(&bp->napi);
593 }
594 }
595
596 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
597 MACB_BIT(ISR_RLE)))
598 macb_tx(bp);
599
600 /*
601 * Link change detection isn't possible with RMII, so we'll
602 * add that if/when we get our hands on a full-blown MII PHY.
603 */
604
605 if (status & MACB_BIT(ISR_ROVR)) {
606 /* We missed at least one packet */
607 if (macb_is_gem(bp))
608 bp->hw_stats.gem.rx_overruns++;
609 else
610 bp->hw_stats.macb.rx_overruns++;
611 }
612
613 if (status & MACB_BIT(HRESP)) {
614 /*
615 * TODO: Reset the hardware, and maybe move the
616 * netdev_err to a lower-priority context as well
617 * (work queue?)
618 */
619 netdev_err(dev, "DMA bus error: HRESP not OK\n");
620 }
621
622 status = macb_readl(bp, ISR);
623 }
624
625 spin_unlock(&bp->lock);
626
627 return IRQ_HANDLED;
628 }
629
630 #ifdef CONFIG_NET_POLL_CONTROLLER
631 /*
632 * Polling receive - used by netconsole and other diagnostic tools
633 * to allow network i/o with interrupts disabled.
634 */
635 static void macb_poll_controller(struct net_device *dev)
636 {
637 unsigned long flags;
638
639 local_irq_save(flags);
640 macb_interrupt(dev->irq, dev);
641 local_irq_restore(flags);
642 }
643 #endif
644
645 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
646 {
647 struct macb *bp = netdev_priv(dev);
648 dma_addr_t mapping;
649 unsigned int len, entry;
650 u32 ctrl;
651 unsigned long flags;
652
653 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
654 netdev_vdbg(bp->dev,
655 "start_xmit: len %u head %p data %p tail %p end %p\n",
656 skb->len, skb->head, skb->data,
657 skb_tail_pointer(skb), skb_end_pointer(skb));
658 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
659 skb->data, 16, true);
660 #endif
661
662 len = skb->len;
663 spin_lock_irqsave(&bp->lock, flags);
664
665 /* This is a hard error, log it. */
666 if (TX_BUFFS_AVAIL(bp) < 1) {
667 netif_stop_queue(dev);
668 spin_unlock_irqrestore(&bp->lock, flags);
669 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
670 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
671 bp->tx_head, bp->tx_tail);
672 return NETDEV_TX_BUSY;
673 }
674
675 entry = bp->tx_head;
676 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
677 mapping = dma_map_single(&bp->pdev->dev, skb->data,
678 len, DMA_TO_DEVICE);
679 bp->tx_skb[entry].skb = skb;
680 bp->tx_skb[entry].mapping = mapping;
681 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
682 skb->data, (unsigned long)mapping);
683
684 ctrl = MACB_BF(TX_FRMLEN, len);
685 ctrl |= MACB_BIT(TX_LAST);
686 if (entry == (TX_RING_SIZE - 1))
687 ctrl |= MACB_BIT(TX_WRAP);
688
689 bp->tx_ring[entry].addr = mapping;
690 bp->tx_ring[entry].ctrl = ctrl;
691
692 /* Make newly initialized descriptor visible to hardware */
693 wmb();
694
695 entry = NEXT_TX(entry);
696 bp->tx_head = entry;
697
698 skb_tx_timestamp(skb);
699
700 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
701
702 if (TX_BUFFS_AVAIL(bp) < 1)
703 netif_stop_queue(dev);
704
705 spin_unlock_irqrestore(&bp->lock, flags);
706
707 return NETDEV_TX_OK;
708 }
709
710 static void macb_free_consistent(struct macb *bp)
711 {
712 if (bp->tx_skb) {
713 kfree(bp->tx_skb);
714 bp->tx_skb = NULL;
715 }
716 if (bp->rx_ring) {
717 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
718 bp->rx_ring, bp->rx_ring_dma);
719 bp->rx_ring = NULL;
720 }
721 if (bp->tx_ring) {
722 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
723 bp->tx_ring, bp->tx_ring_dma);
724 bp->tx_ring = NULL;
725 }
726 if (bp->rx_buffers) {
727 dma_free_coherent(&bp->pdev->dev,
728 RX_RING_SIZE * RX_BUFFER_SIZE,
729 bp->rx_buffers, bp->rx_buffers_dma);
730 bp->rx_buffers = NULL;
731 }
732 }
733
734 static int macb_alloc_consistent(struct macb *bp)
735 {
736 int size;
737
738 size = TX_RING_SIZE * sizeof(struct ring_info);
739 bp->tx_skb = kmalloc(size, GFP_KERNEL);
740 if (!bp->tx_skb)
741 goto out_err;
742
743 size = RX_RING_BYTES;
744 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
745 &bp->rx_ring_dma, GFP_KERNEL);
746 if (!bp->rx_ring)
747 goto out_err;
748 netdev_dbg(bp->dev,
749 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
750 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
751
752 size = TX_RING_BYTES;
753 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
754 &bp->tx_ring_dma, GFP_KERNEL);
755 if (!bp->tx_ring)
756 goto out_err;
757 netdev_dbg(bp->dev,
758 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
759 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
760
761 size = RX_RING_SIZE * RX_BUFFER_SIZE;
762 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
763 &bp->rx_buffers_dma, GFP_KERNEL);
764 if (!bp->rx_buffers)
765 goto out_err;
766 netdev_dbg(bp->dev,
767 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
768 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
769
770 return 0;
771
772 out_err:
773 macb_free_consistent(bp);
774 return -ENOMEM;
775 }
776
777 static void macb_init_rings(struct macb *bp)
778 {
779 int i;
780 dma_addr_t addr;
781
782 addr = bp->rx_buffers_dma;
783 for (i = 0; i < RX_RING_SIZE; i++) {
784 bp->rx_ring[i].addr = addr;
785 bp->rx_ring[i].ctrl = 0;
786 addr += RX_BUFFER_SIZE;
787 }
788 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
789
790 for (i = 0; i < TX_RING_SIZE; i++) {
791 bp->tx_ring[i].addr = 0;
792 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
793 }
794 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
795
796 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
797 }
798
799 static void macb_reset_hw(struct macb *bp)
800 {
801 /*
802 * Disable RX and TX (XXX: Should we halt the transmission
803 * more gracefully?)
804 */
805 macb_writel(bp, NCR, 0);
806
807 /* Clear the stats registers (XXX: Update stats first?) */
808 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
809
810 /* Clear all status flags */
811 macb_writel(bp, TSR, -1);
812 macb_writel(bp, RSR, -1);
813
814 /* Disable all interrupts */
815 macb_writel(bp, IDR, -1);
816 macb_readl(bp, ISR);
817 }
818
819 static u32 gem_mdc_clk_div(struct macb *bp)
820 {
821 u32 config;
822 unsigned long pclk_hz = clk_get_rate(bp->pclk);
823
824 if (pclk_hz <= 20000000)
825 config = GEM_BF(CLK, GEM_CLK_DIV8);
826 else if (pclk_hz <= 40000000)
827 config = GEM_BF(CLK, GEM_CLK_DIV16);
828 else if (pclk_hz <= 80000000)
829 config = GEM_BF(CLK, GEM_CLK_DIV32);
830 else if (pclk_hz <= 120000000)
831 config = GEM_BF(CLK, GEM_CLK_DIV48);
832 else if (pclk_hz <= 160000000)
833 config = GEM_BF(CLK, GEM_CLK_DIV64);
834 else
835 config = GEM_BF(CLK, GEM_CLK_DIV96);
836
837 return config;
838 }
839
840 static u32 macb_mdc_clk_div(struct macb *bp)
841 {
842 u32 config;
843 unsigned long pclk_hz;
844
845 if (macb_is_gem(bp))
846 return gem_mdc_clk_div(bp);
847
848 pclk_hz = clk_get_rate(bp->pclk);
849 if (pclk_hz <= 20000000)
850 config = MACB_BF(CLK, MACB_CLK_DIV8);
851 else if (pclk_hz <= 40000000)
852 config = MACB_BF(CLK, MACB_CLK_DIV16);
853 else if (pclk_hz <= 80000000)
854 config = MACB_BF(CLK, MACB_CLK_DIV32);
855 else
856 config = MACB_BF(CLK, MACB_CLK_DIV64);
857
858 return config;
859 }
860
861 /*
862 * Get the DMA bus width field of the network configuration register that we
863 * should program. We find the width from decoding the design configuration
864 * register to find the maximum supported data bus width.
865 */
866 static u32 macb_dbw(struct macb *bp)
867 {
868 if (!macb_is_gem(bp))
869 return 0;
870
871 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
872 case 4:
873 return GEM_BF(DBW, GEM_DBW128);
874 case 2:
875 return GEM_BF(DBW, GEM_DBW64);
876 case 1:
877 default:
878 return GEM_BF(DBW, GEM_DBW32);
879 }
880 }
881
882 /*
883 * Configure the receive DMA engine to use the correct receive buffer size.
884 * This is a configurable parameter for GEM.
885 */
886 static void macb_configure_dma(struct macb *bp)
887 {
888 u32 dmacfg;
889
890 if (macb_is_gem(bp)) {
891 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
892 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
893 gem_writel(bp, DMACFG, dmacfg);
894 }
895 }
896
897 static void macb_init_hw(struct macb *bp)
898 {
899 u32 config;
900
901 macb_reset_hw(bp);
902 __macb_set_hwaddr(bp);
903
904 config = macb_mdc_clk_div(bp);
905 config |= MACB_BIT(PAE); /* PAuse Enable */
906 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
907 config |= MACB_BIT(BIG); /* Receive oversized frames */
908 if (bp->dev->flags & IFF_PROMISC)
909 config |= MACB_BIT(CAF); /* Copy All Frames */
910 if (!(bp->dev->flags & IFF_BROADCAST))
911 config |= MACB_BIT(NBC); /* No BroadCast */
912 config |= macb_dbw(bp);
913 macb_writel(bp, NCFGR, config);
914
915 macb_configure_dma(bp);
916
917 /* Initialize TX and RX buffers */
918 macb_writel(bp, RBQP, bp->rx_ring_dma);
919 macb_writel(bp, TBQP, bp->tx_ring_dma);
920
921 /* Enable TX and RX */
922 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
923
924 /* Enable interrupts */
925 macb_writel(bp, IER, (MACB_BIT(RCOMP)
926 | MACB_BIT(RXUBR)
927 | MACB_BIT(ISR_TUND)
928 | MACB_BIT(ISR_RLE)
929 | MACB_BIT(TXERR)
930 | MACB_BIT(TCOMP)
931 | MACB_BIT(ISR_ROVR)
932 | MACB_BIT(HRESP)));
933
934 }
935
936 /*
937 * The hash address register is 64 bits long and takes up two
938 * locations in the memory map. The least significant bits are stored
939 * in EMAC_HSL and the most significant bits in EMAC_HSH.
940 *
941 * The unicast hash enable and the multicast hash enable bits in the
942 * network configuration register enable the reception of hash matched
943 * frames. The destination address is reduced to a 6 bit index into
944 * the 64 bit hash register using the following hash function. The
945 * hash function is an exclusive or of every sixth bit of the
946 * destination address.
947 *
948 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
949 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
950 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
951 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
952 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
953 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
954 *
955 * da[0] represents the least significant bit of the first byte
956 * received, that is, the multicast/unicast indicator, and da[47]
957 * represents the most significant bit of the last byte received. If
958 * the hash index, hi[n], points to a bit that is set in the hash
959 * register then the frame will be matched according to whether the
960 * frame is multicast or unicast. A multicast match will be signalled
961 * if the multicast hash enable bit is set, da[0] is 1 and the hash
962 * index points to a bit set in the hash register. A unicast match
963 * will be signalled if the unicast hash enable bit is set, da[0] is 0
964 * and the hash index points to a bit set in the hash register. To
965 * receive all multicast frames, the hash register should be set with
966 * all ones and the multicast hash enable bit should be set in the
967 * network configuration register.
968 */
969
970 static inline int hash_bit_value(int bitnr, __u8 *addr)
971 {
972 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
973 return 1;
974 return 0;
975 }
976
977 /*
978 * Return the hash index value for the specified address.
979 */
980 static int hash_get_index(__u8 *addr)
981 {
982 int i, j, bitval;
983 int hash_index = 0;
984
985 for (j = 0; j < 6; j++) {
986 for (i = 0, bitval = 0; i < 8; i++)
987 bitval ^= hash_bit_value(i*6 + j, addr);
988
989 hash_index |= (bitval << j);
990 }
991
992 return hash_index;
993 }
994
995 /*
996 * Add multicast addresses to the internal multicast-hash table.
997 */
998 static void macb_sethashtable(struct net_device *dev)
999 {
1000 struct netdev_hw_addr *ha;
1001 unsigned long mc_filter[2];
1002 unsigned int bitnr;
1003 struct macb *bp = netdev_priv(dev);
1004
1005 mc_filter[0] = mc_filter[1] = 0;
1006
1007 netdev_for_each_mc_addr(ha, dev) {
1008 bitnr = hash_get_index(ha->addr);
1009 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1010 }
1011
1012 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1013 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1014 }
1015
1016 /*
1017 * Enable/Disable promiscuous and multicast modes.
1018 */
1019 void macb_set_rx_mode(struct net_device *dev)
1020 {
1021 unsigned long cfg;
1022 struct macb *bp = netdev_priv(dev);
1023
1024 cfg = macb_readl(bp, NCFGR);
1025
1026 if (dev->flags & IFF_PROMISC)
1027 /* Enable promiscuous mode */
1028 cfg |= MACB_BIT(CAF);
1029 else if (dev->flags & (~IFF_PROMISC))
1030 /* Disable promiscuous mode */
1031 cfg &= ~MACB_BIT(CAF);
1032
1033 if (dev->flags & IFF_ALLMULTI) {
1034 /* Enable all multicast mode */
1035 macb_or_gem_writel(bp, HRB, -1);
1036 macb_or_gem_writel(bp, HRT, -1);
1037 cfg |= MACB_BIT(NCFGR_MTI);
1038 } else if (!netdev_mc_empty(dev)) {
1039 /* Enable specific multicasts */
1040 macb_sethashtable(dev);
1041 cfg |= MACB_BIT(NCFGR_MTI);
1042 } else if (dev->flags & (~IFF_ALLMULTI)) {
1043 /* Disable all multicast mode */
1044 macb_or_gem_writel(bp, HRB, 0);
1045 macb_or_gem_writel(bp, HRT, 0);
1046 cfg &= ~MACB_BIT(NCFGR_MTI);
1047 }
1048
1049 macb_writel(bp, NCFGR, cfg);
1050 }
1051 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1052
1053 static int macb_open(struct net_device *dev)
1054 {
1055 struct macb *bp = netdev_priv(dev);
1056 int err;
1057
1058 netdev_dbg(bp->dev, "open\n");
1059
1060 /* carrier starts down */
1061 netif_carrier_off(dev);
1062
1063 /* if the phy is not yet register, retry later*/
1064 if (!bp->phy_dev)
1065 return -EAGAIN;
1066
1067 if (!is_valid_ether_addr(dev->dev_addr))
1068 return -EADDRNOTAVAIL;
1069
1070 err = macb_alloc_consistent(bp);
1071 if (err) {
1072 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1073 err);
1074 return err;
1075 }
1076
1077 napi_enable(&bp->napi);
1078
1079 macb_init_rings(bp);
1080 macb_init_hw(bp);
1081
1082 /* schedule a link state check */
1083 phy_start(bp->phy_dev);
1084
1085 netif_start_queue(dev);
1086
1087 return 0;
1088 }
1089
1090 static int macb_close(struct net_device *dev)
1091 {
1092 struct macb *bp = netdev_priv(dev);
1093 unsigned long flags;
1094
1095 netif_stop_queue(dev);
1096 napi_disable(&bp->napi);
1097
1098 if (bp->phy_dev)
1099 phy_stop(bp->phy_dev);
1100
1101 spin_lock_irqsave(&bp->lock, flags);
1102 macb_reset_hw(bp);
1103 netif_carrier_off(dev);
1104 spin_unlock_irqrestore(&bp->lock, flags);
1105
1106 macb_free_consistent(bp);
1107
1108 return 0;
1109 }
1110
1111 static void gem_update_stats(struct macb *bp)
1112 {
1113 u32 __iomem *reg = bp->regs + GEM_OTX;
1114 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1115 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1116
1117 for (; p < end; p++, reg++)
1118 *p += __raw_readl(reg);
1119 }
1120
1121 static struct net_device_stats *gem_get_stats(struct macb *bp)
1122 {
1123 struct gem_stats *hwstat = &bp->hw_stats.gem;
1124 struct net_device_stats *nstat = &bp->stats;
1125
1126 gem_update_stats(bp);
1127
1128 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1129 hwstat->rx_alignment_errors +
1130 hwstat->rx_resource_errors +
1131 hwstat->rx_overruns +
1132 hwstat->rx_oversize_frames +
1133 hwstat->rx_jabbers +
1134 hwstat->rx_undersized_frames +
1135 hwstat->rx_length_field_frame_errors);
1136 nstat->tx_errors = (hwstat->tx_late_collisions +
1137 hwstat->tx_excessive_collisions +
1138 hwstat->tx_underrun +
1139 hwstat->tx_carrier_sense_errors);
1140 nstat->multicast = hwstat->rx_multicast_frames;
1141 nstat->collisions = (hwstat->tx_single_collision_frames +
1142 hwstat->tx_multiple_collision_frames +
1143 hwstat->tx_excessive_collisions);
1144 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1145 hwstat->rx_jabbers +
1146 hwstat->rx_undersized_frames +
1147 hwstat->rx_length_field_frame_errors);
1148 nstat->rx_over_errors = hwstat->rx_resource_errors;
1149 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1150 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1151 nstat->rx_fifo_errors = hwstat->rx_overruns;
1152 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1153 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1154 nstat->tx_fifo_errors = hwstat->tx_underrun;
1155
1156 return nstat;
1157 }
1158
1159 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1160 {
1161 struct macb *bp = netdev_priv(dev);
1162 struct net_device_stats *nstat = &bp->stats;
1163 struct macb_stats *hwstat = &bp->hw_stats.macb;
1164
1165 if (macb_is_gem(bp))
1166 return gem_get_stats(bp);
1167
1168 /* read stats from hardware */
1169 macb_update_stats(bp);
1170
1171 /* Convert HW stats into netdevice stats */
1172 nstat->rx_errors = (hwstat->rx_fcs_errors +
1173 hwstat->rx_align_errors +
1174 hwstat->rx_resource_errors +
1175 hwstat->rx_overruns +
1176 hwstat->rx_oversize_pkts +
1177 hwstat->rx_jabbers +
1178 hwstat->rx_undersize_pkts +
1179 hwstat->sqe_test_errors +
1180 hwstat->rx_length_mismatch);
1181 nstat->tx_errors = (hwstat->tx_late_cols +
1182 hwstat->tx_excessive_cols +
1183 hwstat->tx_underruns +
1184 hwstat->tx_carrier_errors);
1185 nstat->collisions = (hwstat->tx_single_cols +
1186 hwstat->tx_multiple_cols +
1187 hwstat->tx_excessive_cols);
1188 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1189 hwstat->rx_jabbers +
1190 hwstat->rx_undersize_pkts +
1191 hwstat->rx_length_mismatch);
1192 nstat->rx_over_errors = hwstat->rx_resource_errors +
1193 hwstat->rx_overruns;
1194 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1195 nstat->rx_frame_errors = hwstat->rx_align_errors;
1196 nstat->rx_fifo_errors = hwstat->rx_overruns;
1197 /* XXX: What does "missed" mean? */
1198 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1199 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1200 nstat->tx_fifo_errors = hwstat->tx_underruns;
1201 /* Don't know about heartbeat or window errors... */
1202
1203 return nstat;
1204 }
1205
1206 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1207 {
1208 struct macb *bp = netdev_priv(dev);
1209 struct phy_device *phydev = bp->phy_dev;
1210
1211 if (!phydev)
1212 return -ENODEV;
1213
1214 return phy_ethtool_gset(phydev, cmd);
1215 }
1216
1217 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1218 {
1219 struct macb *bp = netdev_priv(dev);
1220 struct phy_device *phydev = bp->phy_dev;
1221
1222 if (!phydev)
1223 return -ENODEV;
1224
1225 return phy_ethtool_sset(phydev, cmd);
1226 }
1227
1228 const struct ethtool_ops macb_ethtool_ops = {
1229 .get_settings = macb_get_settings,
1230 .set_settings = macb_set_settings,
1231 .get_link = ethtool_op_get_link,
1232 .get_ts_info = ethtool_op_get_ts_info,
1233 };
1234 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1235
1236 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1237 {
1238 struct macb *bp = netdev_priv(dev);
1239 struct phy_device *phydev = bp->phy_dev;
1240
1241 if (!netif_running(dev))
1242 return -EINVAL;
1243
1244 if (!phydev)
1245 return -ENODEV;
1246
1247 return phy_mii_ioctl(phydev, rq, cmd);
1248 }
1249 EXPORT_SYMBOL_GPL(macb_ioctl);
1250
1251 static const struct net_device_ops macb_netdev_ops = {
1252 .ndo_open = macb_open,
1253 .ndo_stop = macb_close,
1254 .ndo_start_xmit = macb_start_xmit,
1255 .ndo_set_rx_mode = macb_set_rx_mode,
1256 .ndo_get_stats = macb_get_stats,
1257 .ndo_do_ioctl = macb_ioctl,
1258 .ndo_validate_addr = eth_validate_addr,
1259 .ndo_change_mtu = eth_change_mtu,
1260 .ndo_set_mac_address = eth_mac_addr,
1261 #ifdef CONFIG_NET_POLL_CONTROLLER
1262 .ndo_poll_controller = macb_poll_controller,
1263 #endif
1264 };
1265
1266 #if defined(CONFIG_OF)
1267 static const struct of_device_id macb_dt_ids[] = {
1268 { .compatible = "cdns,at32ap7000-macb" },
1269 { .compatible = "cdns,at91sam9260-macb" },
1270 { .compatible = "cdns,macb" },
1271 { .compatible = "cdns,pc302-gem" },
1272 { .compatible = "cdns,gem" },
1273 { /* sentinel */ }
1274 };
1275
1276 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1277
1278 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1279 {
1280 struct device_node *np = pdev->dev.of_node;
1281
1282 if (np)
1283 return of_get_phy_mode(np);
1284
1285 return -ENODEV;
1286 }
1287
1288 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1289 {
1290 struct device_node *np = bp->pdev->dev.of_node;
1291 if (np) {
1292 const char *mac = of_get_mac_address(np);
1293 if (mac) {
1294 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1295 return 0;
1296 }
1297 }
1298
1299 return -ENODEV;
1300 }
1301 #else
1302 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1303 {
1304 return -ENODEV;
1305 }
1306 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1307 {
1308 return -ENODEV;
1309 }
1310 #endif
1311
1312 static int __init macb_probe(struct platform_device *pdev)
1313 {
1314 struct macb_platform_data *pdata;
1315 struct resource *regs;
1316 struct net_device *dev;
1317 struct macb *bp;
1318 struct phy_device *phydev;
1319 u32 config;
1320 int err = -ENXIO;
1321
1322 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1323 if (!regs) {
1324 dev_err(&pdev->dev, "no mmio resource defined\n");
1325 goto err_out;
1326 }
1327
1328 err = -ENOMEM;
1329 dev = alloc_etherdev(sizeof(*bp));
1330 if (!dev)
1331 goto err_out;
1332
1333 SET_NETDEV_DEV(dev, &pdev->dev);
1334
1335 /* TODO: Actually, we have some interesting features... */
1336 dev->features |= 0;
1337
1338 bp = netdev_priv(dev);
1339 bp->pdev = pdev;
1340 bp->dev = dev;
1341
1342 spin_lock_init(&bp->lock);
1343
1344 bp->pclk = clk_get(&pdev->dev, "pclk");
1345 if (IS_ERR(bp->pclk)) {
1346 dev_err(&pdev->dev, "failed to get macb_clk\n");
1347 goto err_out_free_dev;
1348 }
1349 clk_enable(bp->pclk);
1350
1351 bp->hclk = clk_get(&pdev->dev, "hclk");
1352 if (IS_ERR(bp->hclk)) {
1353 dev_err(&pdev->dev, "failed to get hclk\n");
1354 goto err_out_put_pclk;
1355 }
1356 clk_enable(bp->hclk);
1357
1358 bp->regs = ioremap(regs->start, resource_size(regs));
1359 if (!bp->regs) {
1360 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1361 err = -ENOMEM;
1362 goto err_out_disable_clocks;
1363 }
1364
1365 dev->irq = platform_get_irq(pdev, 0);
1366 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1367 if (err) {
1368 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1369 dev->irq, err);
1370 goto err_out_iounmap;
1371 }
1372
1373 dev->netdev_ops = &macb_netdev_ops;
1374 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1375 dev->ethtool_ops = &macb_ethtool_ops;
1376
1377 dev->base_addr = regs->start;
1378
1379 /* Set MII management clock divider */
1380 config = macb_mdc_clk_div(bp);
1381 config |= macb_dbw(bp);
1382 macb_writel(bp, NCFGR, config);
1383
1384 err = macb_get_hwaddr_dt(bp);
1385 if (err < 0)
1386 macb_get_hwaddr(bp);
1387
1388 err = macb_get_phy_mode_dt(pdev);
1389 if (err < 0) {
1390 pdata = pdev->dev.platform_data;
1391 if (pdata && pdata->is_rmii)
1392 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1393 else
1394 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1395 } else {
1396 bp->phy_interface = err;
1397 }
1398
1399 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1400 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1401 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1402 #if defined(CONFIG_ARCH_AT91)
1403 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1404 MACB_BIT(CLKEN)));
1405 #else
1406 macb_or_gem_writel(bp, USRIO, 0);
1407 #endif
1408 else
1409 #if defined(CONFIG_ARCH_AT91)
1410 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1411 #else
1412 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1413 #endif
1414
1415 bp->tx_pending = DEF_TX_RING_PENDING;
1416
1417 err = register_netdev(dev);
1418 if (err) {
1419 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1420 goto err_out_free_irq;
1421 }
1422
1423 if (macb_mii_init(bp) != 0) {
1424 goto err_out_unregister_netdev;
1425 }
1426
1427 platform_set_drvdata(pdev, dev);
1428
1429 netif_carrier_off(dev);
1430
1431 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1432 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1433 dev->irq, dev->dev_addr);
1434
1435 phydev = bp->phy_dev;
1436 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1437 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1438
1439 return 0;
1440
1441 err_out_unregister_netdev:
1442 unregister_netdev(dev);
1443 err_out_free_irq:
1444 free_irq(dev->irq, dev);
1445 err_out_iounmap:
1446 iounmap(bp->regs);
1447 err_out_disable_clocks:
1448 clk_disable(bp->hclk);
1449 clk_put(bp->hclk);
1450 clk_disable(bp->pclk);
1451 err_out_put_pclk:
1452 clk_put(bp->pclk);
1453 err_out_free_dev:
1454 free_netdev(dev);
1455 err_out:
1456 platform_set_drvdata(pdev, NULL);
1457 return err;
1458 }
1459
1460 static int __exit macb_remove(struct platform_device *pdev)
1461 {
1462 struct net_device *dev;
1463 struct macb *bp;
1464
1465 dev = platform_get_drvdata(pdev);
1466
1467 if (dev) {
1468 bp = netdev_priv(dev);
1469 if (bp->phy_dev)
1470 phy_disconnect(bp->phy_dev);
1471 mdiobus_unregister(bp->mii_bus);
1472 kfree(bp->mii_bus->irq);
1473 mdiobus_free(bp->mii_bus);
1474 unregister_netdev(dev);
1475 free_irq(dev->irq, dev);
1476 iounmap(bp->regs);
1477 clk_disable(bp->hclk);
1478 clk_put(bp->hclk);
1479 clk_disable(bp->pclk);
1480 clk_put(bp->pclk);
1481 free_netdev(dev);
1482 platform_set_drvdata(pdev, NULL);
1483 }
1484
1485 return 0;
1486 }
1487
1488 #ifdef CONFIG_PM
1489 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1490 {
1491 struct net_device *netdev = platform_get_drvdata(pdev);
1492 struct macb *bp = netdev_priv(netdev);
1493
1494 netif_carrier_off(netdev);
1495 netif_device_detach(netdev);
1496
1497 clk_disable(bp->hclk);
1498 clk_disable(bp->pclk);
1499
1500 return 0;
1501 }
1502
1503 static int macb_resume(struct platform_device *pdev)
1504 {
1505 struct net_device *netdev = platform_get_drvdata(pdev);
1506 struct macb *bp = netdev_priv(netdev);
1507
1508 clk_enable(bp->pclk);
1509 clk_enable(bp->hclk);
1510
1511 netif_device_attach(netdev);
1512
1513 return 0;
1514 }
1515 #else
1516 #define macb_suspend NULL
1517 #define macb_resume NULL
1518 #endif
1519
1520 static struct platform_driver macb_driver = {
1521 .remove = __exit_p(macb_remove),
1522 .suspend = macb_suspend,
1523 .resume = macb_resume,
1524 .driver = {
1525 .name = "macb",
1526 .owner = THIS_MODULE,
1527 .of_match_table = of_match_ptr(macb_dt_ids),
1528 },
1529 };
1530
1531 static int __init macb_init(void)
1532 {
1533 return platform_driver_probe(&macb_driver, macb_probe);
1534 }
1535
1536 static void __exit macb_exit(void)
1537 {
1538 platform_driver_unregister(&macb_driver);
1539 }
1540
1541 module_init(macb_init);
1542 module_exit(macb_exit);
1543
1544 MODULE_LICENSE("GPL");
1545 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1546 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1547 MODULE_ALIAS("platform:macb");
CJK support for tty framebuffer vt