arch/mips/sni/irq.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 Linus Torvalds
   7  * Copyright (C) 1994 - 2000 Ralf Baechle
   8  */
   9 #include <linux/delay.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14 #include <linux/spinlock.h>
  15
  16 #include <asm/i8259.h>
  17 #include <asm/io.h>
  18 #include <asm/sni.h>
  19
  20 DEFINE_SPINLOCK(pciasic_lock);
  21
  22 static void enable_pciasic_irq(unsigned int irq)
  23 {
  24         unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
  25         unsigned long flags;
  26
  27         spin_lock_irqsave(&pciasic_lock, flags);
  28         *(volatile u8 *) PCIMT_IRQSEL |= mask;
  29         spin_unlock_irqrestore(&pciasic_lock, flags);
  30 }
  31
  32 static unsigned int startup_pciasic_irq(unsigned int irq)
  33 {
  34         enable_pciasic_irq(irq);
  35         return 0; /* never anything pending */
  36 }
  37
  38 #define shutdown_pciasic_irq    disable_pciasic_irq
  39
  40 void disable_pciasic_irq(unsigned int irq)
  41 {
  42         unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
  43         unsigned long flags;
  44
  45         spin_lock_irqsave(&pciasic_lock, flags);
  46         *(volatile u8 *) PCIMT_IRQSEL &= mask;
  47         spin_unlock_irqrestore(&pciasic_lock, flags);
  48 }
  49
  50 #define mask_and_ack_pciasic_irq disable_pciasic_irq
  51
  52 static void end_pciasic_irq(unsigned int irq)
  53 {
  54         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  55                 enable_pciasic_irq(irq);
  56 }
  57
  58 static struct irq_chip pciasic_irq_type = {
  59         .typename = "ASIC-PCI",
  60         .startup = startup_pciasic_irq,
  61         .shutdown = shutdown_pciasic_irq,
  62         .enable = enable_pciasic_irq,
  63         .disable = disable_pciasic_irq,
  64         .ack = mask_and_ack_pciasic_irq,
  65         .end = end_pciasic_irq,
  66 };
  67
  68 /*
  69  * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
  70  * button interrupts.  Later ...
  71  */
  72 static void pciasic_hwint0(void)
  73 {
  74         panic("Received int0 but no handler yet ...");
  75 }
  76
  77 /* This interrupt was used for the com1 console on the first prototypes.  */
  78 static void pciasic_hwint2(void)
  79 {
  80         /* I think this shouldn't happen on production machines.  */
  81         panic("hwint2 and no handler yet");
  82 }
  83
  84 /* hwint5 is the r4k count / compare interrupt  */
  85 static void pciasic_hwint5(void)
  86 {
  87         panic("hwint5 and no handler yet");
  88 }
  89
  90 static unsigned int ls1bit8(unsigned int x)
  91 {
  92         int b = 7, s;
  93
  94         s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s;
  95         s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s;
  96         s = 1; if ((x & 0x40) == 0) s = 0; b -= s;
  97
  98         return b;
  99 }
 100
 101 /*
 102  * hwint 1 deals with EISA and SCSI interrupts,
 103  *
 104  * The EISA_INT bit in CSITPEND is high active, all others are low active.
 105  */
 106 static void pciasic_hwint1(void)
 107 {
 108         u8 pend = *(volatile char *)PCIMT_CSITPEND;
 109         unsigned long flags;
 110
 111         if (pend & IT_EISA) {
 112                 int irq;
 113                 /*
 114                  * Note: ASIC PCI's builtin interrupt achknowledge feature is
 115                  * broken.  Using it may result in loss of some or all i8259
 116                  * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
 117                  */
 118                 irq = i8259_irq();
 119                 if (unlikely(irq < 0))
 120                         return;
 121
 122                 do_IRQ(irq);
 123         }
 124
 125         if (!(pend & IT_SCSI)) {
 126                 flags = read_c0_status();
 127                 clear_c0_status(ST0_IM);
 128                 do_IRQ(PCIMT_IRQ_SCSI);
 129                 write_c0_status(flags);
 130         }
 131 }
 132
 133 /*
 134  * hwint 3 should deal with the PCI A - D interrupts,
 135  */
 136 static void pciasic_hwint3(void)
 137 {
 138         u8 pend = *(volatile char *)PCIMT_CSITPEND;
 139         int irq;
 140
 141         pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
 142         clear_c0_status(IE_IRQ3);
 143         irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
 144         do_IRQ(irq);
 145         set_c0_status(IE_IRQ3);
 146 }
 147
 148 /*
 149  * hwint 4 is used for only the onboard PCnet 32.
 150  */
 151 static void pciasic_hwint4(void)
 152 {
 153         clear_c0_status(IE_IRQ4);
 154         do_IRQ(PCIMT_IRQ_ETHERNET);
 155         set_c0_status(IE_IRQ4);
 156 }
 157
 158 asmlinkage void plat_irq_dispatch(void)
 159 {
 160         unsigned int pending = read_c0_status() & read_c0_cause();
 161         static unsigned char led_cache;
 162
 163         *(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
 164
 165         if (pending & 0x0800)
 166                 pciasic_hwint1();
 167         else if (pending & 0x4000)
 168                 pciasic_hwint4();
 169         else if (pending & 0x2000)
 170                 pciasic_hwint3();
 171         else if (pending & 0x1000)
 172                 pciasic_hwint2();
 173         else if (pending & 0x8000)
 174                 pciasic_hwint5();
 175         else if (pending & 0x0400)
 176                 pciasic_hwint0();
 177 }
 178
 179 void __init init_pciasic(void)
 180 {
 181         unsigned long flags;
 182
 183         spin_lock_irqsave(&pciasic_lock, flags);
 184         * (volatile u8 *) PCIMT_IRQSEL =
 185                 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
 186         spin_unlock_irqrestore(&pciasic_lock, flags);
 187 }
 188
 189 /*
 190  * On systems with i8259-style interrupt controllers we assume for
 191  * driver compatibility reasons interrupts 0 - 15 to be the i8295
 192  * interrupts even if the hardware uses a different interrupt numbering.
 193  */
 194 void __init arch_init_irq(void)
 195 {
 196         int i;
 197
 198         init_i8259_irqs();                      /* Integrated i8259  */
 199         init_pciasic();
 200
 201         /* Actually we've got more interrupts to handle ...  */
 202         for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) {
 203                 irq_desc[i].status     = IRQ_DISABLED;
 204                 irq_desc[i].action     = 0;
 205                 irq_desc[i].depth      = 1;
 206                 irq_desc[i].chip    = &pciasic_irq_type;
 207         }
 208
 209         change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
 210 }