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mmc: SDHC 3.0: Base clock frequency change in spec 3.0
[linux-2.6/cjktty.git] / drivers / mmc / host / sdhci.c
blobac8b12b18fa4c558a68f4285285e0e9e15f6942b
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <linux/leds.h>
25
26 #include <linux/mmc/host.h>
27
28 #include "sdhci.h"
29
30 #define DRIVER_NAME "sdhci"
31
32 #define DBG(f, x...) \
33 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
34
35 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
36 defined(CONFIG_MMC_SDHCI_MODULE))
37 #define SDHCI_USE_LEDS_CLASS
38 #endif
39
40 static unsigned int debug_quirks = 0;
41
42 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
43 static void sdhci_finish_data(struct sdhci_host *);
44
45 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
46 static void sdhci_finish_command(struct sdhci_host *);
47
48 static void sdhci_dumpregs(struct sdhci_host *host)
49 {
50 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
51
52 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
53 sdhci_readl(host, SDHCI_DMA_ADDRESS),
54 sdhci_readw(host, SDHCI_HOST_VERSION));
55 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
56 sdhci_readw(host, SDHCI_BLOCK_SIZE),
57 sdhci_readw(host, SDHCI_BLOCK_COUNT));
58 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
59 sdhci_readl(host, SDHCI_ARGUMENT),
60 sdhci_readw(host, SDHCI_TRANSFER_MODE));
61 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
62 sdhci_readl(host, SDHCI_PRESENT_STATE),
63 sdhci_readb(host, SDHCI_HOST_CONTROL));
64 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
65 sdhci_readb(host, SDHCI_POWER_CONTROL),
66 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
67 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
68 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
69 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
70 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
71 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
72 sdhci_readl(host, SDHCI_INT_STATUS));
73 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
74 sdhci_readl(host, SDHCI_INT_ENABLE),
75 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
76 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
77 sdhci_readw(host, SDHCI_ACMD12_ERR),
78 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
79 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
80 sdhci_readl(host, SDHCI_CAPABILITIES),
81 sdhci_readl(host, SDHCI_MAX_CURRENT));
82
83 if (host->flags & SDHCI_USE_ADMA)
84 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
85 readl(host->ioaddr + SDHCI_ADMA_ERROR),
86 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
87
88 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
89 }
90
91 /*****************************************************************************\
92 * *
93 * Low level functions *
94 * *
95 \*****************************************************************************/
96
97 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
98 {
99 u32 ier;
100
101 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
102 ier &= ~clear;
103 ier |= set;
104 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
105 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
106 }
107
108 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
109 {
110 sdhci_clear_set_irqs(host, 0, irqs);
111 }
112
113 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
114 {
115 sdhci_clear_set_irqs(host, irqs, 0);
116 }
117
118 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
119 {
120 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
121
122 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
123 return;
124
125 if (enable)
126 sdhci_unmask_irqs(host, irqs);
127 else
128 sdhci_mask_irqs(host, irqs);
129 }
130
131 static void sdhci_enable_card_detection(struct sdhci_host *host)
132 {
133 sdhci_set_card_detection(host, true);
134 }
135
136 static void sdhci_disable_card_detection(struct sdhci_host *host)
137 {
138 sdhci_set_card_detection(host, false);
139 }
140
141 static void sdhci_reset(struct sdhci_host *host, u8 mask)
142 {
143 unsigned long timeout;
144 u32 uninitialized_var(ier);
145
146 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
147 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
148 SDHCI_CARD_PRESENT))
149 return;
150 }
151
152 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
153 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
154
155 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
156
157 if (mask & SDHCI_RESET_ALL)
158 host->clock = 0;
159
160 /* Wait max 100 ms */
161 timeout = 100;
162
163 /* hw clears the bit when it's done */
164 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
165 if (timeout == 0) {
166 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
167 mmc_hostname(host->mmc), (int)mask);
168 sdhci_dumpregs(host);
169 return;
170 }
171 timeout--;
172 mdelay(1);
173 }
174
175 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
176 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
177 }
178
179 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
180
181 static void sdhci_init(struct sdhci_host *host, int soft)
182 {
183 if (soft)
184 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
185 else
186 sdhci_reset(host, SDHCI_RESET_ALL);
187
188 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
189 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
190 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
191 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
192 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
193
194 if (soft) {
195 /* force clock reconfiguration */
196 host->clock = 0;
197 sdhci_set_ios(host->mmc, &host->mmc->ios);
198 }
199 }
200
201 static void sdhci_reinit(struct sdhci_host *host)
202 {
203 sdhci_init(host, 0);
204 sdhci_enable_card_detection(host);
205 }
206
207 static void sdhci_activate_led(struct sdhci_host *host)
208 {
209 u8 ctrl;
210
211 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
212 ctrl |= SDHCI_CTRL_LED;
213 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
214 }
215
216 static void sdhci_deactivate_led(struct sdhci_host *host)
217 {
218 u8 ctrl;
219
220 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
221 ctrl &= ~SDHCI_CTRL_LED;
222 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
223 }
224
225 #ifdef SDHCI_USE_LEDS_CLASS
226 static void sdhci_led_control(struct led_classdev *led,
227 enum led_brightness brightness)
228 {
229 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
230 unsigned long flags;
231
232 spin_lock_irqsave(&host->lock, flags);
233
234 if (brightness == LED_OFF)
235 sdhci_deactivate_led(host);
236 else
237 sdhci_activate_led(host);
238
239 spin_unlock_irqrestore(&host->lock, flags);
240 }
241 #endif
242
243 /*****************************************************************************\
244 * *
245 * Core functions *
246 * *
247 \*****************************************************************************/
248
249 static void sdhci_read_block_pio(struct sdhci_host *host)
250 {
251 unsigned long flags;
252 size_t blksize, len, chunk;
253 u32 uninitialized_var(scratch);
254 u8 *buf;
255
256 DBG("PIO reading\n");
257
258 blksize = host->data->blksz;
259 chunk = 0;
260
261 local_irq_save(flags);
262
263 while (blksize) {
264 if (!sg_miter_next(&host->sg_miter))
265 BUG();
266
267 len = min(host->sg_miter.length, blksize);
268
269 blksize -= len;
270 host->sg_miter.consumed = len;
271
272 buf = host->sg_miter.addr;
273
274 while (len) {
275 if (chunk == 0) {
276 scratch = sdhci_readl(host, SDHCI_BUFFER);
277 chunk = 4;
278 }
279
280 *buf = scratch & 0xFF;
281
282 buf++;
283 scratch >>= 8;
284 chunk--;
285 len--;
286 }
287 }
288
289 sg_miter_stop(&host->sg_miter);
290
291 local_irq_restore(flags);
292 }
293
294 static void sdhci_write_block_pio(struct sdhci_host *host)
295 {
296 unsigned long flags;
297 size_t blksize, len, chunk;
298 u32 scratch;
299 u8 *buf;
300
301 DBG("PIO writing\n");
302
303 blksize = host->data->blksz;
304 chunk = 0;
305 scratch = 0;
306
307 local_irq_save(flags);
308
309 while (blksize) {
310 if (!sg_miter_next(&host->sg_miter))
311 BUG();
312
313 len = min(host->sg_miter.length, blksize);
314
315 blksize -= len;
316 host->sg_miter.consumed = len;
317
318 buf = host->sg_miter.addr;
319
320 while (len) {
321 scratch |= (u32)*buf << (chunk * 8);
322
323 buf++;
324 chunk++;
325 len--;
326
327 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
328 sdhci_writel(host, scratch, SDHCI_BUFFER);
329 chunk = 0;
330 scratch = 0;
331 }
332 }
333 }
334
335 sg_miter_stop(&host->sg_miter);
336
337 local_irq_restore(flags);
338 }
339
340 static void sdhci_transfer_pio(struct sdhci_host *host)
341 {
342 u32 mask;
343
344 BUG_ON(!host->data);
345
346 if (host->blocks == 0)
347 return;
348
349 if (host->data->flags & MMC_DATA_READ)
350 mask = SDHCI_DATA_AVAILABLE;
351 else
352 mask = SDHCI_SPACE_AVAILABLE;
353
354 /*
355 * Some controllers (JMicron JMB38x) mess up the buffer bits
356 * for transfers < 4 bytes. As long as it is just one block,
357 * we can ignore the bits.
358 */
359 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
360 (host->data->blocks == 1))
361 mask = ~0;
362
363 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
364 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
365 udelay(100);
366
367 if (host->data->flags & MMC_DATA_READ)
368 sdhci_read_block_pio(host);
369 else
370 sdhci_write_block_pio(host);
371
372 host->blocks--;
373 if (host->blocks == 0)
374 break;
375 }
376
377 DBG("PIO transfer complete.\n");
378 }
379
380 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
381 {
382 local_irq_save(*flags);
383 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
384 }
385
386 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
387 {
388 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
389 local_irq_restore(*flags);
390 }
391
392 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
393 {
394 __le32 *dataddr = (__le32 __force *)(desc + 4);
395 __le16 *cmdlen = (__le16 __force *)desc;
396
397 /* SDHCI specification says ADMA descriptors should be 4 byte
398 * aligned, so using 16 or 32bit operations should be safe. */
399
400 cmdlen[0] = cpu_to_le16(cmd);
401 cmdlen[1] = cpu_to_le16(len);
402
403 dataddr[0] = cpu_to_le32(addr);
404 }
405
406 static int sdhci_adma_table_pre(struct sdhci_host *host,
407 struct mmc_data *data)
408 {
409 int direction;
410
411 u8 *desc;
412 u8 *align;
413 dma_addr_t addr;
414 dma_addr_t align_addr;
415 int len, offset;
416
417 struct scatterlist *sg;
418 int i;
419 char *buffer;
420 unsigned long flags;
421
422 /*
423 * The spec does not specify endianness of descriptor table.
424 * We currently guess that it is LE.
425 */
426
427 if (data->flags & MMC_DATA_READ)
428 direction = DMA_FROM_DEVICE;
429 else
430 direction = DMA_TO_DEVICE;
431
432 /*
433 * The ADMA descriptor table is mapped further down as we
434 * need to fill it with data first.
435 */
436
437 host->align_addr = dma_map_single(mmc_dev(host->mmc),
438 host->align_buffer, 128 * 4, direction);
439 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
440 goto fail;
441 BUG_ON(host->align_addr & 0x3);
442
443 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
444 data->sg, data->sg_len, direction);
445 if (host->sg_count == 0)
446 goto unmap_align;
447
448 desc = host->adma_desc;
449 align = host->align_buffer;
450
451 align_addr = host->align_addr;
452
453 for_each_sg(data->sg, sg, host->sg_count, i) {
454 addr = sg_dma_address(sg);
455 len = sg_dma_len(sg);
456
457 /*
458 * The SDHCI specification states that ADMA
459 * addresses must be 32-bit aligned. If they
460 * aren't, then we use a bounce buffer for
461 * the (up to three) bytes that screw up the
462 * alignment.
463 */
464 offset = (4 - (addr & 0x3)) & 0x3;
465 if (offset) {
466 if (data->flags & MMC_DATA_WRITE) {
467 buffer = sdhci_kmap_atomic(sg, &flags);
468 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
469 memcpy(align, buffer, offset);
470 sdhci_kunmap_atomic(buffer, &flags);
471 }
472
473 /* tran, valid */
474 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
475
476 BUG_ON(offset > 65536);
477
478 align += 4;
479 align_addr += 4;
480
481 desc += 8;
482
483 addr += offset;
484 len -= offset;
485 }
486
487 BUG_ON(len > 65536);
488
489 /* tran, valid */
490 sdhci_set_adma_desc(desc, addr, len, 0x21);
491 desc += 8;
492
493 /*
494 * If this triggers then we have a calculation bug
495 * somewhere. :/
496 */
497 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
498 }
499
500 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
501 /*
502 * Mark the last descriptor as the terminating descriptor
503 */
504 if (desc != host->adma_desc) {
505 desc -= 8;
506 desc[0] |= 0x2; /* end */
507 }
508 } else {
509 /*
510 * Add a terminating entry.
511 */
512
513 /* nop, end, valid */
514 sdhci_set_adma_desc(desc, 0, 0, 0x3);
515 }
516
517 /*
518 * Resync align buffer as we might have changed it.
519 */
520 if (data->flags & MMC_DATA_WRITE) {
521 dma_sync_single_for_device(mmc_dev(host->mmc),
522 host->align_addr, 128 * 4, direction);
523 }
524
525 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
526 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
527 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
528 goto unmap_entries;
529 BUG_ON(host->adma_addr & 0x3);
530
531 return 0;
532
533 unmap_entries:
534 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
535 data->sg_len, direction);
536 unmap_align:
537 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
538 128 * 4, direction);
539 fail:
540 return -EINVAL;
541 }
542
543 static void sdhci_adma_table_post(struct sdhci_host *host,
544 struct mmc_data *data)
545 {
546 int direction;
547
548 struct scatterlist *sg;
549 int i, size;
550 u8 *align;
551 char *buffer;
552 unsigned long flags;
553
554 if (data->flags & MMC_DATA_READ)
555 direction = DMA_FROM_DEVICE;
556 else
557 direction = DMA_TO_DEVICE;
558
559 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
560 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
561
562 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
563 128 * 4, direction);
564
565 if (data->flags & MMC_DATA_READ) {
566 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
567 data->sg_len, direction);
568
569 align = host->align_buffer;
570
571 for_each_sg(data->sg, sg, host->sg_count, i) {
572 if (sg_dma_address(sg) & 0x3) {
573 size = 4 - (sg_dma_address(sg) & 0x3);
574
575 buffer = sdhci_kmap_atomic(sg, &flags);
576 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
577 memcpy(buffer, align, size);
578 sdhci_kunmap_atomic(buffer, &flags);
579
580 align += 4;
581 }
582 }
583 }
584
585 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
586 data->sg_len, direction);
587 }
588
589 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
590 {
591 u8 count;
592 unsigned target_timeout, current_timeout;
593
594 /*
595 * If the host controller provides us with an incorrect timeout
596 * value, just skip the check and use 0xE. The hardware may take
597 * longer to time out, but that's much better than having a too-short
598 * timeout value.
599 */
600 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
601 return 0xE;
602
603 /* timeout in us */
604 target_timeout = data->timeout_ns / 1000 +
605 data->timeout_clks / host->clock;
606
607 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
608 host->timeout_clk = host->clock / 1000;
609
610 /*
611 * Figure out needed cycles.
612 * We do this in steps in order to fit inside a 32 bit int.
613 * The first step is the minimum timeout, which will have a
614 * minimum resolution of 6 bits:
615 * (1) 2^13*1000 > 2^22,
616 * (2) host->timeout_clk < 2^16
617 * =>
618 * (1) / (2) > 2^6
619 */
620 count = 0;
621 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
622 while (current_timeout < target_timeout) {
623 count++;
624 current_timeout <<= 1;
625 if (count >= 0xF)
626 break;
627 }
628
629 if (count >= 0xF) {
630 printk(KERN_WARNING "%s: Too large timeout requested!\n",
631 mmc_hostname(host->mmc));
632 count = 0xE;
633 }
634
635 return count;
636 }
637
638 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
639 {
640 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
641 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
642
643 if (host->flags & SDHCI_REQ_USE_DMA)
644 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
645 else
646 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
647 }
648
649 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
650 {
651 u8 count;
652 u8 ctrl;
653 int ret;
654
655 WARN_ON(host->data);
656
657 if (data == NULL)
658 return;
659
660 /* Sanity checks */
661 BUG_ON(data->blksz * data->blocks > 524288);
662 BUG_ON(data->blksz > host->mmc->max_blk_size);
663 BUG_ON(data->blocks > 65535);
664
665 host->data = data;
666 host->data_early = 0;
667
668 count = sdhci_calc_timeout(host, data);
669 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
670
671 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
672 host->flags |= SDHCI_REQ_USE_DMA;
673
674 /*
675 * FIXME: This doesn't account for merging when mapping the
676 * scatterlist.
677 */
678 if (host->flags & SDHCI_REQ_USE_DMA) {
679 int broken, i;
680 struct scatterlist *sg;
681
682 broken = 0;
683 if (host->flags & SDHCI_USE_ADMA) {
684 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
685 broken = 1;
686 } else {
687 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
688 broken = 1;
689 }
690
691 if (unlikely(broken)) {
692 for_each_sg(data->sg, sg, data->sg_len, i) {
693 if (sg->length & 0x3) {
694 DBG("Reverting to PIO because of "
695 "transfer size (%d)\n",
696 sg->length);
697 host->flags &= ~SDHCI_REQ_USE_DMA;
698 break;
699 }
700 }
701 }
702 }
703
704 /*
705 * The assumption here being that alignment is the same after
706 * translation to device address space.
707 */
708 if (host->flags & SDHCI_REQ_USE_DMA) {
709 int broken, i;
710 struct scatterlist *sg;
711
712 broken = 0;
713 if (host->flags & SDHCI_USE_ADMA) {
714 /*
715 * As we use 3 byte chunks to work around
716 * alignment problems, we need to check this
717 * quirk.
718 */
719 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
720 broken = 1;
721 } else {
722 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
723 broken = 1;
724 }
725
726 if (unlikely(broken)) {
727 for_each_sg(data->sg, sg, data->sg_len, i) {
728 if (sg->offset & 0x3) {
729 DBG("Reverting to PIO because of "
730 "bad alignment\n");
731 host->flags &= ~SDHCI_REQ_USE_DMA;
732 break;
733 }
734 }
735 }
736 }
737
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 if (host->flags & SDHCI_USE_ADMA) {
740 ret = sdhci_adma_table_pre(host, data);
741 if (ret) {
742 /*
743 * This only happens when someone fed
744 * us an invalid request.
745 */
746 WARN_ON(1);
747 host->flags &= ~SDHCI_REQ_USE_DMA;
748 } else {
749 sdhci_writel(host, host->adma_addr,
750 SDHCI_ADMA_ADDRESS);
751 }
752 } else {
753 int sg_cnt;
754
755 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
756 data->sg, data->sg_len,
757 (data->flags & MMC_DATA_READ) ?
758 DMA_FROM_DEVICE :
759 DMA_TO_DEVICE);
760 if (sg_cnt == 0) {
761 /*
762 * This only happens when someone fed
763 * us an invalid request.
764 */
765 WARN_ON(1);
766 host->flags &= ~SDHCI_REQ_USE_DMA;
767 } else {
768 WARN_ON(sg_cnt != 1);
769 sdhci_writel(host, sg_dma_address(data->sg),
770 SDHCI_DMA_ADDRESS);
771 }
772 }
773 }
774
775 /*
776 * Always adjust the DMA selection as some controllers
777 * (e.g. JMicron) can't do PIO properly when the selection
778 * is ADMA.
779 */
780 if (host->version >= SDHCI_SPEC_200) {
781 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
782 ctrl &= ~SDHCI_CTRL_DMA_MASK;
783 if ((host->flags & SDHCI_REQ_USE_DMA) &&
784 (host->flags & SDHCI_USE_ADMA))
785 ctrl |= SDHCI_CTRL_ADMA32;
786 else
787 ctrl |= SDHCI_CTRL_SDMA;
788 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
789 }
790
791 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
792 int flags;
793
794 flags = SG_MITER_ATOMIC;
795 if (host->data->flags & MMC_DATA_READ)
796 flags |= SG_MITER_TO_SG;
797 else
798 flags |= SG_MITER_FROM_SG;
799 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
800 host->blocks = data->blocks;
801 }
802
803 sdhci_set_transfer_irqs(host);
804
805 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
806 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
807 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
808 }
809
810 static void sdhci_set_transfer_mode(struct sdhci_host *host,
811 struct mmc_data *data)
812 {
813 u16 mode;
814
815 if (data == NULL)
816 return;
817
818 WARN_ON(!host->data);
819
820 mode = SDHCI_TRNS_BLK_CNT_EN;
821 if (data->blocks > 1) {
822 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
823 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
824 else
825 mode |= SDHCI_TRNS_MULTI;
826 }
827 if (data->flags & MMC_DATA_READ)
828 mode |= SDHCI_TRNS_READ;
829 if (host->flags & SDHCI_REQ_USE_DMA)
830 mode |= SDHCI_TRNS_DMA;
831
832 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
833 }
834
835 static void sdhci_finish_data(struct sdhci_host *host)
836 {
837 struct mmc_data *data;
838
839 BUG_ON(!host->data);
840
841 data = host->data;
842 host->data = NULL;
843
844 if (host->flags & SDHCI_REQ_USE_DMA) {
845 if (host->flags & SDHCI_USE_ADMA)
846 sdhci_adma_table_post(host, data);
847 else {
848 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
849 data->sg_len, (data->flags & MMC_DATA_READ) ?
850 DMA_FROM_DEVICE : DMA_TO_DEVICE);
851 }
852 }
853
854 /*
855 * The specification states that the block count register must
856 * be updated, but it does not specify at what point in the
857 * data flow. That makes the register entirely useless to read
858 * back so we have to assume that nothing made it to the card
859 * in the event of an error.
860 */
861 if (data->error)
862 data->bytes_xfered = 0;
863 else
864 data->bytes_xfered = data->blksz * data->blocks;
865
866 if (data->stop) {
867 /*
868 * The controller needs a reset of internal state machines
869 * upon error conditions.
870 */
871 if (data->error) {
872 sdhci_reset(host, SDHCI_RESET_CMD);
873 sdhci_reset(host, SDHCI_RESET_DATA);
874 }
875
876 sdhci_send_command(host, data->stop);
877 } else
878 tasklet_schedule(&host->finish_tasklet);
879 }
880
881 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
882 {
883 int flags;
884 u32 mask;
885 unsigned long timeout;
886
887 WARN_ON(host->cmd);
888
889 /* Wait max 10 ms */
890 timeout = 10;
891
892 mask = SDHCI_CMD_INHIBIT;
893 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
894 mask |= SDHCI_DATA_INHIBIT;
895
896 /* We shouldn't wait for data inihibit for stop commands, even
897 though they might use busy signaling */
898 if (host->mrq->data && (cmd == host->mrq->data->stop))
899 mask &= ~SDHCI_DATA_INHIBIT;
900
901 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
902 if (timeout == 0) {
903 printk(KERN_ERR "%s: Controller never released "
904 "inhibit bit(s).\n", mmc_hostname(host->mmc));
905 sdhci_dumpregs(host);
906 cmd->error = -EIO;
907 tasklet_schedule(&host->finish_tasklet);
908 return;
909 }
910 timeout--;
911 mdelay(1);
912 }
913
914 mod_timer(&host->timer, jiffies + 10 * HZ);
915
916 host->cmd = cmd;
917
918 sdhci_prepare_data(host, cmd->data);
919
920 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
921
922 sdhci_set_transfer_mode(host, cmd->data);
923
924 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
925 printk(KERN_ERR "%s: Unsupported response type!\n",
926 mmc_hostname(host->mmc));
927 cmd->error = -EINVAL;
928 tasklet_schedule(&host->finish_tasklet);
929 return;
930 }
931
932 if (!(cmd->flags & MMC_RSP_PRESENT))
933 flags = SDHCI_CMD_RESP_NONE;
934 else if (cmd->flags & MMC_RSP_136)
935 flags = SDHCI_CMD_RESP_LONG;
936 else if (cmd->flags & MMC_RSP_BUSY)
937 flags = SDHCI_CMD_RESP_SHORT_BUSY;
938 else
939 flags = SDHCI_CMD_RESP_SHORT;
940
941 if (cmd->flags & MMC_RSP_CRC)
942 flags |= SDHCI_CMD_CRC;
943 if (cmd->flags & MMC_RSP_OPCODE)
944 flags |= SDHCI_CMD_INDEX;
945 if (cmd->data)
946 flags |= SDHCI_CMD_DATA;
947
948 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
949 }
950
951 static void sdhci_finish_command(struct sdhci_host *host)
952 {
953 int i;
954
955 BUG_ON(host->cmd == NULL);
956
957 if (host->cmd->flags & MMC_RSP_PRESENT) {
958 if (host->cmd->flags & MMC_RSP_136) {
959 /* CRC is stripped so we need to do some shifting. */
960 for (i = 0;i < 4;i++) {
961 host->cmd->resp[i] = sdhci_readl(host,
962 SDHCI_RESPONSE + (3-i)*4) << 8;
963 if (i != 3)
964 host->cmd->resp[i] |=
965 sdhci_readb(host,
966 SDHCI_RESPONSE + (3-i)*4-1);
967 }
968 } else {
969 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
970 }
971 }
972
973 host->cmd->error = 0;
974
975 if (host->data && host->data_early)
976 sdhci_finish_data(host);
977
978 if (!host->cmd->data)
979 tasklet_schedule(&host->finish_tasklet);
980
981 host->cmd = NULL;
982 }
983
984 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
985 {
986 int div;
987 u16 clk;
988 unsigned long timeout;
989
990 if (clock == host->clock)
991 return;
992
993 if (host->ops->set_clock) {
994 host->ops->set_clock(host, clock);
995 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
996 return;
997 }
998
999 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1000
1001 if (clock == 0)
1002 goto out;
1003
1004 if (host->version >= SDHCI_SPEC_300) {
1005 /* Version 3.00 divisors must be a multiple of 2. */
1006 if (host->max_clk <= clock)
1007 div = 1;
1008 else {
1009 for (div = 2; div < 2046; div += 2) {
1010 if ((host->max_clk / div) <= clock)
1011 break;
1012 }
1013 }
1014 } else {
1015 /* Version 2.00 divisors must be a power of 2. */
1016 for (div = 1; div < 256; div *= 2) {
1017 if ((host->max_clk / div) <= clock)
1018 break;
1019 }
1020 }
1021 div >>= 1;
1022
1023 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1024 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1025 << SDHCI_DIVIDER_HI_SHIFT;
1026 clk |= SDHCI_CLOCK_INT_EN;
1027 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1028
1029 /* Wait max 20 ms */
1030 timeout = 20;
1031 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1032 & SDHCI_CLOCK_INT_STABLE)) {
1033 if (timeout == 0) {
1034 printk(KERN_ERR "%s: Internal clock never "
1035 "stabilised.\n", mmc_hostname(host->mmc));
1036 sdhci_dumpregs(host);
1037 return;
1038 }
1039 timeout--;
1040 mdelay(1);
1041 }
1042
1043 clk |= SDHCI_CLOCK_CARD_EN;
1044 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1045
1046 out:
1047 host->clock = clock;
1048 }
1049
1050 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1051 {
1052 u8 pwr;
1053
1054 if (power == (unsigned short)-1)
1055 pwr = 0;
1056 else {
1057 switch (1 << power) {
1058 case MMC_VDD_165_195:
1059 pwr = SDHCI_POWER_180;
1060 break;
1061 case MMC_VDD_29_30:
1062 case MMC_VDD_30_31:
1063 pwr = SDHCI_POWER_300;
1064 break;
1065 case MMC_VDD_32_33:
1066 case MMC_VDD_33_34:
1067 pwr = SDHCI_POWER_330;
1068 break;
1069 default:
1070 BUG();
1071 }
1072 }
1073
1074 if (host->pwr == pwr)
1075 return;
1076
1077 host->pwr = pwr;
1078
1079 if (pwr == 0) {
1080 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1081 return;
1082 }
1083
1084 /*
1085 * Spec says that we should clear the power reg before setting
1086 * a new value. Some controllers don't seem to like this though.
1087 */
1088 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1089 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1090
1091 /*
1092 * At least the Marvell CaFe chip gets confused if we set the voltage
1093 * and set turn on power at the same time, so set the voltage first.
1094 */
1095 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1096 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1097
1098 pwr |= SDHCI_POWER_ON;
1099
1100 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1101
1102 /*
1103 * Some controllers need an extra 10ms delay of 10ms before they
1104 * can apply clock after applying power
1105 */
1106 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1107 mdelay(10);
1108 }
1109
1110 /*****************************************************************************\
1111 * *
1112 * MMC callbacks *
1113 * *
1114 \*****************************************************************************/
1115
1116 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1117 {
1118 struct sdhci_host *host;
1119 bool present;
1120 unsigned long flags;
1121
1122 host = mmc_priv(mmc);
1123
1124 spin_lock_irqsave(&host->lock, flags);
1125
1126 WARN_ON(host->mrq != NULL);
1127
1128 #ifndef SDHCI_USE_LEDS_CLASS
1129 sdhci_activate_led(host);
1130 #endif
1131 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1132 if (mrq->stop) {
1133 mrq->data->stop = NULL;
1134 mrq->stop = NULL;
1135 }
1136 }
1137
1138 host->mrq = mrq;
1139
1140 /* If polling, assume that the card is always present. */
1141 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1142 present = true;
1143 else
1144 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1145 SDHCI_CARD_PRESENT;
1146
1147 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1148 host->mrq->cmd->error = -ENOMEDIUM;
1149 tasklet_schedule(&host->finish_tasklet);
1150 } else
1151 sdhci_send_command(host, mrq->cmd);
1152
1153 mmiowb();
1154 spin_unlock_irqrestore(&host->lock, flags);
1155 }
1156
1157 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1158 {
1159 struct sdhci_host *host;
1160 unsigned long flags;
1161 u8 ctrl;
1162
1163 host = mmc_priv(mmc);
1164
1165 spin_lock_irqsave(&host->lock, flags);
1166
1167 if (host->flags & SDHCI_DEVICE_DEAD)
1168 goto out;
1169
1170 /*
1171 * Reset the chip on each power off.
1172 * Should clear out any weird states.
1173 */
1174 if (ios->power_mode == MMC_POWER_OFF) {
1175 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1176 sdhci_reinit(host);
1177 }
1178
1179 sdhci_set_clock(host, ios->clock);
1180
1181 if (ios->power_mode == MMC_POWER_OFF)
1182 sdhci_set_power(host, -1);
1183 else
1184 sdhci_set_power(host, ios->vdd);
1185
1186 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1187
1188 if (ios->bus_width == MMC_BUS_WIDTH_8)
1189 ctrl |= SDHCI_CTRL_8BITBUS;
1190 else
1191 ctrl &= ~SDHCI_CTRL_8BITBUS;
1192
1193 if (ios->bus_width == MMC_BUS_WIDTH_4)
1194 ctrl |= SDHCI_CTRL_4BITBUS;
1195 else
1196 ctrl &= ~SDHCI_CTRL_4BITBUS;
1197
1198 if (ios->timing == MMC_TIMING_SD_HS &&
1199 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1200 ctrl |= SDHCI_CTRL_HISPD;
1201 else
1202 ctrl &= ~SDHCI_CTRL_HISPD;
1203
1204 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1205
1206 /*
1207 * Some (ENE) controllers go apeshit on some ios operation,
1208 * signalling timeout and CRC errors even on CMD0. Resetting
1209 * it on each ios seems to solve the problem.
1210 */
1211 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1212 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1213
1214 out:
1215 mmiowb();
1216 spin_unlock_irqrestore(&host->lock, flags);
1217 }
1218
1219 static int sdhci_get_ro(struct mmc_host *mmc)
1220 {
1221 struct sdhci_host *host;
1222 unsigned long flags;
1223 int present;
1224
1225 host = mmc_priv(mmc);
1226
1227 spin_lock_irqsave(&host->lock, flags);
1228
1229 if (host->flags & SDHCI_DEVICE_DEAD)
1230 present = 0;
1231 else
1232 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1233
1234 spin_unlock_irqrestore(&host->lock, flags);
1235
1236 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1237 return !!(present & SDHCI_WRITE_PROTECT);
1238 return !(present & SDHCI_WRITE_PROTECT);
1239 }
1240
1241 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1242 {
1243 struct sdhci_host *host;
1244 unsigned long flags;
1245
1246 host = mmc_priv(mmc);
1247
1248 spin_lock_irqsave(&host->lock, flags);
1249
1250 if (host->flags & SDHCI_DEVICE_DEAD)
1251 goto out;
1252
1253 if (enable)
1254 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1255 else
1256 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1257 out:
1258 mmiowb();
1259
1260 spin_unlock_irqrestore(&host->lock, flags);
1261 }
1262
1263 static const struct mmc_host_ops sdhci_ops = {
1264 .request = sdhci_request,
1265 .set_ios = sdhci_set_ios,
1266 .get_ro = sdhci_get_ro,
1267 .enable_sdio_irq = sdhci_enable_sdio_irq,
1268 };
1269
1270 /*****************************************************************************\
1271 * *
1272 * Tasklets *
1273 * *
1274 \*****************************************************************************/
1275
1276 static void sdhci_tasklet_card(unsigned long param)
1277 {
1278 struct sdhci_host *host;
1279 unsigned long flags;
1280
1281 host = (struct sdhci_host*)param;
1282
1283 spin_lock_irqsave(&host->lock, flags);
1284
1285 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1286 if (host->mrq) {
1287 printk(KERN_ERR "%s: Card removed during transfer!\n",
1288 mmc_hostname(host->mmc));
1289 printk(KERN_ERR "%s: Resetting controller.\n",
1290 mmc_hostname(host->mmc));
1291
1292 sdhci_reset(host, SDHCI_RESET_CMD);
1293 sdhci_reset(host, SDHCI_RESET_DATA);
1294
1295 host->mrq->cmd->error = -ENOMEDIUM;
1296 tasklet_schedule(&host->finish_tasklet);
1297 }
1298 }
1299
1300 spin_unlock_irqrestore(&host->lock, flags);
1301
1302 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1303 }
1304
1305 static void sdhci_tasklet_finish(unsigned long param)
1306 {
1307 struct sdhci_host *host;
1308 unsigned long flags;
1309 struct mmc_request *mrq;
1310
1311 host = (struct sdhci_host*)param;
1312
1313 spin_lock_irqsave(&host->lock, flags);
1314
1315 del_timer(&host->timer);
1316
1317 mrq = host->mrq;
1318
1319 /*
1320 * The controller needs a reset of internal state machines
1321 * upon error conditions.
1322 */
1323 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1324 (mrq->cmd->error ||
1325 (mrq->data && (mrq->data->error ||
1326 (mrq->data->stop && mrq->data->stop->error))) ||
1327 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1328
1329 /* Some controllers need this kick or reset won't work here */
1330 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1331 unsigned int clock;
1332
1333 /* This is to force an update */
1334 clock = host->clock;
1335 host->clock = 0;
1336 sdhci_set_clock(host, clock);
1337 }
1338
1339 /* Spec says we should do both at the same time, but Ricoh
1340 controllers do not like that. */
1341 sdhci_reset(host, SDHCI_RESET_CMD);
1342 sdhci_reset(host, SDHCI_RESET_DATA);
1343 }
1344
1345 host->mrq = NULL;
1346 host->cmd = NULL;
1347 host->data = NULL;
1348
1349 #ifndef SDHCI_USE_LEDS_CLASS
1350 sdhci_deactivate_led(host);
1351 #endif
1352
1353 mmiowb();
1354 spin_unlock_irqrestore(&host->lock, flags);
1355
1356 mmc_request_done(host->mmc, mrq);
1357 }
1358
1359 static void sdhci_timeout_timer(unsigned long data)
1360 {
1361 struct sdhci_host *host;
1362 unsigned long flags;
1363
1364 host = (struct sdhci_host*)data;
1365
1366 spin_lock_irqsave(&host->lock, flags);
1367
1368 if (host->mrq) {
1369 printk(KERN_ERR "%s: Timeout waiting for hardware "
1370 "interrupt.\n", mmc_hostname(host->mmc));
1371 sdhci_dumpregs(host);
1372
1373 if (host->data) {
1374 host->data->error = -ETIMEDOUT;
1375 sdhci_finish_data(host);
1376 } else {
1377 if (host->cmd)
1378 host->cmd->error = -ETIMEDOUT;
1379 else
1380 host->mrq->cmd->error = -ETIMEDOUT;
1381
1382 tasklet_schedule(&host->finish_tasklet);
1383 }
1384 }
1385
1386 mmiowb();
1387 spin_unlock_irqrestore(&host->lock, flags);
1388 }
1389
1390 /*****************************************************************************\
1391 * *
1392 * Interrupt handling *
1393 * *
1394 \*****************************************************************************/
1395
1396 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1397 {
1398 BUG_ON(intmask == 0);
1399
1400 if (!host->cmd) {
1401 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1402 "though no command operation was in progress.\n",
1403 mmc_hostname(host->mmc), (unsigned)intmask);
1404 sdhci_dumpregs(host);
1405 return;
1406 }
1407
1408 if (intmask & SDHCI_INT_TIMEOUT)
1409 host->cmd->error = -ETIMEDOUT;
1410 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1411 SDHCI_INT_INDEX))
1412 host->cmd->error = -EILSEQ;
1413
1414 if (host->cmd->error) {
1415 tasklet_schedule(&host->finish_tasklet);
1416 return;
1417 }
1418
1419 /*
1420 * The host can send and interrupt when the busy state has
1421 * ended, allowing us to wait without wasting CPU cycles.
1422 * Unfortunately this is overloaded on the "data complete"
1423 * interrupt, so we need to take some care when handling
1424 * it.
1425 *
1426 * Note: The 1.0 specification is a bit ambiguous about this
1427 * feature so there might be some problems with older
1428 * controllers.
1429 */
1430 if (host->cmd->flags & MMC_RSP_BUSY) {
1431 if (host->cmd->data)
1432 DBG("Cannot wait for busy signal when also "
1433 "doing a data transfer");
1434 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1435 return;
1436
1437 /* The controller does not support the end-of-busy IRQ,
1438 * fall through and take the SDHCI_INT_RESPONSE */
1439 }
1440
1441 if (intmask & SDHCI_INT_RESPONSE)
1442 sdhci_finish_command(host);
1443 }
1444
1445 #ifdef CONFIG_MMC_DEBUG
1446 static void sdhci_show_adma_error(struct sdhci_host *host)
1447 {
1448 const char *name = mmc_hostname(host->mmc);
1449 u8 *desc = host->adma_desc;
1450 __le32 *dma;
1451 __le16 *len;
1452 u8 attr;
1453
1454 sdhci_dumpregs(host);
1455
1456 while (true) {
1457 dma = (__le32 *)(desc + 4);
1458 len = (__le16 *)(desc + 2);
1459 attr = *desc;
1460
1461 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1462 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1463
1464 desc += 8;
1465
1466 if (attr & 2)
1467 break;
1468 }
1469 }
1470 #else
1471 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1472 #endif
1473
1474 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1475 {
1476 BUG_ON(intmask == 0);
1477
1478 if (!host->data) {
1479 /*
1480 * The "data complete" interrupt is also used to
1481 * indicate that a busy state has ended. See comment
1482 * above in sdhci_cmd_irq().
1483 */
1484 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1485 if (intmask & SDHCI_INT_DATA_END) {
1486 sdhci_finish_command(host);
1487 return;
1488 }
1489 }
1490
1491 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1492 "though no data operation was in progress.\n",
1493 mmc_hostname(host->mmc), (unsigned)intmask);
1494 sdhci_dumpregs(host);
1495
1496 return;
1497 }
1498
1499 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1500 host->data->error = -ETIMEDOUT;
1501 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1502 host->data->error = -EILSEQ;
1503 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1504 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1505 sdhci_show_adma_error(host);
1506 host->data->error = -EIO;
1507 }
1508
1509 if (host->data->error)
1510 sdhci_finish_data(host);
1511 else {
1512 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1513 sdhci_transfer_pio(host);
1514
1515 /*
1516 * We currently don't do anything fancy with DMA
1517 * boundaries, but as we can't disable the feature
1518 * we need to at least restart the transfer.
1519 */
1520 if (intmask & SDHCI_INT_DMA_END)
1521 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1522 SDHCI_DMA_ADDRESS);
1523
1524 if (intmask & SDHCI_INT_DATA_END) {
1525 if (host->cmd) {
1526 /*
1527 * Data managed to finish before the
1528 * command completed. Make sure we do
1529 * things in the proper order.
1530 */
1531 host->data_early = 1;
1532 } else {
1533 sdhci_finish_data(host);
1534 }
1535 }
1536 }
1537 }
1538
1539 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1540 {
1541 irqreturn_t result;
1542 struct sdhci_host* host = dev_id;
1543 u32 intmask;
1544 int cardint = 0;
1545
1546 spin_lock(&host->lock);
1547
1548 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1549
1550 if (!intmask || intmask == 0xffffffff) {
1551 result = IRQ_NONE;
1552 goto out;
1553 }
1554
1555 DBG("*** %s got interrupt: 0x%08x\n",
1556 mmc_hostname(host->mmc), intmask);
1557
1558 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1559 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1560 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1561 tasklet_schedule(&host->card_tasklet);
1562 }
1563
1564 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1565
1566 if (intmask & SDHCI_INT_CMD_MASK) {
1567 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1568 SDHCI_INT_STATUS);
1569 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1570 }
1571
1572 if (intmask & SDHCI_INT_DATA_MASK) {
1573 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1574 SDHCI_INT_STATUS);
1575 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1576 }
1577
1578 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1579
1580 intmask &= ~SDHCI_INT_ERROR;
1581
1582 if (intmask & SDHCI_INT_BUS_POWER) {
1583 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1584 mmc_hostname(host->mmc));
1585 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1586 }
1587
1588 intmask &= ~SDHCI_INT_BUS_POWER;
1589
1590 if (intmask & SDHCI_INT_CARD_INT)
1591 cardint = 1;
1592
1593 intmask &= ~SDHCI_INT_CARD_INT;
1594
1595 if (intmask) {
1596 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1597 mmc_hostname(host->mmc), intmask);
1598 sdhci_dumpregs(host);
1599
1600 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1601 }
1602
1603 result = IRQ_HANDLED;
1604
1605 mmiowb();
1606 out:
1607 spin_unlock(&host->lock);
1608
1609 /*
1610 * We have to delay this as it calls back into the driver.
1611 */
1612 if (cardint)
1613 mmc_signal_sdio_irq(host->mmc);
1614
1615 return result;
1616 }
1617
1618 /*****************************************************************************\
1619 * *
1620 * Suspend/resume *
1621 * *
1622 \*****************************************************************************/
1623
1624 #ifdef CONFIG_PM
1625
1626 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1627 {
1628 int ret;
1629
1630 sdhci_disable_card_detection(host);
1631
1632 ret = mmc_suspend_host(host->mmc);
1633 if (ret)
1634 return ret;
1635
1636 free_irq(host->irq, host);
1637
1638 if (host->vmmc)
1639 ret = regulator_disable(host->vmmc);
1640
1641 return ret;
1642 }
1643
1644 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1645
1646 int sdhci_resume_host(struct sdhci_host *host)
1647 {
1648 int ret;
1649
1650 if (host->vmmc) {
1651 int ret = regulator_enable(host->vmmc);
1652 if (ret)
1653 return ret;
1654 }
1655
1656
1657 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1658 if (host->ops->enable_dma)
1659 host->ops->enable_dma(host);
1660 }
1661
1662 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1663 mmc_hostname(host->mmc), host);
1664 if (ret)
1665 return ret;
1666
1667 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1668 mmiowb();
1669
1670 ret = mmc_resume_host(host->mmc);
1671 sdhci_enable_card_detection(host);
1672
1673 return ret;
1674 }
1675
1676 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1677
1678 #endif /* CONFIG_PM */
1679
1680 /*****************************************************************************\
1681 * *
1682 * Device allocation/registration *
1683 * *
1684 \*****************************************************************************/
1685
1686 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1687 size_t priv_size)
1688 {
1689 struct mmc_host *mmc;
1690 struct sdhci_host *host;
1691
1692 WARN_ON(dev == NULL);
1693
1694 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1695 if (!mmc)
1696 return ERR_PTR(-ENOMEM);
1697
1698 host = mmc_priv(mmc);
1699 host->mmc = mmc;
1700
1701 return host;
1702 }
1703
1704 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1705
1706 int sdhci_add_host(struct sdhci_host *host)
1707 {
1708 struct mmc_host *mmc;
1709 unsigned int caps;
1710 int ret;
1711
1712 WARN_ON(host == NULL);
1713 if (host == NULL)
1714 return -EINVAL;
1715
1716 mmc = host->mmc;
1717
1718 if (debug_quirks)
1719 host->quirks = debug_quirks;
1720
1721 sdhci_reset(host, SDHCI_RESET_ALL);
1722
1723 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1724 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1725 >> SDHCI_SPEC_VER_SHIFT;
1726 if (host->version > SDHCI_SPEC_300) {
1727 printk(KERN_ERR "%s: Unknown controller version (%d). "
1728 "You may experience problems.\n", mmc_hostname(mmc),
1729 host->version);
1730 }
1731
1732 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1733 sdhci_readl(host, SDHCI_CAPABILITIES);
1734
1735 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1736 host->flags |= SDHCI_USE_SDMA;
1737 else if (!(caps & SDHCI_CAN_DO_SDMA))
1738 DBG("Controller doesn't have SDMA capability\n");
1739 else
1740 host->flags |= SDHCI_USE_SDMA;
1741
1742 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1743 (host->flags & SDHCI_USE_SDMA)) {
1744 DBG("Disabling DMA as it is marked broken\n");
1745 host->flags &= ~SDHCI_USE_SDMA;
1746 }
1747
1748 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1749 host->flags |= SDHCI_USE_ADMA;
1750
1751 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1752 (host->flags & SDHCI_USE_ADMA)) {
1753 DBG("Disabling ADMA as it is marked broken\n");
1754 host->flags &= ~SDHCI_USE_ADMA;
1755 }
1756
1757 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1758 if (host->ops->enable_dma) {
1759 if (host->ops->enable_dma(host)) {
1760 printk(KERN_WARNING "%s: No suitable DMA "
1761 "available. Falling back to PIO.\n",
1762 mmc_hostname(mmc));
1763 host->flags &=
1764 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1765 }
1766 }
1767 }
1768
1769 if (host->flags & SDHCI_USE_ADMA) {
1770 /*
1771 * We need to allocate descriptors for all sg entries
1772 * (128) and potentially one alignment transfer for
1773 * each of those entries.
1774 */
1775 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1776 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1777 if (!host->adma_desc || !host->align_buffer) {
1778 kfree(host->adma_desc);
1779 kfree(host->align_buffer);
1780 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1781 "buffers. Falling back to standard DMA.\n",
1782 mmc_hostname(mmc));
1783 host->flags &= ~SDHCI_USE_ADMA;
1784 }
1785 }
1786
1787 /*
1788 * If we use DMA, then it's up to the caller to set the DMA
1789 * mask, but PIO does not need the hw shim so we set a new
1790 * mask here in that case.
1791 */
1792 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1793 host->dma_mask = DMA_BIT_MASK(64);
1794 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1795 }
1796
1797 if (host->version >= SDHCI_SPEC_300)
1798 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
1799 >> SDHCI_CLOCK_BASE_SHIFT;
1800 else
1801 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
1802 >> SDHCI_CLOCK_BASE_SHIFT;
1803
1804 host->max_clk *= 1000000;
1805 if (host->max_clk == 0 || host->quirks &
1806 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1807 if (!host->ops->get_max_clock) {
1808 printk(KERN_ERR
1809 "%s: Hardware doesn't specify base clock "
1810 "frequency.\n", mmc_hostname(mmc));
1811 return -ENODEV;
1812 }
1813 host->max_clk = host->ops->get_max_clock(host);
1814 }
1815
1816 host->timeout_clk =
1817 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1818 if (host->timeout_clk == 0) {
1819 if (host->ops->get_timeout_clock) {
1820 host->timeout_clk = host->ops->get_timeout_clock(host);
1821 } else if (!(host->quirks &
1822 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1823 printk(KERN_ERR
1824 "%s: Hardware doesn't specify timeout clock "
1825 "frequency.\n", mmc_hostname(mmc));
1826 return -ENODEV;
1827 }
1828 }
1829 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1830 host->timeout_clk *= 1000;
1831
1832 /*
1833 * Set host parameters.
1834 */
1835 mmc->ops = &sdhci_ops;
1836 if (host->ops->get_min_clock)
1837 mmc->f_min = host->ops->get_min_clock(host);
1838 else
1839 mmc->f_min = host->max_clk / 256;
1840 mmc->f_max = host->max_clk;
1841 mmc->caps |= MMC_CAP_SDIO_IRQ;
1842
1843 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1844 mmc->caps |= MMC_CAP_4_BIT_DATA;
1845
1846 if (caps & SDHCI_CAN_DO_HISPD)
1847 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1848
1849 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1850 mmc->caps |= MMC_CAP_NEEDS_POLL;
1851
1852 mmc->ocr_avail = 0;
1853 if (caps & SDHCI_CAN_VDD_330)
1854 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1855 if (caps & SDHCI_CAN_VDD_300)
1856 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1857 if (caps & SDHCI_CAN_VDD_180)
1858 mmc->ocr_avail |= MMC_VDD_165_195;
1859
1860 if (mmc->ocr_avail == 0) {
1861 printk(KERN_ERR "%s: Hardware doesn't report any "
1862 "support voltages.\n", mmc_hostname(mmc));
1863 return -ENODEV;
1864 }
1865
1866 spin_lock_init(&host->lock);
1867
1868 /*
1869 * Maximum number of segments. Depends on if the hardware
1870 * can do scatter/gather or not.
1871 */
1872 if (host->flags & SDHCI_USE_ADMA)
1873 mmc->max_segs = 128;
1874 else if (host->flags & SDHCI_USE_SDMA)
1875 mmc->max_segs = 1;
1876 else /* PIO */
1877 mmc->max_segs = 128;
1878
1879 /*
1880 * Maximum number of sectors in one transfer. Limited by DMA boundary
1881 * size (512KiB).
1882 */
1883 mmc->max_req_size = 524288;
1884
1885 /*
1886 * Maximum segment size. Could be one segment with the maximum number
1887 * of bytes. When doing hardware scatter/gather, each entry cannot
1888 * be larger than 64 KiB though.
1889 */
1890 if (host->flags & SDHCI_USE_ADMA)
1891 mmc->max_seg_size = 65536;
1892 else
1893 mmc->max_seg_size = mmc->max_req_size;
1894
1895 /*
1896 * Maximum block size. This varies from controller to controller and
1897 * is specified in the capabilities register.
1898 */
1899 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1900 mmc->max_blk_size = 2;
1901 } else {
1902 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1903 SDHCI_MAX_BLOCK_SHIFT;
1904 if (mmc->max_blk_size >= 3) {
1905 printk(KERN_WARNING "%s: Invalid maximum block size, "
1906 "assuming 512 bytes\n", mmc_hostname(mmc));
1907 mmc->max_blk_size = 0;
1908 }
1909 }
1910
1911 mmc->max_blk_size = 512 << mmc->max_blk_size;
1912
1913 /*
1914 * Maximum block count.
1915 */
1916 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1917
1918 /*
1919 * Init tasklets.
1920 */
1921 tasklet_init(&host->card_tasklet,
1922 sdhci_tasklet_card, (unsigned long)host);
1923 tasklet_init(&host->finish_tasklet,
1924 sdhci_tasklet_finish, (unsigned long)host);
1925
1926 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1927
1928 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1929 mmc_hostname(mmc), host);
1930 if (ret)
1931 goto untasklet;
1932
1933 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1934 if (IS_ERR(host->vmmc)) {
1935 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1936 host->vmmc = NULL;
1937 } else {
1938 regulator_enable(host->vmmc);
1939 }
1940
1941 sdhci_init(host, 0);
1942
1943 #ifdef CONFIG_MMC_DEBUG
1944 sdhci_dumpregs(host);
1945 #endif
1946
1947 #ifdef SDHCI_USE_LEDS_CLASS
1948 snprintf(host->led_name, sizeof(host->led_name),
1949 "%s::", mmc_hostname(mmc));
1950 host->led.name = host->led_name;
1951 host->led.brightness = LED_OFF;
1952 host->led.default_trigger = mmc_hostname(mmc);
1953 host->led.brightness_set = sdhci_led_control;
1954
1955 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1956 if (ret)
1957 goto reset;
1958 #endif
1959
1960 mmiowb();
1961
1962 mmc_add_host(mmc);
1963
1964 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1965 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1966 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1967 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1968
1969 sdhci_enable_card_detection(host);
1970
1971 return 0;
1972
1973 #ifdef SDHCI_USE_LEDS_CLASS
1974 reset:
1975 sdhci_reset(host, SDHCI_RESET_ALL);
1976 free_irq(host->irq, host);
1977 #endif
1978 untasklet:
1979 tasklet_kill(&host->card_tasklet);
1980 tasklet_kill(&host->finish_tasklet);
1981
1982 return ret;
1983 }
1984
1985 EXPORT_SYMBOL_GPL(sdhci_add_host);
1986
1987 void sdhci_remove_host(struct sdhci_host *host, int dead)
1988 {
1989 unsigned long flags;
1990
1991 if (dead) {
1992 spin_lock_irqsave(&host->lock, flags);
1993
1994 host->flags |= SDHCI_DEVICE_DEAD;
1995
1996 if (host->mrq) {
1997 printk(KERN_ERR "%s: Controller removed during "
1998 " transfer!\n", mmc_hostname(host->mmc));
1999
2000 host->mrq->cmd->error = -ENOMEDIUM;
2001 tasklet_schedule(&host->finish_tasklet);
2002 }
2003
2004 spin_unlock_irqrestore(&host->lock, flags);
2005 }
2006
2007 sdhci_disable_card_detection(host);
2008
2009 mmc_remove_host(host->mmc);
2010
2011 #ifdef SDHCI_USE_LEDS_CLASS
2012 led_classdev_unregister(&host->led);
2013 #endif
2014
2015 if (!dead)
2016 sdhci_reset(host, SDHCI_RESET_ALL);
2017
2018 free_irq(host->irq, host);
2019
2020 del_timer_sync(&host->timer);
2021
2022 tasklet_kill(&host->card_tasklet);
2023 tasklet_kill(&host->finish_tasklet);
2024
2025 if (host->vmmc) {
2026 regulator_disable(host->vmmc);
2027 regulator_put(host->vmmc);
2028 }
2029
2030 kfree(host->adma_desc);
2031 kfree(host->align_buffer);
2032
2033 host->adma_desc = NULL;
2034 host->align_buffer = NULL;
2035 }
2036
2037 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2038
2039 void sdhci_free_host(struct sdhci_host *host)
2040 {
2041 mmc_free_host(host->mmc);
2042 }
2043
2044 EXPORT_SYMBOL_GPL(sdhci_free_host);
2045
2046 /*****************************************************************************\
2047 * *
2048 * Driver init/exit *
2049 * *
2050 \*****************************************************************************/
2051
2052 static int __init sdhci_drv_init(void)
2053 {
2054 printk(KERN_INFO DRIVER_NAME
2055 ": Secure Digital Host Controller Interface driver\n");
2056 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2057
2058 return 0;
2059 }
2060
2061 static void __exit sdhci_drv_exit(void)
2062 {
2063 }
2064
2065 module_init(sdhci_drv_init);
2066 module_exit(sdhci_drv_exit);
2067
2068 module_param(debug_quirks, uint, 0444);
2069
2070 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2071 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2072 MODULE_LICENSE("GPL");
2073
2074 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
CJK support for tty framebuffer vt