| blob | 5aaa9bd036dbcae88e8dc36e705af4c47dc9ecc1 |
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
72 /******************\
73 * Internal defines *
74 \******************/
76 /* Module info */
85 /* Known PCI ids */
106 };
109 /* Known SREVs */
147 };
188 /* XR missing */
189 };
191 /*
192 * Prototypes - PCI stack related functions
193 */
197 #ifdef CONFIG_PM
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
203 #else
204 #define ATH5K_PM_OPS NULL
213 };
217 /*
218 * Prototypes - MAC 802.11 stack related functions
219 */
237 u64 multicast);
254 u32 changes);
277 };
279 /*
280 * Prototypes - Internal functions
281 */
282 /* Attach detach */
287 /* Channel/mode setup */
300 /* Descriptor setup */
305 /* Buffers setup */
313 {
318 PCI_DMA_TODEVICE);
321 }
325 {
330 PCI_DMA_FROMDEVICE);
333 }
336 /* Queues setup */
345 /* Rx handling */
353 /* Tx handling */
357 /* Beacon handling */
366 {
373 }
375 /* Interrupt handling */
384 /*
385 * Module init/exit functions
386 */
387 static int __init
389 {
398 }
401 }
403 static void __exit
405 {
409 }
415 /********************\
416 * PCI Initialization *
417 \********************/
421 {
435 }
436 }
439 }
441 {
444 }
447 {
450 }
455 };
457 static int __devinit
460 {
466 u8 csz;
472 }
474 /* XXX 32-bit addressing only */
479 }
481 /*
482 * Cache line size is used to size and align various
483 * structures used to communicate with the hardware.
484 */
487 /*
488 * Linux 2.4.18 (at least) writes the cache line size
489 * register as a 16-bit wide register which is wrong.
490 * We must have this setup properly for rx buffer
491 * DMA to work so force a reasonable value here if it
492 * comes up zero.
493 */
496 }
497 /*
498 * The default setting of latency timer yields poor results,
499 * set it to the value used by other systems. It may be worth
500 * tweaking this setting more.
501 */
504 /* Enable bus mastering */
507 /*
508 * Disable the RETRY_TIMEOUT register (0x41) to keep
509 * PCI Tx retries from interfering with C3 CPU state.
510 */
517 }
524 }
526 /*
527 * Allocate hw (mac80211 main struct)
528 * and hw->priv (driver private data)
529 */
535 }
539 /* Initialize driver private data */
542 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
543 IEEE80211_HW_SIGNAL_DBM |
544 IEEE80211_HW_NOISE_DBM;
560 /*
561 * Mark the device as detached to avoid processing
562 * interrupts until setup is complete.
563 */
574 /* Set private data */
577 /* Setup interrupt handler */
582 }
584 /*If we passed the test malloc a ath5k_hw struct*/
590 }
600 /* Initialize device */
604 }
606 /* set up multi-rate retry capabilities */
610 }
612 /* Finish private driver data initialization */
623 /* Single chip radio (!RF5111) */
626 /* No 5GHz support -> report 2GHz radio */
633 /* No 2GHz support (5110 and some
634 * 5Ghz only cards) -> report 5Ghz radio */
641 /* Multiband radio */
648 }
649 }
650 /* Multi chip radio (RF5111 - RF2111) ->
651 * report both 2GHz/5GHz radios */
662 }
663 }
666 /* ready to process interrupts */
670 err_ah:
672 err_irq:
674 err_free_ah:
676 err_free:
678 err_map:
680 err_reg:
682 err_dis:
684 err:
686 }
688 static void __devexit
690 {
703 }
705 #ifdef CONFIG_PM
707 {
713 }
716 {
721 /*
722 * Suspend/Resume resets the PCI configuration space, so we have to
723 * re-disable the RETRY_TIMEOUT register (0x41) to keep
724 * PCI Tx retries from interfering with C3 CPU state
725 */
730 }
734 /***********************\
735 * Driver Initialization *
736 \***********************/
739 {
745 }
747 static int
749 {
758 /*
759 * Check if the MAC has multi-rate retry support.
760 * We do this by trying to setup a fake extended
761 * descriptor. MAC's that don't have support will
762 * return false w/o doing anything. MAC's that do
763 * support it will return true w/o doing anything.
764 */
771 /*
772 * Collect the channel list. The 802.11 layer
773 * is resposible for filtering this list based
774 * on settings like the phy mode and regulatory
775 * domain restrictions.
776 */
781 }
783 /* NB: setup here so ath5k_rate_update is happy */
786 else
789 /*
790 * Allocate tx+rx descriptors and populate the lists.
791 */
796 }
798 /*
799 * Allocate hardware transmit queues: one queue for
800 * beacon frames and one data queue for each QoS
801 * priority. Note that hw functions handle reseting
802 * these queues at the needed time.
803 */
808 }
815 }
822 }
835 }
838 /* All MAC address bits matter for ACKs */
847 }
853 }
861 err_queues:
863 err_bhal:
865 err_desc:
867 err:
869 }
871 static void
873 {
876 /*
877 * NB: the order of these is important:
878 * o call the 802.11 layer before detaching ath5k_hw to
879 * insure callbacks into the driver to delete global
880 * key cache entries can be handled
881 * o reclaim the tx queue data structures after calling
882 * the 802.11 layer as we'll get called back to reclaim
883 * node state and potentially want to use them
884 * o to cleanup the tx queues the hal is called, so detach
885 * it last
886 * XXX: ??? detach ath5k_hw ???
887 * Other than that, it's straightforward...
888 */
895 /*
896 * NB: can't reclaim these until after ieee80211_ifdetach
897 * returns because we'll get called back to reclaim node
898 * state and potentially want to use them.
899 */
900 }
905 /********************\
906 * Channel/mode setup *
907 \********************/
909 /*
910 * Convert IEEE channel number to MHz frequency.
911 */
914 {
917 else
919 }
921 /*
922 * Returns true for the channel numbers used without all_channels modparam.
923 */
925 {
927 /* UNII 1,2 */
929 /* midband */
931 /* UNII-3 */
933 }
935 static unsigned int
940 {
949 /* 1..220, but 2GHz frequencies are filtered by check_channel */
962 }
968 /* Check if channel is supported by the chipset */
975 /* Write channel info and increment counter */
991 }
993 count++;
994 max--;
995 }
998 }
1000 static void
1002 {
1003 u8 i;
1012 }
1013 }
1015 static int
1017 {
1027 /* 2GHz band */
1033 /* G mode */
1046 /* B mode */
1051 /* 5211 only supports B rates and uses 4bit rate codes
1052 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1053 * fix them up here:
1054 */
1061 }
1062 }
1071 }
1074 /* 5GHz band, A mode */
1089 }
1095 }
1097 /*
1098 * Set/change channels. We always reset the chip.
1099 * To accomplish this we must first cleanup any pending DMA,
1100 * then restart stuff after a la ath5k_init.
1101 *
1102 * Called with sc->lock.
1103 */
1104 static int
1106 {
1110 /*
1111 * To switch channels clear any pending DMA operations;
1112 * wait long enough for the RX fifo to drain, reset the
1113 * hardware at the new frequency, and then re-enable
1114 * the relevant bits of the h/w.
1115 */
1117 }
1119 static void
1121 {
1128 }
1129 }
1131 static void
1133 {
1135 u32 rfilt;
1139 /* configure rx filter */
1146 /* configure operational mode */
1151 }
1155 {
1158 /* return base rate on errors */
1168 }
1170 /***************\
1171 * Buffers setup *
1172 \***************/
1174 static
1176 {
1180 /*
1181 * Allocate buffer with headroom_needed space for the
1182 * fake physical layer header at the start.
1183 */
1186 GFP_ATOMIC);
1192 }
1200 }
1202 }
1204 static int
1206 {
1216 }
1218 /*
1219 * Setup descriptors. For receive we always terminate
1220 * the descriptor list with a self-linked entry so we'll
1221 * not get overrun under high load (as can happen with a
1222 * 5212 when ANI processing enables PHY error frames).
1223 *
1224 * To insure the last descriptor is self-linked we create
1225 * each descriptor as self-linked and add it to the end. As
1226 * each additional descriptor is added the previous self-linked
1227 * entry is ``fixed'' naturally. This should be safe even
1228 * if DMA is happening. When processing RX interrupts we
1229 * never remove/process the last, self-linked, entry on the
1230 * descriptor list. This insures the hardware always has
1231 * someplace to write a new frame.
1232 */
1244 }
1246 static int
1249 {
1258 u16 hw_rate;
1261 u8 rc_flags;
1265 /* XXX endianness */
1267 PCI_DMA_TODEVICE);
1280 /* FIXME: If we are in g mode and rate is a CCK rate
1281 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1282 * from tx power (value is in dB units already) */
1286 }
1292 }
1298 }
1302 hw_rate,
1317 }
1341 err_unmap:
1344 }
1346 /*******************\
1347 * Descriptors setup *
1348 \*******************/
1350 static int
1352 {
1355 dma_addr_t da;
1359 /* allocate descriptors */
1367 }
1379 }
1387 }
1396 }
1398 /* beacon buffer */
1404 err_free:
1406 err:
1409 }
1411 static void
1413 {
1422 /* Free memory associated with all descriptors */
1427 }
1433 /**************\
1434 * Queues setup *
1435 \**************/
1440 {
1448 };
1451 /*
1452 * Enable interrupts only for EOL and DESC conditions.
1453 * We mark tx descriptors to receive a DESC interrupt
1454 * when a tx queue gets deep; otherwise waiting for the
1455 * EOL to reap descriptors. Note that this is done to
1456 * reduce interrupt load and this only defers reaping
1457 * descriptors, never transmitting frames. Aside from
1458 * reducing interrupts this also permits more concurrency.
1459 * The only potential downside is if the tx queue backs
1460 * up in which case the top half of the kernel may backup
1461 * due to a lack of tx descriptors.
1462 */
1464 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1467 /*
1468 * NB: don't print a message, this happens
1469 * normally on parts with too few tx queues
1470 */
1472 }
1478 }
1486 }
1488 }
1490 static int
1492 {
1497 /* NB: for dynamic turbo, don't enable any other interrupts */
1499 };
1502 }
1504 static int
1506 {
1516 /*
1517 * Always burst out beacon and CAB traffic
1518 * (aifs = cwmin = cwmax = 0)
1519 */
1524 /*
1525 * Adhoc mode; backoff between 0 and (2 * cw_min).
1526 */
1530 }
1541 }
1544 }
1546 static void
1548 {
1551 /*
1552 * NB: this assumes output has been stopped and
1553 * we do not need to block ath5k_tx_tasklet
1554 */
1566 }
1569 }
1571 /*
1572 * Drain the transmit queues and reclaim resources.
1573 */
1574 static void
1576 {
1580 /* XXX return value */
1582 /* don't touch the hardware if marked invalid */
1595 }
1596 }
1602 }
1604 static void
1606 {
1614 }
1615 }
1620 /*************\
1621 * RX Handling *
1622 \*************/
1624 /*
1625 * Enable the receive h/w following a reset.
1626 */
1627 static int
1629 {
1647 }
1648 }
1658 err:
1660 }
1662 /*
1663 * Disable the receive h/w in preparation for a reset.
1664 */
1665 static void
1667 {
1677 }
1679 static unsigned int
1682 {
1690 /* Apparently when a default key is used to decrypt the packet
1691 the hw does not set the index used to decrypt. In such cases
1692 get the index from the packet. */
1701 }
1704 }
1707 static void
1710 {
1713 u32 hw_tu;
1719 /*
1720 * Received an IBSS beacon with the same BSSID. Hardware *must*
1721 * have updated the local TSF. We have to work around various
1722 * hardware bugs, though...
1723 */
1735 /*
1736 * Sometimes the HW will give us a wrong tstamp in the rx
1737 * status, causing the timestamp extension to go wrong.
1738 * (This seems to happen especially with beacon frames bigger
1739 * than 78 byte (incl. FCS))
1740 * But we know that the receive timestamp must be later than the
1741 * timestamp of the beacon since HW must have synced to that.
1742 *
1743 * NOTE: here we assume mactime to be after the frame was
1744 * received, not like mac80211 which defines it at the start.
1745 */
1752 }
1754 /*
1755 * Local TSF might have moved higher than our beacon timers,
1756 * in that case we have to update them to continue sending
1757 * beacons. This also takes care of synchronizing beacon sending
1758 * times with other stations.
1759 */
1762 }
1763 }
1765 static void
1767 {
1771 dma_addr_t next_skb_addr;
1784 }
1793 /* bail if HW is still using self-linked descriptor */
1804 }
1809 }
1815 /*
1816 * Decrypt error. If the error occurred
1817 * because there was no hardware key, then
1818 * let the frame through so the upper layers
1819 * can process it. This is necessary for 5210
1820 * parts which have no way to setup a ``clear''
1821 * key cache entry.
1822 *
1823 * XXX do key cache faulting
1824 */
1828 }
1832 }
1834 /* let crypto-error packets fall through in MNTR */
1839 }
1840 accept:
1843 /*
1844 * If we can't replace bf->skb with a new skb under memory
1845 * pressure, just skip this packet
1846 */
1851 PCI_DMA_FROMDEVICE);
1854 /* The MAC header is padded to have 32-bit boundary if the
1855 * packet payload is non-zero. The general calculation for
1856 * padsize would take into account odd header lengths:
1857 * padsize = (4 - hdrlen % 4) % 4; However, since only
1858 * even-length headers are used, padding can only be 0 or 2
1859 * bytes and we can optimize this a bit. In addition, we must
1860 * not try to remove padding from short control frames that do
1861 * not have payload. */
1867 }
1870 /*
1871 * always extend the mac timestamp, since this information is
1872 * also needed for proper IBSS merging.
1873 *
1874 * XXX: it might be too late to do it here, since rs_tstamp is
1875 * 15bit only. that means TSF extension has to be done within
1876 * 32768usec (about 32ms). it might be necessary to move this to
1877 * the interrupt handler, like it is done in madwifi.
1878 *
1879 * Unfortunately we don't know when the hardware takes the rx
1880 * timestamp (beginning of phy frame, data frame, end of rx?).
1881 * The only thing we know is that it is hardware specific...
1882 * On AR5213 it seems the rx timestamp is at the end of the
1883 * frame, but i'm not sure.
1884 *
1885 * NOTE: mac80211 defines mactime at the beginning of the first
1886 * data symbol. Since we don't have any time references it's
1887 * impossible to comply to that. This affects IBSS merge only
1888 * right now, so it's not too bad...
1889 */
1899 /* An rssi of 35 indicates you should be able use
1900 * 54 Mbps reliably. A more elaborate scheme can be used
1901 * here but it requires a map of SNR/throughput for each
1902 * possible mode used */
1905 /* rssi can be more than 35 though, anything above that
1906 * should be considered at 100% */
1920 /* check beacons in IBSS mode */
1928 next:
1931 unlock:
1933 }
1938 /*************\
1939 * TX Handling *
1940 \*************/
1942 static void
1944 {
1963 }
1970 PCI_DMA_TODEVICE);
1983 }
1984 }
1986 /* count the successful attempt as well */
1996 }
2006 }
2012 }
2014 static void
2016 {
2023 }
2026 /*****************\
2027 * Beacon handling *
2028 \*****************/
2030 /*
2031 * Setup the beacon frame for transmit.
2032 */
2033 static int
2035 {
2041 u8 antenna;
2042 u32 flags;
2045 PCI_DMA_TODEVICE);
2052 }
2064 /*
2065 * If we use multiple antennas on AP and use
2066 * the Sectored AP scenario, switch antenna every
2067 * 4 beacons to make sure everybody hears our AP.
2068 * When a client tries to associate, hw will keep
2069 * track of the tx antenna to be used for this client
2070 * automaticaly, based on ACKed packets.
2071 *
2072 * Note: AP still listens and transmits RTS on the
2073 * default antenna which is supposed to be an omni.
2074 *
2075 * Note2: On sectored scenarios it's possible to have
2076 * multiple antennas (1omni -the default- and 14 sectors)
2077 * so if we choose to actually support this mode we need
2078 * to allow user to set how many antennas we have and tweak
2079 * the code below to send beacons on all of them.
2080 */
2085 /* FIXME: If we are in g mode and rate is a CCK rate
2086 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2087 * from tx power (value is in dB units already) */
2099 err_unmap:
2102 }
2104 /*
2105 * Transmit a beacon frame at SWBA. Dynamic updates to the
2106 * frame contents are done as needed and the slot time is
2107 * also adjusted based on current state.
2108 *
2109 * This is called from software irq context (beacontq or restq
2110 * tasklets) or user context from ath5k_beacon_config.
2111 */
2112 static void
2114 {
2125 }
2126 /*
2127 * Check if the previous beacon has gone out. If
2128 * not don't don't try to post another, skip this
2129 * period and wait for the next. Missed beacons
2130 * indicate a problem and should not occur. If we
2131 * miss too many consecutive beacons reset the device.
2132 */
2142 }
2144 }
2150 }
2152 /*
2153 * Stop any current dma and put the new frame on the queue.
2154 * This should never fail since we check above that no frames
2155 * are still pending on the queue.
2156 */
2159 /* NB: hw still stops DMA, so proceed */
2160 }
2162 /* refresh the beacon for AP mode */
2175 }
2178 }
2181 /**
2182 * ath5k_beacon_update_timers - update beacon timers
2183 *
2184 * @sc: struct ath5k_softc pointer we are operating on
2185 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2186 * beacon timer update based on the current HW TSF.
2187 *
2188 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2189 * of a received beacon or the current local hardware TSF and write it to the
2190 * beacon timer registers.
2191 *
2192 * This is called in a variety of situations, e.g. when a beacon is received,
2193 * when a TSF update has been detected, but also when an new IBSS is created or
2194 * when we otherwise know we have to update the timers, but we keep it in this
2195 * function to have it all together in one place.
2196 */
2197 static void
2199 {
2202 u64 hw_tsf;
2208 /* beacon TSF converted to TU */
2211 /* current TSF converted to TU */
2215 #define FUDGE 3
2216 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2218 /*
2219 * no beacons received, called internally.
2220 * just need to refresh timers based on HW TSF.
2221 */
2224 /*
2225 * no beacon received, probably called by ath5k_reset_tsf().
2226 * reset TSF to start with 0.
2227 */
2231 /*
2232 * beacon received, SW merge happend but HW TSF not yet updated.
2233 * not possible to reconfigure timers yet, but next time we
2234 * receive a beacon with the same BSSID, the hardware will
2235 * automatically update the TSF and then we need to reconfigure
2236 * the timers.
2237 */
2242 /*
2243 * most important case for beacon synchronization between STA.
2244 *
2245 * beacon received and HW TSF has been already updated by HW.
2246 * update next TBTT based on the TSF of the beacon, but make
2247 * sure it is ahead of our local TSF timer.
2248 */
2250 }
2251 #undef FUDGE
2258 /*
2259 * debugging output last in order to preserve the time critical aspect
2260 * of this function
2261 */
2268 else
2280 }
2283 /**
2284 * ath5k_beacon_config - Configure the beacon queues and interrupts
2285 *
2286 * @sc: struct ath5k_softc pointer we are operating on
2287 *
2288 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2289 * interrupts to detect TSF updates only.
2290 */
2291 static void
2293 {
2302 /*
2303 * In IBSS mode we use a self-linked tx descriptor and let the
2304 * hardware send the beacons automatically. We have to load it
2305 * only once here.
2306 * We use the SWBA interrupt only to keep track of the beacon
2307 * timers in order to detect automatic TSF updates.
2308 */
2320 }
2325 }
2328 {
2331 /*
2332 * Software beacon alert--time to send a beacon.
2333 *
2334 * In IBSS mode we use this interrupt just to
2335 * keep track of the next TBTT (target beacon
2336 * transmission time) in order to detect wether
2337 * automatic TSF updates happened.
2338 */
2340 /* XXX: only if VEOL suppported */
2344 "SWBA nexttbtt: %x hw_tu: %x "
2353 }
2354 }
2357 /********************\
2358 * Interrupt handling *
2359 \********************/
2361 static int
2363 {
2371 /*
2372 * Stop anything previously setup. This is safe
2373 * no matter this is the first time through or not.
2374 */
2377 /*
2378 * The basic interface to setting the hardware in a good
2379 * state is ``reset''. On return the hardware is known to
2380 * be powered up and with interrupts disabled. This must
2381 * be followed by initialization of the appropriate bits
2382 * and then setup of the interrupt mask.
2383 */
2395 /*
2396 * Reset the key cache since some parts do not reset the
2397 * contents on initial power up or resume from suspend.
2398 */
2402 /* Set ack to be sent at low bit-rates */
2405 /* Set PHY calibration inteval */
2409 done:
2413 }
2415 static int
2417 {
2423 /*
2424 * Shutdown the hardware and driver:
2425 * stop output from above
2426 * disable interrupts
2427 * turn off timers
2428 * turn off the radio
2429 * clear transmit machinery
2430 * clear receive machinery
2431 * drain and release tx queues
2432 * reclaim beacon resources
2433 * power down hardware
2434 *
2435 * Note that some of this work is not possible if the
2436 * hardware is gone (invalid).
2437 */
2444 }
2453 }
2455 /*
2456 * Stop the device, grabbing the top-level lock to protect
2457 * against concurrent entry through ath5k_init (which can happen
2458 * if another thread does a system call and the thread doing the
2459 * stop is preempted).
2460 */
2461 static int
2463 {
2469 /*
2470 * Don't set the card in full sleep mode!
2471 *
2472 * a) When the device is in this state it must be carefully
2473 * woken up or references to registers in the PCI clock
2474 * domain may freeze the bus (and system). This varies
2475 * by chip and is mostly an issue with newer parts
2476 * (madwifi sources mentioned srev >= 0x78) that go to
2477 * sleep more quickly.
2478 *
2479 * b) On older chips full sleep results a weird behaviour
2480 * during wakeup. I tested various cards with srev < 0x78
2481 * and they don't wake up after module reload, a second
2482 * module reload is needed to bring the card up again.
2483 *
2484 * Until we figure out what's going on don't enable
2485 * full chip reset on any chip (this is what Legacy HAL
2486 * and Sam's HAL do anyway). Instead Perform a full reset
2487 * on the device (same as initial state after attach) and
2488 * leave it idle (keep MAC/BB on warm reset) */
2493 }
2508 }
2510 static irqreturn_t
2512 {
2527 /*
2528 * Fatal errors are unrecoverable.
2529 * Typically these are caused by DMA errors.
2530 */
2537 }
2539 /*
2540 * NB: the hardware should re-read the link when
2541 * RXE bit is written, but it doesn't work at
2542 * least on older hardware revs.
2543 */
2545 }
2547 /* bump tx trigger level */
2549 }
2556 /* TODO */
2557 }
2560 }
2562 /*
2563 * These stats are also used for ANI i think
2564 * so how about updating them more often ?
2565 */
2567 }
2571 }
2580 }
2582 static void
2584 {
2588 }
2590 /*
2591 * Periodically recalibrate the PHY to account
2592 * for temperature/environment changes.
2593 */
2594 static void
2596 {
2600 /* Only full calibration for now */
2604 /* Stop queues so that calibration
2605 * doesn't interfere with tx */
2613 /*
2614 * Rfgain is out of bounds, reset the chip
2615 * to load new gain values.
2616 */
2619 }
2627 /* Wake queues */
2630 }
2633 /********************\
2634 * Mac80211 functions *
2635 \********************/
2637 static int
2639 {
2643 }
2647 {
2659 /*
2660 * the hardware expects the header padded to 4 byte boundaries
2661 * if this is not the case we add the padding after the header
2662 */
2671 }
2674 }
2682 }
2699 }
2702 drop_packet:
2705 }
2707 /*
2708 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2709 * and change to the given channel.
2710 */
2711 static int
2713 {
2726 }
2731 }
2737 }
2739 /*
2740 * Change channels and update the h/w rate map if we're switching;
2741 * e.g. 11a to 11b/g.
2742 *
2743 * We may be doing a reset in response to an ioctl that changes the
2744 * channel so update any state that might change as a result.
2745 *
2746 * XXX needed?
2747 */
2748 /* ath5k_chan_change(sc, c); */
2751 /* intrs are enabled by ath5k_beacon_config */
2754 err:
2756 }
2758 static int
2760 {
2768 }
2771 {
2773 }
2776 {
2778 }
2782 {
2790 }
2805 }
2811 end:
2814 }
2816 static void
2819 {
2829 end:
2831 }
2833 /*
2834 * TODO: Phy disable/diversity etc
2835 */
2836 static int
2838 {
2850 }
2856 /* Half dB steps */
2858 }
2860 /* TODO:
2861 * 1) Move this on config_interface and handle each case
2862 * separately eg. when we have only one STA vif, use
2863 * AR5K_ANTMODE_SINGLE_AP
2864 *
2865 * 2) Allow the user to change antenna mode eg. when only
2866 * one antenna is present
2867 *
2868 * 3) Allow the user to set default/tx antenna when possible
2869 *
2870 * 4) Default mode should handle 90% of the cases, together
2871 * with fixed a/b and single AP modes we should be able to
2872 * handle 99%. Sectored modes are extreme cases and i still
2873 * haven't found a usage for them. If we decide to support them,
2874 * then we must allow the user to set how many tx antennas we
2875 * have available
2876 */
2879 unlock:
2882 }
2886 {
2889 u8 pos;
2897 /* calculate XOR of eight 6-bit values */
2904 /* XXX: we might be able to just do this instead,
2905 * but not sure, needs testing, if we do use this we'd
2906 * neet to inform below to not reset the mcast */
2907 /* ath5k_hw_set_mcast_filterindex(ah,
2908 * mclist->dmi_addr[5]); */
2910 }
2913 }
2915 #define SUPPORTED_FIF_FLAGS \
2916 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2917 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2918 FIF_BCN_PRBRESP_PROMISC
2919 /*
2920 * o always accept unicast, broadcast, and multicast traffic
2921 * o multicast traffic for all BSSIDs will be enabled if mac80211
2922 * says it should be
2923 * o maintain current state of phy ofdm or phy cck error reception.
2924 * If the hardware detects any of these type of errors then
2925 * ath5k_hw_get_rx_filter() will pass to us the respective
2926 * hardware filters to be able to receive these type of frames.
2927 * o probe request frames are accepted only when operating in
2928 * hostap, adhoc, or monitor modes
2929 * o enable promiscuous mode according to the interface state
2930 * o accept beacons:
2931 * - when operating in adhoc mode so the 802.11 layer creates
2932 * node table entries for peers,
2933 * - when operating in station mode for collecting rssi data when
2934 * the station is otherwise quiet, or
2935 * - when scanning
2936 */
2940 u64 multicast)
2941 {
2951 /* Only deal with supported flags */
2955 /* If HW detects any phy or radar errors, leave those filters on.
2956 * Also, always enable Unicast, Broadcasts and Multicast
2957 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2960 AR5K_RX_FILTER_MCAST);
2968 }
2969 }
2971 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2975 }
2977 /* This is the best we can do */
2981 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2982 * and probes for any BSSID, this needs testing */
2986 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2987 * set we should only pass on control frames for this
2988 * station. This needs testing. I believe right now this
2989 * enables *all* control frames, which is OK.. but
2990 * but we should see if we can improve on granularity */
2994 /* Additional settings per mode -- this is per ath5k */
2996 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3002 AR5K_RX_FILTER_BEACON |
3003 AR5K_RX_FILTER_PROBEREQ |
3004 AR5K_RX_FILTER_PROM;
3009 AR5K_RX_FILTER_BEACON;
3016 }
3018 /* Set filters */
3021 /* Set multicast bits */
3023 /* Set the cached hw filter flags, this will alter actually
3024 * be set in HW */
3028 }
3030 static int
3034 {
3056 }
3067 }
3071 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3080 }
3082 unlock:
3086 }
3088 static int
3091 {
3095 /* Force update */
3101 }
3103 static int
3106 {
3112 }
3114 static u64
3116 {
3120 }
3122 static void
3124 {
3128 }
3130 static void
3132 {
3135 /*
3136 * in IBSS mode we need to update the beacon timers too.
3137 * this will also reset the TSF if we call it with 0
3138 */
3141 else
3143 }
3145 /*
3146 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3147 * this is called only once at config_bss time, for AP we do it every
3148 * SWBA interrupt so that the TIM will reflect buffered frames.
3149 *
3150 * Called with the beacon lock.
3151 */
3152 static int
3154 {
3162 }
3169 }
3178 out:
3180 }
3182 static void
3184 {
3187 u32 rfilt;
3191 else
3195 }
3200 u32 changes)
3201 {
3212 /* Cache for later use during resets */
3214 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3215 * a clean way of letting us retrieve this yet. */
3218 }
3229 }
3235 }
3241 BSS_CHANGED_BEACON_INT))
3244 unlock:
3246 }
3249 {
3253 }
3256 {
3260 }