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ACPI: execute Notify() handlers on new thread
[linux-2.6/cjktty.git] / drivers / scsi / ahci.c
blobffba65656a838464bc0e05c48a6730821be54028
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.2"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69 AHCI_CMD_PREFETCH = (1 << 7),
70 AHCI_CMD_RESET = (1 << 8),
71 AHCI_CMD_CLR_BUSY = (1 << 10),
72
73 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
74
75 board_ahci = 0,
76
77 /* global controller registers */
78 HOST_CAP = 0x00, /* host capabilities */
79 HOST_CTL = 0x04, /* global host control */
80 HOST_IRQ_STAT = 0x08, /* interrupt status */
81 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
82 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
83
84 /* HOST_CTL bits */
85 HOST_RESET = (1 << 0), /* reset controller; self-clear */
86 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
87 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
88
89 /* HOST_CAP bits */
90 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
91 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
92
93 /* registers for each SATA port */
94 PORT_LST_ADDR = 0x00, /* command list DMA addr */
95 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
96 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
97 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
98 PORT_IRQ_STAT = 0x10, /* interrupt status */
99 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
100 PORT_CMD = 0x18, /* port command */
101 PORT_TFDATA = 0x20, /* taskfile data */
102 PORT_SIG = 0x24, /* device TF signature */
103 PORT_CMD_ISSUE = 0x38, /* command issue */
104 PORT_SCR = 0x28, /* SATA phy register block */
105 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
106 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
107 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
108 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
109
110 /* PORT_IRQ_{STAT,MASK} bits */
111 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
112 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
113 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
114 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
115 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
116 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
117 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
118 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
119
120 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
121 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
122 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
123 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
124 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
125 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
126 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
127 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
128 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
129
130 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
131 PORT_IRQ_HBUS_ERR |
132 PORT_IRQ_HBUS_DATA_ERR |
133 PORT_IRQ_IF_ERR,
134 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
135 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
136 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
137 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
138 PORT_IRQ_D2H_REG_FIS,
139
140 /* PORT_CMD bits */
141 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
142 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
143 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
144 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
145 PORT_CMD_CLO = (1 << 3), /* Command list override */
146 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
147 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
148 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
149
150 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
151 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
152 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
153
154 /* hpriv->flags bits */
155 AHCI_FLAG_MSI = (1 << 0),
156 };
157
158 struct ahci_cmd_hdr {
159 u32 opts;
160 u32 status;
161 u32 tbl_addr;
162 u32 tbl_addr_hi;
163 u32 reserved[4];
164 };
165
166 struct ahci_sg {
167 u32 addr;
168 u32 addr_hi;
169 u32 reserved;
170 u32 flags_size;
171 };
172
173 struct ahci_host_priv {
174 unsigned long flags;
175 u32 cap; /* cache of HOST_CAP register */
176 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
177 };
178
179 struct ahci_port_priv {
180 struct ahci_cmd_hdr *cmd_slot;
181 dma_addr_t cmd_slot_dma;
182 void *cmd_tbl;
183 dma_addr_t cmd_tbl_dma;
184 struct ahci_sg *cmd_tbl_sg;
185 void *rx_fis;
186 dma_addr_t rx_fis_dma;
187 };
188
189 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
190 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
191 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
192 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
193 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
194 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
195 static void ahci_irq_clear(struct ata_port *ap);
196 static void ahci_eng_timeout(struct ata_port *ap);
197 static int ahci_port_start(struct ata_port *ap);
198 static void ahci_port_stop(struct ata_port *ap);
199 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
200 static void ahci_qc_prep(struct ata_queued_cmd *qc);
201 static u8 ahci_check_status(struct ata_port *ap);
202 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
203 static void ahci_remove_one (struct pci_dev *pdev);
204
205 static struct scsi_host_template ahci_sht = {
206 .module = THIS_MODULE,
207 .name = DRV_NAME,
208 .ioctl = ata_scsi_ioctl,
209 .queuecommand = ata_scsi_queuecmd,
210 .eh_strategy_handler = ata_scsi_error,
211 .can_queue = ATA_DEF_QUEUE,
212 .this_id = ATA_SHT_THIS_ID,
213 .sg_tablesize = AHCI_MAX_SG,
214 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
215 .emulated = ATA_SHT_EMULATED,
216 .use_clustering = AHCI_USE_CLUSTERING,
217 .proc_name = DRV_NAME,
218 .dma_boundary = AHCI_DMA_BOUNDARY,
219 .slave_configure = ata_scsi_slave_config,
220 .bios_param = ata_std_bios_param,
221 };
222
223 static const struct ata_port_operations ahci_ops = {
224 .port_disable = ata_port_disable,
225
226 .check_status = ahci_check_status,
227 .check_altstatus = ahci_check_status,
228 .dev_select = ata_noop_dev_select,
229
230 .tf_read = ahci_tf_read,
231
232 .probe_reset = ahci_probe_reset,
233
234 .qc_prep = ahci_qc_prep,
235 .qc_issue = ahci_qc_issue,
236
237 .eng_timeout = ahci_eng_timeout,
238
239 .irq_handler = ahci_interrupt,
240 .irq_clear = ahci_irq_clear,
241
242 .scr_read = ahci_scr_read,
243 .scr_write = ahci_scr_write,
244
245 .port_start = ahci_port_start,
246 .port_stop = ahci_port_stop,
247 };
248
249 static const struct ata_port_info ahci_port_info[] = {
250 /* board_ahci */
251 {
252 .sht = &ahci_sht,
253 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
255 .pio_mask = 0x1f, /* pio0-4 */
256 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
257 .port_ops = &ahci_ops,
258 },
259 };
260
261 static const struct pci_device_id ahci_pci_tbl[] = {
262 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6 */
264 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH6M */
266 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7 */
268 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7M */
270 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ICH7R */
272 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ULi M5288 */
274 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ESB2 */
280 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
281 board_ahci }, /* ICH7-M DH */
282 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
283 board_ahci }, /* ICH8 */
284 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
285 board_ahci }, /* ICH8 */
286 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
287 board_ahci }, /* ICH8 */
288 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH8M */
290 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH8M */
292 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* JMicron JMB360 */
294 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* JMicron JMB363 */
296 { } /* terminate list */
297 };
298
299
300 static struct pci_driver ahci_pci_driver = {
301 .name = DRV_NAME,
302 .id_table = ahci_pci_tbl,
303 .probe = ahci_init_one,
304 .remove = ahci_remove_one,
305 };
306
307
308 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
309 {
310 return base + 0x100 + (port * 0x80);
311 }
312
313 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
314 {
315 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
316 }
317
318 static int ahci_port_start(struct ata_port *ap)
319 {
320 struct device *dev = ap->host_set->dev;
321 struct ahci_host_priv *hpriv = ap->host_set->private_data;
322 struct ahci_port_priv *pp;
323 void __iomem *mmio = ap->host_set->mmio_base;
324 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
325 void *mem;
326 dma_addr_t mem_dma;
327 int rc;
328
329 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
330 if (!pp)
331 return -ENOMEM;
332 memset(pp, 0, sizeof(*pp));
333
334 rc = ata_pad_alloc(ap, dev);
335 if (rc) {
336 kfree(pp);
337 return rc;
338 }
339
340 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
341 if (!mem) {
342 ata_pad_free(ap, dev);
343 kfree(pp);
344 return -ENOMEM;
345 }
346 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
347
348 /*
349 * First item in chunk of DMA memory: 32-slot command table,
350 * 32 bytes each in size
351 */
352 pp->cmd_slot = mem;
353 pp->cmd_slot_dma = mem_dma;
354
355 mem += AHCI_CMD_SLOT_SZ;
356 mem_dma += AHCI_CMD_SLOT_SZ;
357
358 /*
359 * Second item: Received-FIS area
360 */
361 pp->rx_fis = mem;
362 pp->rx_fis_dma = mem_dma;
363
364 mem += AHCI_RX_FIS_SZ;
365 mem_dma += AHCI_RX_FIS_SZ;
366
367 /*
368 * Third item: data area for storing a single command
369 * and its scatter-gather table
370 */
371 pp->cmd_tbl = mem;
372 pp->cmd_tbl_dma = mem_dma;
373
374 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
375
376 ap->private_data = pp;
377
378 if (hpriv->cap & HOST_CAP_64)
379 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
380 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
381 readl(port_mmio + PORT_LST_ADDR); /* flush */
382
383 if (hpriv->cap & HOST_CAP_64)
384 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
385 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
386 readl(port_mmio + PORT_FIS_ADDR); /* flush */
387
388 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
389 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
390 PORT_CMD_START, port_mmio + PORT_CMD);
391 readl(port_mmio + PORT_CMD); /* flush */
392
393 return 0;
394 }
395
396
397 static void ahci_port_stop(struct ata_port *ap)
398 {
399 struct device *dev = ap->host_set->dev;
400 struct ahci_port_priv *pp = ap->private_data;
401 void __iomem *mmio = ap->host_set->mmio_base;
402 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
403 u32 tmp;
404
405 tmp = readl(port_mmio + PORT_CMD);
406 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
407 writel(tmp, port_mmio + PORT_CMD);
408 readl(port_mmio + PORT_CMD); /* flush */
409
410 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
411 * this is slightly incorrect.
412 */
413 msleep(500);
414
415 ap->private_data = NULL;
416 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
417 pp->cmd_slot, pp->cmd_slot_dma);
418 ata_pad_free(ap, dev);
419 kfree(pp);
420 }
421
422 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
423 {
424 unsigned int sc_reg;
425
426 switch (sc_reg_in) {
427 case SCR_STATUS: sc_reg = 0; break;
428 case SCR_CONTROL: sc_reg = 1; break;
429 case SCR_ERROR: sc_reg = 2; break;
430 case SCR_ACTIVE: sc_reg = 3; break;
431 default:
432 return 0xffffffffU;
433 }
434
435 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
436 }
437
438
439 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
440 u32 val)
441 {
442 unsigned int sc_reg;
443
444 switch (sc_reg_in) {
445 case SCR_STATUS: sc_reg = 0; break;
446 case SCR_CONTROL: sc_reg = 1; break;
447 case SCR_ERROR: sc_reg = 2; break;
448 case SCR_ACTIVE: sc_reg = 3; break;
449 default:
450 return;
451 }
452
453 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
454 }
455
456 static int ahci_stop_engine(struct ata_port *ap)
457 {
458 void __iomem *mmio = ap->host_set->mmio_base;
459 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
460 int work;
461 u32 tmp;
462
463 tmp = readl(port_mmio + PORT_CMD);
464 tmp &= ~PORT_CMD_START;
465 writel(tmp, port_mmio + PORT_CMD);
466
467 /* wait for engine to stop. TODO: this could be
468 * as long as 500 msec
469 */
470 work = 1000;
471 while (work-- > 0) {
472 tmp = readl(port_mmio + PORT_CMD);
473 if ((tmp & PORT_CMD_LIST_ON) == 0)
474 return 0;
475 udelay(10);
476 }
477
478 return -EIO;
479 }
480
481 static void ahci_start_engine(struct ata_port *ap)
482 {
483 void __iomem *mmio = ap->host_set->mmio_base;
484 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
485 u32 tmp;
486
487 tmp = readl(port_mmio + PORT_CMD);
488 tmp |= PORT_CMD_START;
489 writel(tmp, port_mmio + PORT_CMD);
490 readl(port_mmio + PORT_CMD); /* flush */
491 }
492
493 static unsigned int ahci_dev_classify(struct ata_port *ap)
494 {
495 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
496 struct ata_taskfile tf;
497 u32 tmp;
498
499 tmp = readl(port_mmio + PORT_SIG);
500 tf.lbah = (tmp >> 24) & 0xff;
501 tf.lbam = (tmp >> 16) & 0xff;
502 tf.lbal = (tmp >> 8) & 0xff;
503 tf.nsect = (tmp) & 0xff;
504
505 return ata_dev_classify(&tf);
506 }
507
508 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
509 {
510 pp->cmd_slot[0].opts = cpu_to_le32(opts);
511 pp->cmd_slot[0].status = 0;
512 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
513 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
514 }
515
516 static int ahci_poll_register(void __iomem *reg, u32 mask, u32 val,
517 unsigned long interval_msec,
518 unsigned long timeout_msec)
519 {
520 unsigned long timeout;
521 u32 tmp;
522
523 timeout = jiffies + (timeout_msec * HZ) / 1000;
524 do {
525 tmp = readl(reg);
526 if ((tmp & mask) == val)
527 return 0;
528 msleep(interval_msec);
529 } while (time_before(jiffies, timeout));
530
531 return -1;
532 }
533
534 static int ahci_softreset(struct ata_port *ap, int verbose, unsigned int *class)
535 {
536 struct ahci_host_priv *hpriv = ap->host_set->private_data;
537 struct ahci_port_priv *pp = ap->private_data;
538 void __iomem *mmio = ap->host_set->mmio_base;
539 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
540 const u32 cmd_fis_len = 5; /* five dwords */
541 const char *reason = NULL;
542 struct ata_taskfile tf;
543 u8 *fis;
544 int rc;
545
546 DPRINTK("ENTER\n");
547
548 /* prepare for SRST (AHCI-1.1 10.4.1) */
549 rc = ahci_stop_engine(ap);
550 if (rc) {
551 reason = "failed to stop engine";
552 goto fail_restart;
553 }
554
555 /* check BUSY/DRQ, perform Command List Override if necessary */
556 ahci_tf_read(ap, &tf);
557 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
558 u32 tmp;
559
560 if (!(hpriv->cap & HOST_CAP_CLO)) {
561 rc = -EIO;
562 reason = "port busy but no CLO";
563 goto fail_restart;
564 }
565
566 tmp = readl(port_mmio + PORT_CMD);
567 tmp |= PORT_CMD_CLO;
568 writel(tmp, port_mmio + PORT_CMD);
569 readl(port_mmio + PORT_CMD); /* flush */
570
571 if (ahci_poll_register(port_mmio + PORT_CMD, PORT_CMD_CLO, 0x0,
572 1, 500)) {
573 rc = -EIO;
574 reason = "CLO failed";
575 goto fail_restart;
576 }
577 }
578
579 /* restart engine */
580 ahci_start_engine(ap);
581
582 ata_tf_init(ap, &tf, 0);
583 fis = pp->cmd_tbl;
584
585 /* issue the first D2H Register FIS */
586 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
587
588 tf.ctl |= ATA_SRST;
589 ata_tf_to_fis(&tf, fis, 0);
590 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
591
592 writel(1, port_mmio + PORT_CMD_ISSUE);
593 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
594
595 if (ahci_poll_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x0, 1, 500)) {
596 rc = -EIO;
597 reason = "1st FIS failed";
598 goto fail;
599 }
600
601 /* spec says at least 5us, but be generous and sleep for 1ms */
602 msleep(1);
603
604 /* issue the second D2H Register FIS */
605 ahci_fill_cmd_slot(pp, cmd_fis_len);
606
607 tf.ctl &= ~ATA_SRST;
608 ata_tf_to_fis(&tf, fis, 0);
609 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
610
611 writel(1, port_mmio + PORT_CMD_ISSUE);
612 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
613
614 /* spec mandates ">= 2ms" before checking status.
615 * We wait 150ms, because that was the magic delay used for
616 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
617 * between when the ATA command register is written, and then
618 * status is checked. Because waiting for "a while" before
619 * checking status is fine, post SRST, we perform this magic
620 * delay here as well.
621 */
622 msleep(150);
623
624 *class = ATA_DEV_NONE;
625 if (sata_dev_present(ap)) {
626 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
627 rc = -EIO;
628 reason = "device not ready";
629 goto fail;
630 }
631 *class = ahci_dev_classify(ap);
632 }
633
634 DPRINTK("EXIT, class=%u\n", *class);
635 return 0;
636
637 fail_restart:
638 ahci_start_engine(ap);
639 fail:
640 if (verbose)
641 printk(KERN_ERR "ata%u: softreset failed (%s)\n",
642 ap->id, reason);
643 else
644 DPRINTK("EXIT, rc=%d reason=\"%s\"\n", rc, reason);
645 return rc;
646 }
647
648 static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
649 {
650 int rc;
651
652 DPRINTK("ENTER\n");
653
654 ahci_stop_engine(ap);
655 rc = sata_std_hardreset(ap, verbose, class);
656 ahci_start_engine(ap);
657
658 if (rc == 0)
659 *class = ahci_dev_classify(ap);
660 if (*class == ATA_DEV_UNKNOWN)
661 *class = ATA_DEV_NONE;
662
663 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
664 return rc;
665 }
666
667 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
668 {
669 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
670 u32 new_tmp, tmp;
671
672 ata_std_postreset(ap, class);
673
674 /* Make sure port's ATAPI bit is set appropriately */
675 new_tmp = tmp = readl(port_mmio + PORT_CMD);
676 if (*class == ATA_DEV_ATAPI)
677 new_tmp |= PORT_CMD_ATAPI;
678 else
679 new_tmp &= ~PORT_CMD_ATAPI;
680 if (new_tmp != tmp) {
681 writel(new_tmp, port_mmio + PORT_CMD);
682 readl(port_mmio + PORT_CMD); /* flush */
683 }
684 }
685
686 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
687 {
688 return ata_drive_probe_reset(ap, ata_std_probeinit,
689 ahci_softreset, ahci_hardreset,
690 ahci_postreset, classes);
691 }
692
693 static u8 ahci_check_status(struct ata_port *ap)
694 {
695 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
696
697 return readl(mmio + PORT_TFDATA) & 0xFF;
698 }
699
700 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
701 {
702 struct ahci_port_priv *pp = ap->private_data;
703 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
704
705 ata_tf_from_fis(d2h_fis, tf);
706 }
707
708 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
709 {
710 struct ahci_port_priv *pp = qc->ap->private_data;
711 struct scatterlist *sg;
712 struct ahci_sg *ahci_sg;
713 unsigned int n_sg = 0;
714
715 VPRINTK("ENTER\n");
716
717 /*
718 * Next, the S/G list.
719 */
720 ahci_sg = pp->cmd_tbl_sg;
721 ata_for_each_sg(sg, qc) {
722 dma_addr_t addr = sg_dma_address(sg);
723 u32 sg_len = sg_dma_len(sg);
724
725 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
726 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
727 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
728
729 ahci_sg++;
730 n_sg++;
731 }
732
733 return n_sg;
734 }
735
736 static void ahci_qc_prep(struct ata_queued_cmd *qc)
737 {
738 struct ata_port *ap = qc->ap;
739 struct ahci_port_priv *pp = ap->private_data;
740 int is_atapi = is_atapi_taskfile(&qc->tf);
741 u32 opts;
742 const u32 cmd_fis_len = 5; /* five dwords */
743 unsigned int n_elem;
744
745 /*
746 * Fill in command table information. First, the header,
747 * a SATA Register - Host to Device command FIS.
748 */
749 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
750 if (is_atapi) {
751 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
752 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
753 qc->dev->cdb_len);
754 }
755
756 n_elem = 0;
757 if (qc->flags & ATA_QCFLAG_DMAMAP)
758 n_elem = ahci_fill_sg(qc);
759
760 /*
761 * Fill in command slot information.
762 */
763 opts = cmd_fis_len | n_elem << 16;
764 if (qc->tf.flags & ATA_TFLAG_WRITE)
765 opts |= AHCI_CMD_WRITE;
766 if (is_atapi)
767 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
768
769 ahci_fill_cmd_slot(pp, opts);
770 }
771
772 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
773 {
774 void __iomem *mmio = ap->host_set->mmio_base;
775 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
776 u32 tmp;
777
778 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
779 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
780 printk(KERN_WARNING "ata%u: port reset, "
781 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
782 ap->id,
783 irq_stat,
784 readl(mmio + HOST_IRQ_STAT),
785 readl(port_mmio + PORT_IRQ_STAT),
786 readl(port_mmio + PORT_CMD),
787 readl(port_mmio + PORT_TFDATA),
788 readl(port_mmio + PORT_SCR_STAT),
789 readl(port_mmio + PORT_SCR_ERR));
790
791 /* stop DMA */
792 ahci_stop_engine(ap);
793
794 /* clear SATA phy error, if any */
795 tmp = readl(port_mmio + PORT_SCR_ERR);
796 writel(tmp, port_mmio + PORT_SCR_ERR);
797
798 /* if DRQ/BSY is set, device needs to be reset.
799 * if so, issue COMRESET
800 */
801 tmp = readl(port_mmio + PORT_TFDATA);
802 if (tmp & (ATA_BUSY | ATA_DRQ)) {
803 writel(0x301, port_mmio + PORT_SCR_CTL);
804 readl(port_mmio + PORT_SCR_CTL); /* flush */
805 udelay(10);
806 writel(0x300, port_mmio + PORT_SCR_CTL);
807 readl(port_mmio + PORT_SCR_CTL); /* flush */
808 }
809
810 /* re-start DMA */
811 ahci_start_engine(ap);
812 }
813
814 static void ahci_eng_timeout(struct ata_port *ap)
815 {
816 struct ata_host_set *host_set = ap->host_set;
817 void __iomem *mmio = host_set->mmio_base;
818 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
819 struct ata_queued_cmd *qc;
820 unsigned long flags;
821
822 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
823
824 spin_lock_irqsave(&host_set->lock, flags);
825
826 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
827 qc = ata_qc_from_tag(ap, ap->active_tag);
828 qc->err_mask |= AC_ERR_TIMEOUT;
829
830 spin_unlock_irqrestore(&host_set->lock, flags);
831
832 ata_eh_qc_complete(qc);
833 }
834
835 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
836 {
837 void __iomem *mmio = ap->host_set->mmio_base;
838 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
839 u32 status, serr, ci;
840
841 serr = readl(port_mmio + PORT_SCR_ERR);
842 writel(serr, port_mmio + PORT_SCR_ERR);
843
844 status = readl(port_mmio + PORT_IRQ_STAT);
845 writel(status, port_mmio + PORT_IRQ_STAT);
846
847 ci = readl(port_mmio + PORT_CMD_ISSUE);
848 if (likely((ci & 0x1) == 0)) {
849 if (qc) {
850 WARN_ON(qc->err_mask);
851 ata_qc_complete(qc);
852 qc = NULL;
853 }
854 }
855
856 if (status & PORT_IRQ_FATAL) {
857 unsigned int err_mask;
858 if (status & PORT_IRQ_TF_ERR)
859 err_mask = AC_ERR_DEV;
860 else if (status & PORT_IRQ_IF_ERR)
861 err_mask = AC_ERR_ATA_BUS;
862 else
863 err_mask = AC_ERR_HOST_BUS;
864
865 /* command processing has stopped due to error; restart */
866 ahci_restart_port(ap, status);
867
868 if (qc) {
869 qc->err_mask |= err_mask;
870 ata_qc_complete(qc);
871 }
872 }
873
874 return 1;
875 }
876
877 static void ahci_irq_clear(struct ata_port *ap)
878 {
879 /* TODO */
880 }
881
882 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
883 {
884 struct ata_host_set *host_set = dev_instance;
885 struct ahci_host_priv *hpriv;
886 unsigned int i, handled = 0;
887 void __iomem *mmio;
888 u32 irq_stat, irq_ack = 0;
889
890 VPRINTK("ENTER\n");
891
892 hpriv = host_set->private_data;
893 mmio = host_set->mmio_base;
894
895 /* sigh. 0xffffffff is a valid return from h/w */
896 irq_stat = readl(mmio + HOST_IRQ_STAT);
897 irq_stat &= hpriv->port_map;
898 if (!irq_stat)
899 return IRQ_NONE;
900
901 spin_lock(&host_set->lock);
902
903 for (i = 0; i < host_set->n_ports; i++) {
904 struct ata_port *ap;
905
906 if (!(irq_stat & (1 << i)))
907 continue;
908
909 ap = host_set->ports[i];
910 if (ap) {
911 struct ata_queued_cmd *qc;
912 qc = ata_qc_from_tag(ap, ap->active_tag);
913 if (!ahci_host_intr(ap, qc))
914 if (ata_ratelimit())
915 dev_printk(KERN_WARNING, host_set->dev,
916 "unhandled interrupt on port %u\n",
917 i);
918
919 VPRINTK("port %u\n", i);
920 } else {
921 VPRINTK("port %u (no irq)\n", i);
922 if (ata_ratelimit())
923 dev_printk(KERN_WARNING, host_set->dev,
924 "interrupt on disabled port %u\n", i);
925 }
926
927 irq_ack |= (1 << i);
928 }
929
930 if (irq_ack) {
931 writel(irq_ack, mmio + HOST_IRQ_STAT);
932 handled = 1;
933 }
934
935 spin_unlock(&host_set->lock);
936
937 VPRINTK("EXIT\n");
938
939 return IRQ_RETVAL(handled);
940 }
941
942 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
943 {
944 struct ata_port *ap = qc->ap;
945 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
946
947 writel(1, port_mmio + PORT_CMD_ISSUE);
948 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
949
950 return 0;
951 }
952
953 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
954 unsigned int port_idx)
955 {
956 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
957 base = ahci_port_base_ul(base, port_idx);
958 VPRINTK("base now==0x%lx\n", base);
959
960 port->cmd_addr = base;
961 port->scr_addr = base + PORT_SCR;
962
963 VPRINTK("EXIT\n");
964 }
965
966 static int ahci_host_init(struct ata_probe_ent *probe_ent)
967 {
968 struct ahci_host_priv *hpriv = probe_ent->private_data;
969 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
970 void __iomem *mmio = probe_ent->mmio_base;
971 u32 tmp, cap_save;
972 unsigned int i, j, using_dac;
973 int rc;
974 void __iomem *port_mmio;
975
976 cap_save = readl(mmio + HOST_CAP);
977 cap_save &= ( (1<<28) | (1<<17) );
978 cap_save |= (1 << 27);
979
980 /* global controller reset */
981 tmp = readl(mmio + HOST_CTL);
982 if ((tmp & HOST_RESET) == 0) {
983 writel(tmp | HOST_RESET, mmio + HOST_CTL);
984 readl(mmio + HOST_CTL); /* flush */
985 }
986
987 /* reset must complete within 1 second, or
988 * the hardware should be considered fried.
989 */
990 ssleep(1);
991
992 tmp = readl(mmio + HOST_CTL);
993 if (tmp & HOST_RESET) {
994 dev_printk(KERN_ERR, &pdev->dev,
995 "controller reset failed (0x%x)\n", tmp);
996 return -EIO;
997 }
998
999 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1000 (void) readl(mmio + HOST_CTL); /* flush */
1001 writel(cap_save, mmio + HOST_CAP);
1002 writel(0xf, mmio + HOST_PORTS_IMPL);
1003 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1004
1005 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1006 u16 tmp16;
1007
1008 pci_read_config_word(pdev, 0x92, &tmp16);
1009 tmp16 |= 0xf;
1010 pci_write_config_word(pdev, 0x92, tmp16);
1011 }
1012
1013 hpriv->cap = readl(mmio + HOST_CAP);
1014 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1015 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1016
1017 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1018 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1019
1020 using_dac = hpriv->cap & HOST_CAP_64;
1021 if (using_dac &&
1022 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1023 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1024 if (rc) {
1025 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1026 if (rc) {
1027 dev_printk(KERN_ERR, &pdev->dev,
1028 "64-bit DMA enable failed\n");
1029 return rc;
1030 }
1031 }
1032 } else {
1033 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1034 if (rc) {
1035 dev_printk(KERN_ERR, &pdev->dev,
1036 "32-bit DMA enable failed\n");
1037 return rc;
1038 }
1039 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1040 if (rc) {
1041 dev_printk(KERN_ERR, &pdev->dev,
1042 "32-bit consistent DMA enable failed\n");
1043 return rc;
1044 }
1045 }
1046
1047 for (i = 0; i < probe_ent->n_ports; i++) {
1048 #if 0 /* BIOSen initialize this incorrectly */
1049 if (!(hpriv->port_map & (1 << i)))
1050 continue;
1051 #endif
1052
1053 port_mmio = ahci_port_base(mmio, i);
1054 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1055
1056 ahci_setup_port(&probe_ent->port[i],
1057 (unsigned long) mmio, i);
1058
1059 /* make sure port is not active */
1060 tmp = readl(port_mmio + PORT_CMD);
1061 VPRINTK("PORT_CMD 0x%x\n", tmp);
1062 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1063 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1064 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1065 PORT_CMD_FIS_RX | PORT_CMD_START);
1066 writel(tmp, port_mmio + PORT_CMD);
1067 readl(port_mmio + PORT_CMD); /* flush */
1068
1069 /* spec says 500 msecs for each bit, so
1070 * this is slightly incorrect.
1071 */
1072 msleep(500);
1073 }
1074
1075 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1076
1077 j = 0;
1078 while (j < 100) {
1079 msleep(10);
1080 tmp = readl(port_mmio + PORT_SCR_STAT);
1081 if ((tmp & 0xf) == 0x3)
1082 break;
1083 j++;
1084 }
1085
1086 tmp = readl(port_mmio + PORT_SCR_ERR);
1087 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1088 writel(tmp, port_mmio + PORT_SCR_ERR);
1089
1090 /* ack any pending irq events for this port */
1091 tmp = readl(port_mmio + PORT_IRQ_STAT);
1092 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1093 if (tmp)
1094 writel(tmp, port_mmio + PORT_IRQ_STAT);
1095
1096 writel(1 << i, mmio + HOST_IRQ_STAT);
1097
1098 /* set irq mask (enables interrupts) */
1099 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1100 }
1101
1102 tmp = readl(mmio + HOST_CTL);
1103 VPRINTK("HOST_CTL 0x%x\n", tmp);
1104 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1105 tmp = readl(mmio + HOST_CTL);
1106 VPRINTK("HOST_CTL 0x%x\n", tmp);
1107
1108 pci_set_master(pdev);
1109
1110 return 0;
1111 }
1112
1113 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1114 {
1115 struct ahci_host_priv *hpriv = probe_ent->private_data;
1116 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1117 void __iomem *mmio = probe_ent->mmio_base;
1118 u32 vers, cap, impl, speed;
1119 const char *speed_s;
1120 u16 cc;
1121 const char *scc_s;
1122
1123 vers = readl(mmio + HOST_VERSION);
1124 cap = hpriv->cap;
1125 impl = hpriv->port_map;
1126
1127 speed = (cap >> 20) & 0xf;
1128 if (speed == 1)
1129 speed_s = "1.5";
1130 else if (speed == 2)
1131 speed_s = "3";
1132 else
1133 speed_s = "?";
1134
1135 pci_read_config_word(pdev, 0x0a, &cc);
1136 if (cc == 0x0101)
1137 scc_s = "IDE";
1138 else if (cc == 0x0106)
1139 scc_s = "SATA";
1140 else if (cc == 0x0104)
1141 scc_s = "RAID";
1142 else
1143 scc_s = "unknown";
1144
1145 dev_printk(KERN_INFO, &pdev->dev,
1146 "AHCI %02x%02x.%02x%02x "
1147 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1148 ,
1149
1150 (vers >> 24) & 0xff,
1151 (vers >> 16) & 0xff,
1152 (vers >> 8) & 0xff,
1153 vers & 0xff,
1154
1155 ((cap >> 8) & 0x1f) + 1,
1156 (cap & 0x1f) + 1,
1157 speed_s,
1158 impl,
1159 scc_s);
1160
1161 dev_printk(KERN_INFO, &pdev->dev,
1162 "flags: "
1163 "%s%s%s%s%s%s"
1164 "%s%s%s%s%s%s%s\n"
1165 ,
1166
1167 cap & (1 << 31) ? "64bit " : "",
1168 cap & (1 << 30) ? "ncq " : "",
1169 cap & (1 << 28) ? "ilck " : "",
1170 cap & (1 << 27) ? "stag " : "",
1171 cap & (1 << 26) ? "pm " : "",
1172 cap & (1 << 25) ? "led " : "",
1173
1174 cap & (1 << 24) ? "clo " : "",
1175 cap & (1 << 19) ? "nz " : "",
1176 cap & (1 << 18) ? "only " : "",
1177 cap & (1 << 17) ? "pmp " : "",
1178 cap & (1 << 15) ? "pio " : "",
1179 cap & (1 << 14) ? "slum " : "",
1180 cap & (1 << 13) ? "part " : ""
1181 );
1182 }
1183
1184 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1185 {
1186 static int printed_version;
1187 struct ata_probe_ent *probe_ent = NULL;
1188 struct ahci_host_priv *hpriv;
1189 unsigned long base;
1190 void __iomem *mmio_base;
1191 unsigned int board_idx = (unsigned int) ent->driver_data;
1192 int have_msi, pci_dev_busy = 0;
1193 int rc;
1194
1195 VPRINTK("ENTER\n");
1196
1197 if (!printed_version++)
1198 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1199
1200 rc = pci_enable_device(pdev);
1201 if (rc)
1202 return rc;
1203
1204 rc = pci_request_regions(pdev, DRV_NAME);
1205 if (rc) {
1206 pci_dev_busy = 1;
1207 goto err_out;
1208 }
1209
1210 if (pci_enable_msi(pdev) == 0)
1211 have_msi = 1;
1212 else {
1213 pci_intx(pdev, 1);
1214 have_msi = 0;
1215 }
1216
1217 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1218 if (probe_ent == NULL) {
1219 rc = -ENOMEM;
1220 goto err_out_msi;
1221 }
1222
1223 memset(probe_ent, 0, sizeof(*probe_ent));
1224 probe_ent->dev = pci_dev_to_dev(pdev);
1225 INIT_LIST_HEAD(&probe_ent->node);
1226
1227 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1228 if (mmio_base == NULL) {
1229 rc = -ENOMEM;
1230 goto err_out_free_ent;
1231 }
1232 base = (unsigned long) mmio_base;
1233
1234 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1235 if (!hpriv) {
1236 rc = -ENOMEM;
1237 goto err_out_iounmap;
1238 }
1239 memset(hpriv, 0, sizeof(*hpriv));
1240
1241 probe_ent->sht = ahci_port_info[board_idx].sht;
1242 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1243 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1244 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1245 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1246
1247 probe_ent->irq = pdev->irq;
1248 probe_ent->irq_flags = SA_SHIRQ;
1249 probe_ent->mmio_base = mmio_base;
1250 probe_ent->private_data = hpriv;
1251
1252 if (have_msi)
1253 hpriv->flags |= AHCI_FLAG_MSI;
1254
1255 /* JMicron-specific fixup: make sure we're in AHCI mode */
1256 if (pdev->vendor == 0x197b)
1257 pci_write_config_byte(pdev, 0x41, 0xa1);
1258
1259 /* initialize adapter */
1260 rc = ahci_host_init(probe_ent);
1261 if (rc)
1262 goto err_out_hpriv;
1263
1264 ahci_print_info(probe_ent);
1265
1266 /* FIXME: check ata_device_add return value */
1267 ata_device_add(probe_ent);
1268 kfree(probe_ent);
1269
1270 return 0;
1271
1272 err_out_hpriv:
1273 kfree(hpriv);
1274 err_out_iounmap:
1275 pci_iounmap(pdev, mmio_base);
1276 err_out_free_ent:
1277 kfree(probe_ent);
1278 err_out_msi:
1279 if (have_msi)
1280 pci_disable_msi(pdev);
1281 else
1282 pci_intx(pdev, 0);
1283 pci_release_regions(pdev);
1284 err_out:
1285 if (!pci_dev_busy)
1286 pci_disable_device(pdev);
1287 return rc;
1288 }
1289
1290 static void ahci_remove_one (struct pci_dev *pdev)
1291 {
1292 struct device *dev = pci_dev_to_dev(pdev);
1293 struct ata_host_set *host_set = dev_get_drvdata(dev);
1294 struct ahci_host_priv *hpriv = host_set->private_data;
1295 struct ata_port *ap;
1296 unsigned int i;
1297 int have_msi;
1298
1299 for (i = 0; i < host_set->n_ports; i++) {
1300 ap = host_set->ports[i];
1301
1302 scsi_remove_host(ap->host);
1303 }
1304
1305 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1306 free_irq(host_set->irq, host_set);
1307
1308 for (i = 0; i < host_set->n_ports; i++) {
1309 ap = host_set->ports[i];
1310
1311 ata_scsi_release(ap->host);
1312 scsi_host_put(ap->host);
1313 }
1314
1315 kfree(hpriv);
1316 pci_iounmap(pdev, host_set->mmio_base);
1317 kfree(host_set);
1318
1319 if (have_msi)
1320 pci_disable_msi(pdev);
1321 else
1322 pci_intx(pdev, 0);
1323 pci_release_regions(pdev);
1324 pci_disable_device(pdev);
1325 dev_set_drvdata(dev, NULL);
1326 }
1327
1328 static int __init ahci_init(void)
1329 {
1330 return pci_module_init(&ahci_pci_driver);
1331 }
1332
1333 static void __exit ahci_exit(void)
1334 {
1335 pci_unregister_driver(&ahci_pci_driver);
1336 }
1337
1338
1339 MODULE_AUTHOR("Jeff Garzik");
1340 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1341 MODULE_LICENSE("GPL");
1342 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1343 MODULE_VERSION(DRV_VERSION);
1344
1345 module_init(ahci_init);
1346 module_exit(ahci_exit);
CJK support for tty framebuffer vt