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ALSA: hda - Retry codec-verbs at errors
[linux-2.6/cjktty.git] / sound / pci / hda / hda_intel.c
blob803b72098ed3bc2d7b904fceef293e00c9a6b48f
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71 module_param_array(model, charp, NULL, 0444);
72 MODULE_PARM_DESC(model, "Use the given board model.");
73 module_param_array(position_fix, int, NULL, 0444);
74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
75 "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj, int, NULL, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
78 module_param_array(probe_mask, int, NULL, 0444);
79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only, bool, NULL, 0444);
81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
82 module_param(single_cmd, bool, 0444);
83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
85 module_param(enable_msi, int, 0444);
86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
87
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90 module_param(power_save, int, 0644);
91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
93
94 /* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
96 * wake up.
97 */
98 static int power_save_controller = 1;
99 module_param(power_save_controller, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101 #endif
102
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105 "{Intel, ICH6M},"
106 "{Intel, ICH7},"
107 "{Intel, ESB2},"
108 "{Intel, ICH8},"
109 "{Intel, ICH9},"
110 "{Intel, ICH10},"
111 "{Intel, PCH},"
112 "{Intel, SCH},"
113 "{ATI, SB450},"
114 "{ATI, SB600},"
115 "{ATI, RS600},"
116 "{ATI, RS690},"
117 "{ATI, RS780},"
118 "{ATI, R600},"
119 "{ATI, RV630},"
120 "{ATI, RV610},"
121 "{ATI, RV670},"
122 "{ATI, RV635},"
123 "{ATI, RV620},"
124 "{ATI, RV770},"
125 "{VIA, VT8251},"
126 "{VIA, VT8237A},"
127 "{SiS, SIS966},"
128 "{ULI, M5461}}");
129 MODULE_DESCRIPTION("Intel HDA driver");
130
131 #define SFX "hda-intel: "
132
133
134 /*
135 * registers
136 */
137 #define ICH6_REG_GCAP 0x00
138 #define ICH6_REG_VMIN 0x02
139 #define ICH6_REG_VMAJ 0x03
140 #define ICH6_REG_OUTPAY 0x04
141 #define ICH6_REG_INPAY 0x06
142 #define ICH6_REG_GCTL 0x08
143 #define ICH6_REG_WAKEEN 0x0c
144 #define ICH6_REG_STATESTS 0x0e
145 #define ICH6_REG_GSTS 0x10
146 #define ICH6_REG_INTCTL 0x20
147 #define ICH6_REG_INTSTS 0x24
148 #define ICH6_REG_WALCLK 0x30
149 #define ICH6_REG_SYNC 0x34
150 #define ICH6_REG_CORBLBASE 0x40
151 #define ICH6_REG_CORBUBASE 0x44
152 #define ICH6_REG_CORBWP 0x48
153 #define ICH6_REG_CORBRP 0x4A
154 #define ICH6_REG_CORBCTL 0x4c
155 #define ICH6_REG_CORBSTS 0x4d
156 #define ICH6_REG_CORBSIZE 0x4e
157
158 #define ICH6_REG_RIRBLBASE 0x50
159 #define ICH6_REG_RIRBUBASE 0x54
160 #define ICH6_REG_RIRBWP 0x58
161 #define ICH6_REG_RINTCNT 0x5a
162 #define ICH6_REG_RIRBCTL 0x5c
163 #define ICH6_REG_RIRBSTS 0x5d
164 #define ICH6_REG_RIRBSIZE 0x5e
165
166 #define ICH6_REG_IC 0x60
167 #define ICH6_REG_IR 0x64
168 #define ICH6_REG_IRS 0x68
169 #define ICH6_IRS_VALID (1<<1)
170 #define ICH6_IRS_BUSY (1<<0)
171
172 #define ICH6_REG_DPLBASE 0x70
173 #define ICH6_REG_DPUBASE 0x74
174 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
175
176 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
177 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
178
179 /* stream register offsets from stream base */
180 #define ICH6_REG_SD_CTL 0x00
181 #define ICH6_REG_SD_STS 0x03
182 #define ICH6_REG_SD_LPIB 0x04
183 #define ICH6_REG_SD_CBL 0x08
184 #define ICH6_REG_SD_LVI 0x0c
185 #define ICH6_REG_SD_FIFOW 0x0e
186 #define ICH6_REG_SD_FIFOSIZE 0x10
187 #define ICH6_REG_SD_FORMAT 0x12
188 #define ICH6_REG_SD_BDLPL 0x18
189 #define ICH6_REG_SD_BDLPU 0x1c
190
191 /* PCI space */
192 #define ICH6_PCIREG_TCSEL 0x44
193
194 /*
195 * other constants
196 */
197
198 /* max number of SDs */
199 /* ICH, ATI and VIA have 4 playback and 4 capture */
200 #define ICH6_NUM_CAPTURE 4
201 #define ICH6_NUM_PLAYBACK 4
202
203 /* ULI has 6 playback and 5 capture */
204 #define ULI_NUM_CAPTURE 5
205 #define ULI_NUM_PLAYBACK 6
206
207 /* ATI HDMI has 1 playback and 0 capture */
208 #define ATIHDMI_NUM_CAPTURE 0
209 #define ATIHDMI_NUM_PLAYBACK 1
210
211 /* TERA has 4 playback and 3 capture */
212 #define TERA_NUM_CAPTURE 3
213 #define TERA_NUM_PLAYBACK 4
214
215 /* this number is statically defined for simplicity */
216 #define MAX_AZX_DEV 16
217
218 /* max number of fragments - we may use more if allocating more pages for BDL */
219 #define BDL_SIZE 4096
220 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
221 #define AZX_MAX_FRAG 32
222 /* max buffer size - no h/w limit, you can increase as you like */
223 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
224 /* max number of PCM devics per card */
225 #define AZX_MAX_PCMS 8
226
227 /* RIRB int mask: overrun[2], response[0] */
228 #define RIRB_INT_RESPONSE 0x01
229 #define RIRB_INT_OVERRUN 0x04
230 #define RIRB_INT_MASK 0x05
231
232 /* STATESTS int mask: S3,SD2,SD1,SD0 */
233 #define AZX_MAX_CODECS 4
234 #define STATESTS_INT_MASK 0x0f
235
236 /* SD_CTL bits */
237 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
238 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
239 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
240 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
241 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
242 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
243 #define SD_CTL_STREAM_TAG_SHIFT 20
244
245 /* SD_CTL and SD_STS */
246 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
247 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
248 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
249 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
250 SD_INT_COMPLETE)
251
252 /* SD_STS */
253 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
254
255 /* INTCTL and INTSTS */
256 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
257 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
258 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
259
260 /* GCTL unsolicited response enable bit */
261 #define ICH6_GCTL_UREN (1<<8)
262
263 /* GCTL reset bit */
264 #define ICH6_GCTL_RESET (1<<0)
265
266 /* CORB/RIRB control, read/write pointer */
267 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
268 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
269 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
270 /* below are so far hardcoded - should read registers in future */
271 #define ICH6_MAX_CORB_ENTRIES 256
272 #define ICH6_MAX_RIRB_ENTRIES 256
273
274 /* position fix mode */
275 enum {
276 POS_FIX_AUTO,
277 POS_FIX_LPIB,
278 POS_FIX_POSBUF,
279 };
280
281 /* Defines for ATI HD Audio support in SB450 south bridge */
282 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
283 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
284
285 /* Defines for Nvidia HDA support */
286 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
287 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
288 #define NVIDIA_HDA_ISTRM_COH 0x4d
289 #define NVIDIA_HDA_OSTRM_COH 0x4c
290 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
291
292 /* Defines for Intel SCH HDA snoop control */
293 #define INTEL_SCH_HDA_DEVC 0x78
294 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
295
296 /* Define IN stream 0 FIFO size offset in VIA controller */
297 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
298 /* Define VIA HD Audio Device ID*/
299 #define VIA_HDAC_DEVICE_ID 0x3288
300
301 /* HD Audio class code */
302 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
303
304 /*
305 */
306
307 struct azx_dev {
308 struct snd_dma_buffer bdl; /* BDL buffer */
309 u32 *posbuf; /* position buffer pointer */
310
311 unsigned int bufsize; /* size of the play buffer in bytes */
312 unsigned int period_bytes; /* size of the period in bytes */
313 unsigned int frags; /* number for period in the play buffer */
314 unsigned int fifo_size; /* FIFO size */
315
316 void __iomem *sd_addr; /* stream descriptor pointer */
317
318 u32 sd_int_sta_mask; /* stream int status mask */
319
320 /* pcm support */
321 struct snd_pcm_substream *substream; /* assigned substream,
322 * set in PCM open
323 */
324 unsigned int format_val; /* format value to be set in the
325 * controller and the codec
326 */
327 unsigned char stream_tag; /* assigned stream */
328 unsigned char index; /* stream index */
329
330 unsigned int opened :1;
331 unsigned int running :1;
332 unsigned int irq_pending :1;
333 unsigned int irq_ignore :1;
334 /*
335 * For VIA:
336 * A flag to ensure DMA position is 0
337 * when link position is not greater than FIFO size
338 */
339 unsigned int insufficient :1;
340 };
341
342 /* CORB/RIRB */
343 struct azx_rb {
344 u32 *buf; /* CORB/RIRB buffer
345 * Each CORB entry is 4byte, RIRB is 8byte
346 */
347 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
348 /* for RIRB */
349 unsigned short rp, wp; /* read/write pointers */
350 int cmds; /* number of pending requests */
351 u32 res; /* last read value */
352 };
353
354 struct azx {
355 struct snd_card *card;
356 struct pci_dev *pci;
357 int dev_index;
358
359 /* chip type specific */
360 int driver_type;
361 int playback_streams;
362 int playback_index_offset;
363 int capture_streams;
364 int capture_index_offset;
365 int num_streams;
366
367 /* pci resources */
368 unsigned long addr;
369 void __iomem *remap_addr;
370 int irq;
371
372 /* locks */
373 spinlock_t reg_lock;
374 struct mutex open_mutex;
375
376 /* streams (x num_streams) */
377 struct azx_dev *azx_dev;
378
379 /* PCM */
380 struct snd_pcm *pcm[AZX_MAX_PCMS];
381
382 /* HD codec */
383 unsigned short codec_mask;
384 int codec_probe_mask; /* copied from probe_mask option */
385 struct hda_bus *bus;
386
387 /* CORB/RIRB */
388 struct azx_rb corb;
389 struct azx_rb rirb;
390
391 /* CORB/RIRB and position buffers */
392 struct snd_dma_buffer rb;
393 struct snd_dma_buffer posbuf;
394
395 /* flags */
396 int position_fix;
397 unsigned int running :1;
398 unsigned int initialized :1;
399 unsigned int single_cmd :1;
400 unsigned int polling_mode :1;
401 unsigned int msi :1;
402 unsigned int irq_pending_warned :1;
403 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
404 unsigned int probing :1; /* codec probing phase */
405
406 /* for debugging */
407 unsigned int last_cmd; /* last issued command (to sync) */
408
409 /* for pending irqs */
410 struct work_struct irq_pending_work;
411
412 /* reboot notifier (for mysterious hangup problem at power-down) */
413 struct notifier_block reboot_notifier;
414 };
415
416 /* driver types */
417 enum {
418 AZX_DRIVER_ICH,
419 AZX_DRIVER_SCH,
420 AZX_DRIVER_ATI,
421 AZX_DRIVER_ATIHDMI,
422 AZX_DRIVER_VIA,
423 AZX_DRIVER_SIS,
424 AZX_DRIVER_ULI,
425 AZX_DRIVER_NVIDIA,
426 AZX_DRIVER_TERA,
427 AZX_DRIVER_GENERIC,
428 AZX_NUM_DRIVERS, /* keep this as last entry */
429 };
430
431 static char *driver_short_names[] __devinitdata = {
432 [AZX_DRIVER_ICH] = "HDA Intel",
433 [AZX_DRIVER_SCH] = "HDA Intel MID",
434 [AZX_DRIVER_ATI] = "HDA ATI SB",
435 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
436 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
437 [AZX_DRIVER_SIS] = "HDA SIS966",
438 [AZX_DRIVER_ULI] = "HDA ULI M5461",
439 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
440 [AZX_DRIVER_TERA] = "HDA Teradici",
441 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
442 };
443
444 /*
445 * macros for easy use
446 */
447 #define azx_writel(chip,reg,value) \
448 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
449 #define azx_readl(chip,reg) \
450 readl((chip)->remap_addr + ICH6_REG_##reg)
451 #define azx_writew(chip,reg,value) \
452 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
453 #define azx_readw(chip,reg) \
454 readw((chip)->remap_addr + ICH6_REG_##reg)
455 #define azx_writeb(chip,reg,value) \
456 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
457 #define azx_readb(chip,reg) \
458 readb((chip)->remap_addr + ICH6_REG_##reg)
459
460 #define azx_sd_writel(dev,reg,value) \
461 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
462 #define azx_sd_readl(dev,reg) \
463 readl((dev)->sd_addr + ICH6_REG_##reg)
464 #define azx_sd_writew(dev,reg,value) \
465 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
466 #define azx_sd_readw(dev,reg) \
467 readw((dev)->sd_addr + ICH6_REG_##reg)
468 #define azx_sd_writeb(dev,reg,value) \
469 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
470 #define azx_sd_readb(dev,reg) \
471 readb((dev)->sd_addr + ICH6_REG_##reg)
472
473 /* for pcm support */
474 #define get_azx_dev(substream) (substream->runtime->private_data)
475
476 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
477
478 /*
479 * Interface for HD codec
480 */
481
482 /*
483 * CORB / RIRB interface
484 */
485 static int azx_alloc_cmd_io(struct azx *chip)
486 {
487 int err;
488
489 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
490 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
491 snd_dma_pci_data(chip->pci),
492 PAGE_SIZE, &chip->rb);
493 if (err < 0) {
494 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
495 return err;
496 }
497 return 0;
498 }
499
500 static void azx_init_cmd_io(struct azx *chip)
501 {
502 /* CORB set up */
503 chip->corb.addr = chip->rb.addr;
504 chip->corb.buf = (u32 *)chip->rb.area;
505 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
506 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
507
508 /* set the corb size to 256 entries (ULI requires explicitly) */
509 azx_writeb(chip, CORBSIZE, 0x02);
510 /* set the corb write pointer to 0 */
511 azx_writew(chip, CORBWP, 0);
512 /* reset the corb hw read pointer */
513 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
514 /* enable corb dma */
515 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
516
517 /* RIRB set up */
518 chip->rirb.addr = chip->rb.addr + 2048;
519 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
520 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
521 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
522
523 /* set the rirb size to 256 entries (ULI requires explicitly) */
524 azx_writeb(chip, RIRBSIZE, 0x02);
525 /* reset the rirb hw write pointer */
526 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
527 /* set N=1, get RIRB response interrupt for new entry */
528 azx_writew(chip, RINTCNT, 1);
529 /* enable rirb dma and response irq */
530 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
531 chip->rirb.rp = chip->rirb.cmds = 0;
532 }
533
534 static void azx_free_cmd_io(struct azx *chip)
535 {
536 /* disable ringbuffer DMAs */
537 azx_writeb(chip, RIRBCTL, 0);
538 azx_writeb(chip, CORBCTL, 0);
539 }
540
541 /* send a command */
542 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
543 {
544 struct azx *chip = bus->private_data;
545 unsigned int wp;
546
547 /* add command to corb */
548 wp = azx_readb(chip, CORBWP);
549 wp++;
550 wp %= ICH6_MAX_CORB_ENTRIES;
551
552 spin_lock_irq(&chip->reg_lock);
553 chip->rirb.cmds++;
554 chip->corb.buf[wp] = cpu_to_le32(val);
555 azx_writel(chip, CORBWP, wp);
556 spin_unlock_irq(&chip->reg_lock);
557
558 return 0;
559 }
560
561 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
562
563 /* retrieve RIRB entry - called from interrupt handler */
564 static void azx_update_rirb(struct azx *chip)
565 {
566 unsigned int rp, wp;
567 u32 res, res_ex;
568
569 wp = azx_readb(chip, RIRBWP);
570 if (wp == chip->rirb.wp)
571 return;
572 chip->rirb.wp = wp;
573
574 while (chip->rirb.rp != wp) {
575 chip->rirb.rp++;
576 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
577
578 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
579 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
580 res = le32_to_cpu(chip->rirb.buf[rp]);
581 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
582 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
583 else if (chip->rirb.cmds) {
584 chip->rirb.res = res;
585 smp_wmb();
586 chip->rirb.cmds--;
587 }
588 }
589 }
590
591 /* receive a response */
592 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
593 {
594 struct azx *chip = bus->private_data;
595 unsigned long timeout;
596
597 again:
598 timeout = jiffies + msecs_to_jiffies(1000);
599 for (;;) {
600 if (chip->polling_mode) {
601 spin_lock_irq(&chip->reg_lock);
602 azx_update_rirb(chip);
603 spin_unlock_irq(&chip->reg_lock);
604 }
605 if (!chip->rirb.cmds) {
606 smp_rmb();
607 bus->rirb_error = 0;
608 return chip->rirb.res; /* the last value */
609 }
610 if (time_after(jiffies, timeout))
611 break;
612 if (bus->needs_damn_long_delay)
613 msleep(2); /* temporary workaround */
614 else {
615 udelay(10);
616 cond_resched();
617 }
618 }
619
620 if (chip->msi) {
621 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
622 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
623 free_irq(chip->irq, chip);
624 chip->irq = -1;
625 pci_disable_msi(chip->pci);
626 chip->msi = 0;
627 if (azx_acquire_irq(chip, 1) < 0) {
628 bus->rirb_error = 1;
629 return -1;
630 }
631 goto again;
632 }
633
634 if (!chip->polling_mode) {
635 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
636 "switching to polling mode: last cmd=0x%08x\n",
637 chip->last_cmd);
638 chip->polling_mode = 1;
639 goto again;
640 }
641
642 if (chip->probing) {
643 /* If this critical timeout happens during the codec probing
644 * phase, this is likely an access to a non-existing codec
645 * slot. Better to return an error and reset the system.
646 */
647 return -1;
648 }
649
650 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout (ERROR): "
651 "last cmd=0x%08x\n", chip->last_cmd);
652 spin_lock_irq(&chip->reg_lock);
653 chip->rirb.cmds = 0; /* reset the index */
654 bus->rirb_error = 1;
655 spin_unlock_irq(&chip->reg_lock);
656 return -1;
657 }
658
659 /*
660 * Use the single immediate command instead of CORB/RIRB for simplicity
661 *
662 * Note: according to Intel, this is not preferred use. The command was
663 * intended for the BIOS only, and may get confused with unsolicited
664 * responses. So, we shouldn't use it for normal operation from the
665 * driver.
666 * I left the codes, however, for debugging/testing purposes.
667 */
668
669 /* send a command */
670 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
671 {
672 struct azx *chip = bus->private_data;
673 int timeout = 50;
674
675 while (timeout--) {
676 /* check ICB busy bit */
677 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
678 /* Clear IRV valid bit */
679 azx_writew(chip, IRS, azx_readw(chip, IRS) |
680 ICH6_IRS_VALID);
681 azx_writel(chip, IC, val);
682 azx_writew(chip, IRS, azx_readw(chip, IRS) |
683 ICH6_IRS_BUSY);
684 return 0;
685 }
686 udelay(1);
687 }
688 if (printk_ratelimit())
689 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
690 azx_readw(chip, IRS), val);
691 return -EIO;
692 }
693
694 /* receive a response */
695 static unsigned int azx_single_get_response(struct hda_bus *bus)
696 {
697 struct azx *chip = bus->private_data;
698 int timeout = 50;
699
700 while (timeout--) {
701 /* check IRV busy bit */
702 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
703 return azx_readl(chip, IR);
704 udelay(1);
705 }
706 if (printk_ratelimit())
707 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
708 azx_readw(chip, IRS));
709 return (unsigned int)-1;
710 }
711
712 /*
713 * The below are the main callbacks from hda_codec.
714 *
715 * They are just the skeleton to call sub-callbacks according to the
716 * current setting of chip->single_cmd.
717 */
718
719 /* send a command */
720 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
721 {
722 struct azx *chip = bus->private_data;
723
724 chip->last_cmd = val;
725 if (chip->single_cmd)
726 return azx_single_send_cmd(bus, val);
727 else
728 return azx_corb_send_cmd(bus, val);
729 }
730
731 /* get a response */
732 static unsigned int azx_get_response(struct hda_bus *bus)
733 {
734 struct azx *chip = bus->private_data;
735 if (chip->single_cmd)
736 return azx_single_get_response(bus);
737 else
738 return azx_rirb_get_response(bus);
739 }
740
741 #ifdef CONFIG_SND_HDA_POWER_SAVE
742 static void azx_power_notify(struct hda_bus *bus);
743 #endif
744
745 /* reset codec link */
746 static int azx_reset(struct azx *chip)
747 {
748 int count;
749
750 /* clear STATESTS */
751 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
752
753 /* reset controller */
754 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
755
756 count = 50;
757 while (azx_readb(chip, GCTL) && --count)
758 msleep(1);
759
760 /* delay for >= 100us for codec PLL to settle per spec
761 * Rev 0.9 section 5.5.1
762 */
763 msleep(1);
764
765 /* Bring controller out of reset */
766 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
767
768 count = 50;
769 while (!azx_readb(chip, GCTL) && --count)
770 msleep(1);
771
772 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
773 msleep(1);
774
775 /* check to see if controller is ready */
776 if (!azx_readb(chip, GCTL)) {
777 snd_printd("azx_reset: controller not ready!\n");
778 return -EBUSY;
779 }
780
781 /* Accept unsolicited responses */
782 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
783
784 /* detect codecs */
785 if (!chip->codec_mask) {
786 chip->codec_mask = azx_readw(chip, STATESTS);
787 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
788 }
789
790 return 0;
791 }
792
793
794 /*
795 * Lowlevel interface
796 */
797
798 /* enable interrupts */
799 static void azx_int_enable(struct azx *chip)
800 {
801 /* enable controller CIE and GIE */
802 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
803 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
804 }
805
806 /* disable interrupts */
807 static void azx_int_disable(struct azx *chip)
808 {
809 int i;
810
811 /* disable interrupts in stream descriptor */
812 for (i = 0; i < chip->num_streams; i++) {
813 struct azx_dev *azx_dev = &chip->azx_dev[i];
814 azx_sd_writeb(azx_dev, SD_CTL,
815 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
816 }
817
818 /* disable SIE for all streams */
819 azx_writeb(chip, INTCTL, 0);
820
821 /* disable controller CIE and GIE */
822 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
823 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
824 }
825
826 /* clear interrupts */
827 static void azx_int_clear(struct azx *chip)
828 {
829 int i;
830
831 /* clear stream status */
832 for (i = 0; i < chip->num_streams; i++) {
833 struct azx_dev *azx_dev = &chip->azx_dev[i];
834 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
835 }
836
837 /* clear STATESTS */
838 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
839
840 /* clear rirb status */
841 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
842
843 /* clear int status */
844 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
845 }
846
847 /* start a stream */
848 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
849 {
850 /*
851 * Before stream start, initialize parameter
852 */
853 azx_dev->insufficient = 1;
854
855 /* enable SIE */
856 azx_writeb(chip, INTCTL,
857 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
858 /* set DMA start and interrupt mask */
859 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
860 SD_CTL_DMA_START | SD_INT_MASK);
861 }
862
863 /* stop DMA */
864 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
865 {
866 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
867 ~(SD_CTL_DMA_START | SD_INT_MASK));
868 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
869 }
870
871 /* stop a stream */
872 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
873 {
874 azx_stream_clear(chip, azx_dev);
875 /* disable SIE */
876 azx_writeb(chip, INTCTL,
877 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
878 }
879
880
881 /*
882 * reset and start the controller registers
883 */
884 static void azx_init_chip(struct azx *chip)
885 {
886 if (chip->initialized)
887 return;
888
889 /* reset controller */
890 azx_reset(chip);
891
892 /* initialize interrupts */
893 azx_int_clear(chip);
894 azx_int_enable(chip);
895
896 /* initialize the codec command I/O */
897 if (!chip->single_cmd)
898 azx_init_cmd_io(chip);
899
900 /* program the position buffer */
901 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
902 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
903
904 chip->initialized = 1;
905 }
906
907 /*
908 * initialize the PCI registers
909 */
910 /* update bits in a PCI register byte */
911 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
912 unsigned char mask, unsigned char val)
913 {
914 unsigned char data;
915
916 pci_read_config_byte(pci, reg, &data);
917 data &= ~mask;
918 data |= (val & mask);
919 pci_write_config_byte(pci, reg, data);
920 }
921
922 static void azx_init_pci(struct azx *chip)
923 {
924 unsigned short snoop;
925
926 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
927 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
928 * Ensuring these bits are 0 clears playback static on some HD Audio
929 * codecs
930 */
931 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
932
933 switch (chip->driver_type) {
934 case AZX_DRIVER_ATI:
935 /* For ATI SB450 azalia HD audio, we need to enable snoop */
936 update_pci_byte(chip->pci,
937 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
938 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
939 break;
940 case AZX_DRIVER_NVIDIA:
941 /* For NVIDIA HDA, enable snoop */
942 update_pci_byte(chip->pci,
943 NVIDIA_HDA_TRANSREG_ADDR,
944 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
945 update_pci_byte(chip->pci,
946 NVIDIA_HDA_ISTRM_COH,
947 0x01, NVIDIA_HDA_ENABLE_COHBIT);
948 update_pci_byte(chip->pci,
949 NVIDIA_HDA_OSTRM_COH,
950 0x01, NVIDIA_HDA_ENABLE_COHBIT);
951 break;
952 case AZX_DRIVER_SCH:
953 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
954 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
955 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
956 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
957 pci_read_config_word(chip->pci,
958 INTEL_SCH_HDA_DEVC, &snoop);
959 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
960 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
961 ? "Failed" : "OK");
962 }
963 break;
964
965 }
966 }
967
968
969 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
970
971 /*
972 * interrupt handler
973 */
974 static irqreturn_t azx_interrupt(int irq, void *dev_id)
975 {
976 struct azx *chip = dev_id;
977 struct azx_dev *azx_dev;
978 u32 status;
979 int i;
980
981 spin_lock(&chip->reg_lock);
982
983 status = azx_readl(chip, INTSTS);
984 if (status == 0) {
985 spin_unlock(&chip->reg_lock);
986 return IRQ_NONE;
987 }
988
989 for (i = 0; i < chip->num_streams; i++) {
990 azx_dev = &chip->azx_dev[i];
991 if (status & azx_dev->sd_int_sta_mask) {
992 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
993 if (!azx_dev->substream || !azx_dev->running)
994 continue;
995 /* ignore the first dummy IRQ (due to pos_adj) */
996 if (azx_dev->irq_ignore) {
997 azx_dev->irq_ignore = 0;
998 continue;
999 }
1000 /* check whether this IRQ is really acceptable */
1001 if (azx_position_ok(chip, azx_dev)) {
1002 azx_dev->irq_pending = 0;
1003 spin_unlock(&chip->reg_lock);
1004 snd_pcm_period_elapsed(azx_dev->substream);
1005 spin_lock(&chip->reg_lock);
1006 } else if (chip->bus && chip->bus->workq) {
1007 /* bogus IRQ, process it later */
1008 azx_dev->irq_pending = 1;
1009 queue_work(chip->bus->workq,
1010 &chip->irq_pending_work);
1011 }
1012 }
1013 }
1014
1015 /* clear rirb int */
1016 status = azx_readb(chip, RIRBSTS);
1017 if (status & RIRB_INT_MASK) {
1018 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1019 azx_update_rirb(chip);
1020 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1021 }
1022
1023 #if 0
1024 /* clear state status int */
1025 if (azx_readb(chip, STATESTS) & 0x04)
1026 azx_writeb(chip, STATESTS, 0x04);
1027 #endif
1028 spin_unlock(&chip->reg_lock);
1029
1030 return IRQ_HANDLED;
1031 }
1032
1033
1034 /*
1035 * set up a BDL entry
1036 */
1037 static int setup_bdle(struct snd_pcm_substream *substream,
1038 struct azx_dev *azx_dev, u32 **bdlp,
1039 int ofs, int size, int with_ioc)
1040 {
1041 u32 *bdl = *bdlp;
1042
1043 while (size > 0) {
1044 dma_addr_t addr;
1045 int chunk;
1046
1047 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1048 return -EINVAL;
1049
1050 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1051 /* program the address field of the BDL entry */
1052 bdl[0] = cpu_to_le32((u32)addr);
1053 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1054 /* program the size field of the BDL entry */
1055 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1056 bdl[2] = cpu_to_le32(chunk);
1057 /* program the IOC to enable interrupt
1058 * only when the whole fragment is processed
1059 */
1060 size -= chunk;
1061 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1062 bdl += 4;
1063 azx_dev->frags++;
1064 ofs += chunk;
1065 }
1066 *bdlp = bdl;
1067 return ofs;
1068 }
1069
1070 /*
1071 * set up BDL entries
1072 */
1073 static int azx_setup_periods(struct azx *chip,
1074 struct snd_pcm_substream *substream,
1075 struct azx_dev *azx_dev)
1076 {
1077 u32 *bdl;
1078 int i, ofs, periods, period_bytes;
1079 int pos_adj;
1080
1081 /* reset BDL address */
1082 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1083 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1084
1085 period_bytes = azx_dev->period_bytes;
1086 periods = azx_dev->bufsize / period_bytes;
1087
1088 /* program the initial BDL entries */
1089 bdl = (u32 *)azx_dev->bdl.area;
1090 ofs = 0;
1091 azx_dev->frags = 0;
1092 azx_dev->irq_ignore = 0;
1093 pos_adj = bdl_pos_adj[chip->dev_index];
1094 if (pos_adj > 0) {
1095 struct snd_pcm_runtime *runtime = substream->runtime;
1096 int pos_align = pos_adj;
1097 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1098 if (!pos_adj)
1099 pos_adj = pos_align;
1100 else
1101 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1102 pos_align;
1103 pos_adj = frames_to_bytes(runtime, pos_adj);
1104 if (pos_adj >= period_bytes) {
1105 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1106 bdl_pos_adj[chip->dev_index]);
1107 pos_adj = 0;
1108 } else {
1109 ofs = setup_bdle(substream, azx_dev,
1110 &bdl, ofs, pos_adj, 1);
1111 if (ofs < 0)
1112 goto error;
1113 azx_dev->irq_ignore = 1;
1114 }
1115 } else
1116 pos_adj = 0;
1117 for (i = 0; i < periods; i++) {
1118 if (i == periods - 1 && pos_adj)
1119 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1120 period_bytes - pos_adj, 0);
1121 else
1122 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1123 period_bytes, 1);
1124 if (ofs < 0)
1125 goto error;
1126 }
1127 return 0;
1128
1129 error:
1130 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1131 azx_dev->bufsize, period_bytes);
1132 return -EINVAL;
1133 }
1134
1135 /* reset stream */
1136 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1137 {
1138 unsigned char val;
1139 int timeout;
1140
1141 azx_stream_clear(chip, azx_dev);
1142
1143 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1144 SD_CTL_STREAM_RESET);
1145 udelay(3);
1146 timeout = 300;
1147 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1148 --timeout)
1149 ;
1150 val &= ~SD_CTL_STREAM_RESET;
1151 azx_sd_writeb(azx_dev, SD_CTL, val);
1152 udelay(3);
1153
1154 timeout = 300;
1155 /* waiting for hardware to report that the stream is out of reset */
1156 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1157 --timeout)
1158 ;
1159 }
1160
1161 /*
1162 * set up the SD for streaming
1163 */
1164 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1165 {
1166 /* make sure the run bit is zero for SD */
1167 azx_stream_clear(chip, azx_dev);
1168 /* program the stream_tag */
1169 azx_sd_writel(azx_dev, SD_CTL,
1170 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1171 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1172
1173 /* program the length of samples in cyclic buffer */
1174 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1175
1176 /* program the stream format */
1177 /* this value needs to be the same as the one programmed */
1178 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1179
1180 /* program the stream LVI (last valid index) of the BDL */
1181 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1182
1183 /* program the BDL address */
1184 /* lower BDL address */
1185 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1186 /* upper BDL address */
1187 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1188
1189 /* enable the position buffer */
1190 if (chip->position_fix == POS_FIX_POSBUF ||
1191 chip->position_fix == POS_FIX_AUTO ||
1192 chip->via_dmapos_patch) {
1193 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1194 azx_writel(chip, DPLBASE,
1195 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1196 }
1197
1198 /* set the interrupt enable bits in the descriptor control register */
1199 azx_sd_writel(azx_dev, SD_CTL,
1200 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1201
1202 return 0;
1203 }
1204
1205 /*
1206 * Probe the given codec address
1207 */
1208 static int probe_codec(struct azx *chip, int addr)
1209 {
1210 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1211 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1212 unsigned int res;
1213
1214 chip->probing = 1;
1215 azx_send_cmd(chip->bus, cmd);
1216 res = azx_get_response(chip->bus);
1217 chip->probing = 0;
1218 if (res == -1)
1219 return -EIO;
1220 snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1221 return 0;
1222 }
1223
1224 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1225 struct hda_pcm *cpcm);
1226 static void azx_stop_chip(struct azx *chip);
1227
1228 /*
1229 * Codec initialization
1230 */
1231
1232 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1233 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1234 [AZX_DRIVER_TERA] = 1,
1235 };
1236
1237 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1238 int no_init)
1239 {
1240 struct hda_bus_template bus_temp;
1241 int c, codecs, err;
1242 int max_slots;
1243
1244 memset(&bus_temp, 0, sizeof(bus_temp));
1245 bus_temp.private_data = chip;
1246 bus_temp.modelname = model;
1247 bus_temp.pci = chip->pci;
1248 bus_temp.ops.command = azx_send_cmd;
1249 bus_temp.ops.get_response = azx_get_response;
1250 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1251 #ifdef CONFIG_SND_HDA_POWER_SAVE
1252 bus_temp.power_save = &power_save;
1253 bus_temp.ops.pm_notify = azx_power_notify;
1254 #endif
1255
1256 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1257 if (err < 0)
1258 return err;
1259
1260 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1261 chip->bus->needs_damn_long_delay = 1;
1262
1263 codecs = 0;
1264 max_slots = azx_max_codecs[chip->driver_type];
1265 if (!max_slots)
1266 max_slots = AZX_MAX_CODECS;
1267
1268 /* First try to probe all given codec slots */
1269 for (c = 0; c < max_slots; c++) {
1270 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1271 if (probe_codec(chip, c) < 0) {
1272 /* Some BIOSen give you wrong codec addresses
1273 * that don't exist
1274 */
1275 snd_printk(KERN_WARNING
1276 "hda_intel: Codec #%d probe error; "
1277 "disabling it...\n", c);
1278 chip->codec_mask &= ~(1 << c);
1279 /* More badly, accessing to a non-existing
1280 * codec often screws up the controller chip,
1281 * and distrubs the further communications.
1282 * Thus if an error occurs during probing,
1283 * better to reset the controller chip to
1284 * get back to the sanity state.
1285 */
1286 azx_stop_chip(chip);
1287 azx_init_chip(chip);
1288 }
1289 }
1290 }
1291
1292 /* Then create codec instances */
1293 for (c = 0; c < max_slots; c++) {
1294 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1295 struct hda_codec *codec;
1296 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1297 if (err < 0)
1298 continue;
1299 codecs++;
1300 }
1301 }
1302 if (!codecs) {
1303 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1304 return -ENXIO;
1305 }
1306
1307 return 0;
1308 }
1309
1310
1311 /*
1312 * PCM support
1313 */
1314
1315 /* assign a stream for the PCM */
1316 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1317 {
1318 int dev, i, nums;
1319 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1320 dev = chip->playback_index_offset;
1321 nums = chip->playback_streams;
1322 } else {
1323 dev = chip->capture_index_offset;
1324 nums = chip->capture_streams;
1325 }
1326 for (i = 0; i < nums; i++, dev++)
1327 if (!chip->azx_dev[dev].opened) {
1328 chip->azx_dev[dev].opened = 1;
1329 return &chip->azx_dev[dev];
1330 }
1331 return NULL;
1332 }
1333
1334 /* release the assigned stream */
1335 static inline void azx_release_device(struct azx_dev *azx_dev)
1336 {
1337 azx_dev->opened = 0;
1338 }
1339
1340 static struct snd_pcm_hardware azx_pcm_hw = {
1341 .info = (SNDRV_PCM_INFO_MMAP |
1342 SNDRV_PCM_INFO_INTERLEAVED |
1343 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1344 SNDRV_PCM_INFO_MMAP_VALID |
1345 /* No full-resume yet implemented */
1346 /* SNDRV_PCM_INFO_RESUME |*/
1347 SNDRV_PCM_INFO_PAUSE |
1348 SNDRV_PCM_INFO_SYNC_START),
1349 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1350 .rates = SNDRV_PCM_RATE_48000,
1351 .rate_min = 48000,
1352 .rate_max = 48000,
1353 .channels_min = 2,
1354 .channels_max = 2,
1355 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1356 .period_bytes_min = 128,
1357 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1358 .periods_min = 2,
1359 .periods_max = AZX_MAX_FRAG,
1360 .fifo_size = 0,
1361 };
1362
1363 struct azx_pcm {
1364 struct azx *chip;
1365 struct hda_codec *codec;
1366 struct hda_pcm_stream *hinfo[2];
1367 };
1368
1369 static int azx_pcm_open(struct snd_pcm_substream *substream)
1370 {
1371 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1372 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1373 struct azx *chip = apcm->chip;
1374 struct azx_dev *azx_dev;
1375 struct snd_pcm_runtime *runtime = substream->runtime;
1376 unsigned long flags;
1377 int err;
1378
1379 mutex_lock(&chip->open_mutex);
1380 azx_dev = azx_assign_device(chip, substream->stream);
1381 if (azx_dev == NULL) {
1382 mutex_unlock(&chip->open_mutex);
1383 return -EBUSY;
1384 }
1385 runtime->hw = azx_pcm_hw;
1386 runtime->hw.channels_min = hinfo->channels_min;
1387 runtime->hw.channels_max = hinfo->channels_max;
1388 runtime->hw.formats = hinfo->formats;
1389 runtime->hw.rates = hinfo->rates;
1390 snd_pcm_limit_hw_rates(runtime);
1391 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1392 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1393 128);
1394 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1395 128);
1396 snd_hda_power_up(apcm->codec);
1397 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1398 if (err < 0) {
1399 azx_release_device(azx_dev);
1400 snd_hda_power_down(apcm->codec);
1401 mutex_unlock(&chip->open_mutex);
1402 return err;
1403 }
1404 spin_lock_irqsave(&chip->reg_lock, flags);
1405 azx_dev->substream = substream;
1406 azx_dev->running = 0;
1407 spin_unlock_irqrestore(&chip->reg_lock, flags);
1408
1409 runtime->private_data = azx_dev;
1410 snd_pcm_set_sync(substream);
1411 mutex_unlock(&chip->open_mutex);
1412
1413 azx_stream_reset(chip, azx_dev);
1414 return 0;
1415 }
1416
1417 static int azx_pcm_close(struct snd_pcm_substream *substream)
1418 {
1419 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1420 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1421 struct azx *chip = apcm->chip;
1422 struct azx_dev *azx_dev = get_azx_dev(substream);
1423 unsigned long flags;
1424
1425 mutex_lock(&chip->open_mutex);
1426 spin_lock_irqsave(&chip->reg_lock, flags);
1427 azx_dev->substream = NULL;
1428 azx_dev->running = 0;
1429 spin_unlock_irqrestore(&chip->reg_lock, flags);
1430 azx_release_device(azx_dev);
1431 hinfo->ops.close(hinfo, apcm->codec, substream);
1432 snd_hda_power_down(apcm->codec);
1433 mutex_unlock(&chip->open_mutex);
1434 return 0;
1435 }
1436
1437 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1438 struct snd_pcm_hw_params *hw_params)
1439 {
1440 struct azx_dev *azx_dev = get_azx_dev(substream);
1441
1442 azx_dev->bufsize = 0;
1443 azx_dev->period_bytes = 0;
1444 azx_dev->format_val = 0;
1445 return snd_pcm_lib_malloc_pages(substream,
1446 params_buffer_bytes(hw_params));
1447 }
1448
1449 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1450 {
1451 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1452 struct azx_dev *azx_dev = get_azx_dev(substream);
1453 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1454
1455 /* reset BDL address */
1456 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1457 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1458 azx_sd_writel(azx_dev, SD_CTL, 0);
1459 azx_dev->bufsize = 0;
1460 azx_dev->period_bytes = 0;
1461 azx_dev->format_val = 0;
1462
1463 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1464
1465 return snd_pcm_lib_free_pages(substream);
1466 }
1467
1468 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1469 {
1470 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1471 struct azx *chip = apcm->chip;
1472 struct azx_dev *azx_dev = get_azx_dev(substream);
1473 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1474 struct snd_pcm_runtime *runtime = substream->runtime;
1475 unsigned int bufsize, period_bytes, format_val;
1476 int err;
1477
1478 format_val = snd_hda_calc_stream_format(runtime->rate,
1479 runtime->channels,
1480 runtime->format,
1481 hinfo->maxbps);
1482 if (!format_val) {
1483 snd_printk(KERN_ERR SFX
1484 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1485 runtime->rate, runtime->channels, runtime->format);
1486 return -EINVAL;
1487 }
1488
1489 bufsize = snd_pcm_lib_buffer_bytes(substream);
1490 period_bytes = snd_pcm_lib_period_bytes(substream);
1491
1492 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1493 bufsize, format_val);
1494
1495 if (bufsize != azx_dev->bufsize ||
1496 period_bytes != azx_dev->period_bytes ||
1497 format_val != azx_dev->format_val) {
1498 azx_dev->bufsize = bufsize;
1499 azx_dev->period_bytes = period_bytes;
1500 azx_dev->format_val = format_val;
1501 err = azx_setup_periods(chip, substream, azx_dev);
1502 if (err < 0)
1503 return err;
1504 }
1505
1506 azx_setup_controller(chip, azx_dev);
1507 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1508 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1509 else
1510 azx_dev->fifo_size = 0;
1511
1512 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1513 azx_dev->format_val, substream);
1514 }
1515
1516 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1517 {
1518 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1519 struct azx *chip = apcm->chip;
1520 struct azx_dev *azx_dev;
1521 struct snd_pcm_substream *s;
1522 int start, nsync = 0, sbits = 0;
1523 int nwait, timeout;
1524
1525 switch (cmd) {
1526 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1527 case SNDRV_PCM_TRIGGER_RESUME:
1528 case SNDRV_PCM_TRIGGER_START:
1529 start = 1;
1530 break;
1531 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1532 case SNDRV_PCM_TRIGGER_SUSPEND:
1533 case SNDRV_PCM_TRIGGER_STOP:
1534 start = 0;
1535 break;
1536 default:
1537 return -EINVAL;
1538 }
1539
1540 snd_pcm_group_for_each_entry(s, substream) {
1541 if (s->pcm->card != substream->pcm->card)
1542 continue;
1543 azx_dev = get_azx_dev(s);
1544 sbits |= 1 << azx_dev->index;
1545 nsync++;
1546 snd_pcm_trigger_done(s, substream);
1547 }
1548
1549 spin_lock(&chip->reg_lock);
1550 if (nsync > 1) {
1551 /* first, set SYNC bits of corresponding streams */
1552 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1553 }
1554 snd_pcm_group_for_each_entry(s, substream) {
1555 if (s->pcm->card != substream->pcm->card)
1556 continue;
1557 azx_dev = get_azx_dev(s);
1558 if (start)
1559 azx_stream_start(chip, azx_dev);
1560 else
1561 azx_stream_stop(chip, azx_dev);
1562 azx_dev->running = start;
1563 }
1564 spin_unlock(&chip->reg_lock);
1565 if (start) {
1566 if (nsync == 1)
1567 return 0;
1568 /* wait until all FIFOs get ready */
1569 for (timeout = 5000; timeout; timeout--) {
1570 nwait = 0;
1571 snd_pcm_group_for_each_entry(s, substream) {
1572 if (s->pcm->card != substream->pcm->card)
1573 continue;
1574 azx_dev = get_azx_dev(s);
1575 if (!(azx_sd_readb(azx_dev, SD_STS) &
1576 SD_STS_FIFO_READY))
1577 nwait++;
1578 }
1579 if (!nwait)
1580 break;
1581 cpu_relax();
1582 }
1583 } else {
1584 /* wait until all RUN bits are cleared */
1585 for (timeout = 5000; timeout; timeout--) {
1586 nwait = 0;
1587 snd_pcm_group_for_each_entry(s, substream) {
1588 if (s->pcm->card != substream->pcm->card)
1589 continue;
1590 azx_dev = get_azx_dev(s);
1591 if (azx_sd_readb(azx_dev, SD_CTL) &
1592 SD_CTL_DMA_START)
1593 nwait++;
1594 }
1595 if (!nwait)
1596 break;
1597 cpu_relax();
1598 }
1599 }
1600 if (nsync > 1) {
1601 spin_lock(&chip->reg_lock);
1602 /* reset SYNC bits */
1603 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1604 spin_unlock(&chip->reg_lock);
1605 }
1606 return 0;
1607 }
1608
1609 /* get the current DMA position with correction on VIA chips */
1610 static unsigned int azx_via_get_position(struct azx *chip,
1611 struct azx_dev *azx_dev)
1612 {
1613 unsigned int link_pos, mini_pos, bound_pos;
1614 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1615 unsigned int fifo_size;
1616
1617 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1618 if (azx_dev->index >= 4) {
1619 /* Playback, no problem using link position */
1620 return link_pos;
1621 }
1622
1623 /* Capture */
1624 /* For new chipset,
1625 * use mod to get the DMA position just like old chipset
1626 */
1627 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1628 mod_dma_pos %= azx_dev->period_bytes;
1629
1630 /* azx_dev->fifo_size can't get FIFO size of in stream.
1631 * Get from base address + offset.
1632 */
1633 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1634
1635 if (azx_dev->insufficient) {
1636 /* Link position never gather than FIFO size */
1637 if (link_pos <= fifo_size)
1638 return 0;
1639
1640 azx_dev->insufficient = 0;
1641 }
1642
1643 if (link_pos <= fifo_size)
1644 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1645 else
1646 mini_pos = link_pos - fifo_size;
1647
1648 /* Find nearest previous boudary */
1649 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1650 mod_link_pos = link_pos % azx_dev->period_bytes;
1651 if (mod_link_pos >= fifo_size)
1652 bound_pos = link_pos - mod_link_pos;
1653 else if (mod_dma_pos >= mod_mini_pos)
1654 bound_pos = mini_pos - mod_mini_pos;
1655 else {
1656 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1657 if (bound_pos >= azx_dev->bufsize)
1658 bound_pos = 0;
1659 }
1660
1661 /* Calculate real DMA position we want */
1662 return bound_pos + mod_dma_pos;
1663 }
1664
1665 static unsigned int azx_get_position(struct azx *chip,
1666 struct azx_dev *azx_dev)
1667 {
1668 unsigned int pos;
1669
1670 if (chip->via_dmapos_patch)
1671 pos = azx_via_get_position(chip, azx_dev);
1672 else if (chip->position_fix == POS_FIX_POSBUF ||
1673 chip->position_fix == POS_FIX_AUTO) {
1674 /* use the position buffer */
1675 pos = le32_to_cpu(*azx_dev->posbuf);
1676 } else {
1677 /* read LPIB */
1678 pos = azx_sd_readl(azx_dev, SD_LPIB);
1679 }
1680 if (pos >= azx_dev->bufsize)
1681 pos = 0;
1682 return pos;
1683 }
1684
1685 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1686 {
1687 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1688 struct azx *chip = apcm->chip;
1689 struct azx_dev *azx_dev = get_azx_dev(substream);
1690 return bytes_to_frames(substream->runtime,
1691 azx_get_position(chip, azx_dev));
1692 }
1693
1694 /*
1695 * Check whether the current DMA position is acceptable for updating
1696 * periods. Returns non-zero if it's OK.
1697 *
1698 * Many HD-audio controllers appear pretty inaccurate about
1699 * the update-IRQ timing. The IRQ is issued before actually the
1700 * data is processed. So, we need to process it afterwords in a
1701 * workqueue.
1702 */
1703 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1704 {
1705 unsigned int pos;
1706
1707 pos = azx_get_position(chip, azx_dev);
1708 if (chip->position_fix == POS_FIX_AUTO) {
1709 if (!pos) {
1710 printk(KERN_WARNING
1711 "hda-intel: Invalid position buffer, "
1712 "using LPIB read method instead.\n");
1713 chip->position_fix = POS_FIX_LPIB;
1714 pos = azx_get_position(chip, azx_dev);
1715 } else
1716 chip->position_fix = POS_FIX_POSBUF;
1717 }
1718
1719 if (!bdl_pos_adj[chip->dev_index])
1720 return 1; /* no delayed ack */
1721 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1722 return 0; /* NG - it's below the period boundary */
1723 return 1; /* OK, it's fine */
1724 }
1725
1726 /*
1727 * The work for pending PCM period updates.
1728 */
1729 static void azx_irq_pending_work(struct work_struct *work)
1730 {
1731 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1732 int i, pending;
1733
1734 if (!chip->irq_pending_warned) {
1735 printk(KERN_WARNING
1736 "hda-intel: IRQ timing workaround is activated "
1737 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1738 chip->card->number);
1739 chip->irq_pending_warned = 1;
1740 }
1741
1742 for (;;) {
1743 pending = 0;
1744 spin_lock_irq(&chip->reg_lock);
1745 for (i = 0; i < chip->num_streams; i++) {
1746 struct azx_dev *azx_dev = &chip->azx_dev[i];
1747 if (!azx_dev->irq_pending ||
1748 !azx_dev->substream ||
1749 !azx_dev->running)
1750 continue;
1751 if (azx_position_ok(chip, azx_dev)) {
1752 azx_dev->irq_pending = 0;
1753 spin_unlock(&chip->reg_lock);
1754 snd_pcm_period_elapsed(azx_dev->substream);
1755 spin_lock(&chip->reg_lock);
1756 } else
1757 pending++;
1758 }
1759 spin_unlock_irq(&chip->reg_lock);
1760 if (!pending)
1761 return;
1762 cond_resched();
1763 }
1764 }
1765
1766 /* clear irq_pending flags and assure no on-going workq */
1767 static void azx_clear_irq_pending(struct azx *chip)
1768 {
1769 int i;
1770
1771 spin_lock_irq(&chip->reg_lock);
1772 for (i = 0; i < chip->num_streams; i++)
1773 chip->azx_dev[i].irq_pending = 0;
1774 spin_unlock_irq(&chip->reg_lock);
1775 }
1776
1777 static struct snd_pcm_ops azx_pcm_ops = {
1778 .open = azx_pcm_open,
1779 .close = azx_pcm_close,
1780 .ioctl = snd_pcm_lib_ioctl,
1781 .hw_params = azx_pcm_hw_params,
1782 .hw_free = azx_pcm_hw_free,
1783 .prepare = azx_pcm_prepare,
1784 .trigger = azx_pcm_trigger,
1785 .pointer = azx_pcm_pointer,
1786 .page = snd_pcm_sgbuf_ops_page,
1787 };
1788
1789 static void azx_pcm_free(struct snd_pcm *pcm)
1790 {
1791 struct azx_pcm *apcm = pcm->private_data;
1792 if (apcm) {
1793 apcm->chip->pcm[pcm->device] = NULL;
1794 kfree(apcm);
1795 }
1796 }
1797
1798 static int
1799 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1800 struct hda_pcm *cpcm)
1801 {
1802 struct azx *chip = bus->private_data;
1803 struct snd_pcm *pcm;
1804 struct azx_pcm *apcm;
1805 int pcm_dev = cpcm->device;
1806 int s, err;
1807
1808 if (pcm_dev >= AZX_MAX_PCMS) {
1809 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1810 pcm_dev);
1811 return -EINVAL;
1812 }
1813 if (chip->pcm[pcm_dev]) {
1814 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1815 return -EBUSY;
1816 }
1817 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1818 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1819 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1820 &pcm);
1821 if (err < 0)
1822 return err;
1823 strcpy(pcm->name, cpcm->name);
1824 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1825 if (apcm == NULL)
1826 return -ENOMEM;
1827 apcm->chip = chip;
1828 apcm->codec = codec;
1829 pcm->private_data = apcm;
1830 pcm->private_free = azx_pcm_free;
1831 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1832 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1833 chip->pcm[pcm_dev] = pcm;
1834 cpcm->pcm = pcm;
1835 for (s = 0; s < 2; s++) {
1836 apcm->hinfo[s] = &cpcm->stream[s];
1837 if (cpcm->stream[s].substreams)
1838 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1839 }
1840 /* buffer pre-allocation */
1841 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1842 snd_dma_pci_data(chip->pci),
1843 1024 * 64, 32 * 1024 * 1024);
1844 return 0;
1845 }
1846
1847 /*
1848 * mixer creation - all stuff is implemented in hda module
1849 */
1850 static int __devinit azx_mixer_create(struct azx *chip)
1851 {
1852 return snd_hda_build_controls(chip->bus);
1853 }
1854
1855
1856 /*
1857 * initialize SD streams
1858 */
1859 static int __devinit azx_init_stream(struct azx *chip)
1860 {
1861 int i;
1862
1863 /* initialize each stream (aka device)
1864 * assign the starting bdl address to each stream (device)
1865 * and initialize
1866 */
1867 for (i = 0; i < chip->num_streams; i++) {
1868 struct azx_dev *azx_dev = &chip->azx_dev[i];
1869 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1870 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1871 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1872 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1873 azx_dev->sd_int_sta_mask = 1 << i;
1874 /* stream tag: must be non-zero and unique */
1875 azx_dev->index = i;
1876 azx_dev->stream_tag = i + 1;
1877 }
1878
1879 return 0;
1880 }
1881
1882 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1883 {
1884 if (request_irq(chip->pci->irq, azx_interrupt,
1885 chip->msi ? 0 : IRQF_SHARED,
1886 "HDA Intel", chip)) {
1887 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1888 "disabling device\n", chip->pci->irq);
1889 if (do_disconnect)
1890 snd_card_disconnect(chip->card);
1891 return -1;
1892 }
1893 chip->irq = chip->pci->irq;
1894 pci_intx(chip->pci, !chip->msi);
1895 return 0;
1896 }
1897
1898
1899 static void azx_stop_chip(struct azx *chip)
1900 {
1901 if (!chip->initialized)
1902 return;
1903
1904 /* disable interrupts */
1905 azx_int_disable(chip);
1906 azx_int_clear(chip);
1907
1908 /* disable CORB/RIRB */
1909 azx_free_cmd_io(chip);
1910
1911 /* disable position buffer */
1912 azx_writel(chip, DPLBASE, 0);
1913 azx_writel(chip, DPUBASE, 0);
1914
1915 chip->initialized = 0;
1916 }
1917
1918 #ifdef CONFIG_SND_HDA_POWER_SAVE
1919 /* power-up/down the controller */
1920 static void azx_power_notify(struct hda_bus *bus)
1921 {
1922 struct azx *chip = bus->private_data;
1923 struct hda_codec *c;
1924 int power_on = 0;
1925
1926 list_for_each_entry(c, &bus->codec_list, list) {
1927 if (c->power_on) {
1928 power_on = 1;
1929 break;
1930 }
1931 }
1932 if (power_on)
1933 azx_init_chip(chip);
1934 else if (chip->running && power_save_controller)
1935 azx_stop_chip(chip);
1936 }
1937 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1938
1939 #ifdef CONFIG_PM
1940 /*
1941 * power management
1942 */
1943
1944 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1945 {
1946 struct hda_codec *codec;
1947
1948 list_for_each_entry(codec, &bus->codec_list, list) {
1949 if (snd_hda_codec_needs_resume(codec))
1950 return 1;
1951 }
1952 return 0;
1953 }
1954
1955 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1956 {
1957 struct snd_card *card = pci_get_drvdata(pci);
1958 struct azx *chip = card->private_data;
1959 int i;
1960
1961 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1962 azx_clear_irq_pending(chip);
1963 for (i = 0; i < AZX_MAX_PCMS; i++)
1964 snd_pcm_suspend_all(chip->pcm[i]);
1965 if (chip->initialized)
1966 snd_hda_suspend(chip->bus, state);
1967 azx_stop_chip(chip);
1968 if (chip->irq >= 0) {
1969 free_irq(chip->irq, chip);
1970 chip->irq = -1;
1971 }
1972 if (chip->msi)
1973 pci_disable_msi(chip->pci);
1974 pci_disable_device(pci);
1975 pci_save_state(pci);
1976 pci_set_power_state(pci, pci_choose_state(pci, state));
1977 return 0;
1978 }
1979
1980 static int azx_resume(struct pci_dev *pci)
1981 {
1982 struct snd_card *card = pci_get_drvdata(pci);
1983 struct azx *chip = card->private_data;
1984
1985 pci_set_power_state(pci, PCI_D0);
1986 pci_restore_state(pci);
1987 if (pci_enable_device(pci) < 0) {
1988 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1989 "disabling device\n");
1990 snd_card_disconnect(card);
1991 return -EIO;
1992 }
1993 pci_set_master(pci);
1994 if (chip->msi)
1995 if (pci_enable_msi(pci) < 0)
1996 chip->msi = 0;
1997 if (azx_acquire_irq(chip, 1) < 0)
1998 return -EIO;
1999 azx_init_pci(chip);
2000
2001 if (snd_hda_codecs_inuse(chip->bus))
2002 azx_init_chip(chip);
2003
2004 snd_hda_resume(chip->bus);
2005 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2006 return 0;
2007 }
2008 #endif /* CONFIG_PM */
2009
2010
2011 /*
2012 * reboot notifier for hang-up problem at power-down
2013 */
2014 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2015 {
2016 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2017 azx_stop_chip(chip);
2018 return NOTIFY_OK;
2019 }
2020
2021 static void azx_notifier_register(struct azx *chip)
2022 {
2023 chip->reboot_notifier.notifier_call = azx_halt;
2024 register_reboot_notifier(&chip->reboot_notifier);
2025 }
2026
2027 static void azx_notifier_unregister(struct azx *chip)
2028 {
2029 if (chip->reboot_notifier.notifier_call)
2030 unregister_reboot_notifier(&chip->reboot_notifier);
2031 }
2032
2033 /*
2034 * destructor
2035 */
2036 static int azx_free(struct azx *chip)
2037 {
2038 int i;
2039
2040 azx_notifier_unregister(chip);
2041
2042 if (chip->initialized) {
2043 azx_clear_irq_pending(chip);
2044 for (i = 0; i < chip->num_streams; i++)
2045 azx_stream_stop(chip, &chip->azx_dev[i]);
2046 azx_stop_chip(chip);
2047 }
2048
2049 if (chip->irq >= 0)
2050 free_irq(chip->irq, (void*)chip);
2051 if (chip->msi)
2052 pci_disable_msi(chip->pci);
2053 if (chip->remap_addr)
2054 iounmap(chip->remap_addr);
2055
2056 if (chip->azx_dev) {
2057 for (i = 0; i < chip->num_streams; i++)
2058 if (chip->azx_dev[i].bdl.area)
2059 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2060 }
2061 if (chip->rb.area)
2062 snd_dma_free_pages(&chip->rb);
2063 if (chip->posbuf.area)
2064 snd_dma_free_pages(&chip->posbuf);
2065 pci_release_regions(chip->pci);
2066 pci_disable_device(chip->pci);
2067 kfree(chip->azx_dev);
2068 kfree(chip);
2069
2070 return 0;
2071 }
2072
2073 static int azx_dev_free(struct snd_device *device)
2074 {
2075 return azx_free(device->device_data);
2076 }
2077
2078 /*
2079 * white/black-listing for position_fix
2080 */
2081 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2082 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2083 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2084 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2085 {}
2086 };
2087
2088 static int __devinit check_position_fix(struct azx *chip, int fix)
2089 {
2090 const struct snd_pci_quirk *q;
2091
2092 switch (fix) {
2093 case POS_FIX_LPIB:
2094 case POS_FIX_POSBUF:
2095 return fix;
2096 }
2097
2098 /* Check VIA/ATI HD Audio Controller exist */
2099 switch (chip->driver_type) {
2100 case AZX_DRIVER_VIA:
2101 case AZX_DRIVER_ATI:
2102 chip->via_dmapos_patch = 1;
2103 /* Use link position directly, avoid any transfer problem. */
2104 return POS_FIX_LPIB;
2105 }
2106 chip->via_dmapos_patch = 0;
2107
2108 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2109 if (q) {
2110 printk(KERN_INFO
2111 "hda_intel: position_fix set to %d "
2112 "for device %04x:%04x\n",
2113 q->value, q->subvendor, q->subdevice);
2114 return q->value;
2115 }
2116 return POS_FIX_AUTO;
2117 }
2118
2119 /*
2120 * black-lists for probe_mask
2121 */
2122 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2123 /* Thinkpad often breaks the controller communication when accessing
2124 * to the non-working (or non-existing) modem codec slot.
2125 */
2126 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2127 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2128 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2129 /* broken BIOS */
2130 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2131 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2132 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2133 /* forced codec slots */
2134 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2135 {}
2136 };
2137
2138 #define AZX_FORCE_CODEC_MASK 0x100
2139
2140 static void __devinit check_probe_mask(struct azx *chip, int dev)
2141 {
2142 const struct snd_pci_quirk *q;
2143
2144 chip->codec_probe_mask = probe_mask[dev];
2145 if (chip->codec_probe_mask == -1) {
2146 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2147 if (q) {
2148 printk(KERN_INFO
2149 "hda_intel: probe_mask set to 0x%x "
2150 "for device %04x:%04x\n",
2151 q->value, q->subvendor, q->subdevice);
2152 chip->codec_probe_mask = q->value;
2153 }
2154 }
2155
2156 /* check forced option */
2157 if (chip->codec_probe_mask != -1 &&
2158 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2159 chip->codec_mask = chip->codec_probe_mask & 0xff;
2160 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2161 chip->codec_mask);
2162 }
2163 }
2164
2165
2166 /*
2167 * constructor
2168 */
2169 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2170 int dev, int driver_type,
2171 struct azx **rchip)
2172 {
2173 struct azx *chip;
2174 int i, err;
2175 unsigned short gcap;
2176 static struct snd_device_ops ops = {
2177 .dev_free = azx_dev_free,
2178 };
2179
2180 *rchip = NULL;
2181
2182 err = pci_enable_device(pci);
2183 if (err < 0)
2184 return err;
2185
2186 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2187 if (!chip) {
2188 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2189 pci_disable_device(pci);
2190 return -ENOMEM;
2191 }
2192
2193 spin_lock_init(&chip->reg_lock);
2194 mutex_init(&chip->open_mutex);
2195 chip->card = card;
2196 chip->pci = pci;
2197 chip->irq = -1;
2198 chip->driver_type = driver_type;
2199 chip->msi = enable_msi;
2200 chip->dev_index = dev;
2201 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2202
2203 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2204 check_probe_mask(chip, dev);
2205
2206 chip->single_cmd = single_cmd;
2207
2208 if (bdl_pos_adj[dev] < 0) {
2209 switch (chip->driver_type) {
2210 case AZX_DRIVER_ICH:
2211 bdl_pos_adj[dev] = 1;
2212 break;
2213 default:
2214 bdl_pos_adj[dev] = 32;
2215 break;
2216 }
2217 }
2218
2219 #if BITS_PER_LONG != 64
2220 /* Fix up base address on ULI M5461 */
2221 if (chip->driver_type == AZX_DRIVER_ULI) {
2222 u16 tmp3;
2223 pci_read_config_word(pci, 0x40, &tmp3);
2224 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2225 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2226 }
2227 #endif
2228
2229 err = pci_request_regions(pci, "ICH HD audio");
2230 if (err < 0) {
2231 kfree(chip);
2232 pci_disable_device(pci);
2233 return err;
2234 }
2235
2236 chip->addr = pci_resource_start(pci, 0);
2237 chip->remap_addr = pci_ioremap_bar(pci, 0);
2238 if (chip->remap_addr == NULL) {
2239 snd_printk(KERN_ERR SFX "ioremap error\n");
2240 err = -ENXIO;
2241 goto errout;
2242 }
2243
2244 if (chip->msi)
2245 if (pci_enable_msi(pci) < 0)
2246 chip->msi = 0;
2247
2248 if (azx_acquire_irq(chip, 0) < 0) {
2249 err = -EBUSY;
2250 goto errout;
2251 }
2252
2253 pci_set_master(pci);
2254 synchronize_irq(chip->irq);
2255
2256 gcap = azx_readw(chip, GCAP);
2257 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2258
2259 /* ATI chips seems buggy about 64bit DMA addresses */
2260 if (chip->driver_type == AZX_DRIVER_ATI)
2261 gcap &= ~0x01;
2262
2263 /* allow 64bit DMA address if supported by H/W */
2264 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2265 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2266 else {
2267 pci_set_dma_mask(pci, DMA_32BIT_MASK);
2268 pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK);
2269 }
2270
2271 /* read number of streams from GCAP register instead of using
2272 * hardcoded value
2273 */
2274 chip->capture_streams = (gcap >> 8) & 0x0f;
2275 chip->playback_streams = (gcap >> 12) & 0x0f;
2276 if (!chip->playback_streams && !chip->capture_streams) {
2277 /* gcap didn't give any info, switching to old method */
2278
2279 switch (chip->driver_type) {
2280 case AZX_DRIVER_ULI:
2281 chip->playback_streams = ULI_NUM_PLAYBACK;
2282 chip->capture_streams = ULI_NUM_CAPTURE;
2283 break;
2284 case AZX_DRIVER_ATIHDMI:
2285 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2286 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2287 break;
2288 case AZX_DRIVER_GENERIC:
2289 default:
2290 chip->playback_streams = ICH6_NUM_PLAYBACK;
2291 chip->capture_streams = ICH6_NUM_CAPTURE;
2292 break;
2293 }
2294 }
2295 chip->capture_index_offset = 0;
2296 chip->playback_index_offset = chip->capture_streams;
2297 chip->num_streams = chip->playback_streams + chip->capture_streams;
2298 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2299 GFP_KERNEL);
2300 if (!chip->azx_dev) {
2301 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2302 goto errout;
2303 }
2304
2305 for (i = 0; i < chip->num_streams; i++) {
2306 /* allocate memory for the BDL for each stream */
2307 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2308 snd_dma_pci_data(chip->pci),
2309 BDL_SIZE, &chip->azx_dev[i].bdl);
2310 if (err < 0) {
2311 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2312 goto errout;
2313 }
2314 }
2315 /* allocate memory for the position buffer */
2316 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2317 snd_dma_pci_data(chip->pci),
2318 chip->num_streams * 8, &chip->posbuf);
2319 if (err < 0) {
2320 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2321 goto errout;
2322 }
2323 /* allocate CORB/RIRB */
2324 if (!chip->single_cmd) {
2325 err = azx_alloc_cmd_io(chip);
2326 if (err < 0)
2327 goto errout;
2328 }
2329
2330 /* initialize streams */
2331 azx_init_stream(chip);
2332
2333 /* initialize chip */
2334 azx_init_pci(chip);
2335 azx_init_chip(chip);
2336
2337 /* codec detection */
2338 if (!chip->codec_mask) {
2339 snd_printk(KERN_ERR SFX "no codecs found!\n");
2340 err = -ENODEV;
2341 goto errout;
2342 }
2343
2344 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2345 if (err <0) {
2346 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2347 goto errout;
2348 }
2349
2350 strcpy(card->driver, "HDA-Intel");
2351 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2352 sprintf(card->longname, "%s at 0x%lx irq %i",
2353 card->shortname, chip->addr, chip->irq);
2354
2355 *rchip = chip;
2356 return 0;
2357
2358 errout:
2359 azx_free(chip);
2360 return err;
2361 }
2362
2363 static void power_down_all_codecs(struct azx *chip)
2364 {
2365 #ifdef CONFIG_SND_HDA_POWER_SAVE
2366 /* The codecs were powered up in snd_hda_codec_new().
2367 * Now all initialization done, so turn them down if possible
2368 */
2369 struct hda_codec *codec;
2370 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2371 snd_hda_power_down(codec);
2372 }
2373 #endif
2374 }
2375
2376 static int __devinit azx_probe(struct pci_dev *pci,
2377 const struct pci_device_id *pci_id)
2378 {
2379 static int dev;
2380 struct snd_card *card;
2381 struct azx *chip;
2382 int err;
2383
2384 if (dev >= SNDRV_CARDS)
2385 return -ENODEV;
2386 if (!enable[dev]) {
2387 dev++;
2388 return -ENOENT;
2389 }
2390
2391 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2392 if (err < 0) {
2393 snd_printk(KERN_ERR SFX "Error creating card!\n");
2394 return err;
2395 }
2396
2397 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2398 if (err < 0)
2399 goto out_free;
2400 card->private_data = chip;
2401
2402 /* create codec instances */
2403 err = azx_codec_create(chip, model[dev], probe_only[dev]);
2404 if (err < 0)
2405 goto out_free;
2406
2407 /* create PCM streams */
2408 err = snd_hda_build_pcms(chip->bus);
2409 if (err < 0)
2410 goto out_free;
2411
2412 /* create mixer controls */
2413 err = azx_mixer_create(chip);
2414 if (err < 0)
2415 goto out_free;
2416
2417 snd_card_set_dev(card, &pci->dev);
2418
2419 err = snd_card_register(card);
2420 if (err < 0)
2421 goto out_free;
2422
2423 pci_set_drvdata(pci, card);
2424 chip->running = 1;
2425 power_down_all_codecs(chip);
2426 azx_notifier_register(chip);
2427
2428 dev++;
2429 return err;
2430 out_free:
2431 snd_card_free(card);
2432 return err;
2433 }
2434
2435 static void __devexit azx_remove(struct pci_dev *pci)
2436 {
2437 snd_card_free(pci_get_drvdata(pci));
2438 pci_set_drvdata(pci, NULL);
2439 }
2440
2441 /* PCI IDs */
2442 static struct pci_device_id azx_ids[] = {
2443 /* ICH 6..10 */
2444 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2445 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2446 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2447 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2448 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2449 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2450 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2451 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2452 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2453 /* PCH */
2454 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2455 /* SCH */
2456 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2457 /* ATI SB 450/600 */
2458 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2459 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2460 /* ATI HDMI */
2461 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2462 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2463 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2464 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2465 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2466 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2467 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2468 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2469 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2470 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2471 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2472 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2473 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2474 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2475 /* VIA VT8251/VT8237A */
2476 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2477 /* SIS966 */
2478 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2479 /* ULI M5461 */
2480 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2481 /* NVIDIA MCP */
2482 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2483 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2484 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2485 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2486 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2487 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2488 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2489 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2490 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2491 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2492 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2493 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2494 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2495 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2496 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2497 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2498 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2499 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2500 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2501 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2502 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2503 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2504 /* Teradici */
2505 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2506 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2507 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2508 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2509 .class_mask = 0xffffff,
2510 .driver_data = AZX_DRIVER_GENERIC },
2511 { 0, }
2512 };
2513 MODULE_DEVICE_TABLE(pci, azx_ids);
2514
2515 /* pci_driver definition */
2516 static struct pci_driver driver = {
2517 .name = "HDA Intel",
2518 .id_table = azx_ids,
2519 .probe = azx_probe,
2520 .remove = __devexit_p(azx_remove),
2521 #ifdef CONFIG_PM
2522 .suspend = azx_suspend,
2523 .resume = azx_resume,
2524 #endif
2525 };
2526
2527 static int __init alsa_card_azx_init(void)
2528 {
2529 return pci_register_driver(&driver);
2530 }
2531
2532 static void __exit alsa_card_azx_exit(void)
2533 {
2534 pci_unregister_driver(&driver);
2535 }
2536
2537 module_init(alsa_card_azx_init)
2538 module_exit(alsa_card_azx_exit)
CJK support for tty framebuffer vt