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radeon: add RS400 family support.
[linux-2.6/cjktty.git] / drivers / gpu / drm / radeon / radeon_drv.h
blob9278429af9ed301b73ccfbe97a1357059259ffa4
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20080528"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
102 */
103 #define DRIVER_MAJOR 1
104 #define DRIVER_MINOR 29
105 #define DRIVER_PATCHLEVEL 0
106
107 /*
108 * Radeon chip families
109 */
110 enum radeon_family {
111 CHIP_R100,
112 CHIP_RV100,
113 CHIP_RS100,
114 CHIP_RV200,
115 CHIP_RS200,
116 CHIP_R200,
117 CHIP_RV250,
118 CHIP_RS300,
119 CHIP_RV280,
120 CHIP_R300,
121 CHIP_R350,
122 CHIP_RV350,
123 CHIP_RV380,
124 CHIP_R420,
125 CHIP_RV410,
126 CHIP_RS400,
127 CHIP_RS480,
128 CHIP_RS690,
129 CHIP_RS740,
130 CHIP_RV515,
131 CHIP_R520,
132 CHIP_RV530,
133 CHIP_RV560,
134 CHIP_RV570,
135 CHIP_R580,
136 CHIP_LAST,
137 };
138
139 enum radeon_cp_microcode_version {
140 UCODE_R100,
141 UCODE_R200,
142 UCODE_R300,
143 };
144
145 /*
146 * Chip flags
147 */
148 enum radeon_chip_flags {
149 RADEON_FAMILY_MASK = 0x0000ffffUL,
150 RADEON_FLAGS_MASK = 0xffff0000UL,
151 RADEON_IS_MOBILITY = 0x00010000UL,
152 RADEON_IS_IGP = 0x00020000UL,
153 RADEON_SINGLE_CRTC = 0x00040000UL,
154 RADEON_IS_AGP = 0x00080000UL,
155 RADEON_HAS_HIERZ = 0x00100000UL,
156 RADEON_IS_PCIE = 0x00200000UL,
157 RADEON_NEW_MEMMAP = 0x00400000UL,
158 RADEON_IS_PCI = 0x00800000UL,
159 RADEON_IS_IGPGART = 0x01000000UL,
160 };
161
162 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
163 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
164 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
165
166 typedef struct drm_radeon_freelist {
167 unsigned int age;
168 struct drm_buf *buf;
169 struct drm_radeon_freelist *next;
170 struct drm_radeon_freelist *prev;
171 } drm_radeon_freelist_t;
172
173 typedef struct drm_radeon_ring_buffer {
174 u32 *start;
175 u32 *end;
176 int size;
177 int size_l2qw;
178
179 int rptr_update; /* Double Words */
180 int rptr_update_l2qw; /* log2 Quad Words */
181
182 int fetch_size; /* Double Words */
183 int fetch_size_l2ow; /* log2 Oct Words */
184
185 u32 tail;
186 u32 tail_mask;
187 int space;
188
189 int high_mark;
190 } drm_radeon_ring_buffer_t;
191
192 typedef struct drm_radeon_depth_clear_t {
193 u32 rb3d_cntl;
194 u32 rb3d_zstencilcntl;
195 u32 se_cntl;
196 } drm_radeon_depth_clear_t;
197
198 struct drm_radeon_driver_file_fields {
199 int64_t radeon_fb_delta;
200 };
201
202 struct mem_block {
203 struct mem_block *next;
204 struct mem_block *prev;
205 int start;
206 int size;
207 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
208 };
209
210 struct radeon_surface {
211 int refcount;
212 u32 lower;
213 u32 upper;
214 u32 flags;
215 };
216
217 struct radeon_virt_surface {
218 int surface_index;
219 u32 lower;
220 u32 upper;
221 u32 flags;
222 struct drm_file *file_priv;
223 };
224
225 #define RADEON_FLUSH_EMITED (1 < 0)
226 #define RADEON_PURGE_EMITED (1 < 1)
227
228 typedef struct drm_radeon_private {
229 drm_radeon_ring_buffer_t ring;
230 drm_radeon_sarea_t *sarea_priv;
231
232 u32 fb_location;
233 u32 fb_size;
234 int new_memmap;
235
236 int gart_size;
237 u32 gart_vm_start;
238 unsigned long gart_buffers_offset;
239
240 int cp_mode;
241 int cp_running;
242
243 drm_radeon_freelist_t *head;
244 drm_radeon_freelist_t *tail;
245 int last_buf;
246 volatile u32 *scratch;
247 int writeback_works;
248
249 int usec_timeout;
250
251 int microcode_version;
252
253 struct {
254 u32 boxes;
255 int freelist_timeouts;
256 int freelist_loops;
257 int requested_bufs;
258 int last_frame_reads;
259 int last_clear_reads;
260 int clears;
261 int texture_uploads;
262 } stats;
263
264 int do_boxes;
265 int page_flipping;
266
267 u32 color_fmt;
268 unsigned int front_offset;
269 unsigned int front_pitch;
270 unsigned int back_offset;
271 unsigned int back_pitch;
272
273 u32 depth_fmt;
274 unsigned int depth_offset;
275 unsigned int depth_pitch;
276
277 u32 front_pitch_offset;
278 u32 back_pitch_offset;
279 u32 depth_pitch_offset;
280
281 drm_radeon_depth_clear_t depth_clear;
282
283 unsigned long ring_offset;
284 unsigned long ring_rptr_offset;
285 unsigned long buffers_offset;
286 unsigned long gart_textures_offset;
287
288 drm_local_map_t *sarea;
289 drm_local_map_t *mmio;
290 drm_local_map_t *cp_ring;
291 drm_local_map_t *ring_rptr;
292 drm_local_map_t *gart_textures;
293
294 struct mem_block *gart_heap;
295 struct mem_block *fb_heap;
296
297 /* SW interrupt */
298 wait_queue_head_t swi_queue;
299 atomic_t swi_emitted;
300 int vblank_crtc;
301 uint32_t irq_enable_reg;
302 int irq_enabled;
303 uint32_t r500_disp_irq_reg;
304
305 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
306 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
307
308 unsigned long pcigart_offset;
309 unsigned int pcigart_offset_set;
310 struct drm_ati_pcigart_info gart_info;
311
312 u32 scratch_ages[5];
313
314 /* starting from here on, data is preserved accross an open */
315 uint32_t flags; /* see radeon_chip_flags */
316 unsigned long fb_aper_offset;
317
318 int num_gb_pipes;
319 int track_flush;
320 } drm_radeon_private_t;
321
322 typedef struct drm_radeon_buf_priv {
323 u32 age;
324 } drm_radeon_buf_priv_t;
325
326 typedef struct drm_radeon_kcmd_buffer {
327 int bufsz;
328 char *buf;
329 int nbox;
330 struct drm_clip_rect __user *boxes;
331 } drm_radeon_kcmd_buffer_t;
332
333 extern int radeon_no_wb;
334 extern struct drm_ioctl_desc radeon_ioctls[];
335 extern int radeon_max_ioctl;
336
337 /* Check whether the given hardware address is inside the framebuffer or the
338 * GART area.
339 */
340 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
341 u64 off)
342 {
343 u32 fb_start = dev_priv->fb_location;
344 u32 fb_end = fb_start + dev_priv->fb_size - 1;
345 u32 gart_start = dev_priv->gart_vm_start;
346 u32 gart_end = gart_start + dev_priv->gart_size - 1;
347
348 return ((off >= fb_start && off <= fb_end) ||
349 (off >= gart_start && off <= gart_end));
350 }
351
352 /* radeon_cp.c */
353 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
354 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
355 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
356 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
357 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
358 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
359 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
360 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
361 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
362 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
363
364 extern void radeon_freelist_reset(struct drm_device * dev);
365 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
366
367 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
368
369 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
370
371 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
372 extern int radeon_presetup(struct drm_device *dev);
373 extern int radeon_driver_postcleanup(struct drm_device *dev);
374
375 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
376 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
377 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
378 extern void radeon_mem_takedown(struct mem_block **heap);
379 extern void radeon_mem_release(struct drm_file *file_priv,
380 struct mem_block *heap);
381
382 /* radeon_irq.c */
383 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
384 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
385 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
386
387 extern void radeon_do_release(struct drm_device * dev);
388 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
389 extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
390 extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
391 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
392 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
393 extern int radeon_driver_irq_postinstall(struct drm_device *dev);
394 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
395 extern void radeon_enable_interrupt(struct drm_device *dev);
396 extern int radeon_vblank_crtc_get(struct drm_device *dev);
397 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
398
399 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
400 extern int radeon_driver_unload(struct drm_device *dev);
401 extern int radeon_driver_firstopen(struct drm_device *dev);
402 extern void radeon_driver_preclose(struct drm_device *dev,
403 struct drm_file *file_priv);
404 extern void radeon_driver_postclose(struct drm_device *dev,
405 struct drm_file *file_priv);
406 extern void radeon_driver_lastclose(struct drm_device * dev);
407 extern int radeon_driver_open(struct drm_device *dev,
408 struct drm_file *file_priv);
409 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
410 unsigned long arg);
411
412 /* r300_cmdbuf.c */
413 extern void r300_init_reg_flags(struct drm_device *dev);
414
415 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
416 struct drm_file *file_priv,
417 drm_radeon_kcmd_buffer_t *cmdbuf);
418
419 /* Flags for stats.boxes
420 */
421 #define RADEON_BOX_DMA_IDLE 0x1
422 #define RADEON_BOX_RING_FULL 0x2
423 #define RADEON_BOX_FLIP 0x4
424 #define RADEON_BOX_WAIT_IDLE 0x8
425 #define RADEON_BOX_TEXTURE_LOAD 0x10
426
427 /* Register definitions, register access macros and drmAddMap constants
428 * for Radeon kernel driver.
429 */
430
431 #define RADEON_AGP_COMMAND 0x0f60
432 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
433 # define RADEON_AGP_ENABLE (1<<8)
434 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
435 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
436 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
437 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
438 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
439 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
440 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
441
442 #define RADEON_BUS_CNTL 0x0030
443 # define RADEON_BUS_MASTER_DIS (1 << 6)
444
445 #define RADEON_CLOCK_CNTL_DATA 0x000c
446 # define RADEON_PLL_WR_EN (1 << 7)
447 #define RADEON_CLOCK_CNTL_INDEX 0x0008
448 #define RADEON_CONFIG_APER_SIZE 0x0108
449 #define RADEON_CONFIG_MEMSIZE 0x00f8
450 #define RADEON_CRTC_OFFSET 0x0224
451 #define RADEON_CRTC_OFFSET_CNTL 0x0228
452 # define RADEON_CRTC_TILE_EN (1 << 15)
453 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
454 #define RADEON_CRTC2_OFFSET 0x0324
455 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
456
457 #define RADEON_PCIE_INDEX 0x0030
458 #define RADEON_PCIE_DATA 0x0034
459 #define RADEON_PCIE_TX_GART_CNTL 0x10
460 # define RADEON_PCIE_TX_GART_EN (1 << 0)
461 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
462 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
463 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
464 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
465 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
466 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
467 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
468 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
469 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
470 #define RADEON_PCIE_TX_GART_BASE 0x13
471 #define RADEON_PCIE_TX_GART_START_LO 0x14
472 #define RADEON_PCIE_TX_GART_START_HI 0x15
473 #define RADEON_PCIE_TX_GART_END_LO 0x16
474 #define RADEON_PCIE_TX_GART_END_HI 0x17
475
476 #define RS480_NB_MC_INDEX 0x168
477 # define RS480_NB_MC_IND_WR_EN (1 << 8)
478 #define RS480_NB_MC_DATA 0x16c
479
480 #define RS690_MC_INDEX 0x78
481 # define RS690_MC_INDEX_MASK 0x1ff
482 # define RS690_MC_INDEX_WR_EN (1 << 9)
483 # define RS690_MC_INDEX_WR_ACK 0x7f
484 #define RS690_MC_DATA 0x7c
485
486 /* MC indirect registers */
487 #define RS480_MC_MISC_CNTL 0x18
488 # define RS480_DISABLE_GTW (1 << 1)
489 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
490 # define RS480_GART_INDEX_REG_EN (1 << 12)
491 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
492 #define RS480_K8_FB_LOCATION 0x1e
493 #define RS480_GART_FEATURE_ID 0x2b
494 # define RS480_HANG_EN (1 << 11)
495 # define RS480_TLB_ENABLE (1 << 18)
496 # define RS480_P2P_ENABLE (1 << 19)
497 # define RS480_GTW_LAC_EN (1 << 25)
498 # define RS480_2LEVEL_GART (0 << 30)
499 # define RS480_1LEVEL_GART (1 << 30)
500 # define RS480_PDC_EN (1 << 31)
501 #define RS480_GART_BASE 0x2c
502 #define RS480_GART_CACHE_CNTRL 0x2e
503 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
504 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
505 # define RS480_GART_EN (1 << 0)
506 # define RS480_VA_SIZE_32MB (0 << 1)
507 # define RS480_VA_SIZE_64MB (1 << 1)
508 # define RS480_VA_SIZE_128MB (2 << 1)
509 # define RS480_VA_SIZE_256MB (3 << 1)
510 # define RS480_VA_SIZE_512MB (4 << 1)
511 # define RS480_VA_SIZE_1GB (5 << 1)
512 # define RS480_VA_SIZE_2GB (6 << 1)
513 #define RS480_AGP_MODE_CNTL 0x39
514 # define RS480_POST_GART_Q_SIZE (1 << 18)
515 # define RS480_NONGART_SNOOP (1 << 19)
516 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
517 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
518 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
519 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
520 #define RS480_MC_MISC_UMA_CNTL 0x5f
521 #define RS480_MC_MCLK_CNTL 0x7a
522 #define RS480_MC_UMA_DUALCH_CNTL 0x86
523
524 #define RS690_MC_FB_LOCATION 0x100
525 #define RS690_MC_AGP_LOCATION 0x101
526 #define RS690_MC_AGP_BASE 0x102
527 #define RS690_MC_AGP_BASE_2 0x103
528
529 #define R520_MC_IND_INDEX 0x70
530 #define R520_MC_IND_WR_EN (1 << 24)
531 #define R520_MC_IND_DATA 0x74
532
533 #define RV515_MC_FB_LOCATION 0x01
534 #define RV515_MC_AGP_LOCATION 0x02
535 #define RV515_MC_AGP_BASE 0x03
536 #define RV515_MC_AGP_BASE_2 0x04
537
538 #define R520_MC_FB_LOCATION 0x04
539 #define R520_MC_AGP_LOCATION 0x05
540 #define R520_MC_AGP_BASE 0x06
541 #define R520_MC_AGP_BASE_2 0x07
542
543 #define RADEON_MPP_TB_CONFIG 0x01c0
544 #define RADEON_MEM_CNTL 0x0140
545 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
546 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
547 #define RS480_AGP_BASE_2 0x0164
548 #define RADEON_AGP_BASE 0x0170
549
550 /* pipe config regs */
551 #define R400_GB_PIPE_SELECT 0x402c
552 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
553 #define R500_SU_REG_DEST 0x42c8
554 #define R300_GB_TILE_CONFIG 0x4018
555 # define R300_ENABLE_TILING (1 << 0)
556 # define R300_PIPE_COUNT_RV350 (0 << 1)
557 # define R300_PIPE_COUNT_R300 (3 << 1)
558 # define R300_PIPE_COUNT_R420_3P (6 << 1)
559 # define R300_PIPE_COUNT_R420 (7 << 1)
560 # define R300_TILE_SIZE_8 (0 << 4)
561 # define R300_TILE_SIZE_16 (1 << 4)
562 # define R300_TILE_SIZE_32 (2 << 4)
563 # define R300_SUBPIXEL_1_12 (0 << 16)
564 # define R300_SUBPIXEL_1_16 (1 << 16)
565 #define R300_DST_PIPE_CONFIG 0x170c
566 # define R300_PIPE_AUTO_CONFIG (1 << 31)
567 #define R300_RB2D_DSTCACHE_MODE 0x3428
568 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
569 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
570
571 #define RADEON_RB3D_COLOROFFSET 0x1c40
572 #define RADEON_RB3D_COLORPITCH 0x1c48
573
574 #define RADEON_SRC_X_Y 0x1590
575
576 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
577 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
578 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
579 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
580 # define RADEON_GMC_BRUSH_NONE (15 << 4)
581 # define RADEON_GMC_DST_16BPP (4 << 8)
582 # define RADEON_GMC_DST_24BPP (5 << 8)
583 # define RADEON_GMC_DST_32BPP (6 << 8)
584 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
585 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
586 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
587 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
588 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
589 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
590 # define RADEON_ROP3_S 0x00cc0000
591 # define RADEON_ROP3_P 0x00f00000
592 #define RADEON_DP_WRITE_MASK 0x16cc
593 #define RADEON_SRC_PITCH_OFFSET 0x1428
594 #define RADEON_DST_PITCH_OFFSET 0x142c
595 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
596 # define RADEON_DST_TILE_LINEAR (0 << 30)
597 # define RADEON_DST_TILE_MACRO (1 << 30)
598 # define RADEON_DST_TILE_MICRO (2 << 30)
599 # define RADEON_DST_TILE_BOTH (3 << 30)
600
601 #define RADEON_SCRATCH_REG0 0x15e0
602 #define RADEON_SCRATCH_REG1 0x15e4
603 #define RADEON_SCRATCH_REG2 0x15e8
604 #define RADEON_SCRATCH_REG3 0x15ec
605 #define RADEON_SCRATCH_REG4 0x15f0
606 #define RADEON_SCRATCH_REG5 0x15f4
607 #define RADEON_SCRATCH_UMSK 0x0770
608 #define RADEON_SCRATCH_ADDR 0x0774
609
610 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
611
612 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
613 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
614 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
615
616 #define RADEON_GEN_INT_CNTL 0x0040
617 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
618 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
619 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
620 # define RADEON_SW_INT_ENABLE (1 << 25)
621
622 #define RADEON_GEN_INT_STATUS 0x0044
623 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
624 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
625 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
626 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
627 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
628 # define RADEON_SW_INT_TEST (1 << 25)
629 # define RADEON_SW_INT_TEST_ACK (1 << 25)
630 # define RADEON_SW_INT_FIRE (1 << 26)
631 # define R500_DISPLAY_INT_STATUS (1 << 0)
632
633 #define RADEON_HOST_PATH_CNTL 0x0130
634 # define RADEON_HDP_SOFT_RESET (1 << 26)
635 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
636 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
637
638 #define RADEON_ISYNC_CNTL 0x1724
639 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
640 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
641 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
642 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
643 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
644 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
645
646 #define RADEON_RBBM_GUICNTL 0x172c
647 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
648 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
649 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
650 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
651
652 #define RADEON_MC_AGP_LOCATION 0x014c
653 #define RADEON_MC_FB_LOCATION 0x0148
654 #define RADEON_MCLK_CNTL 0x0012
655 # define RADEON_FORCEON_MCLKA (1 << 16)
656 # define RADEON_FORCEON_MCLKB (1 << 17)
657 # define RADEON_FORCEON_YCLKA (1 << 18)
658 # define RADEON_FORCEON_YCLKB (1 << 19)
659 # define RADEON_FORCEON_MC (1 << 20)
660 # define RADEON_FORCEON_AIC (1 << 21)
661
662 #define RADEON_PP_BORDER_COLOR_0 0x1d40
663 #define RADEON_PP_BORDER_COLOR_1 0x1d44
664 #define RADEON_PP_BORDER_COLOR_2 0x1d48
665 #define RADEON_PP_CNTL 0x1c38
666 # define RADEON_SCISSOR_ENABLE (1 << 1)
667 #define RADEON_PP_LUM_MATRIX 0x1d00
668 #define RADEON_PP_MISC 0x1c14
669 #define RADEON_PP_ROT_MATRIX_0 0x1d58
670 #define RADEON_PP_TXFILTER_0 0x1c54
671 #define RADEON_PP_TXOFFSET_0 0x1c5c
672 #define RADEON_PP_TXFILTER_1 0x1c6c
673 #define RADEON_PP_TXFILTER_2 0x1c84
674
675 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
676 #define R300_DSTCACHE_CTLSTAT 0x1714
677 # define R300_RB2D_DC_FLUSH (3 << 0)
678 # define R300_RB2D_DC_FREE (3 << 2)
679 # define R300_RB2D_DC_FLUSH_ALL 0xf
680 # define R300_RB2D_DC_BUSY (1 << 31)
681 #define RADEON_RB3D_CNTL 0x1c3c
682 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
683 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
684 # define RADEON_DITHER_ENABLE (1 << 2)
685 # define RADEON_ROUND_ENABLE (1 << 3)
686 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
687 # define RADEON_DITHER_INIT (1 << 5)
688 # define RADEON_ROP_ENABLE (1 << 6)
689 # define RADEON_STENCIL_ENABLE (1 << 7)
690 # define RADEON_Z_ENABLE (1 << 8)
691 # define RADEON_ZBLOCK16 (1 << 15)
692 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
693 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
694 #define RADEON_RB3D_DEPTHPITCH 0x1c28
695 #define RADEON_RB3D_PLANEMASK 0x1d84
696 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
697 #define RADEON_RB3D_ZCACHE_MODE 0x3250
698 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
699 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
700 # define RADEON_RB3D_ZC_FREE (1 << 2)
701 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
702 # define RADEON_RB3D_ZC_BUSY (1 << 31)
703 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
704 # define R300_ZC_FLUSH (1 << 0)
705 # define R300_ZC_FREE (1 << 1)
706 # define R300_ZC_BUSY (1 << 31)
707 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
708 # define RADEON_RB3D_DC_FLUSH (3 << 0)
709 # define RADEON_RB3D_DC_FREE (3 << 2)
710 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
711 # define RADEON_RB3D_DC_BUSY (1 << 31)
712 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
713 # define R300_RB3D_DC_FLUSH (2 << 0)
714 # define R300_RB3D_DC_FREE (2 << 2)
715 # define R300_RB3D_DC_FINISH (1 << 4)
716 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
717 # define RADEON_Z_TEST_MASK (7 << 4)
718 # define RADEON_Z_TEST_ALWAYS (7 << 4)
719 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
720 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
721 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
722 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
723 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
724 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
725 # define RADEON_FORCE_Z_DIRTY (1 << 29)
726 # define RADEON_Z_WRITE_ENABLE (1 << 30)
727 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
728 #define RADEON_RBBM_SOFT_RESET 0x00f0
729 # define RADEON_SOFT_RESET_CP (1 << 0)
730 # define RADEON_SOFT_RESET_HI (1 << 1)
731 # define RADEON_SOFT_RESET_SE (1 << 2)
732 # define RADEON_SOFT_RESET_RE (1 << 3)
733 # define RADEON_SOFT_RESET_PP (1 << 4)
734 # define RADEON_SOFT_RESET_E2 (1 << 5)
735 # define RADEON_SOFT_RESET_RB (1 << 6)
736 # define RADEON_SOFT_RESET_HDP (1 << 7)
737 /*
738 * 6:0 Available slots in the FIFO
739 * 8 Host Interface active
740 * 9 CP request active
741 * 10 FIFO request active
742 * 11 Host Interface retry active
743 * 12 CP retry active
744 * 13 FIFO retry active
745 * 14 FIFO pipeline busy
746 * 15 Event engine busy
747 * 16 CP command stream busy
748 * 17 2D engine busy
749 * 18 2D portion of render backend busy
750 * 20 3D setup engine busy
751 * 26 GA engine busy
752 * 27 CBA 2D engine busy
753 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
754 * command stream queue not empty or Ring Buffer not empty
755 */
756 #define RADEON_RBBM_STATUS 0x0e40
757 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
758 /* #define RADEON_RBBM_STATUS 0x1740 */
759 /* bits 6:0 are dword slots available in the cmd fifo */
760 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
761 # define RADEON_HIRQ_ON_RBB (1 << 8)
762 # define RADEON_CPRQ_ON_RBB (1 << 9)
763 # define RADEON_CFRQ_ON_RBB (1 << 10)
764 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
765 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
766 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
767 # define RADEON_PIPE_BUSY (1 << 14)
768 # define RADEON_ENG_EV_BUSY (1 << 15)
769 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
770 # define RADEON_E2_BUSY (1 << 17)
771 # define RADEON_RB2D_BUSY (1 << 18)
772 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
773 # define RADEON_VAP_BUSY (1 << 20)
774 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
775 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
776 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
777 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
778 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
779 # define RADEON_GA_BUSY (1 << 26)
780 # define RADEON_CBA2D_BUSY (1 << 27)
781 # define RADEON_RBBM_ACTIVE (1 << 31)
782 #define RADEON_RE_LINE_PATTERN 0x1cd0
783 #define RADEON_RE_MISC 0x26c4
784 #define RADEON_RE_TOP_LEFT 0x26c0
785 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
786 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
787 #define RADEON_RE_STIPPLE_DATA 0x1ccc
788
789 #define RADEON_SCISSOR_TL_0 0x1cd8
790 #define RADEON_SCISSOR_BR_0 0x1cdc
791 #define RADEON_SCISSOR_TL_1 0x1ce0
792 #define RADEON_SCISSOR_BR_1 0x1ce4
793 #define RADEON_SCISSOR_TL_2 0x1ce8
794 #define RADEON_SCISSOR_BR_2 0x1cec
795 #define RADEON_SE_COORD_FMT 0x1c50
796 #define RADEON_SE_CNTL 0x1c4c
797 # define RADEON_FFACE_CULL_CW (0 << 0)
798 # define RADEON_BFACE_SOLID (3 << 1)
799 # define RADEON_FFACE_SOLID (3 << 3)
800 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
801 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
802 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
803 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
804 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
805 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
806 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
807 # define RADEON_FOG_SHADE_FLAT (1 << 14)
808 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
809 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
810 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
811 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
812 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
813 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
814 #define RADEON_SE_CNTL_STATUS 0x2140
815 #define RADEON_SE_LINE_WIDTH 0x1db8
816 #define RADEON_SE_VPORT_XSCALE 0x1d98
817 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
818 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
819 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
820 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
821 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
822 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
823 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
824 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
825 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
826 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
827 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
828 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
829 #define RADEON_SURFACE_CNTL 0x0b00
830 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
831 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
832 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
833 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
834 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
835 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
836 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
837 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
838 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
839 #define RADEON_SURFACE0_INFO 0x0b0c
840 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
841 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
842 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
843 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
844 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
845 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
846 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
847 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
848 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
849 #define RADEON_SURFACE1_INFO 0x0b1c
850 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
851 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
852 #define RADEON_SURFACE2_INFO 0x0b2c
853 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
854 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
855 #define RADEON_SURFACE3_INFO 0x0b3c
856 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
857 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
858 #define RADEON_SURFACE4_INFO 0x0b4c
859 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
860 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
861 #define RADEON_SURFACE5_INFO 0x0b5c
862 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
863 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
864 #define RADEON_SURFACE6_INFO 0x0b6c
865 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
866 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
867 #define RADEON_SURFACE7_INFO 0x0b7c
868 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
869 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
870 #define RADEON_SW_SEMAPHORE 0x013c
871
872 #define RADEON_WAIT_UNTIL 0x1720
873 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
874 # define RADEON_WAIT_2D_IDLE (1 << 14)
875 # define RADEON_WAIT_3D_IDLE (1 << 15)
876 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
877 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
878 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
879
880 #define RADEON_RB3D_ZMASKOFFSET 0x3234
881 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
882 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
883 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
884
885 /* CP registers */
886 #define RADEON_CP_ME_RAM_ADDR 0x07d4
887 #define RADEON_CP_ME_RAM_RADDR 0x07d8
888 #define RADEON_CP_ME_RAM_DATAH 0x07dc
889 #define RADEON_CP_ME_RAM_DATAL 0x07e0
890
891 #define RADEON_CP_RB_BASE 0x0700
892 #define RADEON_CP_RB_CNTL 0x0704
893 # define RADEON_BUF_SWAP_32BIT (2 << 16)
894 # define RADEON_RB_NO_UPDATE (1 << 27)
895 #define RADEON_CP_RB_RPTR_ADDR 0x070c
896 #define RADEON_CP_RB_RPTR 0x0710
897 #define RADEON_CP_RB_WPTR 0x0714
898
899 #define RADEON_CP_RB_WPTR_DELAY 0x0718
900 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
901 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
902
903 #define RADEON_CP_IB_BASE 0x0738
904
905 #define RADEON_CP_CSQ_CNTL 0x0740
906 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
907 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
908 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
909 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
910 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
911 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
912 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
913
914 #define RADEON_AIC_CNTL 0x01d0
915 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
916 #define RADEON_AIC_STAT 0x01d4
917 #define RADEON_AIC_PT_BASE 0x01d8
918 #define RADEON_AIC_LO_ADDR 0x01dc
919 #define RADEON_AIC_HI_ADDR 0x01e0
920 #define RADEON_AIC_TLB_ADDR 0x01e4
921 #define RADEON_AIC_TLB_DATA 0x01e8
922
923 /* CP command packets */
924 #define RADEON_CP_PACKET0 0x00000000
925 # define RADEON_ONE_REG_WR (1 << 15)
926 #define RADEON_CP_PACKET1 0x40000000
927 #define RADEON_CP_PACKET2 0x80000000
928 #define RADEON_CP_PACKET3 0xC0000000
929 # define RADEON_CP_NOP 0x00001000
930 # define RADEON_CP_NEXT_CHAR 0x00001900
931 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
932 # define RADEON_CP_SET_SCISSORS 0x00001E00
933 /* GEN_INDX_PRIM is unsupported starting with R300 */
934 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
935 # define RADEON_WAIT_FOR_IDLE 0x00002600
936 # define RADEON_3D_DRAW_VBUF 0x00002800
937 # define RADEON_3D_DRAW_IMMD 0x00002900
938 # define RADEON_3D_DRAW_INDX 0x00002A00
939 # define RADEON_CP_LOAD_PALETTE 0x00002C00
940 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
941 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
942 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
943 # define RADEON_3D_CLEAR_ZMASK 0x00003200
944 # define RADEON_CP_INDX_BUFFER 0x00003300
945 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
946 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
947 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
948 # define RADEON_3D_CLEAR_HIZ 0x00003700
949 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
950 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
951 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
952 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
953 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
954
955 #define RADEON_CP_PACKET_MASK 0xC0000000
956 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
957 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
958 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
959 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
960
961 #define RADEON_VTX_Z_PRESENT (1 << 31)
962 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
963
964 #define RADEON_PRIM_TYPE_NONE (0 << 0)
965 #define RADEON_PRIM_TYPE_POINT (1 << 0)
966 #define RADEON_PRIM_TYPE_LINE (2 << 0)
967 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
968 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
969 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
970 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
971 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
972 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
973 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
974 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
975 #define RADEON_PRIM_TYPE_MASK 0xf
976 #define RADEON_PRIM_WALK_IND (1 << 4)
977 #define RADEON_PRIM_WALK_LIST (2 << 4)
978 #define RADEON_PRIM_WALK_RING (3 << 4)
979 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
980 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
981 #define RADEON_MAOS_ENABLE (1 << 7)
982 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
983 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
984 #define RADEON_NUM_VERTICES_SHIFT 16
985
986 #define RADEON_COLOR_FORMAT_CI8 2
987 #define RADEON_COLOR_FORMAT_ARGB1555 3
988 #define RADEON_COLOR_FORMAT_RGB565 4
989 #define RADEON_COLOR_FORMAT_ARGB8888 6
990 #define RADEON_COLOR_FORMAT_RGB332 7
991 #define RADEON_COLOR_FORMAT_RGB8 9
992 #define RADEON_COLOR_FORMAT_ARGB4444 15
993
994 #define RADEON_TXFORMAT_I8 0
995 #define RADEON_TXFORMAT_AI88 1
996 #define RADEON_TXFORMAT_RGB332 2
997 #define RADEON_TXFORMAT_ARGB1555 3
998 #define RADEON_TXFORMAT_RGB565 4
999 #define RADEON_TXFORMAT_ARGB4444 5
1000 #define RADEON_TXFORMAT_ARGB8888 6
1001 #define RADEON_TXFORMAT_RGBA8888 7
1002 #define RADEON_TXFORMAT_Y8 8
1003 #define RADEON_TXFORMAT_VYUY422 10
1004 #define RADEON_TXFORMAT_YVYU422 11
1005 #define RADEON_TXFORMAT_DXT1 12
1006 #define RADEON_TXFORMAT_DXT23 14
1007 #define RADEON_TXFORMAT_DXT45 15
1008
1009 #define R200_PP_TXCBLEND_0 0x2f00
1010 #define R200_PP_TXCBLEND_1 0x2f10
1011 #define R200_PP_TXCBLEND_2 0x2f20
1012 #define R200_PP_TXCBLEND_3 0x2f30
1013 #define R200_PP_TXCBLEND_4 0x2f40
1014 #define R200_PP_TXCBLEND_5 0x2f50
1015 #define R200_PP_TXCBLEND_6 0x2f60
1016 #define R200_PP_TXCBLEND_7 0x2f70
1017 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1018 #define R200_PP_TFACTOR_0 0x2ee0
1019 #define R200_SE_VTX_FMT_0 0x2088
1020 #define R200_SE_VAP_CNTL 0x2080
1021 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1022 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1023 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1024 #define R200_PP_TXFILTER_5 0x2ca0
1025 #define R200_PP_TXFILTER_4 0x2c80
1026 #define R200_PP_TXFILTER_3 0x2c60
1027 #define R200_PP_TXFILTER_2 0x2c40
1028 #define R200_PP_TXFILTER_1 0x2c20
1029 #define R200_PP_TXFILTER_0 0x2c00
1030 #define R200_PP_TXOFFSET_5 0x2d78
1031 #define R200_PP_TXOFFSET_4 0x2d60
1032 #define R200_PP_TXOFFSET_3 0x2d48
1033 #define R200_PP_TXOFFSET_2 0x2d30
1034 #define R200_PP_TXOFFSET_1 0x2d18
1035 #define R200_PP_TXOFFSET_0 0x2d00
1036
1037 #define R200_PP_CUBIC_FACES_0 0x2c18
1038 #define R200_PP_CUBIC_FACES_1 0x2c38
1039 #define R200_PP_CUBIC_FACES_2 0x2c58
1040 #define R200_PP_CUBIC_FACES_3 0x2c78
1041 #define R200_PP_CUBIC_FACES_4 0x2c98
1042 #define R200_PP_CUBIC_FACES_5 0x2cb8
1043 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1044 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1045 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1046 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1047 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1048 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1049 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1050 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1051 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1052 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1053 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1054 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1055 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1056 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1057 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1058 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1059 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1060 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1061 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1062 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1063 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1064 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1065 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1066 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1067 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1068 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1069 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1070 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1071 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1072 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1073
1074 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1075 #define R200_SE_VTE_CNTL 0x20b0
1076 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1077 #define R200_PP_TAM_DEBUG3 0x2d9c
1078 #define R200_PP_CNTL_X 0x2cc4
1079 #define R200_SE_VAP_CNTL_STATUS 0x2140
1080 #define R200_RE_SCISSOR_TL_0 0x1cd8
1081 #define R200_RE_SCISSOR_TL_1 0x1ce0
1082 #define R200_RE_SCISSOR_TL_2 0x1ce8
1083 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1084 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1085 #define R200_SE_VTX_STATE_CNTL 0x2180
1086 #define R200_RE_POINTSIZE 0x2648
1087 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1088
1089 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1090 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1091 #define RADEON_PP_TEX_SIZE_2 0x1d14
1092
1093 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1094 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1095 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1096 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1097 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1098 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1099
1100 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1101
1102 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1103 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1104 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1105 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1106 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1107 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1108 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1109 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1110 #define R200_3D_DRAW_IMMD_2 0xC0003500
1111 #define R200_SE_VTX_FMT_1 0x208c
1112 #define R200_RE_CNTL 0x1c50
1113
1114 #define R200_RB3D_BLENDCOLOR 0x3218
1115
1116 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1117
1118 #define R200_PP_TRI_PERF 0x2cf8
1119
1120 #define R200_PP_AFS_0 0x2f80
1121 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1122
1123 #define R200_VAP_PVS_CNTL_1 0x22D0
1124
1125 #define RADEON_CRTC_CRNT_FRAME 0x0214
1126 #define RADEON_CRTC2_CRNT_FRAME 0x0314
1127
1128 #define R500_D1CRTC_STATUS 0x609c
1129 #define R500_D2CRTC_STATUS 0x689c
1130 #define R500_CRTC_V_BLANK (1<<0)
1131
1132 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1133 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1134
1135 #define R500_D1MODE_V_COUNTER 0x6530
1136 #define R500_D2MODE_V_COUNTER 0x6d30
1137
1138 #define R500_D1MODE_VBLANK_STATUS 0x6534
1139 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1140 #define R500_VBLANK_OCCURED (1<<0)
1141 #define R500_VBLANK_ACK (1<<4)
1142 #define R500_VBLANK_STAT (1<<12)
1143 #define R500_VBLANK_INT (1<<16)
1144
1145 #define R500_DxMODE_INT_MASK 0x6540
1146 #define R500_D1MODE_INT_MASK (1<<0)
1147 #define R500_D2MODE_INT_MASK (1<<8)
1148
1149 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1150 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1151 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1152
1153 /* Constants */
1154 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1155
1156 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1157 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1158 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1159 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1160 #define RADEON_LAST_DISPATCH 1
1161
1162 #define RADEON_MAX_VB_AGE 0x7fffffff
1163 #define RADEON_MAX_VB_VERTS (0xffff)
1164
1165 #define RADEON_RING_HIGH_MARK 128
1166
1167 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1168
1169 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1170 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1171 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1172 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1173
1174 #define RADEON_WRITE_PLL(addr, val) \
1175 do { \
1176 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1177 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1178 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1179 } while (0)
1180
1181 #define RADEON_WRITE_PCIE(addr, val) \
1182 do { \
1183 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1184 ((addr) & 0xff)); \
1185 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1186 } while (0)
1187
1188 #define R500_WRITE_MCIND(addr, val) \
1189 do { \
1190 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1191 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1192 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1193 } while (0)
1194
1195 #define RS480_WRITE_MCIND(addr, val) \
1196 do { \
1197 RADEON_WRITE(RS480_NB_MC_INDEX, \
1198 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1199 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1200 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1201 } while (0)
1202
1203 #define RS690_WRITE_MCIND(addr, val) \
1204 do { \
1205 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1206 RADEON_WRITE(RS690_MC_DATA, val); \
1207 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1208 } while (0)
1209
1210 #define IGP_WRITE_MCIND(addr, val) \
1211 do { \
1212 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1213 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1214 RS690_WRITE_MCIND(addr, val); \
1215 else \
1216 RS480_WRITE_MCIND(addr, val); \
1217 } while (0)
1218
1219 #define CP_PACKET0( reg, n ) \
1220 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1221 #define CP_PACKET0_TABLE( reg, n ) \
1222 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1223 #define CP_PACKET1( reg0, reg1 ) \
1224 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1225 #define CP_PACKET2() \
1226 (RADEON_CP_PACKET2)
1227 #define CP_PACKET3( pkt, n ) \
1228 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1229
1230 /* ================================================================
1231 * Engine control helper macros
1232 */
1233
1234 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1235 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1236 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1237 RADEON_WAIT_HOST_IDLECLEAN) ); \
1238 } while (0)
1239
1240 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1241 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1242 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1243 RADEON_WAIT_HOST_IDLECLEAN) ); \
1244 } while (0)
1245
1246 #define RADEON_WAIT_UNTIL_IDLE() do { \
1247 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1248 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1249 RADEON_WAIT_3D_IDLECLEAN | \
1250 RADEON_WAIT_HOST_IDLECLEAN) ); \
1251 } while (0)
1252
1253 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1254 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1255 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1256 } while (0)
1257
1258 #define RADEON_FLUSH_CACHE() do { \
1259 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1260 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1261 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1262 } else { \
1263 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1264 OUT_RING(R300_RB3D_DC_FLUSH); \
1265 } \
1266 } while (0)
1267
1268 #define RADEON_PURGE_CACHE() do { \
1269 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1270 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1271 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1272 } else { \
1273 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1274 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1275 } \
1276 } while (0)
1277
1278 #define RADEON_FLUSH_ZCACHE() do { \
1279 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1280 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1281 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1282 } else { \
1283 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1284 OUT_RING(R300_ZC_FLUSH); \
1285 } \
1286 } while (0)
1287
1288 #define RADEON_PURGE_ZCACHE() do { \
1289 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1290 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1291 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1292 } else { \
1293 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1294 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1295 } \
1296 } while (0)
1297
1298 /* ================================================================
1299 * Misc helper macros
1300 */
1301
1302 /* Perfbox functionality only.
1303 */
1304 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1305 do { \
1306 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1307 u32 head = GET_RING_HEAD( dev_priv ); \
1308 if (head == dev_priv->ring.tail) \
1309 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1310 } \
1311 } while (0)
1312
1313 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1314 do { \
1315 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1316 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1317 int __ret = radeon_do_cp_idle( dev_priv ); \
1318 if ( __ret ) return __ret; \
1319 sarea_priv->last_dispatch = 0; \
1320 radeon_freelist_reset( dev ); \
1321 } \
1322 } while (0)
1323
1324 #define RADEON_DISPATCH_AGE( age ) do { \
1325 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1326 OUT_RING( age ); \
1327 } while (0)
1328
1329 #define RADEON_FRAME_AGE( age ) do { \
1330 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1331 OUT_RING( age ); \
1332 } while (0)
1333
1334 #define RADEON_CLEAR_AGE( age ) do { \
1335 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1336 OUT_RING( age ); \
1337 } while (0)
1338
1339 /* ================================================================
1340 * Ring control
1341 */
1342
1343 #define RADEON_VERBOSE 0
1344
1345 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1346
1347 #define BEGIN_RING( n ) do { \
1348 if ( RADEON_VERBOSE ) { \
1349 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1350 } \
1351 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1352 COMMIT_RING(); \
1353 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1354 } \
1355 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1356 ring = dev_priv->ring.start; \
1357 write = dev_priv->ring.tail; \
1358 mask = dev_priv->ring.tail_mask; \
1359 } while (0)
1360
1361 #define ADVANCE_RING() do { \
1362 if ( RADEON_VERBOSE ) { \
1363 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1364 write, dev_priv->ring.tail ); \
1365 } \
1366 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1367 DRM_ERROR( \
1368 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1369 ((dev_priv->ring.tail + _nr) & mask), \
1370 write, __LINE__); \
1371 } else \
1372 dev_priv->ring.tail = write; \
1373 } while (0)
1374
1375 #define COMMIT_RING() do { \
1376 /* Flush writes to ring */ \
1377 DRM_MEMORYBARRIER(); \
1378 GET_RING_HEAD( dev_priv ); \
1379 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1380 /* read from PCI bus to ensure correct posting */ \
1381 RADEON_READ( RADEON_CP_RB_RPTR ); \
1382 } while (0)
1383
1384 #define OUT_RING( x ) do { \
1385 if ( RADEON_VERBOSE ) { \
1386 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1387 (unsigned int)(x), write ); \
1388 } \
1389 ring[write++] = (x); \
1390 write &= mask; \
1391 } while (0)
1392
1393 #define OUT_RING_REG( reg, val ) do { \
1394 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1395 OUT_RING( val ); \
1396 } while (0)
1397
1398 #define OUT_RING_TABLE( tab, sz ) do { \
1399 int _size = (sz); \
1400 int *_tab = (int *)(tab); \
1401 \
1402 if (write + _size > mask) { \
1403 int _i = (mask+1) - write; \
1404 _size -= _i; \
1405 while (_i > 0 ) { \
1406 *(int *)(ring + write) = *_tab++; \
1407 write++; \
1408 _i--; \
1409 } \
1410 write = 0; \
1411 _tab += _i; \
1412 } \
1413 while (_size > 0) { \
1414 *(ring + write) = *_tab++; \
1415 write++; \
1416 _size--; \
1417 } \
1418 write &= mask; \
1419 } while (0)
1420
1421 #endif /* __RADEON_DRV_H__ */
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