2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.16"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg
=
86 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
87 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
90 static int debug
= -1; /* defaults above */
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly
= 128;
95 module_param(copybreak
, int, 0);
96 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
98 static int disable_msi
= 0;
99 module_param(disable_msi
, int, 0);
100 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
102 static int idle_timeout
= 100;
103 module_param(idle_timeout
, int, 0);
104 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
106 static const struct pci_device_id sky2_id_table
[] = {
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
140 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
144 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
145 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name
[] = {
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
156 /* Access to external PHY */
157 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
161 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
162 gma_write16(hw
, port
, GM_SMI_CTRL
,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
165 for (i
= 0; i
< PHY_RETRIES
; i
++) {
166 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
171 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
175 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
179 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
180 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
182 for (i
= 0; i
< PHY_RETRIES
; i
++) {
183 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
184 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
194 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
198 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
199 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
204 static void sky2_power_on(struct sky2_hw
*hw
)
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw
, B0_POWER_CTRL
,
208 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
210 /* disable Core Clock Division, */
211 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
213 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
214 /* enable bits are inverted */
215 sky2_write8(hw
, B2_Y2_CLK_GATE
,
216 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
217 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
218 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
220 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
222 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
223 hw
->chip_id
== CHIP_ID_YUKON_EX
) {
226 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
228 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
229 /* set all bits to 0 except bits 15..12 and 8 */
230 reg
&= P_ASPM_CONTROL_MSK
;
231 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
233 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
234 /* set all bits to 0 except bits 28 & 27 */
235 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
236 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
238 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
240 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
241 reg
= sky2_read32(hw
, B2_GP_IO
);
242 reg
|= GLB_GPIO_STAT_RACE_DIS
;
243 sky2_write32(hw
, B2_GP_IO
, reg
);
245 sky2_read32(hw
, B2_GP_IO
);
249 static void sky2_power_aux(struct sky2_hw
*hw
)
251 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
252 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
254 /* enable bits are inverted */
255 sky2_write8(hw
, B2_Y2_CLK_GATE
,
256 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
257 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
258 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
260 /* switch power to VAUX */
261 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
262 sky2_write8(hw
, B0_POWER_CTRL
,
263 (PC_VAUX_ENA
| PC_VCC_ENA
|
264 PC_VAUX_ON
| PC_VCC_OFF
));
267 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
276 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
277 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
278 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
279 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
281 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
282 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
283 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
286 /* flow control to advertise bits */
287 static const u16 copper_fc_adv
[] = {
289 [FC_TX
] = PHY_M_AN_ASP
,
290 [FC_RX
] = PHY_M_AN_PC
,
291 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
294 /* flow control to advertise bits when using 1000BaseX */
295 static const u16 fiber_fc_adv
[] = {
296 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
297 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
298 [FC_RX
] = PHY_M_P_SYM_MD_X
,
299 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
302 /* flow control to GMA disable bits */
303 static const u16 gm_fc_disable
[] = {
304 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
305 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
306 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
311 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
313 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
314 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
316 if (sky2
->autoneg
== AUTONEG_ENABLE
317 && !(hw
->chip_id
== CHIP_ID_YUKON_XL
318 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
319 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
320 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
322 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
324 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
326 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
327 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
328 /* set downshift counter to 3x and enable downshift */
329 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
331 /* set master & slave downshift counter to 1x */
332 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
334 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
337 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
338 if (sky2_is_copper(hw
)) {
339 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
340 /* enable automatic crossover */
341 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
343 /* disable energy detect */
344 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
346 /* enable automatic crossover */
347 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
349 /* downshift on PHY 88E1112 and 88E1149 is changed */
350 if (sky2
->autoneg
== AUTONEG_ENABLE
351 && (hw
->chip_id
== CHIP_ID_YUKON_XL
352 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
353 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
354 /* set downshift counter to 3x and enable downshift */
355 ctrl
&= ~PHY_M_PC_DSC_MSK
;
356 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
360 /* workaround for deviation #4.88 (CRC errors) */
361 /* disable Automatic Crossover */
363 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
366 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
368 /* special setup for PHY 88E1112 Fiber */
369 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
370 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
372 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
373 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
374 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
375 ctrl
&= ~PHY_M_MAC_MD_MSK
;
376 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
377 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
379 if (hw
->pmd_type
== 'P') {
380 /* select page 1 to access Fiber registers */
381 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
383 /* for SFP-module set SIGDET polarity to low */
384 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
385 ctrl
|= PHY_M_FIB_SIGD_POL
;
386 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
389 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
397 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
398 if (sky2_is_copper(hw
)) {
399 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
400 ct1000
|= PHY_M_1000C_AFD
;
401 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
402 ct1000
|= PHY_M_1000C_AHD
;
403 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
404 adv
|= PHY_M_AN_100_FD
;
405 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
406 adv
|= PHY_M_AN_100_HD
;
407 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
408 adv
|= PHY_M_AN_10_FD
;
409 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
410 adv
|= PHY_M_AN_10_HD
;
412 adv
|= copper_fc_adv
[sky2
->flow_mode
];
413 } else { /* special defines for FIBER (88E1040S only) */
414 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
415 adv
|= PHY_M_AN_1000X_AFD
;
416 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
417 adv
|= PHY_M_AN_1000X_AHD
;
419 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
422 /* Restart Auto-negotiation */
423 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
425 /* forced speed/duplex settings */
426 ct1000
= PHY_M_1000C_MSE
;
428 /* Disable auto update for duplex flow control and speed */
429 reg
|= GM_GPCR_AU_ALL_DIS
;
431 switch (sky2
->speed
) {
433 ctrl
|= PHY_CT_SP1000
;
434 reg
|= GM_GPCR_SPEED_1000
;
437 ctrl
|= PHY_CT_SP100
;
438 reg
|= GM_GPCR_SPEED_100
;
442 if (sky2
->duplex
== DUPLEX_FULL
) {
443 reg
|= GM_GPCR_DUP_FULL
;
444 ctrl
|= PHY_CT_DUP_MD
;
445 } else if (sky2
->speed
< SPEED_1000
)
446 sky2
->flow_mode
= FC_NONE
;
449 reg
|= gm_fc_disable
[sky2
->flow_mode
];
451 /* Forward pause packets to GMAC? */
452 if (sky2
->flow_mode
& FC_RX
)
453 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
455 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
458 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
460 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
461 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
463 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
464 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
466 /* Setup Phy LED's */
467 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
470 switch (hw
->chip_id
) {
471 case CHIP_ID_YUKON_FE
:
472 /* on 88E3082 these bits are at 11..9 (shifted left) */
473 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
475 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
477 /* delete ACT LED control bits */
478 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
479 /* change ACT LED control to blink mode */
480 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
481 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
484 case CHIP_ID_YUKON_XL
:
485 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
487 /* select page 3 to access LED control register */
488 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
490 /* set LED Function Control register */
491 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
492 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
493 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
494 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
495 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
497 /* set Polarity Control register */
498 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
499 (PHY_M_POLC_LS1_P_MIX(4) |
500 PHY_M_POLC_IS0_P_MIX(4) |
501 PHY_M_POLC_LOS_CTRL(2) |
502 PHY_M_POLC_INIT_CTRL(2) |
503 PHY_M_POLC_STA1_CTRL(2) |
504 PHY_M_POLC_STA0_CTRL(2)));
506 /* restore page register */
507 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
510 case CHIP_ID_YUKON_EC_U
:
511 case CHIP_ID_YUKON_EX
:
512 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
514 /* select page 3 to access LED control register */
515 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
517 /* set LED Function Control register */
518 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
519 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
520 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
521 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
522 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
524 /* set Blink Rate in LED Timer Control Register */
525 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
526 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
527 /* restore page register */
528 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
532 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
533 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
534 /* turn off the Rx LED (LED_RX) */
535 ledover
&= ~PHY_M_LED_MO_RX
;
538 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
539 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
540 /* apply fixes in PHY AFE */
541 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
543 /* increase differential signal amplitude in 10BASE-T */
544 gm_phy_write(hw
, port
, 0x18, 0xaa99);
545 gm_phy_write(hw
, port
, 0x17, 0x2011);
547 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
548 gm_phy_write(hw
, port
, 0x18, 0xa204);
549 gm_phy_write(hw
, port
, 0x17, 0x2002);
551 /* set page register to 0 */
552 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
553 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
554 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
556 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
557 /* turn on 100 Mbps LED (LED_LINK100) */
558 ledover
|= PHY_M_LED_MO_100
;
562 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
566 /* Enable phy interrupt on auto-negotiation complete (or link up) */
567 if (sky2
->autoneg
== AUTONEG_ENABLE
)
568 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
570 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
573 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
576 static const u32 phy_power
[]
577 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
579 /* looks like this XL is back asswards .. */
580 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
583 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
584 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
586 /* Turn off phy power saving */
587 reg1
&= ~phy_power
[port
];
589 reg1
|= phy_power
[port
];
591 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
592 sky2_pci_read32(hw
, PCI_DEV_REG1
);
593 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
597 /* Force a renegotiation */
598 static void sky2_phy_reinit(struct sky2_port
*sky2
)
600 spin_lock_bh(&sky2
->phy_lock
);
601 sky2_phy_init(sky2
->hw
, sky2
->port
);
602 spin_unlock_bh(&sky2
->phy_lock
);
605 /* Put device in state to listen for Wake On Lan */
606 static void sky2_wol_init(struct sky2_port
*sky2
)
608 struct sky2_hw
*hw
= sky2
->hw
;
609 unsigned port
= sky2
->port
;
610 enum flow_control save_mode
;
614 /* Bring hardware out of reset */
615 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
616 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
618 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
619 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
622 * sky2_reset will re-enable on resume
624 save_mode
= sky2
->flow_mode
;
625 ctrl
= sky2
->advertising
;
627 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
628 sky2
->flow_mode
= FC_NONE
;
629 sky2_phy_power(hw
, port
, 1);
630 sky2_phy_reinit(sky2
);
632 sky2
->flow_mode
= save_mode
;
633 sky2
->advertising
= ctrl
;
635 /* Set GMAC to no flow control and auto update for speed/duplex */
636 gma_write16(hw
, port
, GM_GP_CTRL
,
637 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
638 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
640 /* Set WOL address */
641 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
642 sky2
->netdev
->dev_addr
, ETH_ALEN
);
644 /* Turn on appropriate WOL control bits */
645 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
647 if (sky2
->wol
& WAKE_PHY
)
648 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
650 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
652 if (sky2
->wol
& WAKE_MAGIC
)
653 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
655 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
657 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
658 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
660 /* Turn on legacy PCI-Express PME mode */
661 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
662 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
663 reg1
|= PCI_Y2_PME_LEGACY
;
664 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
665 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
668 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
672 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
674 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) {
675 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
677 (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) ? TX_JUMBO_ENA
: TX_JUMBO_DIS
);
679 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
680 /* set Tx GMAC FIFO Almost Empty Threshold */
681 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
682 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
684 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
685 TX_JUMBO_ENA
| TX_STFW_DIS
);
687 /* Can't do offload because of lack of store/forward */
688 hw
->dev
[port
]->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
691 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
692 TX_JUMBO_DIS
| TX_STFW_ENA
);
696 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
698 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
702 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
704 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
705 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
707 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
709 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
710 /* WA DEV_472 -- looks like crossed wires on port 2 */
711 /* clear GMAC 1 Control reset */
712 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
714 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
715 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
716 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
717 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
718 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
721 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
723 /* Enable Transmit FIFO Underrun */
724 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
726 spin_lock_bh(&sky2
->phy_lock
);
727 sky2_phy_init(hw
, port
);
728 spin_unlock_bh(&sky2
->phy_lock
);
731 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
732 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
734 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
735 gma_read16(hw
, port
, i
);
736 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
738 /* transmit control */
739 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
741 /* receive control reg: unicast + multicast + no FCS */
742 gma_write16(hw
, port
, GM_RX_CTRL
,
743 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
745 /* transmit flow control */
746 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
748 /* transmit parameter */
749 gma_write16(hw
, port
, GM_TX_PARAM
,
750 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
751 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
752 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
753 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
755 /* serial mode register */
756 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
757 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
759 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
760 reg
|= GM_SMOD_JUMBO_ENA
;
762 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
764 /* virtual address for data */
765 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
767 /* physical address: used for pause frames */
768 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
770 /* ignore counter overflows */
771 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
772 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
773 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
775 /* Configure Rx MAC FIFO */
776 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
777 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
778 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
779 rx_reg
|= GMF_RX_OVER_ON
;
781 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
783 /* Flush Rx MAC FIFO on any flow control or error */
784 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
786 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
787 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
789 /* Configure Tx MAC FIFO */
790 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
791 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
793 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
794 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
795 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
797 sky2_set_tx_stfwd(hw
, port
);
802 /* Assign Ram Buffer allocation to queue */
803 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
807 /* convert from K bytes to qwords used for hw register */
810 end
= start
+ space
- 1;
812 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
813 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
814 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
815 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
816 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
818 if (q
== Q_R1
|| q
== Q_R2
) {
819 u32 tp
= space
- space
/4;
821 /* On receive queue's set the thresholds
822 * give receiver priority when > 3/4 full
823 * send pause when down to 2K
825 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
826 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
829 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
830 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
832 /* Enable store & forward on Tx queue's because
833 * Tx FIFO is only 1K on Yukon
835 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
838 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
839 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
842 /* Setup Bus Memory Interface */
843 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
845 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
846 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
847 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
848 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
851 /* Setup prefetch unit registers. This is the interface between
852 * hardware and driver list elements
854 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
857 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
858 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
859 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
860 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
861 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
862 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
864 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
867 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
869 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
871 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
876 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
877 struct sky2_tx_le
*le
)
879 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
882 /* Update chip's next pointer */
883 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
885 /* Make sure write' to descriptors are complete before we tell hardware */
887 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
889 /* Synchronize I/O on since next processor may write to tail */
894 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
896 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
897 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
902 /* Build description to hardware for one receive segment */
903 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
904 dma_addr_t map
, unsigned len
)
906 struct sky2_rx_le
*le
;
907 u32 hi
= upper_32_bits(map
);
909 if (sky2
->rx_addr64
!= hi
) {
910 le
= sky2_next_rx(sky2
);
911 le
->addr
= cpu_to_le32(hi
);
912 le
->opcode
= OP_ADDR64
| HW_OWNER
;
913 sky2
->rx_addr64
= upper_32_bits(map
+ len
);
916 le
= sky2_next_rx(sky2
);
917 le
->addr
= cpu_to_le32((u32
) map
);
918 le
->length
= cpu_to_le16(len
);
919 le
->opcode
= op
| HW_OWNER
;
922 /* Build description to hardware for one possibly fragmented skb */
923 static void sky2_rx_submit(struct sky2_port
*sky2
,
924 const struct rx_ring_info
*re
)
928 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
930 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
931 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
935 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
938 struct sk_buff
*skb
= re
->skb
;
941 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
942 pci_unmap_len_set(re
, data_size
, size
);
944 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
945 re
->frag_addr
[i
] = pci_map_page(pdev
,
946 skb_shinfo(skb
)->frags
[i
].page
,
947 skb_shinfo(skb
)->frags
[i
].page_offset
,
948 skb_shinfo(skb
)->frags
[i
].size
,
952 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
954 struct sk_buff
*skb
= re
->skb
;
957 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
960 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
961 pci_unmap_page(pdev
, re
->frag_addr
[i
],
962 skb_shinfo(skb
)->frags
[i
].size
,
966 /* Tell chip where to start receive checksum.
967 * Actually has two checksums, but set both same to avoid possible byte
970 static void rx_set_checksum(struct sky2_port
*sky2
)
972 struct sky2_rx_le
*le
;
974 if (sky2
->hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
975 le
= sky2_next_rx(sky2
);
976 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
978 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
980 sky2_write32(sky2
->hw
,
981 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
982 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
988 * The RX Stop command will not work for Yukon-2 if the BMU does not
989 * reach the end of packet and since we can't make sure that we have
990 * incoming data, we must reset the BMU while it is not doing a DMA
991 * transfer. Since it is possible that the RX path is still active,
992 * the RX RAM buffer will be stopped first, so any possible incoming
993 * data will not trigger a DMA. After the RAM buffer is stopped, the
994 * BMU is polled until any DMA in progress is ended and only then it
997 static void sky2_rx_stop(struct sky2_port
*sky2
)
999 struct sky2_hw
*hw
= sky2
->hw
;
1000 unsigned rxq
= rxqaddr
[sky2
->port
];
1003 /* disable the RAM Buffer receive queue */
1004 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1006 for (i
= 0; i
< 0xffff; i
++)
1007 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1008 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1011 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1012 sky2
->netdev
->name
);
1014 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1016 /* reset the Rx prefetch unit */
1017 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1021 /* Clean out receive buffer area, assumes receiver hardware stopped */
1022 static void sky2_rx_clean(struct sky2_port
*sky2
)
1026 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1027 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1028 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1031 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1038 /* Basic MII support */
1039 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1041 struct mii_ioctl_data
*data
= if_mii(ifr
);
1042 struct sky2_port
*sky2
= netdev_priv(dev
);
1043 struct sky2_hw
*hw
= sky2
->hw
;
1044 int err
= -EOPNOTSUPP
;
1046 if (!netif_running(dev
))
1047 return -ENODEV
; /* Phy still in reset */
1051 data
->phy_id
= PHY_ADDR_MARV
;
1057 spin_lock_bh(&sky2
->phy_lock
);
1058 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1059 spin_unlock_bh(&sky2
->phy_lock
);
1061 data
->val_out
= val
;
1066 if (!capable(CAP_NET_ADMIN
))
1069 spin_lock_bh(&sky2
->phy_lock
);
1070 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1072 spin_unlock_bh(&sky2
->phy_lock
);
1078 #ifdef SKY2_VLAN_TAG_USED
1079 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1081 struct sky2_port
*sky2
= netdev_priv(dev
);
1082 struct sky2_hw
*hw
= sky2
->hw
;
1083 u16 port
= sky2
->port
;
1085 netif_tx_lock_bh(dev
);
1086 netif_poll_disable(sky2
->hw
->dev
[0]);
1090 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1092 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1095 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1097 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1101 netif_poll_enable(sky2
->hw
->dev
[0]);
1102 netif_tx_unlock_bh(dev
);
1107 * Allocate an skb for receiving. If the MTU is large enough
1108 * make the skb non-linear with a fragment list of pages.
1110 * It appears the hardware has a bug in the FIFO logic that
1111 * cause it to hang if the FIFO gets overrun and the receive buffer
1112 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1113 * aligned except if slab debugging is enabled.
1115 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1117 struct sk_buff
*skb
;
1121 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1125 p
= (unsigned long) skb
->data
;
1126 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1128 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1129 struct page
*page
= alloc_page(GFP_ATOMIC
);
1133 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1143 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1145 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1149 * Allocate and setup receiver buffer pool.
1150 * Normal case this ends up creating one list element for skb
1151 * in the receive ring. Worst case if using large MTU and each
1152 * allocation falls on a different 64 bit region, that results
1153 * in 6 list elements per ring entry.
1154 * One element is used for checksum enable/disable, and one
1155 * extra to avoid wrap.
1157 static int sky2_rx_start(struct sky2_port
*sky2
)
1159 struct sky2_hw
*hw
= sky2
->hw
;
1160 struct rx_ring_info
*re
;
1161 unsigned rxq
= rxqaddr
[sky2
->port
];
1162 unsigned i
, size
, space
, thresh
;
1164 sky2
->rx_put
= sky2
->rx_next
= 0;
1167 /* On PCI express lowering the watermark gives better performance */
1168 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1169 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1171 /* These chips have no ram buffer?
1172 * MAC Rx RAM Read is controlled by hardware */
1173 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1174 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1175 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1176 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1178 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1180 rx_set_checksum(sky2
);
1182 /* Space needed for frame data + headers rounded up */
1183 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1185 /* Stopping point for hardware truncation */
1186 thresh
= (size
- 8) / sizeof(u32
);
1188 /* Account for overhead of skb - to avoid order > 0 allocation */
1189 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1190 + sizeof(struct skb_shared_info
);
1192 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1193 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1195 if (sky2
->rx_nfrags
!= 0) {
1196 /* Compute residue after pages */
1197 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1204 /* Optimize to handle small packets and headers */
1205 if (size
< copybreak
)
1207 if (size
< ETH_HLEN
)
1210 sky2
->rx_data_size
= size
;
1213 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1214 re
= sky2
->rx_ring
+ i
;
1216 re
->skb
= sky2_rx_alloc(sky2
);
1220 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1221 sky2_rx_submit(sky2
, re
);
1225 * The receiver hangs if it receives frames larger than the
1226 * packet buffer. As a workaround, truncate oversize frames, but
1227 * the register is limited to 9 bits, so if you do frames > 2052
1228 * you better get the MTU right!
1231 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1233 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1234 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1237 /* Tell chip about available buffers */
1238 sky2_rx_update(sky2
, rxq
);
1241 sky2_rx_clean(sky2
);
1245 /* Bring up network interface. */
1246 static int sky2_up(struct net_device
*dev
)
1248 struct sky2_port
*sky2
= netdev_priv(dev
);
1249 struct sky2_hw
*hw
= sky2
->hw
;
1250 unsigned port
= sky2
->port
;
1252 int cap
, err
= -ENOMEM
;
1253 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1256 * On dual port PCI-X card, there is an problem where status
1257 * can be received out of order due to split transactions
1259 if (otherdev
&& netif_running(otherdev
) &&
1260 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1261 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1264 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1265 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1266 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1272 if (netif_msg_ifup(sky2
))
1273 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1275 netif_carrier_off(dev
);
1277 /* must be power of 2 */
1278 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1280 sizeof(struct sky2_tx_le
),
1285 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1289 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1291 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1295 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1297 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1302 sky2_phy_power(hw
, port
, 1);
1304 sky2_mac_init(hw
, port
);
1306 /* Register is number of 4K blocks on internal RAM buffer. */
1307 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1308 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1314 rxspace
= ramsize
/ 2;
1316 rxspace
= 8 + (2*(ramsize
- 16))/3;
1318 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1319 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1321 /* Make sure SyncQ is disabled */
1322 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1326 sky2_qset(hw
, txqaddr
[port
]);
1328 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1329 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1330 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1332 /* Set almost empty threshold */
1333 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1334 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1335 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1337 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1340 err
= sky2_rx_start(sky2
);
1344 /* Enable interrupts from phy/mac for port */
1345 imask
= sky2_read32(hw
, B0_IMSK
);
1346 imask
|= portirq_msk
[port
];
1347 sky2_write32(hw
, B0_IMSK
, imask
);
1353 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1354 sky2
->rx_le
, sky2
->rx_le_map
);
1358 pci_free_consistent(hw
->pdev
,
1359 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1360 sky2
->tx_le
, sky2
->tx_le_map
);
1363 kfree(sky2
->tx_ring
);
1364 kfree(sky2
->rx_ring
);
1366 sky2
->tx_ring
= NULL
;
1367 sky2
->rx_ring
= NULL
;
1371 /* Modular subtraction in ring */
1372 static inline int tx_dist(unsigned tail
, unsigned head
)
1374 return (head
- tail
) & (TX_RING_SIZE
- 1);
1377 /* Number of list elements available for next tx */
1378 static inline int tx_avail(const struct sky2_port
*sky2
)
1380 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1383 /* Estimate of number of transmit list elements required */
1384 static unsigned tx_le_req(const struct sk_buff
*skb
)
1388 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1389 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1391 if (skb_is_gso(skb
))
1394 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1401 * Put one packet in ring for transmit.
1402 * A single packet can generate multiple list elements, and
1403 * the number of ring elements will probably be less than the number
1404 * of list elements used.
1406 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1408 struct sky2_port
*sky2
= netdev_priv(dev
);
1409 struct sky2_hw
*hw
= sky2
->hw
;
1410 struct sky2_tx_le
*le
= NULL
;
1411 struct tx_ring_info
*re
;
1418 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1419 return NETDEV_TX_BUSY
;
1421 if (unlikely(netif_msg_tx_queued(sky2
)))
1422 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1423 dev
->name
, sky2
->tx_prod
, skb
->len
);
1425 len
= skb_headlen(skb
);
1426 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1427 addr64
= upper_32_bits(mapping
);
1429 /* Send high bits if changed or crosses boundary */
1430 if (addr64
!= sky2
->tx_addr64
||
1431 upper_32_bits(mapping
+ len
) != sky2
->tx_addr64
) {
1432 le
= get_tx_le(sky2
);
1433 le
->addr
= cpu_to_le32(addr64
);
1434 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1435 sky2
->tx_addr64
= upper_32_bits(mapping
+ len
);
1438 /* Check for TCP Segmentation Offload */
1439 mss
= skb_shinfo(skb
)->gso_size
;
1441 if (hw
->chip_id
!= CHIP_ID_YUKON_EX
)
1442 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1444 if (mss
!= sky2
->tx_last_mss
) {
1445 le
= get_tx_le(sky2
);
1446 le
->addr
= cpu_to_le32(mss
);
1447 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
1448 le
->opcode
= OP_MSS
| HW_OWNER
;
1450 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1451 sky2
->tx_last_mss
= mss
;
1456 #ifdef SKY2_VLAN_TAG_USED
1457 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1458 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1460 le
= get_tx_le(sky2
);
1462 le
->opcode
= OP_VLAN
|HW_OWNER
;
1464 le
->opcode
|= OP_VLAN
;
1465 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1470 /* Handle TCP checksum offload */
1471 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1472 /* On Yukon EX (some versions) encoding change. */
1473 if (hw
->chip_id
== CHIP_ID_YUKON_EX
1474 && hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
1475 ctrl
|= CALSUM
; /* auto checksum */
1477 const unsigned offset
= skb_transport_offset(skb
);
1480 tcpsum
= offset
<< 16; /* sum start */
1481 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1483 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1484 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1487 if (tcpsum
!= sky2
->tx_tcpsum
) {
1488 sky2
->tx_tcpsum
= tcpsum
;
1490 le
= get_tx_le(sky2
);
1491 le
->addr
= cpu_to_le32(tcpsum
);
1492 le
->length
= 0; /* initial checksum value */
1493 le
->ctrl
= 1; /* one packet */
1494 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1499 le
= get_tx_le(sky2
);
1500 le
->addr
= cpu_to_le32((u32
) mapping
);
1501 le
->length
= cpu_to_le16(len
);
1503 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1505 re
= tx_le_re(sky2
, le
);
1507 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1508 pci_unmap_len_set(re
, maplen
, len
);
1510 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1511 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1513 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1514 frag
->size
, PCI_DMA_TODEVICE
);
1515 addr64
= upper_32_bits(mapping
);
1516 if (addr64
!= sky2
->tx_addr64
) {
1517 le
= get_tx_le(sky2
);
1518 le
->addr
= cpu_to_le32(addr64
);
1520 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1521 sky2
->tx_addr64
= addr64
;
1524 le
= get_tx_le(sky2
);
1525 le
->addr
= cpu_to_le32((u32
) mapping
);
1526 le
->length
= cpu_to_le16(frag
->size
);
1528 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1530 re
= tx_le_re(sky2
, le
);
1532 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1533 pci_unmap_len_set(re
, maplen
, frag
->size
);
1538 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1539 netif_stop_queue(dev
);
1541 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1543 dev
->trans_start
= jiffies
;
1544 return NETDEV_TX_OK
;
1548 * Free ring elements from starting at tx_cons until "done"
1550 * NB: the hardware will tell us about partial completion of multi-part
1551 * buffers so make sure not to free skb to early.
1553 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1555 struct net_device
*dev
= sky2
->netdev
;
1556 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1559 BUG_ON(done
>= TX_RING_SIZE
);
1561 for (idx
= sky2
->tx_cons
; idx
!= done
;
1562 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1563 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1564 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1566 switch(le
->opcode
& ~HW_OWNER
) {
1569 pci_unmap_single(pdev
,
1570 pci_unmap_addr(re
, mapaddr
),
1571 pci_unmap_len(re
, maplen
),
1575 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1576 pci_unmap_len(re
, maplen
),
1581 if (le
->ctrl
& EOP
) {
1582 if (unlikely(netif_msg_tx_done(sky2
)))
1583 printk(KERN_DEBUG
"%s: tx done %u\n",
1586 sky2
->net_stats
.tx_packets
++;
1587 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1589 dev_kfree_skb_any(re
->skb
);
1590 sky2
->tx_next
= RING_NEXT(idx
, TX_RING_SIZE
);
1594 sky2
->tx_cons
= idx
;
1597 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1598 netif_wake_queue(dev
);
1601 /* Cleanup all untransmitted buffers, assume transmitter not running */
1602 static void sky2_tx_clean(struct net_device
*dev
)
1604 struct sky2_port
*sky2
= netdev_priv(dev
);
1606 netif_tx_lock_bh(dev
);
1607 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1608 netif_tx_unlock_bh(dev
);
1611 /* Network shutdown */
1612 static int sky2_down(struct net_device
*dev
)
1614 struct sky2_port
*sky2
= netdev_priv(dev
);
1615 struct sky2_hw
*hw
= sky2
->hw
;
1616 unsigned port
= sky2
->port
;
1620 /* Never really got started! */
1624 if (netif_msg_ifdown(sky2
))
1625 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1627 /* Stop more packets from being queued */
1628 netif_stop_queue(dev
);
1630 /* Disable port IRQ */
1631 imask
= sky2_read32(hw
, B0_IMSK
);
1632 imask
&= ~portirq_msk
[port
];
1633 sky2_write32(hw
, B0_IMSK
, imask
);
1635 sky2_gmac_reset(hw
, port
);
1637 /* Stop transmitter */
1638 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1639 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1641 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1642 RB_RST_SET
| RB_DIS_OP_MD
);
1644 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1645 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1646 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1648 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1650 /* Workaround shared GMAC reset */
1651 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1652 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1653 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1655 /* Disable Force Sync bit and Enable Alloc bit */
1656 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1657 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1659 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1660 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1661 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1663 /* Reset the PCI FIFO of the async Tx queue */
1664 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1665 BMU_RST_SET
| BMU_FIFO_RST
);
1667 /* Reset the Tx prefetch units */
1668 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1671 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1675 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1676 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1678 sky2_phy_power(hw
, port
, 0);
1680 netif_carrier_off(dev
);
1682 /* turn off LED's */
1683 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1685 synchronize_irq(hw
->pdev
->irq
);
1688 sky2_rx_clean(sky2
);
1690 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1691 sky2
->rx_le
, sky2
->rx_le_map
);
1692 kfree(sky2
->rx_ring
);
1694 pci_free_consistent(hw
->pdev
,
1695 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1696 sky2
->tx_le
, sky2
->tx_le_map
);
1697 kfree(sky2
->tx_ring
);
1702 sky2
->rx_ring
= NULL
;
1703 sky2
->tx_ring
= NULL
;
1708 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1710 if (!sky2_is_copper(hw
))
1713 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1714 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1716 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1717 case PHY_M_PS_SPEED_1000
:
1719 case PHY_M_PS_SPEED_100
:
1726 static void sky2_link_up(struct sky2_port
*sky2
)
1728 struct sky2_hw
*hw
= sky2
->hw
;
1729 unsigned port
= sky2
->port
;
1731 static const char *fc_name
[] = {
1739 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1740 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1741 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1743 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1745 netif_carrier_on(sky2
->netdev
);
1747 /* Turn on link LED */
1748 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1749 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1751 if (hw
->chip_id
== CHIP_ID_YUKON_XL
1752 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
1753 || hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1754 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1755 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1757 switch(sky2
->speed
) {
1759 led
|= PHY_M_LEDC_INIT_CTRL(7);
1763 led
|= PHY_M_LEDC_STA1_CTRL(7);
1767 led
|= PHY_M_LEDC_STA0_CTRL(7);
1771 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1772 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1773 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1776 if (netif_msg_link(sky2
))
1777 printk(KERN_INFO PFX
1778 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1779 sky2
->netdev
->name
, sky2
->speed
,
1780 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1781 fc_name
[sky2
->flow_status
]);
1784 static void sky2_link_down(struct sky2_port
*sky2
)
1786 struct sky2_hw
*hw
= sky2
->hw
;
1787 unsigned port
= sky2
->port
;
1790 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1792 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1793 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1794 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1796 netif_carrier_off(sky2
->netdev
);
1798 /* Turn on link LED */
1799 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1801 if (netif_msg_link(sky2
))
1802 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1804 sky2_phy_init(hw
, port
);
1807 static enum flow_control
sky2_flow(int rx
, int tx
)
1810 return tx
? FC_BOTH
: FC_RX
;
1812 return tx
? FC_TX
: FC_NONE
;
1815 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1817 struct sky2_hw
*hw
= sky2
->hw
;
1818 unsigned port
= sky2
->port
;
1821 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1822 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1823 if (lpa
& PHY_M_AN_RF
) {
1824 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1828 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1829 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1830 sky2
->netdev
->name
);
1834 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1835 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1837 /* Since the pause result bits seem to in different positions on
1838 * different chips. look at registers.
1840 if (!sky2_is_copper(hw
)) {
1841 /* Shift for bits in fiber PHY */
1842 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1843 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1845 if (advert
& ADVERTISE_1000XPAUSE
)
1846 advert
|= ADVERTISE_PAUSE_CAP
;
1847 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1848 advert
|= ADVERTISE_PAUSE_ASYM
;
1849 if (lpa
& LPA_1000XPAUSE
)
1850 lpa
|= LPA_PAUSE_CAP
;
1851 if (lpa
& LPA_1000XPAUSE_ASYM
)
1852 lpa
|= LPA_PAUSE_ASYM
;
1855 sky2
->flow_status
= FC_NONE
;
1856 if (advert
& ADVERTISE_PAUSE_CAP
) {
1857 if (lpa
& LPA_PAUSE_CAP
)
1858 sky2
->flow_status
= FC_BOTH
;
1859 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1860 sky2
->flow_status
= FC_RX
;
1861 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1862 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1863 sky2
->flow_status
= FC_TX
;
1866 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1867 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1868 sky2
->flow_status
= FC_NONE
;
1870 if (sky2
->flow_status
& FC_TX
)
1871 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1873 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1878 /* Interrupt from PHY */
1879 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1881 struct net_device
*dev
= hw
->dev
[port
];
1882 struct sky2_port
*sky2
= netdev_priv(dev
);
1883 u16 istatus
, phystat
;
1885 if (!netif_running(dev
))
1888 spin_lock(&sky2
->phy_lock
);
1889 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1890 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1892 if (netif_msg_intr(sky2
))
1893 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1894 sky2
->netdev
->name
, istatus
, phystat
);
1896 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1897 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1902 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1903 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1905 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1907 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1909 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1910 if (phystat
& PHY_M_PS_LINK_UP
)
1913 sky2_link_down(sky2
);
1916 spin_unlock(&sky2
->phy_lock
);
1919 /* Transmit timeout is only called if we are running, carrier is up
1920 * and tx queue is full (stopped).
1922 static void sky2_tx_timeout(struct net_device
*dev
)
1924 struct sky2_port
*sky2
= netdev_priv(dev
);
1925 struct sky2_hw
*hw
= sky2
->hw
;
1927 if (netif_msg_timer(sky2
))
1928 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1930 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1931 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1932 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1933 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1935 /* can't restart safely under softirq */
1936 schedule_work(&hw
->restart_work
);
1939 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1941 struct sky2_port
*sky2
= netdev_priv(dev
);
1942 struct sky2_hw
*hw
= sky2
->hw
;
1943 unsigned port
= sky2
->port
;
1948 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1951 if (new_mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_FE
)
1954 if (!netif_running(dev
)) {
1959 imask
= sky2_read32(hw
, B0_IMSK
);
1960 sky2_write32(hw
, B0_IMSK
, 0);
1962 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1963 netif_stop_queue(dev
);
1964 netif_poll_disable(hw
->dev
[0]);
1966 synchronize_irq(hw
->pdev
->irq
);
1968 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
)
1969 sky2_set_tx_stfwd(hw
, port
);
1971 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1972 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1974 sky2_rx_clean(sky2
);
1978 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1979 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1981 if (dev
->mtu
> ETH_DATA_LEN
)
1982 mode
|= GM_SMOD_JUMBO_ENA
;
1984 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
1986 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
1988 err
= sky2_rx_start(sky2
);
1989 sky2_write32(hw
, B0_IMSK
, imask
);
1994 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
1996 netif_poll_enable(hw
->dev
[0]);
1997 netif_wake_queue(dev
);
2003 /* For small just reuse existing skb for next receive */
2004 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2005 const struct rx_ring_info
*re
,
2008 struct sk_buff
*skb
;
2010 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2012 skb_reserve(skb
, 2);
2013 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2014 length
, PCI_DMA_FROMDEVICE
);
2015 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2016 skb
->ip_summed
= re
->skb
->ip_summed
;
2017 skb
->csum
= re
->skb
->csum
;
2018 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2019 length
, PCI_DMA_FROMDEVICE
);
2020 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2021 skb_put(skb
, length
);
2026 /* Adjust length of skb with fragments to match received data */
2027 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2028 unsigned int length
)
2033 /* put header into skb */
2034 size
= min(length
, hdr_space
);
2039 num_frags
= skb_shinfo(skb
)->nr_frags
;
2040 for (i
= 0; i
< num_frags
; i
++) {
2041 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2044 /* don't need this page */
2045 __free_page(frag
->page
);
2046 --skb_shinfo(skb
)->nr_frags
;
2048 size
= min(length
, (unsigned) PAGE_SIZE
);
2051 skb
->data_len
+= size
;
2052 skb
->truesize
+= size
;
2059 /* Normal packet - take skb from ring element and put in a new one */
2060 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2061 struct rx_ring_info
*re
,
2062 unsigned int length
)
2064 struct sk_buff
*skb
, *nskb
;
2065 unsigned hdr_space
= sky2
->rx_data_size
;
2067 /* Don't be tricky about reusing pages (yet) */
2068 nskb
= sky2_rx_alloc(sky2
);
2069 if (unlikely(!nskb
))
2073 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2075 prefetch(skb
->data
);
2077 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2079 if (skb_shinfo(skb
)->nr_frags
)
2080 skb_put_frags(skb
, hdr_space
, length
);
2082 skb_put(skb
, length
);
2087 * Receive one packet.
2088 * For larger packets, get new buffer.
2090 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2091 u16 length
, u32 status
)
2093 struct sky2_port
*sky2
= netdev_priv(dev
);
2094 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2095 struct sk_buff
*skb
= NULL
;
2097 if (unlikely(netif_msg_rx_status(sky2
)))
2098 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2099 dev
->name
, sky2
->rx_next
, status
, length
);
2101 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2102 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2104 if (status
& GMR_FS_ANY_ERR
)
2107 if (!(status
& GMR_FS_RX_OK
))
2110 if (status
>> 16 != length
)
2113 if (length
< copybreak
)
2114 skb
= receive_copy(sky2
, re
, length
);
2116 skb
= receive_new(sky2
, re
, length
);
2118 sky2_rx_submit(sky2
, re
);
2123 /* Truncation of overlength packets
2124 causes PHY length to not match MAC length */
2125 ++sky2
->net_stats
.rx_length_errors
;
2128 ++sky2
->net_stats
.rx_errors
;
2129 if (status
& GMR_FS_RX_FF_OV
) {
2130 sky2
->net_stats
.rx_over_errors
++;
2134 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2135 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2136 dev
->name
, status
, length
);
2138 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2139 sky2
->net_stats
.rx_length_errors
++;
2140 if (status
& GMR_FS_FRAGMENT
)
2141 sky2
->net_stats
.rx_frame_errors
++;
2142 if (status
& GMR_FS_CRC_ERR
)
2143 sky2
->net_stats
.rx_crc_errors
++;
2148 /* Transmit complete */
2149 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2151 struct sky2_port
*sky2
= netdev_priv(dev
);
2153 if (netif_running(dev
)) {
2155 sky2_tx_complete(sky2
, last
);
2156 netif_tx_unlock(dev
);
2160 /* Process status response ring */
2161 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2164 unsigned rx
[2] = { 0, 0 };
2165 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2169 while (hw
->st_idx
!= hwidx
) {
2170 struct sky2_port
*sky2
;
2171 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2172 unsigned port
= le
->css
& CSS_LINK_BIT
;
2173 struct net_device
*dev
;
2174 struct sk_buff
*skb
;
2178 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2180 dev
= hw
->dev
[port
];
2181 sky2
= netdev_priv(dev
);
2182 length
= le16_to_cpu(le
->length
);
2183 status
= le32_to_cpu(le
->status
);
2185 switch (le
->opcode
& ~HW_OWNER
) {
2188 skb
= sky2_receive(dev
, length
, status
);
2189 if (unlikely(!skb
)) {
2190 sky2
->net_stats
.rx_dropped
++;
2194 /* This chip reports checksum status differently */
2195 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2196 if (sky2
->rx_csum
&&
2197 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2198 (le
->css
& CSS_TCPUDPCSOK
))
2199 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2201 skb
->ip_summed
= CHECKSUM_NONE
;
2204 skb
->protocol
= eth_type_trans(skb
, dev
);
2205 sky2
->net_stats
.rx_packets
++;
2206 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2207 dev
->last_rx
= jiffies
;
2209 #ifdef SKY2_VLAN_TAG_USED
2210 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2211 vlan_hwaccel_receive_skb(skb
,
2213 be16_to_cpu(sky2
->rx_tag
));
2216 netif_receive_skb(skb
);
2218 /* Stop after net poll weight */
2219 if (++work_done
>= to_do
)
2223 #ifdef SKY2_VLAN_TAG_USED
2225 sky2
->rx_tag
= length
;
2229 sky2
->rx_tag
= length
;
2236 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2239 /* Both checksum counters are programmed to start at
2240 * the same offset, so unless there is a problem they
2241 * should match. This failure is an early indication that
2242 * hardware receive checksumming won't work.
2244 if (likely(status
>> 16 == (status
& 0xffff))) {
2245 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2246 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2247 skb
->csum
= status
& 0xffff;
2249 printk(KERN_NOTICE PFX
"%s: hardware receive "
2250 "checksum problem (status = %#x)\n",
2253 sky2_write32(sky2
->hw
,
2254 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2260 /* TX index reports status for both ports */
2261 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2262 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2264 sky2_tx_done(hw
->dev
[1],
2265 ((status
>> 24) & 0xff)
2266 | (u16
)(length
& 0xf) << 8);
2270 if (net_ratelimit())
2271 printk(KERN_WARNING PFX
2272 "unknown status opcode 0x%x\n", le
->opcode
);
2276 /* Fully processed status ring so clear irq */
2277 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2281 sky2_rx_update(netdev_priv(hw
->dev
[0]), Q_R1
);
2284 sky2_rx_update(netdev_priv(hw
->dev
[1]), Q_R2
);
2289 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2291 struct net_device
*dev
= hw
->dev
[port
];
2293 if (net_ratelimit())
2294 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2297 if (status
& Y2_IS_PAR_RD1
) {
2298 if (net_ratelimit())
2299 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2302 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2305 if (status
& Y2_IS_PAR_WR1
) {
2306 if (net_ratelimit())
2307 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2310 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2313 if (status
& Y2_IS_PAR_MAC1
) {
2314 if (net_ratelimit())
2315 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2316 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2319 if (status
& Y2_IS_PAR_RX1
) {
2320 if (net_ratelimit())
2321 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2322 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2325 if (status
& Y2_IS_TCP_TXA1
) {
2326 if (net_ratelimit())
2327 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2329 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2333 static void sky2_hw_intr(struct sky2_hw
*hw
)
2335 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2337 if (status
& Y2_IS_TIST_OV
)
2338 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2340 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2343 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2344 if (net_ratelimit())
2345 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2348 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2349 sky2_pci_write16(hw
, PCI_STATUS
,
2350 pci_err
| PCI_STATUS_ERROR_BITS
);
2351 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2354 if (status
& Y2_IS_PCI_EXP
) {
2355 /* PCI-Express uncorrectable Error occurred */
2358 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2360 if (net_ratelimit())
2361 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2364 /* clear the interrupt */
2365 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2366 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2368 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2370 if (pex_err
& PEX_FATAL_ERRORS
) {
2371 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2372 hwmsk
&= ~Y2_IS_PCI_EXP
;
2373 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2377 if (status
& Y2_HWE_L1_MASK
)
2378 sky2_hw_error(hw
, 0, status
);
2380 if (status
& Y2_HWE_L1_MASK
)
2381 sky2_hw_error(hw
, 1, status
);
2384 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2386 struct net_device
*dev
= hw
->dev
[port
];
2387 struct sky2_port
*sky2
= netdev_priv(dev
);
2388 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2390 if (netif_msg_intr(sky2
))
2391 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2394 if (status
& GM_IS_RX_CO_OV
)
2395 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2397 if (status
& GM_IS_TX_CO_OV
)
2398 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2400 if (status
& GM_IS_RX_FF_OR
) {
2401 ++sky2
->net_stats
.rx_fifo_errors
;
2402 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2405 if (status
& GM_IS_TX_FF_UR
) {
2406 ++sky2
->net_stats
.tx_fifo_errors
;
2407 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2411 /* This should never happen it is a bug. */
2412 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2413 u16 q
, unsigned ring_size
)
2415 struct net_device
*dev
= hw
->dev
[port
];
2416 struct sky2_port
*sky2
= netdev_priv(dev
);
2418 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2419 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2421 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2422 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2423 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2424 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2426 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2429 /* If idle then force a fake soft NAPI poll once a second
2430 * to work around cases where sharing an edge triggered interrupt.
2432 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2434 if (idle_timeout
> 0)
2435 mod_timer(&hw
->idle_timer
,
2436 jiffies
+ msecs_to_jiffies(idle_timeout
));
2439 static void sky2_idle(unsigned long arg
)
2441 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2442 struct net_device
*dev
= hw
->dev
[0];
2444 if (__netif_rx_schedule_prep(dev
))
2445 __netif_rx_schedule(dev
);
2447 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2450 /* Hardware/software error handling */
2451 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2453 if (net_ratelimit())
2454 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2456 if (status
& Y2_IS_HW_ERR
)
2459 if (status
& Y2_IS_IRQ_MAC1
)
2460 sky2_mac_intr(hw
, 0);
2462 if (status
& Y2_IS_IRQ_MAC2
)
2463 sky2_mac_intr(hw
, 1);
2465 if (status
& Y2_IS_CHK_RX1
)
2466 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2468 if (status
& Y2_IS_CHK_RX2
)
2469 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2471 if (status
& Y2_IS_CHK_TXA1
)
2472 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2474 if (status
& Y2_IS_CHK_TXA2
)
2475 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2478 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2480 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2482 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2484 if (unlikely(status
& Y2_IS_ERROR
))
2485 sky2_err_intr(hw
, status
);
2487 if (status
& Y2_IS_IRQ_PHY1
)
2488 sky2_phy_intr(hw
, 0);
2490 if (status
& Y2_IS_IRQ_PHY2
)
2491 sky2_phy_intr(hw
, 1);
2493 work_done
= sky2_status_intr(hw
, min(dev0
->quota
, *budget
));
2494 *budget
-= work_done
;
2495 dev0
->quota
-= work_done
;
2498 if (hw
->st_idx
!= sky2_read16(hw
, STAT_PUT_IDX
))
2501 /* Bug/Errata workaround?
2502 * Need to kick the TX irq moderation timer.
2504 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_START
) {
2505 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2506 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2508 netif_rx_complete(dev0
);
2510 sky2_read32(hw
, B0_Y2_SP_LISR
);
2514 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2516 struct sky2_hw
*hw
= dev_id
;
2517 struct net_device
*dev0
= hw
->dev
[0];
2520 /* Reading this mask interrupts as side effect */
2521 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2522 if (status
== 0 || status
== ~0)
2525 prefetch(&hw
->st_le
[hw
->st_idx
]);
2526 if (likely(__netif_rx_schedule_prep(dev0
)))
2527 __netif_rx_schedule(dev0
);
2532 #ifdef CONFIG_NET_POLL_CONTROLLER
2533 static void sky2_netpoll(struct net_device
*dev
)
2535 struct sky2_port
*sky2
= netdev_priv(dev
);
2536 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2538 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2539 __netif_rx_schedule(dev0
);
2543 /* Chip internal frequency for clock calculations */
2544 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2546 switch (hw
->chip_id
) {
2547 case CHIP_ID_YUKON_EC
:
2548 case CHIP_ID_YUKON_EC_U
:
2549 case CHIP_ID_YUKON_EX
:
2550 return 125; /* 125 Mhz */
2551 case CHIP_ID_YUKON_FE
:
2552 return 100; /* 100 Mhz */
2553 default: /* YUKON_XL */
2554 return 156; /* 156 Mhz */
2558 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2560 return sky2_mhz(hw
) * us
;
2563 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2565 return clk
/ sky2_mhz(hw
);
2569 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2573 /* Enable all clocks */
2574 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2576 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2578 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2579 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2580 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2585 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2587 /* This rev is really old, and requires untested workarounds */
2588 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2589 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2590 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2591 hw
->chip_id
, hw
->chip_rev
);
2595 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2597 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2598 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2599 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2606 static void sky2_reset(struct sky2_hw
*hw
)
2612 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2613 status
= sky2_read16(hw
, HCU_CCSR
);
2614 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2615 HCU_CCSR_UC_STATE_MSK
);
2616 sky2_write16(hw
, HCU_CCSR
, status
);
2618 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2619 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2622 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2623 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2625 /* clear PCI errors, if any */
2626 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2628 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2629 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2632 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2634 /* clear any PEX errors */
2635 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2636 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2641 for (i
= 0; i
< hw
->ports
; i
++) {
2642 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2643 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2645 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2646 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
2647 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
2651 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2653 /* Clear I2C IRQ noise */
2654 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2656 /* turn off hardware timer (unused) */
2657 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2658 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2660 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2662 /* Turn off descriptor polling */
2663 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2665 /* Turn off receive timestamp */
2666 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2667 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2669 /* enable the Tx Arbiters */
2670 for (i
= 0; i
< hw
->ports
; i
++)
2671 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2673 /* Initialize ram interface */
2674 for (i
= 0; i
< hw
->ports
; i
++) {
2675 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2677 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2678 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2679 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2680 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2681 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2682 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2683 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2684 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2685 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2686 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2687 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2688 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2691 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2693 for (i
= 0; i
< hw
->ports
; i
++)
2694 sky2_gmac_reset(hw
, i
);
2696 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2699 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2700 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2702 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2703 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2705 /* Set the list last index */
2706 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2708 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2709 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2711 /* set Status-FIFO ISR watermark */
2712 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2713 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2715 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2717 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2718 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2719 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2721 /* enable status unit */
2722 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2724 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2725 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2726 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2729 static void sky2_restart(struct work_struct
*work
)
2731 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2732 struct net_device
*dev
;
2735 del_timer_sync(&hw
->idle_timer
);
2738 sky2_write32(hw
, B0_IMSK
, 0);
2739 sky2_read32(hw
, B0_IMSK
);
2741 netif_poll_disable(hw
->dev
[0]);
2743 for (i
= 0; i
< hw
->ports
; i
++) {
2745 if (netif_running(dev
))
2750 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2751 netif_poll_enable(hw
->dev
[0]);
2753 for (i
= 0; i
< hw
->ports
; i
++) {
2755 if (netif_running(dev
)) {
2758 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2765 sky2_idle_start(hw
);
2770 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2772 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2775 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2777 const struct sky2_port
*sky2
= netdev_priv(dev
);
2779 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2780 wol
->wolopts
= sky2
->wol
;
2783 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2785 struct sky2_port
*sky2
= netdev_priv(dev
);
2786 struct sky2_hw
*hw
= sky2
->hw
;
2788 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2791 sky2
->wol
= wol
->wolopts
;
2793 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
)
2794 sky2_write32(hw
, B0_CTST
, sky2
->wol
2795 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2797 if (!netif_running(dev
))
2798 sky2_wol_init(sky2
);
2802 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2804 if (sky2_is_copper(hw
)) {
2805 u32 modes
= SUPPORTED_10baseT_Half
2806 | SUPPORTED_10baseT_Full
2807 | SUPPORTED_100baseT_Half
2808 | SUPPORTED_100baseT_Full
2809 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2811 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2812 modes
|= SUPPORTED_1000baseT_Half
2813 | SUPPORTED_1000baseT_Full
;
2816 return SUPPORTED_1000baseT_Half
2817 | SUPPORTED_1000baseT_Full
2822 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2824 struct sky2_port
*sky2
= netdev_priv(dev
);
2825 struct sky2_hw
*hw
= sky2
->hw
;
2827 ecmd
->transceiver
= XCVR_INTERNAL
;
2828 ecmd
->supported
= sky2_supported_modes(hw
);
2829 ecmd
->phy_address
= PHY_ADDR_MARV
;
2830 if (sky2_is_copper(hw
)) {
2831 ecmd
->supported
= SUPPORTED_10baseT_Half
2832 | SUPPORTED_10baseT_Full
2833 | SUPPORTED_100baseT_Half
2834 | SUPPORTED_100baseT_Full
2835 | SUPPORTED_1000baseT_Half
2836 | SUPPORTED_1000baseT_Full
2837 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2838 ecmd
->port
= PORT_TP
;
2839 ecmd
->speed
= sky2
->speed
;
2841 ecmd
->speed
= SPEED_1000
;
2842 ecmd
->port
= PORT_FIBRE
;
2845 ecmd
->advertising
= sky2
->advertising
;
2846 ecmd
->autoneg
= sky2
->autoneg
;
2847 ecmd
->duplex
= sky2
->duplex
;
2851 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2853 struct sky2_port
*sky2
= netdev_priv(dev
);
2854 const struct sky2_hw
*hw
= sky2
->hw
;
2855 u32 supported
= sky2_supported_modes(hw
);
2857 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2858 ecmd
->advertising
= supported
;
2864 switch (ecmd
->speed
) {
2866 if (ecmd
->duplex
== DUPLEX_FULL
)
2867 setting
= SUPPORTED_1000baseT_Full
;
2868 else if (ecmd
->duplex
== DUPLEX_HALF
)
2869 setting
= SUPPORTED_1000baseT_Half
;
2874 if (ecmd
->duplex
== DUPLEX_FULL
)
2875 setting
= SUPPORTED_100baseT_Full
;
2876 else if (ecmd
->duplex
== DUPLEX_HALF
)
2877 setting
= SUPPORTED_100baseT_Half
;
2883 if (ecmd
->duplex
== DUPLEX_FULL
)
2884 setting
= SUPPORTED_10baseT_Full
;
2885 else if (ecmd
->duplex
== DUPLEX_HALF
)
2886 setting
= SUPPORTED_10baseT_Half
;
2894 if ((setting
& supported
) == 0)
2897 sky2
->speed
= ecmd
->speed
;
2898 sky2
->duplex
= ecmd
->duplex
;
2901 sky2
->autoneg
= ecmd
->autoneg
;
2902 sky2
->advertising
= ecmd
->advertising
;
2904 if (netif_running(dev
))
2905 sky2_phy_reinit(sky2
);
2910 static void sky2_get_drvinfo(struct net_device
*dev
,
2911 struct ethtool_drvinfo
*info
)
2913 struct sky2_port
*sky2
= netdev_priv(dev
);
2915 strcpy(info
->driver
, DRV_NAME
);
2916 strcpy(info
->version
, DRV_VERSION
);
2917 strcpy(info
->fw_version
, "N/A");
2918 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2921 static const struct sky2_stat
{
2922 char name
[ETH_GSTRING_LEN
];
2925 { "tx_bytes", GM_TXO_OK_HI
},
2926 { "rx_bytes", GM_RXO_OK_HI
},
2927 { "tx_broadcast", GM_TXF_BC_OK
},
2928 { "rx_broadcast", GM_RXF_BC_OK
},
2929 { "tx_multicast", GM_TXF_MC_OK
},
2930 { "rx_multicast", GM_RXF_MC_OK
},
2931 { "tx_unicast", GM_TXF_UC_OK
},
2932 { "rx_unicast", GM_RXF_UC_OK
},
2933 { "tx_mac_pause", GM_TXF_MPAUSE
},
2934 { "rx_mac_pause", GM_RXF_MPAUSE
},
2935 { "collisions", GM_TXF_COL
},
2936 { "late_collision",GM_TXF_LAT_COL
},
2937 { "aborted", GM_TXF_ABO_COL
},
2938 { "single_collisions", GM_TXF_SNG_COL
},
2939 { "multi_collisions", GM_TXF_MUL_COL
},
2941 { "rx_short", GM_RXF_SHT
},
2942 { "rx_runt", GM_RXE_FRAG
},
2943 { "rx_64_byte_packets", GM_RXF_64B
},
2944 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2945 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2946 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2947 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2948 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2949 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2950 { "rx_too_long", GM_RXF_LNG_ERR
},
2951 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2952 { "rx_jabber", GM_RXF_JAB_PKT
},
2953 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2955 { "tx_64_byte_packets", GM_TXF_64B
},
2956 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2957 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2958 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2959 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2960 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2961 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2962 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2965 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2967 struct sky2_port
*sky2
= netdev_priv(dev
);
2969 return sky2
->rx_csum
;
2972 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2974 struct sky2_port
*sky2
= netdev_priv(dev
);
2976 sky2
->rx_csum
= data
;
2978 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2979 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2984 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2986 struct sky2_port
*sky2
= netdev_priv(netdev
);
2987 return sky2
->msg_enable
;
2990 static int sky2_nway_reset(struct net_device
*dev
)
2992 struct sky2_port
*sky2
= netdev_priv(dev
);
2994 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2997 sky2_phy_reinit(sky2
);
3002 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3004 struct sky2_hw
*hw
= sky2
->hw
;
3005 unsigned port
= sky2
->port
;
3008 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3009 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3010 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3011 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3013 for (i
= 2; i
< count
; i
++)
3014 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3017 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3019 struct sky2_port
*sky2
= netdev_priv(netdev
);
3020 sky2
->msg_enable
= value
;
3023 static int sky2_get_stats_count(struct net_device
*dev
)
3025 return ARRAY_SIZE(sky2_stats
);
3028 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3029 struct ethtool_stats
*stats
, u64
* data
)
3031 struct sky2_port
*sky2
= netdev_priv(dev
);
3033 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3036 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3040 switch (stringset
) {
3042 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3043 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3044 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3049 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
3051 struct sky2_port
*sky2
= netdev_priv(dev
);
3052 return &sky2
->net_stats
;
3055 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3057 struct sky2_port
*sky2
= netdev_priv(dev
);
3058 struct sky2_hw
*hw
= sky2
->hw
;
3059 unsigned port
= sky2
->port
;
3060 const struct sockaddr
*addr
= p
;
3062 if (!is_valid_ether_addr(addr
->sa_data
))
3063 return -EADDRNOTAVAIL
;
3065 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3066 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3067 dev
->dev_addr
, ETH_ALEN
);
3068 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3069 dev
->dev_addr
, ETH_ALEN
);
3071 /* virtual address for data */
3072 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3074 /* physical address: used for pause frames */
3075 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3080 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3084 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3085 filter
[bit
>> 3] |= 1 << (bit
& 7);
3088 static void sky2_set_multicast(struct net_device
*dev
)
3090 struct sky2_port
*sky2
= netdev_priv(dev
);
3091 struct sky2_hw
*hw
= sky2
->hw
;
3092 unsigned port
= sky2
->port
;
3093 struct dev_mc_list
*list
= dev
->mc_list
;
3097 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3099 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3100 memset(filter
, 0, sizeof(filter
));
3102 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3103 reg
|= GM_RXCR_UCF_ENA
;
3105 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3106 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3107 else if (dev
->flags
& IFF_ALLMULTI
)
3108 memset(filter
, 0xff, sizeof(filter
));
3109 else if (dev
->mc_count
== 0 && !rx_pause
)
3110 reg
&= ~GM_RXCR_MCF_ENA
;
3113 reg
|= GM_RXCR_MCF_ENA
;
3116 sky2_add_filter(filter
, pause_mc_addr
);
3118 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3119 sky2_add_filter(filter
, list
->dmi_addr
);
3122 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3123 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3124 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3125 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3126 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3127 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3128 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3129 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3131 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3134 /* Can have one global because blinking is controlled by
3135 * ethtool and that is always under RTNL mutex
3137 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3141 switch (hw
->chip_id
) {
3142 case CHIP_ID_YUKON_XL
:
3143 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3144 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3145 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3146 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3147 PHY_M_LEDC_INIT_CTRL(7) |
3148 PHY_M_LEDC_STA1_CTRL(7) |
3149 PHY_M_LEDC_STA0_CTRL(7))
3152 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3156 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3157 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3158 on
? PHY_M_LED_ALL
: 0);
3162 /* blink LED's for finding board */
3163 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3165 struct sky2_port
*sky2
= netdev_priv(dev
);
3166 struct sky2_hw
*hw
= sky2
->hw
;
3167 unsigned port
= sky2
->port
;
3168 u16 ledctrl
, ledover
= 0;
3173 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3174 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3178 /* save initial values */
3179 spin_lock_bh(&sky2
->phy_lock
);
3180 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3181 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3182 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3183 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3184 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3186 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3187 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3191 while (!interrupted
&& ms
> 0) {
3192 sky2_led(hw
, port
, onoff
);
3195 spin_unlock_bh(&sky2
->phy_lock
);
3196 interrupted
= msleep_interruptible(250);
3197 spin_lock_bh(&sky2
->phy_lock
);
3202 /* resume regularly scheduled programming */
3203 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3204 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3205 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3206 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3207 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3209 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3210 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3212 spin_unlock_bh(&sky2
->phy_lock
);
3217 static void sky2_get_pauseparam(struct net_device
*dev
,
3218 struct ethtool_pauseparam
*ecmd
)
3220 struct sky2_port
*sky2
= netdev_priv(dev
);
3222 switch (sky2
->flow_mode
) {
3224 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3227 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3230 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3233 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3236 ecmd
->autoneg
= sky2
->autoneg
;
3239 static int sky2_set_pauseparam(struct net_device
*dev
,
3240 struct ethtool_pauseparam
*ecmd
)
3242 struct sky2_port
*sky2
= netdev_priv(dev
);
3244 sky2
->autoneg
= ecmd
->autoneg
;
3245 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3247 if (netif_running(dev
))
3248 sky2_phy_reinit(sky2
);
3253 static int sky2_get_coalesce(struct net_device
*dev
,
3254 struct ethtool_coalesce
*ecmd
)
3256 struct sky2_port
*sky2
= netdev_priv(dev
);
3257 struct sky2_hw
*hw
= sky2
->hw
;
3259 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3260 ecmd
->tx_coalesce_usecs
= 0;
3262 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3263 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3265 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3267 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3268 ecmd
->rx_coalesce_usecs
= 0;
3270 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3271 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3273 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3275 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3276 ecmd
->rx_coalesce_usecs_irq
= 0;
3278 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3279 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3282 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3287 /* Note: this affect both ports */
3288 static int sky2_set_coalesce(struct net_device
*dev
,
3289 struct ethtool_coalesce
*ecmd
)
3291 struct sky2_port
*sky2
= netdev_priv(dev
);
3292 struct sky2_hw
*hw
= sky2
->hw
;
3293 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3295 if (ecmd
->tx_coalesce_usecs
> tmax
||
3296 ecmd
->rx_coalesce_usecs
> tmax
||
3297 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3300 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3302 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3304 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3307 if (ecmd
->tx_coalesce_usecs
== 0)
3308 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3310 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3311 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3312 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3314 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3316 if (ecmd
->rx_coalesce_usecs
== 0)
3317 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3319 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3320 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3321 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3323 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3325 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3326 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3328 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3329 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3330 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3332 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3336 static void sky2_get_ringparam(struct net_device
*dev
,
3337 struct ethtool_ringparam
*ering
)
3339 struct sky2_port
*sky2
= netdev_priv(dev
);
3341 ering
->rx_max_pending
= RX_MAX_PENDING
;
3342 ering
->rx_mini_max_pending
= 0;
3343 ering
->rx_jumbo_max_pending
= 0;
3344 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3346 ering
->rx_pending
= sky2
->rx_pending
;
3347 ering
->rx_mini_pending
= 0;
3348 ering
->rx_jumbo_pending
= 0;
3349 ering
->tx_pending
= sky2
->tx_pending
;
3352 static int sky2_set_ringparam(struct net_device
*dev
,
3353 struct ethtool_ringparam
*ering
)
3355 struct sky2_port
*sky2
= netdev_priv(dev
);
3358 if (ering
->rx_pending
> RX_MAX_PENDING
||
3359 ering
->rx_pending
< 8 ||
3360 ering
->tx_pending
< MAX_SKB_TX_LE
||
3361 ering
->tx_pending
> TX_RING_SIZE
- 1)
3364 if (netif_running(dev
))
3367 sky2
->rx_pending
= ering
->rx_pending
;
3368 sky2
->tx_pending
= ering
->tx_pending
;
3370 if (netif_running(dev
)) {
3375 sky2_set_multicast(dev
);
3381 static int sky2_get_regs_len(struct net_device
*dev
)
3387 * Returns copy of control register region
3388 * Note: ethtool_get_regs always provides full size (16k) buffer
3390 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3393 const struct sky2_port
*sky2
= netdev_priv(dev
);
3394 const void __iomem
*io
= sky2
->hw
->regs
;
3397 memset(p
, 0, regs
->len
);
3399 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3401 /* skip diagnostic ram region */
3402 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
, 0x2000 - B3_RI_WTO_R1
);
3404 /* copy GMAC registers */
3405 memcpy_fromio(p
+ BASE_GMAC_1
, io
+ BASE_GMAC_1
, 0x1000);
3406 if (sky2
->hw
->ports
> 1)
3407 memcpy_fromio(p
+ BASE_GMAC_2
, io
+ BASE_GMAC_2
, 0x1000);
3411 /* In order to do Jumbo packets on these chips, need to turn off the
3412 * transmit store/forward. Therefore checksum offload won't work.
3414 static int no_tx_offload(struct net_device
*dev
)
3416 const struct sky2_port
*sky2
= netdev_priv(dev
);
3417 const struct sky2_hw
*hw
= sky2
->hw
;
3419 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3422 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3424 if (data
&& no_tx_offload(dev
))
3427 return ethtool_op_set_tx_csum(dev
, data
);
3431 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3433 if (data
&& no_tx_offload(dev
))
3436 return ethtool_op_set_tso(dev
, data
);
3439 static int sky2_get_eeprom_len(struct net_device
*dev
)
3441 struct sky2_port
*sky2
= netdev_priv(dev
);
3444 reg2
= sky2_pci_read32(sky2
->hw
, PCI_DEV_REG2
);
3445 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3448 static u32
sky2_vpd_read(struct sky2_hw
*hw
, int cap
, u16 offset
)
3450 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3452 while (!(sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
))
3454 return sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3457 static void sky2_vpd_write(struct sky2_hw
*hw
, int cap
, u16 offset
, u32 val
)
3459 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
3460 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3463 } while (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
);
3466 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3469 struct sky2_port
*sky2
= netdev_priv(dev
);
3470 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3471 int length
= eeprom
->len
;
3472 u16 offset
= eeprom
->offset
;
3477 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3479 while (length
> 0) {
3480 u32 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3481 int n
= min_t(int, length
, sizeof(val
));
3483 memcpy(data
, &val
, n
);
3491 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3494 struct sky2_port
*sky2
= netdev_priv(dev
);
3495 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3496 int length
= eeprom
->len
;
3497 u16 offset
= eeprom
->offset
;
3502 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3505 while (length
> 0) {
3507 int n
= min_t(int, length
, sizeof(val
));
3509 if (n
< sizeof(val
))
3510 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3511 memcpy(&val
, data
, n
);
3513 sky2_vpd_write(sky2
->hw
, cap
, offset
, val
);
3523 static const struct ethtool_ops sky2_ethtool_ops
= {
3524 .get_settings
= sky2_get_settings
,
3525 .set_settings
= sky2_set_settings
,
3526 .get_drvinfo
= sky2_get_drvinfo
,
3527 .get_wol
= sky2_get_wol
,
3528 .set_wol
= sky2_set_wol
,
3529 .get_msglevel
= sky2_get_msglevel
,
3530 .set_msglevel
= sky2_set_msglevel
,
3531 .nway_reset
= sky2_nway_reset
,
3532 .get_regs_len
= sky2_get_regs_len
,
3533 .get_regs
= sky2_get_regs
,
3534 .get_link
= ethtool_op_get_link
,
3535 .get_eeprom_len
= sky2_get_eeprom_len
,
3536 .get_eeprom
= sky2_get_eeprom
,
3537 .set_eeprom
= sky2_set_eeprom
,
3538 .get_sg
= ethtool_op_get_sg
,
3539 .set_sg
= ethtool_op_set_sg
,
3540 .get_tx_csum
= ethtool_op_get_tx_csum
,
3541 .set_tx_csum
= sky2_set_tx_csum
,
3542 .get_tso
= ethtool_op_get_tso
,
3543 .set_tso
= sky2_set_tso
,
3544 .get_rx_csum
= sky2_get_rx_csum
,
3545 .set_rx_csum
= sky2_set_rx_csum
,
3546 .get_strings
= sky2_get_strings
,
3547 .get_coalesce
= sky2_get_coalesce
,
3548 .set_coalesce
= sky2_set_coalesce
,
3549 .get_ringparam
= sky2_get_ringparam
,
3550 .set_ringparam
= sky2_set_ringparam
,
3551 .get_pauseparam
= sky2_get_pauseparam
,
3552 .set_pauseparam
= sky2_set_pauseparam
,
3553 .phys_id
= sky2_phys_id
,
3554 .get_stats_count
= sky2_get_stats_count
,
3555 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3558 #ifdef CONFIG_SKY2_DEBUG
3560 static struct dentry
*sky2_debug
;
3562 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
3564 struct net_device
*dev
= seq
->private;
3565 const struct sky2_port
*sky2
= netdev_priv(dev
);
3566 const struct sky2_hw
*hw
= sky2
->hw
;
3567 unsigned port
= sky2
->port
;
3571 if (!netif_running(dev
))
3574 seq_printf(seq
, "IRQ src=%x mask=%x control=%x\n",
3575 sky2_read32(hw
, B0_ISRC
),
3576 sky2_read32(hw
, B0_IMSK
),
3577 sky2_read32(hw
, B0_Y2_SP_ICR
));
3579 netif_poll_disable(hw
->dev
[0]);
3580 last
= sky2_read16(hw
, STAT_PUT_IDX
);
3582 if (hw
->st_idx
== last
)
3583 seq_puts(seq
, "Status ring (empty)\n");
3585 seq_puts(seq
, "Status ring\n");
3586 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
3587 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
3588 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
3589 seq_printf(seq
, "[%d] %#x %d %#x\n",
3590 idx
, le
->opcode
, le
->length
, le
->status
);
3592 seq_puts(seq
, "\n");
3595 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
3596 sky2
->tx_cons
, sky2
->tx_prod
,
3597 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
3598 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
3600 /* Dump contents of tx ring */
3602 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< TX_RING_SIZE
;
3603 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
3604 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
3605 u32 a
= le32_to_cpu(le
->addr
);
3608 seq_printf(seq
, "%u:", idx
);
3611 switch(le
->opcode
& ~HW_OWNER
) {
3613 seq_printf(seq
, " %#x:", a
);
3616 seq_printf(seq
, " mtu=%d", a
);
3619 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
3622 seq_printf(seq
, " csum=%#x", a
);
3625 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
3628 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
3631 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
3634 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
3635 a
, le16_to_cpu(le
->length
));
3638 if (le
->ctrl
& EOP
) {
3639 seq_putc(seq
, '\n');
3644 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
3645 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
3646 last
= sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
3647 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
3649 netif_poll_enable(hw
->dev
[0]);
3653 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
3655 return single_open(file
, sky2_debug_show
, inode
->i_private
);
3658 static const struct file_operations sky2_debug_fops
= {
3659 .owner
= THIS_MODULE
,
3660 .open
= sky2_debug_open
,
3662 .llseek
= seq_lseek
,
3663 .release
= single_release
,
3667 * Use network device events to create/remove/rename
3668 * debugfs file entries
3670 static int sky2_device_event(struct notifier_block
*unused
,
3671 unsigned long event
, void *ptr
)
3673 struct net_device
*dev
= ptr
;
3675 if (dev
->open
== sky2_up
) {
3676 struct sky2_port
*sky2
= netdev_priv(dev
);
3679 case NETDEV_CHANGENAME
:
3680 if (!netif_running(dev
))
3684 case NETDEV_GOING_DOWN
:
3685 if (sky2
->debugfs
) {
3686 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
3688 debugfs_remove(sky2
->debugfs
);
3689 sky2
->debugfs
= NULL
;
3692 if (event
!= NETDEV_CHANGENAME
)
3694 /* fallthrough for changename */
3698 d
= debugfs_create_file(dev
->name
, S_IRUGO
,
3701 if (d
== NULL
|| IS_ERR(d
))
3702 printk(KERN_INFO PFX
3703 "%s: debugfs create failed\n",
3715 static struct notifier_block sky2_notifier
= {
3716 .notifier_call
= sky2_device_event
,
3720 static __init
void sky2_debug_init(void)
3724 ent
= debugfs_create_dir("sky2", NULL
);
3725 if (!ent
|| IS_ERR(ent
))
3729 register_netdevice_notifier(&sky2_notifier
);
3732 static __exit
void sky2_debug_cleanup(void)
3735 unregister_netdevice_notifier(&sky2_notifier
);
3736 debugfs_remove(sky2_debug
);
3742 #define sky2_debug_init()
3743 #define sky2_debug_cleanup()
3747 /* Initialize network device */
3748 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3750 int highmem
, int wol
)
3752 struct sky2_port
*sky2
;
3753 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3756 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3760 SET_MODULE_OWNER(dev
);
3761 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3762 dev
->irq
= hw
->pdev
->irq
;
3763 dev
->open
= sky2_up
;
3764 dev
->stop
= sky2_down
;
3765 dev
->do_ioctl
= sky2_ioctl
;
3766 dev
->hard_start_xmit
= sky2_xmit_frame
;
3767 dev
->get_stats
= sky2_get_stats
;
3768 dev
->set_multicast_list
= sky2_set_multicast
;
3769 dev
->set_mac_address
= sky2_set_mac_address
;
3770 dev
->change_mtu
= sky2_change_mtu
;
3771 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3772 dev
->tx_timeout
= sky2_tx_timeout
;
3773 dev
->watchdog_timeo
= TX_WATCHDOG
;
3775 dev
->poll
= sky2_poll
;
3776 dev
->weight
= NAPI_WEIGHT
;
3777 #ifdef CONFIG_NET_POLL_CONTROLLER
3778 /* Network console (only works on port 0)
3779 * because netpoll makes assumptions about NAPI
3782 dev
->poll_controller
= sky2_netpoll
;
3785 sky2
= netdev_priv(dev
);
3788 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3790 /* Auto speed and flow control */
3791 sky2
->autoneg
= AUTONEG_ENABLE
;
3792 sky2
->flow_mode
= FC_BOTH
;
3796 sky2
->advertising
= sky2_supported_modes(hw
);
3800 spin_lock_init(&sky2
->phy_lock
);
3801 sky2
->tx_pending
= TX_DEF_PENDING
;
3802 sky2
->rx_pending
= RX_DEF_PENDING
;
3804 hw
->dev
[port
] = dev
;
3808 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3810 dev
->features
|= NETIF_F_HIGHDMA
;
3812 #ifdef SKY2_VLAN_TAG_USED
3813 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3814 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3817 /* read the mac address */
3818 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3819 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3824 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3826 const struct sky2_port
*sky2
= netdev_priv(dev
);
3828 if (netif_msg_probe(sky2
))
3829 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3831 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3832 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3835 /* Handle software interrupt used during MSI test */
3836 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3838 struct sky2_hw
*hw
= dev_id
;
3839 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3844 if (status
& Y2_IS_IRQ_SW
) {
3846 wake_up(&hw
->msi_wait
);
3847 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3849 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3854 /* Test interrupt path by forcing a a software IRQ */
3855 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3857 struct pci_dev
*pdev
= hw
->pdev
;
3860 init_waitqueue_head (&hw
->msi_wait
);
3862 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3864 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3866 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3870 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3871 sky2_read8(hw
, B0_CTST
);
3873 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3876 /* MSI test failed, go back to INTx mode */
3877 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
3878 "switching to INTx mode.\n");
3881 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3884 sky2_write32(hw
, B0_IMSK
, 0);
3885 sky2_read32(hw
, B0_IMSK
);
3887 free_irq(pdev
->irq
, hw
);
3892 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3894 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3899 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3901 return value
& PCI_PM_CTRL_PME_ENABLE
;
3904 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3905 const struct pci_device_id
*ent
)
3907 struct net_device
*dev
;
3909 int err
, using_dac
= 0, wol_default
;
3911 err
= pci_enable_device(pdev
);
3913 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3917 err
= pci_request_regions(pdev
, DRV_NAME
);
3919 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3920 goto err_out_disable
;
3923 pci_set_master(pdev
);
3925 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3926 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3928 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3930 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
3931 "for consistent allocations\n");
3932 goto err_out_free_regions
;
3935 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3937 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3938 goto err_out_free_regions
;
3942 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3945 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3947 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3948 goto err_out_free_regions
;
3953 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3955 dev_err(&pdev
->dev
, "cannot map device registers\n");
3956 goto err_out_free_hw
;
3960 /* The sk98lin vendor driver uses hardware byte swapping but
3961 * this driver uses software swapping.
3965 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3966 reg
&= ~PCI_REV_DESC
;
3967 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3971 /* ring for status responses */
3972 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3975 goto err_out_iounmap
;
3977 err
= sky2_init(hw
);
3979 goto err_out_iounmap
;
3981 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3982 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3983 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3984 hw
->chip_id
, hw
->chip_rev
);
3988 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3991 goto err_out_free_pci
;
3994 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3995 err
= sky2_test_msi(hw
);
3996 if (err
== -EOPNOTSUPP
)
3997 pci_disable_msi(pdev
);
3999 goto err_out_free_netdev
;
4002 err
= register_netdev(dev
);
4004 dev_err(&pdev
->dev
, "cannot register net device\n");
4005 goto err_out_free_netdev
;
4008 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
4011 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4012 goto err_out_unregister
;
4014 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4016 sky2_show_addr(dev
);
4018 if (hw
->ports
> 1) {
4019 struct net_device
*dev1
;
4021 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4023 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4024 else if ((err
= register_netdev(dev1
))) {
4025 dev_warn(&pdev
->dev
,
4026 "register of second port failed (%d)\n", err
);
4030 sky2_show_addr(dev1
);
4033 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
4034 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4036 sky2_idle_start(hw
);
4038 pci_set_drvdata(pdev
, hw
);
4044 pci_disable_msi(pdev
);
4045 unregister_netdev(dev
);
4046 err_out_free_netdev
:
4049 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4050 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4055 err_out_free_regions
:
4056 pci_release_regions(pdev
);
4058 pci_disable_device(pdev
);
4060 pci_set_drvdata(pdev
, NULL
);
4064 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4066 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4067 struct net_device
*dev0
, *dev1
;
4072 del_timer_sync(&hw
->idle_timer
);
4074 flush_scheduled_work();
4076 sky2_write32(hw
, B0_IMSK
, 0);
4077 synchronize_irq(hw
->pdev
->irq
);
4082 unregister_netdev(dev1
);
4083 unregister_netdev(dev0
);
4087 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4088 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4089 sky2_read8(hw
, B0_CTST
);
4091 free_irq(pdev
->irq
, hw
);
4093 pci_disable_msi(pdev
);
4094 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4095 pci_release_regions(pdev
);
4096 pci_disable_device(pdev
);
4104 pci_set_drvdata(pdev
, NULL
);
4108 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4110 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4116 del_timer_sync(&hw
->idle_timer
);
4117 netif_poll_disable(hw
->dev
[0]);
4119 for (i
= 0; i
< hw
->ports
; i
++) {
4120 struct net_device
*dev
= hw
->dev
[i
];
4121 struct sky2_port
*sky2
= netdev_priv(dev
);
4123 if (netif_running(dev
))
4127 sky2_wol_init(sky2
);
4132 sky2_write32(hw
, B0_IMSK
, 0);
4135 pci_save_state(pdev
);
4136 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4137 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4142 static int sky2_resume(struct pci_dev
*pdev
)
4144 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4150 err
= pci_set_power_state(pdev
, PCI_D0
);
4154 err
= pci_restore_state(pdev
);
4158 pci_enable_wake(pdev
, PCI_D0
, 0);
4160 /* Re-enable all clocks */
4161 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
4162 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4166 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4168 for (i
= 0; i
< hw
->ports
; i
++) {
4169 struct net_device
*dev
= hw
->dev
[i
];
4170 if (netif_running(dev
)) {
4173 printk(KERN_ERR PFX
"%s: could not up: %d\n",
4181 netif_poll_enable(hw
->dev
[0]);
4182 sky2_idle_start(hw
);
4185 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4186 pci_disable_device(pdev
);
4191 static void sky2_shutdown(struct pci_dev
*pdev
)
4193 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4199 del_timer_sync(&hw
->idle_timer
);
4200 netif_poll_disable(hw
->dev
[0]);
4202 for (i
= 0; i
< hw
->ports
; i
++) {
4203 struct net_device
*dev
= hw
->dev
[i
];
4204 struct sky2_port
*sky2
= netdev_priv(dev
);
4208 sky2_wol_init(sky2
);
4215 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4216 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4218 pci_disable_device(pdev
);
4219 pci_set_power_state(pdev
, PCI_D3hot
);
4223 static struct pci_driver sky2_driver
= {
4225 .id_table
= sky2_id_table
,
4226 .probe
= sky2_probe
,
4227 .remove
= __devexit_p(sky2_remove
),
4229 .suspend
= sky2_suspend
,
4230 .resume
= sky2_resume
,
4232 .shutdown
= sky2_shutdown
,
4235 static int __init
sky2_init_module(void)
4238 return pci_register_driver(&sky2_driver
);
4241 static void __exit
sky2_cleanup_module(void)
4243 pci_unregister_driver(&sky2_driver
);
4244 sky2_debug_cleanup();
4247 module_init(sky2_init_module
);
4248 module_exit(sky2_cleanup_module
);
4250 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4251 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4252 MODULE_LICENSE("GPL");
4253 MODULE_VERSION(DRV_VERSION
);