2 * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
4 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/pci.h>
26 #define INCVALUE_MASK 0x7fffffff
27 #define ISGN 0x80000000
30 * The 82580 timesync updates the system timer every 8ns by 8ns,
31 * and this update value cannot be reprogrammed.
33 * Neither the 82576 nor the 82580 offer registers wide enough to hold
34 * nanoseconds time values for very long. For the 82580, SYSTIM always
35 * counts nanoseconds, but the upper 24 bits are not availible. The
36 * frequency is adjusted by changing the 32 bit fractional nanoseconds
39 * For the 82576, the SYSTIM register time unit is affect by the
40 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
41 * field are needed to provide the nominal 16 nanosecond period,
42 * leaving 19 bits for fractional nanoseconds.
44 * We scale the NIC clock cycle by a large factor so that relatively
45 * small clock corrections can be added or subtracted at each clock
46 * tick. The drawbacks of a large factor are a) that the clock
47 * register overflows more quickly (not such a big deal) and b) that
48 * the increment per tick has to fit into 24 bits. As a result we
49 * need to use a shift of 19 so we can fit a value of 16 into the
54 * +--------------+ +---+---+------+
55 * 82576 | 32 | | 8 | 5 | 19 |
56 * +--------------+ +---+---+------+
57 * \________ 45 bits _______/ fract
59 * +----------+---+ +--------------+
60 * 82580 | 24 | 8 | | 32 |
61 * +----------+---+ +--------------+
62 * reserved \______ 40 bits _____/
65 * The 45 bit 82576 SYSTIM overflows every
66 * 2^45 * 10^-9 / 3600 = 9.77 hours.
68 * The 40 bit 82580 SYSTIM overflows every
69 * 2^40 * 10^-9 / 60 = 18.3 minutes.
72 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
73 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
74 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
75 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
76 #define IGB_NBITS_82580 40
79 * SYSTIM read access for the 82576
82 static cycle_t
igb_ptp_read_82576(const struct cyclecounter
*cc
)
84 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
85 struct e1000_hw
*hw
= &igb
->hw
;
89 lo
= rd32(E1000_SYSTIML
);
90 hi
= rd32(E1000_SYSTIMH
);
92 val
= ((u64
) hi
) << 32;
99 * SYSTIM read access for the 82580
102 static cycle_t
igb_ptp_read_82580(const struct cyclecounter
*cc
)
104 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
105 struct e1000_hw
*hw
= &igb
->hw
;
110 * The timestamp latches on lowest register read. For the 82580
111 * the lowest register is SYSTIMR instead of SYSTIML. However we only
112 * need to provide nanosecond resolution, so we just ignore it.
114 jk
= rd32(E1000_SYSTIMR
);
115 lo
= rd32(E1000_SYSTIML
);
116 hi
= rd32(E1000_SYSTIMH
);
118 val
= ((u64
) hi
) << 32;
125 * SYSTIM read access for I210/I211
128 static void igb_ptp_read_i210(struct igb_adapter
*adapter
, struct timespec
*ts
)
130 struct e1000_hw
*hw
= &adapter
->hw
;
134 * The timestamp latches on lowest register read. For I210/I211, the
135 * lowest register is SYSTIMR. Since we only need to provide nanosecond
136 * resolution, we can ignore it.
138 jk
= rd32(E1000_SYSTIMR
);
139 nsec
= rd32(E1000_SYSTIML
);
140 sec
= rd32(E1000_SYSTIMH
);
146 static void igb_ptp_write_i210(struct igb_adapter
*adapter
,
147 const struct timespec
*ts
)
149 struct e1000_hw
*hw
= &adapter
->hw
;
152 * Writing the SYSTIMR register is not necessary as it only provides
153 * sub-nanosecond resolution.
155 wr32(E1000_SYSTIML
, ts
->tv_nsec
);
156 wr32(E1000_SYSTIMH
, ts
->tv_sec
);
160 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
161 * @adapter: board private structure
162 * @hwtstamps: timestamp structure to update
163 * @systim: unsigned 64bit system time value.
165 * We need to convert the system time value stored in the RX/TXSTMP registers
166 * into a hwtstamp which can be used by the upper level timestamping functions.
168 * The 'tmreg_lock' spinlock is used to protect the consistency of the
169 * system time value. This is needed because reading the 64 bit time
170 * value involves reading two (or three) 32 bit registers. The first
171 * read latches the value. Ditto for writing.
173 * In addition, here have extended the system time with an overflow
174 * counter in software.
176 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter
*adapter
,
177 struct skb_shared_hwtstamps
*hwtstamps
,
183 switch (adapter
->hw
.mac
.type
) {
187 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
189 ns
= timecounter_cyc2time(&adapter
->tc
, systim
);
191 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
193 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
194 hwtstamps
->hwtstamp
= ns_to_ktime(ns
);
198 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
199 /* Upper 32 bits contain s, lower 32 bits contain ns. */
200 hwtstamps
->hwtstamp
= ktime_set(systim
>> 32,
201 systim
& 0xFFFFFFFF);
209 * PTP clock operations
212 static int igb_ptp_adjfreq_82576(struct ptp_clock_info
*ptp
, s32 ppb
)
214 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
216 struct e1000_hw
*hw
= &igb
->hw
;
227 rate
= div_u64(rate
, 1953125);
229 incvalue
= 16 << IGB_82576_TSYNC_SHIFT
;
236 wr32(E1000_TIMINCA
, INCPERIOD_82576
| (incvalue
& INCVALUE_82576_MASK
));
241 static int igb_ptp_adjfreq_82580(struct ptp_clock_info
*ptp
, s32 ppb
)
243 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
245 struct e1000_hw
*hw
= &igb
->hw
;
256 rate
= div_u64(rate
, 1953125);
258 inca
= rate
& INCVALUE_MASK
;
262 wr32(E1000_TIMINCA
, inca
);
267 static int igb_ptp_adjtime_82576(struct ptp_clock_info
*ptp
, s64 delta
)
269 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
274 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
276 now
= timecounter_read(&igb
->tc
);
278 timecounter_init(&igb
->tc
, &igb
->cc
, now
);
280 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
285 static int igb_ptp_adjtime_i210(struct ptp_clock_info
*ptp
, s64 delta
)
287 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
290 struct timespec now
, then
= ns_to_timespec(delta
);
292 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
294 igb_ptp_read_i210(igb
, &now
);
295 now
= timespec_add(now
, then
);
296 igb_ptp_write_i210(igb
, (const struct timespec
*)&now
);
298 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
303 static int igb_ptp_gettime_82576(struct ptp_clock_info
*ptp
,
306 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
312 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
314 ns
= timecounter_read(&igb
->tc
);
316 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
318 ts
->tv_sec
= div_u64_rem(ns
, 1000000000, &remainder
);
319 ts
->tv_nsec
= remainder
;
324 static int igb_ptp_gettime_i210(struct ptp_clock_info
*ptp
,
327 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
331 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
333 igb_ptp_read_i210(igb
, ts
);
335 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
340 static int igb_ptp_settime_82576(struct ptp_clock_info
*ptp
,
341 const struct timespec
*ts
)
343 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
348 ns
= ts
->tv_sec
* 1000000000ULL;
351 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
353 timecounter_init(&igb
->tc
, &igb
->cc
, ns
);
355 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
360 static int igb_ptp_settime_i210(struct ptp_clock_info
*ptp
,
361 const struct timespec
*ts
)
363 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
367 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
369 igb_ptp_write_i210(igb
, ts
);
371 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
376 static int igb_ptp_enable(struct ptp_clock_info
*ptp
,
377 struct ptp_clock_request
*rq
, int on
)
384 * @work: pointer to work struct
386 * This work function polls the TSYNCTXCTL valid bit to determine when a
387 * timestamp has been taken for the current stored skb.
389 void igb_ptp_tx_work(struct work_struct
*work
)
391 struct igb_adapter
*adapter
= container_of(work
, struct igb_adapter
,
393 struct e1000_hw
*hw
= &adapter
->hw
;
396 if (!adapter
->ptp_tx_skb
)
399 tsynctxctl
= rd32(E1000_TSYNCTXCTL
);
400 if (tsynctxctl
& E1000_TSYNCTXCTL_VALID
)
401 igb_ptp_tx_hwtstamp(adapter
);
403 /* reschedule to check later */
404 schedule_work(&adapter
->ptp_tx_work
);
407 static void igb_ptp_overflow_check(struct work_struct
*work
)
409 struct igb_adapter
*igb
=
410 container_of(work
, struct igb_adapter
, ptp_overflow_work
.work
);
413 igb
->ptp_caps
.gettime(&igb
->ptp_caps
, &ts
);
415 pr_debug("igb overflow check at %ld.%09lu\n", ts
.tv_sec
, ts
.tv_nsec
);
417 schedule_delayed_work(&igb
->ptp_overflow_work
,
418 IGB_SYSTIM_OVERFLOW_PERIOD
);
422 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
423 * @adapter: Board private structure.
425 * If we were asked to do hardware stamping and such a time stamp is
426 * available, then it must have been for this skb here because we only
427 * allow only one such packet into the queue.
429 void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
)
431 struct e1000_hw
*hw
= &adapter
->hw
;
432 struct skb_shared_hwtstamps shhwtstamps
;
435 regval
= rd32(E1000_TXSTMPL
);
436 regval
|= (u64
)rd32(E1000_TXSTMPH
) << 32;
438 igb_ptp_systim_to_hwtstamp(adapter
, &shhwtstamps
, regval
);
439 skb_tstamp_tx(adapter
->ptp_tx_skb
, &shhwtstamps
);
440 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
441 adapter
->ptp_tx_skb
= NULL
;
445 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
446 * @q_vector: Pointer to interrupt specific structure
447 * @va: Pointer to address containing Rx buffer
448 * @skb: Buffer containing timestamp and packet
450 * This function is meant to retrieve a timestamp from the first buffer of an
451 * incoming frame. The value is stored in little endian format starting on
454 void igb_ptp_rx_pktstamp(struct igb_q_vector
*q_vector
,
458 __le64
*regval
= (__le64
*)va
;
461 * The timestamp is recorded in little endian format.
463 * Field: Reserved Reserved SYSTIML SYSTIMH
465 igb_ptp_systim_to_hwtstamp(q_vector
->adapter
, skb_hwtstamps(skb
),
466 le64_to_cpu(regval
[1]));
470 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
471 * @q_vector: Pointer to interrupt specific structure
472 * @skb: Buffer containing timestamp and packet
474 * This function is meant to retrieve a timestamp from the internal registers
475 * of the adapter and store it in the skb.
477 void igb_ptp_rx_rgtstamp(struct igb_q_vector
*q_vector
,
480 struct igb_adapter
*adapter
= q_vector
->adapter
;
481 struct e1000_hw
*hw
= &adapter
->hw
;
485 * If this bit is set, then the RX registers contain the time stamp. No
486 * other packet will be time stamped until we read these registers, so
487 * read the registers to make them available again. Because only one
488 * packet can be time stamped at a time, we know that the register
489 * values must belong to this one here and therefore we don't need to
490 * compare any of the additional attributes stored for it.
492 * If nothing went wrong, then it should have a shared tx_flags that we
493 * can turn into a skb_shared_hwtstamps.
495 if (!(rd32(E1000_TSYNCRXCTL
) & E1000_TSYNCRXCTL_VALID
))
498 regval
= rd32(E1000_RXSTMPL
);
499 regval
|= (u64
)rd32(E1000_RXSTMPH
) << 32;
501 igb_ptp_systim_to_hwtstamp(adapter
, skb_hwtstamps(skb
), regval
);
505 * igb_ptp_hwtstamp_ioctl - control hardware time stamping
510 * Outgoing time stamping can be enabled and disabled. Play nice and
511 * disable it when requested, although it shouldn't case any overhead
512 * when no packet needs it. At most one packet in the queue may be
513 * marked for time stamping, otherwise it would be impossible to tell
514 * for sure to which packet the hardware time stamp belongs.
516 * Incoming time stamping has to be configured via the hardware
517 * filters. Not all combinations are supported, in particular event
518 * type has to be specified. Matching the kind of event packet is
519 * not supported, with the exception of "all V2 events regardless of
523 int igb_ptp_hwtstamp_ioctl(struct net_device
*netdev
,
524 struct ifreq
*ifr
, int cmd
)
526 struct igb_adapter
*adapter
= netdev_priv(netdev
);
527 struct e1000_hw
*hw
= &adapter
->hw
;
528 struct hwtstamp_config config
;
529 u32 tsync_tx_ctl
= E1000_TSYNCTXCTL_ENABLED
;
530 u32 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
531 u32 tsync_rx_cfg
= 0;
536 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
539 /* reserved for future extensions */
543 switch (config
.tx_type
) {
544 case HWTSTAMP_TX_OFF
:
552 switch (config
.rx_filter
) {
553 case HWTSTAMP_FILTER_NONE
:
556 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
557 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
558 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
559 case HWTSTAMP_FILTER_ALL
:
561 * register TSYNCRXCFG must be set, therefore it is not
562 * possible to time stamp both Sync and Delay_Req messages
563 * => fall back to time stamping all packets
565 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
566 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
568 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
569 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
570 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE
;
573 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
574 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
575 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE
;
578 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
579 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
580 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
581 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE
;
584 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
586 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
587 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
588 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
589 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE
;
592 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
594 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
595 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
596 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
597 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_EVENT_V2
;
598 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
606 if (hw
->mac
.type
== e1000_82575
) {
607 if (tsync_rx_ctl
| tsync_tx_ctl
)
613 * Per-packet timestamping only works if all packets are
614 * timestamped, so enable timestamping in all packets as
615 * long as one rx filter was configured.
617 if ((hw
->mac
.type
>= e1000_82580
) && tsync_rx_ctl
) {
618 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
619 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
621 if ((hw
->mac
.type
== e1000_i210
) ||
622 (hw
->mac
.type
== e1000_i211
)) {
623 regval
= rd32(E1000_RXPBS
);
624 regval
|= E1000_RXPBS_CFG_TS_EN
;
625 wr32(E1000_RXPBS
, regval
);
629 /* enable/disable TX */
630 regval
= rd32(E1000_TSYNCTXCTL
);
631 regval
&= ~E1000_TSYNCTXCTL_ENABLED
;
632 regval
|= tsync_tx_ctl
;
633 wr32(E1000_TSYNCTXCTL
, regval
);
635 /* enable/disable RX */
636 regval
= rd32(E1000_TSYNCRXCTL
);
637 regval
&= ~(E1000_TSYNCRXCTL_ENABLED
| E1000_TSYNCRXCTL_TYPE_MASK
);
638 regval
|= tsync_rx_ctl
;
639 wr32(E1000_TSYNCRXCTL
, regval
);
641 /* define which PTP packets are time stamped */
642 wr32(E1000_TSYNCRXCFG
, tsync_rx_cfg
);
644 /* define ethertype filter for timestamped packets */
647 (E1000_ETQF_FILTER_ENABLE
| /* enable filter */
648 E1000_ETQF_1588
| /* enable timestamping */
649 ETH_P_1588
)); /* 1588 eth protocol type */
651 wr32(E1000_ETQF(3), 0);
654 /* L4 Queue Filter[3]: filter by destination port and protocol */
656 u32 ftqf
= (IPPROTO_UDP
/* UDP */
657 | E1000_FTQF_VF_BP
/* VF not compared */
658 | E1000_FTQF_1588_TIME_STAMP
/* Enable Timestamping */
659 | E1000_FTQF_MASK
); /* mask all inputs */
660 ftqf
&= ~E1000_FTQF_MASK_PROTO_BP
; /* enable protocol check */
662 wr32(E1000_IMIR(3), htons(PTP_PORT
));
663 wr32(E1000_IMIREXT(3),
664 (E1000_IMIREXT_SIZE_BP
| E1000_IMIREXT_CTRL_BP
));
665 if (hw
->mac
.type
== e1000_82576
) {
666 /* enable source port check */
667 wr32(E1000_SPQF(3), htons(PTP_PORT
));
668 ftqf
&= ~E1000_FTQF_MASK_SOURCE_PORT_BP
;
670 wr32(E1000_FTQF(3), ftqf
);
672 wr32(E1000_FTQF(3), E1000_FTQF_MASK
);
676 /* clear TX/RX time stamp registers, just to be sure */
677 regval
= rd32(E1000_TXSTMPL
);
678 regval
= rd32(E1000_TXSTMPH
);
679 regval
= rd32(E1000_RXSTMPL
);
680 regval
= rd32(E1000_RXSTMPH
);
682 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
686 void igb_ptp_init(struct igb_adapter
*adapter
)
688 struct e1000_hw
*hw
= &adapter
->hw
;
689 struct net_device
*netdev
= adapter
->netdev
;
691 switch (hw
->mac
.type
) {
693 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
694 adapter
->ptp_caps
.owner
= THIS_MODULE
;
695 adapter
->ptp_caps
.max_adj
= 1000000000;
696 adapter
->ptp_caps
.n_ext_ts
= 0;
697 adapter
->ptp_caps
.pps
= 0;
698 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82576
;
699 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
700 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_82576
;
701 adapter
->ptp_caps
.settime
= igb_ptp_settime_82576
;
702 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
703 adapter
->cc
.read
= igb_ptp_read_82576
;
704 adapter
->cc
.mask
= CLOCKSOURCE_MASK(64);
705 adapter
->cc
.mult
= 1;
706 adapter
->cc
.shift
= IGB_82576_TSYNC_SHIFT
;
707 /* Dial the nominal frequency. */
708 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
712 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
713 adapter
->ptp_caps
.owner
= THIS_MODULE
;
714 adapter
->ptp_caps
.max_adj
= 62499999;
715 adapter
->ptp_caps
.n_ext_ts
= 0;
716 adapter
->ptp_caps
.pps
= 0;
717 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
718 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
719 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_82576
;
720 adapter
->ptp_caps
.settime
= igb_ptp_settime_82576
;
721 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
722 adapter
->cc
.read
= igb_ptp_read_82580
;
723 adapter
->cc
.mask
= CLOCKSOURCE_MASK(IGB_NBITS_82580
);
724 adapter
->cc
.mult
= 1;
725 adapter
->cc
.shift
= 0;
726 /* Enable the timer functions by clearing bit 31. */
727 wr32(E1000_TSAUXC
, 0x0);
731 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
732 adapter
->ptp_caps
.owner
= THIS_MODULE
;
733 adapter
->ptp_caps
.max_adj
= 62499999;
734 adapter
->ptp_caps
.n_ext_ts
= 0;
735 adapter
->ptp_caps
.pps
= 0;
736 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
737 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_i210
;
738 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_i210
;
739 adapter
->ptp_caps
.settime
= igb_ptp_settime_i210
;
740 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
741 /* Enable the timer functions by clearing bit 31. */
742 wr32(E1000_TSAUXC
, 0x0);
745 adapter
->ptp_clock
= NULL
;
751 spin_lock_init(&adapter
->tmreg_lock
);
752 INIT_WORK(&adapter
->ptp_tx_work
, igb_ptp_tx_work
);
754 /* Initialize the clock and overflow work for devices that need it. */
755 if ((hw
->mac
.type
== e1000_i210
) || (hw
->mac
.type
== e1000_i211
)) {
756 struct timespec ts
= ktime_to_timespec(ktime_get_real());
758 igb_ptp_settime_i210(&adapter
->ptp_caps
, &ts
);
760 timecounter_init(&adapter
->tc
, &adapter
->cc
,
761 ktime_to_ns(ktime_get_real()));
763 INIT_DELAYED_WORK(&adapter
->ptp_overflow_work
,
764 igb_ptp_overflow_check
);
766 schedule_delayed_work(&adapter
->ptp_overflow_work
,
767 IGB_SYSTIM_OVERFLOW_PERIOD
);
770 /* Initialize the time sync interrupts for devices that support it. */
771 if (hw
->mac
.type
>= e1000_82580
) {
772 wr32(E1000_TSIM
, E1000_TSIM_TXTS
);
773 wr32(E1000_IMS
, E1000_IMS_TS
);
776 adapter
->ptp_clock
= ptp_clock_register(&adapter
->ptp_caps
,
777 &adapter
->pdev
->dev
);
778 if (IS_ERR(adapter
->ptp_clock
)) {
779 adapter
->ptp_clock
= NULL
;
780 dev_err(&adapter
->pdev
->dev
, "ptp_clock_register failed\n");
782 dev_info(&adapter
->pdev
->dev
, "added PHC on %s\n",
783 adapter
->netdev
->name
);
784 adapter
->flags
|= IGB_FLAG_PTP
;
789 * igb_ptp_stop - Disable PTP device and stop the overflow check.
790 * @adapter: Board private structure.
792 * This function stops the PTP support and cancels the delayed work.
794 void igb_ptp_stop(struct igb_adapter
*adapter
)
796 switch (adapter
->hw
.mac
.type
) {
800 cancel_delayed_work_sync(&adapter
->ptp_overflow_work
);
804 /* No delayed work to cancel. */
810 cancel_work_sync(&adapter
->ptp_tx_work
);
812 if (adapter
->ptp_clock
) {
813 ptp_clock_unregister(adapter
->ptp_clock
);
814 dev_info(&adapter
->pdev
->dev
, "removed PHC on %s\n",
815 adapter
->netdev
->name
);
816 adapter
->flags
&= ~IGB_FLAG_PTP
;
821 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
822 * @adapter: Board private structure.
824 * This function handles the reset work required to re-enable the PTP device.
826 void igb_ptp_reset(struct igb_adapter
*adapter
)
828 struct e1000_hw
*hw
= &adapter
->hw
;
830 if (!(adapter
->flags
& IGB_FLAG_PTP
))
833 switch (adapter
->hw
.mac
.type
) {
835 /* Dial the nominal frequency. */
836 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
842 /* Enable the timer functions and interrupts. */
843 wr32(E1000_TSAUXC
, 0x0);
844 wr32(E1000_TSIM
, E1000_TSIM_TXTS
);
845 wr32(E1000_IMS
, E1000_IMS_TS
);
852 /* Re-initialize the timer. */
853 if ((hw
->mac
.type
== e1000_i210
) || (hw
->mac
.type
== e1000_i211
)) {
854 struct timespec ts
= ktime_to_timespec(ktime_get_real());
856 igb_ptp_settime_i210(&adapter
->ptp_caps
, &ts
);
858 timecounter_init(&adapter
->tc
, &adapter
->cc
,
859 ktime_to_ns(ktime_get_real()));