2 * linux/drivers/usb/gadget/pxa2xx_udc.c
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 // #define VERBOSE DBG_VERBOSE
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/delay.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/init.h>
39 #include <linux/timer.h>
40 #include <linux/list.h>
41 #include <linux/interrupt.h>
42 #include <linux/proc_fs.h>
44 #include <linux/platform_device.h>
45 #include <linux/dma-mapping.h>
47 #include <asm/byteorder.h>
51 #include <asm/system.h>
52 #include <asm/mach-types.h>
53 #include <asm/unaligned.h>
54 #include <asm/hardware.h>
55 #ifdef CONFIG_ARCH_PXA
56 #include <asm/arch/pxa-regs.h>
59 #include <linux/usb_ch9.h>
60 #include <linux/usb_gadget.h>
62 #include <asm/arch/udc.h>
66 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
67 * series processors. The UDC for the IXP 4xx series is very similar.
68 * There are fifteen endpoints, in addition to ep0.
70 * Such controller drivers work with a gadget driver. The gadget driver
71 * returns descriptors, implements configuration and data protocols used
72 * by the host to interact with this device, and allocates endpoints to
73 * the different protocol interfaces. The controller driver virtualizes
74 * usb hardware so that the gadget drivers will be more portable.
76 * This UDC hardware wants to implement a bit too much USB protocol, so
77 * it constrains the sorts of USB configuration change events that work.
78 * The errata for these chips are misleading; some "fixed" bugs from
79 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
82 #define DRIVER_VERSION "4-May-2005"
83 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
86 static const char driver_name
[] = "pxa2xx_udc";
88 static const char ep0name
[] = "ep0";
92 // #define USE_OUT_DMA
93 // #define DISABLE_TEST_MODE
95 #ifdef CONFIG_ARCH_IXP4XX
98 /* cpu-specific register addresses are compiled in to this code */
99 #ifdef CONFIG_ARCH_PXA
100 #error "Can't configure both IXP and PXA"
105 #include "pxa2xx_udc.h"
109 static int use_dma
= 1;
110 module_param(use_dma
, bool, 0);
111 MODULE_PARM_DESC (use_dma
, "true to use dma");
113 static void dma_nodesc_handler (int dmach
, void *_ep
, struct pt_regs
*r
);
114 static void kick_dma(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
);
117 #define DMASTR " (dma support)"
119 #define DMASTR " (dma in)"
123 #define DMASTR " (pio only)"
127 #ifdef CONFIG_USB_PXA2XX_SMALL
128 #define SIZE_STR " (small)"
133 #ifdef DISABLE_TEST_MODE
134 /* (mode == 0) == no undocumented chip tweaks
135 * (mode & 1) == double buffer bulk IN
136 * (mode & 2) == double buffer bulk OUT
137 * ... so mode = 3 (or 7, 15, etc) does it for both
139 static ushort fifo_mode
= 0;
140 module_param(fifo_mode
, ushort
, 0);
141 MODULE_PARM_DESC (fifo_mode
, "pxa2xx udc fifo mode");
144 /* ---------------------------------------------------------------------------
145 * endpoint related parts of the api to the usb controller hardware,
146 * used by gadget driver; and the inner talker-to-hardware core.
147 * ---------------------------------------------------------------------------
150 static void pxa2xx_ep_fifo_flush (struct usb_ep
*ep
);
151 static void nuke (struct pxa2xx_ep
*, int status
);
153 /* one GPIO should be used to detect VBUS from the host */
154 static int is_vbus_present(void)
156 struct pxa2xx_udc_mach_info
*mach
= the_controller
->mach
;
159 return pxa_gpio_get(mach
->gpio_vbus
);
160 if (mach
->udc_is_connected
)
161 return mach
->udc_is_connected();
165 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
166 static void pullup_off(void)
168 struct pxa2xx_udc_mach_info
*mach
= the_controller
->mach
;
170 if (mach
->gpio_pullup
)
171 pxa_gpio_set(mach
->gpio_pullup
, 0);
172 else if (mach
->udc_command
)
173 mach
->udc_command(PXA2XX_UDC_CMD_DISCONNECT
);
176 static void pullup_on(void)
178 struct pxa2xx_udc_mach_info
*mach
= the_controller
->mach
;
180 if (mach
->gpio_pullup
)
181 pxa_gpio_set(mach
->gpio_pullup
, 1);
182 else if (mach
->udc_command
)
183 mach
->udc_command(PXA2XX_UDC_CMD_CONNECT
);
186 static void pio_irq_enable(int bEndpointAddress
)
188 bEndpointAddress
&= 0xf;
189 if (bEndpointAddress
< 8)
190 UICR0
&= ~(1 << bEndpointAddress
);
192 bEndpointAddress
-= 8;
193 UICR1
&= ~(1 << bEndpointAddress
);
197 static void pio_irq_disable(int bEndpointAddress
)
199 bEndpointAddress
&= 0xf;
200 if (bEndpointAddress
< 8)
201 UICR0
|= 1 << bEndpointAddress
;
203 bEndpointAddress
-= 8;
204 UICR1
|= 1 << bEndpointAddress
;
208 /* The UDCCR reg contains mask and interrupt status bits,
209 * so using '|=' isn't safe as it may ack an interrupt.
211 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
213 static inline void udc_set_mask_UDCCR(int mask
)
215 UDCCR
= (UDCCR
& UDCCR_MASK_BITS
) | (mask
& UDCCR_MASK_BITS
);
218 static inline void udc_clear_mask_UDCCR(int mask
)
220 UDCCR
= (UDCCR
& UDCCR_MASK_BITS
) & ~(mask
& UDCCR_MASK_BITS
);
223 static inline void udc_ack_int_UDCCR(int mask
)
225 /* udccr contains the bits we dont want to change */
226 __u32 udccr
= UDCCR
& UDCCR_MASK_BITS
;
228 UDCCR
= udccr
| (mask
& ~UDCCR_MASK_BITS
);
232 * endpoint enable/disable
234 * we need to verify the descriptors used to enable endpoints. since pxa2xx
235 * endpoint configurations are fixed, and are pretty much always enabled,
236 * there's not a lot to manage here.
238 * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
239 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
240 * for a single interface (with only the default altsetting) and for gadget
241 * drivers that don't halt endpoints (not reset by set_interface). that also
242 * means that if you use ISO, you must violate the USB spec rule that all
243 * iso endpoints must be in non-default altsettings.
245 static int pxa2xx_ep_enable (struct usb_ep
*_ep
,
246 const struct usb_endpoint_descriptor
*desc
)
248 struct pxa2xx_ep
*ep
;
249 struct pxa2xx_udc
*dev
;
251 ep
= container_of (_ep
, struct pxa2xx_ep
, ep
);
252 if (!_ep
|| !desc
|| ep
->desc
|| _ep
->name
== ep0name
253 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
254 || ep
->bEndpointAddress
!= desc
->bEndpointAddress
255 || ep
->fifo_size
< le16_to_cpu
256 (desc
->wMaxPacketSize
)) {
257 DMSG("%s, bad ep or descriptor\n", __FUNCTION__
);
261 /* xfer types must match, except that interrupt ~= bulk */
262 if (ep
->bmAttributes
!= desc
->bmAttributes
263 && ep
->bmAttributes
!= USB_ENDPOINT_XFER_BULK
264 && desc
->bmAttributes
!= USB_ENDPOINT_XFER_INT
) {
265 DMSG("%s, %s type mismatch\n", __FUNCTION__
, _ep
->name
);
269 /* hardware _could_ do smaller, but driver doesn't */
270 if ((desc
->bmAttributes
== USB_ENDPOINT_XFER_BULK
271 && le16_to_cpu (desc
->wMaxPacketSize
)
273 || !desc
->wMaxPacketSize
) {
274 DMSG("%s, bad %s maxpacket\n", __FUNCTION__
, _ep
->name
);
279 if (!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
280 DMSG("%s, bogus device state\n", __FUNCTION__
);
287 ep
->pio_irqs
= ep
->dma_irqs
= 0;
288 ep
->ep
.maxpacket
= le16_to_cpu (desc
->wMaxPacketSize
);
290 /* flush fifo (mostly for OUT buffers) */
291 pxa2xx_ep_fifo_flush (_ep
);
293 /* ... reset halt state too, if we could ... */
296 /* for (some) bulk and ISO endpoints, try to get a DMA channel and
297 * bind it to the endpoint. otherwise use PIO.
299 switch (ep
->bmAttributes
) {
300 case USB_ENDPOINT_XFER_ISOC
:
301 if (le16_to_cpu(desc
->wMaxPacketSize
) % 32)
304 case USB_ENDPOINT_XFER_BULK
:
305 if (!use_dma
|| !ep
->reg_drcmr
)
307 ep
->dma
= pxa_request_dma ((char *)_ep
->name
,
308 (le16_to_cpu (desc
->wMaxPacketSize
) > 64)
309 ? DMA_PRIO_MEDIUM
/* some iso */
311 dma_nodesc_handler
, ep
);
313 *ep
->reg_drcmr
= DRCMR_MAPVLD
| ep
->dma
;
314 DMSG("%s using dma%d\n", _ep
->name
, ep
->dma
);
319 DBG(DBG_VERBOSE
, "enabled %s\n", _ep
->name
);
323 static int pxa2xx_ep_disable (struct usb_ep
*_ep
)
325 struct pxa2xx_ep
*ep
;
328 ep
= container_of (_ep
, struct pxa2xx_ep
, ep
);
329 if (!_ep
|| !ep
->desc
) {
330 DMSG("%s, %s not enabled\n", __FUNCTION__
,
331 _ep
? ep
->ep
.name
: NULL
);
334 local_irq_save(flags
);
336 nuke (ep
, -ESHUTDOWN
);
341 pxa_free_dma (ep
->dma
);
346 /* flush fifo (mostly for IN buffers) */
347 pxa2xx_ep_fifo_flush (_ep
);
352 local_irq_restore(flags
);
353 DBG(DBG_VERBOSE
, "%s disabled\n", _ep
->name
);
357 /*-------------------------------------------------------------------------*/
359 /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers
360 * must still pass correctly initialized endpoints, since other controller
361 * drivers may care about how it's currently set up (dma issues etc).
365 * pxa2xx_ep_alloc_request - allocate a request data structure
367 static struct usb_request
*
368 pxa2xx_ep_alloc_request (struct usb_ep
*_ep
, gfp_t gfp_flags
)
370 struct pxa2xx_request
*req
;
372 req
= kzalloc(sizeof(*req
), gfp_flags
);
376 INIT_LIST_HEAD (&req
->queue
);
382 * pxa2xx_ep_free_request - deallocate a request data structure
385 pxa2xx_ep_free_request (struct usb_ep
*_ep
, struct usb_request
*_req
)
387 struct pxa2xx_request
*req
;
389 req
= container_of (_req
, struct pxa2xx_request
, req
);
390 WARN_ON (!list_empty (&req
->queue
));
395 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
396 * no device-affinity and the heap works perfectly well for i/o buffers.
397 * It wastes much less memory than dma_alloc_coherent() would, and even
398 * prevents cacheline (32 bytes wide) sharing problems.
401 pxa2xx_ep_alloc_buffer(struct usb_ep
*_ep
, unsigned bytes
,
402 dma_addr_t
*dma
, gfp_t gfp_flags
)
406 retval
= kmalloc (bytes
, gfp_flags
& ~(__GFP_DMA
|__GFP_HIGHMEM
));
409 *dma
= virt_to_bus (retval
);
411 *dma
= (dma_addr_t
)~0;
417 pxa2xx_ep_free_buffer(struct usb_ep
*_ep
, void *buf
, dma_addr_t dma
,
423 /*-------------------------------------------------------------------------*/
426 * done - retire a request; caller blocked irqs
428 static void done(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
, int status
)
430 unsigned stopped
= ep
->stopped
;
432 list_del_init(&req
->queue
);
434 if (likely (req
->req
.status
== -EINPROGRESS
))
435 req
->req
.status
= status
;
437 status
= req
->req
.status
;
439 if (status
&& status
!= -ESHUTDOWN
)
440 DBG(DBG_VERBOSE
, "complete %s req %p stat %d len %u/%u\n",
441 ep
->ep
.name
, &req
->req
, status
,
442 req
->req
.actual
, req
->req
.length
);
444 /* don't modify queue heads during completion callback */
446 req
->req
.complete(&ep
->ep
, &req
->req
);
447 ep
->stopped
= stopped
;
451 static inline void ep0_idle (struct pxa2xx_udc
*dev
)
453 dev
->ep0state
= EP0_IDLE
;
457 write_packet(volatile u32
*uddr
, struct pxa2xx_request
*req
, unsigned max
)
460 unsigned length
, count
;
462 buf
= req
->req
.buf
+ req
->req
.actual
;
465 /* how big will this packet be? */
466 length
= min(req
->req
.length
- req
->req
.actual
, max
);
467 req
->req
.actual
+= length
;
470 while (likely(count
--))
477 * write to an IN endpoint fifo, as many packets as possible.
478 * irqs will use this to write the rest later.
479 * caller guarantees at least one packet buffer is ready (or a zlp).
482 write_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
486 max
= le16_to_cpu(ep
->desc
->wMaxPacketSize
);
489 int is_last
, is_short
;
491 count
= write_packet(ep
->reg_uddr
, req
, max
);
493 /* last packet is usually short (or a zlp) */
494 if (unlikely (count
!= max
))
495 is_last
= is_short
= 1;
497 if (likely(req
->req
.length
!= req
->req
.actual
)
502 /* interrupt/iso maxpacket may not fill the fifo */
503 is_short
= unlikely (max
< ep
->fifo_size
);
506 DBG(DBG_VERY_NOISY
, "wrote %s %d bytes%s%s %d left %p\n",
508 is_last
? "/L" : "", is_short
? "/S" : "",
509 req
->req
.length
- req
->req
.actual
, req
);
511 /* let loose that packet. maybe try writing another one,
512 * double buffering might work. TSP, TPC, and TFS
513 * bit values are the same for all normal IN endpoints.
515 *ep
->reg_udccs
= UDCCS_BI_TPC
;
517 *ep
->reg_udccs
= UDCCS_BI_TSP
;
519 /* requests complete when all IN data is in the FIFO */
522 if (list_empty(&ep
->queue
) || unlikely(ep
->dma
>= 0)) {
523 pio_irq_disable (ep
->bEndpointAddress
);
525 /* unaligned data and zlps couldn't use dma */
526 if (unlikely(!list_empty(&ep
->queue
))) {
527 req
= list_entry(ep
->queue
.next
,
528 struct pxa2xx_request
, queue
);
537 // TODO experiment: how robust can fifo mode tweaking be?
538 // double buffering is off in the default fifo mode, which
539 // prevents TFS from being set here.
541 } while (*ep
->reg_udccs
& UDCCS_BI_TFS
);
545 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
546 * ep0 data stage. these chips want very simple state transitions.
549 void ep0start(struct pxa2xx_udc
*dev
, u32 flags
, const char *tag
)
551 UDCCS0
= flags
|UDCCS0_SA
|UDCCS0_OPR
;
553 dev
->req_pending
= 0;
554 DBG(DBG_VERY_NOISY
, "%s %s, %02x/%02x\n",
555 __FUNCTION__
, tag
, UDCCS0
, flags
);
559 write_ep0_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
564 count
= write_packet(&UDDR0
, req
, EP0_FIFO_SIZE
);
565 ep
->dev
->stats
.write
.bytes
+= count
;
567 /* last packet "must be" short (or a zlp) */
568 is_short
= (count
!= EP0_FIFO_SIZE
);
570 DBG(DBG_VERY_NOISY
, "ep0in %d bytes %d left %p\n", count
,
571 req
->req
.length
- req
->req
.actual
, req
);
573 if (unlikely (is_short
)) {
574 if (ep
->dev
->req_pending
)
575 ep0start(ep
->dev
, UDCCS0_IPR
, "short IN");
579 count
= req
->req
.length
;
582 #ifndef CONFIG_ARCH_IXP4XX
584 /* This seems to get rid of lost status irqs in some cases:
585 * host responds quickly, or next request involves config
586 * change automagic, or should have been hidden, or ...
588 * FIXME get rid of all udelays possible...
590 if (count
>= EP0_FIFO_SIZE
) {
593 if ((UDCCS0
& UDCCS0_OPR
) != 0) {
594 /* clear OPR, generate ack */
604 } else if (ep
->dev
->req_pending
)
605 ep0start(ep
->dev
, 0, "IN");
611 * read_fifo - unload packet(s) from the fifo we use for usb OUT
612 * transfers and put them into the request. caller should have made
613 * sure there's at least one packet ready.
615 * returns true if the request completed because of short packet or the
616 * request buffer having filled (and maybe overran till end-of-packet).
619 read_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
624 unsigned bufferspace
, count
, is_short
;
626 /* make sure there's a packet in the FIFO.
627 * UDCCS_{BO,IO}_RPC are all the same bit value.
628 * UDCCS_{BO,IO}_RNE are all the same bit value.
630 udccs
= *ep
->reg_udccs
;
631 if (unlikely ((udccs
& UDCCS_BO_RPC
) == 0))
633 buf
= req
->req
.buf
+ req
->req
.actual
;
635 bufferspace
= req
->req
.length
- req
->req
.actual
;
637 /* read all bytes from this packet */
638 if (likely (udccs
& UDCCS_BO_RNE
)) {
639 count
= 1 + (0x0ff & *ep
->reg_ubcr
);
640 req
->req
.actual
+= min (count
, bufferspace
);
643 is_short
= (count
< ep
->ep
.maxpacket
);
644 DBG(DBG_VERY_NOISY
, "read %s %02x, %d bytes%s req %p %d/%d\n",
645 ep
->ep
.name
, udccs
, count
,
646 is_short
? "/S" : "",
647 req
, req
->req
.actual
, req
->req
.length
);
648 while (likely (count
-- != 0)) {
649 u8 byte
= (u8
) *ep
->reg_uddr
;
651 if (unlikely (bufferspace
== 0)) {
652 /* this happens when the driver's buffer
653 * is smaller than what the host sent.
654 * discard the extra data.
656 if (req
->req
.status
!= -EOVERFLOW
)
657 DMSG("%s overflow %d\n",
659 req
->req
.status
= -EOVERFLOW
;
665 *ep
->reg_udccs
= UDCCS_BO_RPC
;
666 /* RPC/RSP/RNE could now reflect the other packet buffer */
668 /* iso is one request per packet */
669 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
670 if (udccs
& UDCCS_IO_ROF
)
671 req
->req
.status
= -EHOSTUNREACH
;
672 /* more like "is_done" */
677 if (is_short
|| req
->req
.actual
== req
->req
.length
) {
679 if (list_empty(&ep
->queue
))
680 pio_irq_disable (ep
->bEndpointAddress
);
684 /* finished that packet. the next one may be waiting... */
690 * special ep0 version of the above. no UBCR0 or double buffering; status
691 * handshaking is magic. most device protocols don't need control-OUT.
692 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
693 * protocols do use them.
696 read_ep0_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
699 unsigned bufferspace
;
701 buf
= req
->req
.buf
+ req
->req
.actual
;
702 bufferspace
= req
->req
.length
- req
->req
.actual
;
704 while (UDCCS0
& UDCCS0_RNE
) {
707 if (unlikely (bufferspace
== 0)) {
708 /* this happens when the driver's buffer
709 * is smaller than what the host sent.
710 * discard the extra data.
712 if (req
->req
.status
!= -EOVERFLOW
)
713 DMSG("%s overflow\n", ep
->ep
.name
);
714 req
->req
.status
= -EOVERFLOW
;
722 UDCCS0
= UDCCS0_OPR
| UDCCS0_IPR
;
725 if (req
->req
.actual
>= req
->req
.length
)
728 /* finished that packet. the next one may be waiting... */
734 #define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
737 start_dma_nodesc(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
, int is_in
)
739 u32 dcmd
= req
->req
.length
;
740 u32 buf
= req
->req
.dma
;
741 u32 fifo
= io_v2p ((u32
)ep
->reg_uddr
);
743 /* caller guarantees there's a packet or more remaining
744 * - IN may end with a short packet (TSP set separately),
745 * - OUT is always full length
747 buf
+= req
->req
.actual
;
748 dcmd
-= req
->req
.actual
;
751 /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
752 DCSR(ep
->dma
) = DCSR_NODESC
;
754 DSADR(ep
->dma
) = buf
;
755 DTADR(ep
->dma
) = fifo
;
756 if (dcmd
> MAX_IN_DMA
)
759 ep
->dma_fixup
= (dcmd
% ep
->ep
.maxpacket
) != 0;
760 dcmd
|= DCMD_BURST32
| DCMD_WIDTH1
761 | DCMD_FLOWTRG
| DCMD_INCSRCADDR
;
764 DSADR(ep
->dma
) = fifo
;
765 DTADR(ep
->dma
) = buf
;
766 if (ep
->bmAttributes
!= USB_ENDPOINT_XFER_ISOC
)
767 dcmd
= ep
->ep
.maxpacket
;
768 dcmd
|= DCMD_BURST32
| DCMD_WIDTH1
769 | DCMD_FLOWSRC
| DCMD_INCTRGADDR
;
772 DCMD(ep
->dma
) = dcmd
;
773 DCSR(ep
->dma
) = DCSR_RUN
| DCSR_NODESC
775 ? DCSR_STOPIRQEN
/* use dma_nodesc_handler() */
776 : 0); /* use handle_ep() */
779 static void kick_dma(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
781 int is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
784 /* unaligned tx buffers and zlps only work with PIO */
785 if ((req
->req
.dma
& 0x0f) != 0
786 || unlikely((req
->req
.length
- req
->req
.actual
)
788 pio_irq_enable(ep
->bEndpointAddress
);
789 if ((*ep
->reg_udccs
& UDCCS_BI_TFS
) != 0)
790 (void) write_fifo(ep
, req
);
792 start_dma_nodesc(ep
, req
, USB_DIR_IN
);
795 if ((req
->req
.length
- req
->req
.actual
) < ep
->ep
.maxpacket
) {
796 DMSG("%s short dma read...\n", ep
->ep
.name
);
797 /* we're always set up for pio out */
800 *ep
->reg_udccs
= UDCCS_BO_DME
801 | (*ep
->reg_udccs
& UDCCS_BO_FST
);
802 start_dma_nodesc(ep
, req
, USB_DIR_OUT
);
807 static void cancel_dma(struct pxa2xx_ep
*ep
)
809 struct pxa2xx_request
*req
;
812 if (DCSR(ep
->dma
) == 0 || list_empty(&ep
->queue
))
816 while ((DCSR(ep
->dma
) & DCSR_STOPSTATE
) == 0)
819 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
820 tmp
= DCMD(ep
->dma
) & DCMD_LENGTH
;
821 req
->req
.actual
= req
->req
.length
- (tmp
& DCMD_LENGTH
);
823 /* the last tx packet may be incomplete, so flush the fifo.
824 * FIXME correct req.actual if we can
826 if (ep
->bEndpointAddress
& USB_DIR_IN
)
827 *ep
->reg_udccs
= UDCCS_BI_FTF
;
830 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
831 static void dma_nodesc_handler(int dmach
, void *_ep
, struct pt_regs
*r
)
833 struct pxa2xx_ep
*ep
= _ep
;
834 struct pxa2xx_request
*req
;
839 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
842 ep
->dev
->stats
.irqs
++;
843 HEX_DISPLAY(ep
->dev
->stats
.irqs
);
848 if ((tmp
& DCSR_STOPSTATE
) == 0
849 || (DDADR(ep
->dma
) & DDADR_STOP
) != 0) {
850 DBG(DBG_VERBOSE
, "%s, dcsr %08x ddadr %08x\n",
851 ep
->ep
.name
, DCSR(ep
->dma
), DDADR(ep
->dma
));
854 DCSR(ep
->dma
) = 0; /* clear DCSR_STOPSTATE */
856 /* update transfer status */
857 completed
= tmp
& DCSR_BUSERR
;
858 if (ep
->bEndpointAddress
& USB_DIR_IN
)
859 tmp
= DSADR(ep
->dma
);
861 tmp
= DTADR(ep
->dma
);
862 req
->req
.actual
= tmp
- req
->req
.dma
;
864 /* FIXME seems we sometimes see partial transfers... */
866 if (unlikely(completed
!= 0))
867 req
->req
.status
= -EIO
;
868 else if (req
->req
.actual
) {
869 /* these registers have zeroes in low bits; they miscount
870 * some (end-of-transfer) short packets: tx 14 as tx 12
873 req
->req
.actual
= min(req
->req
.actual
+ 3,
876 tmp
= (req
->req
.length
- req
->req
.actual
);
877 completed
= (tmp
== 0);
878 if (completed
&& (ep
->bEndpointAddress
& USB_DIR_IN
)) {
880 /* maybe validate final short packet ... */
881 if ((req
->req
.actual
% ep
->ep
.maxpacket
) != 0)
882 *ep
->reg_udccs
= UDCCS_BI_TSP
/*|UDCCS_BI_TPC*/;
884 /* ... or zlp, using pio fallback */
885 else if (ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
887 DMSG("%s zlp terminate ...\n", ep
->ep
.name
);
893 if (likely(completed
)) {
896 /* maybe re-activate after completion */
897 if (ep
->stopped
|| list_empty(&ep
->queue
))
899 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
908 /*-------------------------------------------------------------------------*/
911 pxa2xx_ep_queue(struct usb_ep
*_ep
, struct usb_request
*_req
, gfp_t gfp_flags
)
913 struct pxa2xx_request
*req
;
914 struct pxa2xx_ep
*ep
;
915 struct pxa2xx_udc
*dev
;
918 req
= container_of(_req
, struct pxa2xx_request
, req
);
919 if (unlikely (!_req
|| !_req
->complete
|| !_req
->buf
920 || !list_empty(&req
->queue
))) {
921 DMSG("%s, bad params\n", __FUNCTION__
);
925 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
926 if (unlikely (!_ep
|| (!ep
->desc
&& ep
->ep
.name
!= ep0name
))) {
927 DMSG("%s, bad ep\n", __FUNCTION__
);
932 if (unlikely (!dev
->driver
933 || dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)) {
934 DMSG("%s, bogus device state\n", __FUNCTION__
);
938 /* iso is always one packet per request, that's the only way
939 * we can report per-packet status. that also helps with dma.
941 if (unlikely (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
942 && req
->req
.length
> le16_to_cpu
943 (ep
->desc
->wMaxPacketSize
)))
947 // FIXME caller may already have done the dma mapping
949 _req
->dma
= dma_map_single(dev
->dev
,
950 _req
->buf
, _req
->length
,
951 ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0)
957 DBG(DBG_NOISY
, "%s queue req %p, len %d buf %p\n",
958 _ep
->name
, _req
, _req
->length
, _req
->buf
);
960 local_irq_save(flags
);
962 _req
->status
= -EINPROGRESS
;
965 /* kickstart this i/o queue? */
966 if (list_empty(&ep
->queue
) && !ep
->stopped
) {
967 if (ep
->desc
== 0 /* ep0 */) {
968 unsigned length
= _req
->length
;
970 switch (dev
->ep0state
) {
971 case EP0_IN_DATA_PHASE
:
972 dev
->stats
.write
.ops
++;
973 if (write_ep0_fifo(ep
, req
))
977 case EP0_OUT_DATA_PHASE
:
978 dev
->stats
.read
.ops
++;
980 if (dev
->req_config
) {
981 DBG(DBG_VERBOSE
, "ep0 config ack%s\n",
982 dev
->has_cfr
? "" : " raced");
984 UDCCFR
= UDCCFR_AREN
|UDCCFR_ACM
987 dev
->ep0state
= EP0_END_XFER
;
988 local_irq_restore (flags
);
991 if (dev
->req_pending
)
992 ep0start(dev
, UDCCS0_IPR
, "OUT");
993 if (length
== 0 || ((UDCCS0
& UDCCS0_RNE
) != 0
994 && read_ep0_fifo(ep
, req
))) {
1002 DMSG("ep0 i/o, odd state %d\n", dev
->ep0state
);
1003 local_irq_restore (flags
);
1007 /* either start dma or prime pio pump */
1008 } else if (ep
->dma
>= 0) {
1011 /* can the FIFO can satisfy the request immediately? */
1012 } else if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0) {
1013 if ((*ep
->reg_udccs
& UDCCS_BI_TFS
) != 0
1014 && write_fifo(ep
, req
))
1016 } else if ((*ep
->reg_udccs
& UDCCS_BO_RFS
) != 0
1017 && read_fifo(ep
, req
)) {
1021 if (likely (req
&& ep
->desc
) && ep
->dma
< 0)
1022 pio_irq_enable(ep
->bEndpointAddress
);
1025 /* pio or dma irq handler advances the queue. */
1026 if (likely (req
!= 0))
1027 list_add_tail(&req
->queue
, &ep
->queue
);
1028 local_irq_restore(flags
);
1035 * nuke - dequeue ALL requests
1037 static void nuke(struct pxa2xx_ep
*ep
, int status
)
1039 struct pxa2xx_request
*req
;
1041 /* called with irqs blocked */
1043 if (ep
->dma
>= 0 && !ep
->stopped
)
1046 while (!list_empty(&ep
->queue
)) {
1047 req
= list_entry(ep
->queue
.next
,
1048 struct pxa2xx_request
,
1050 done(ep
, req
, status
);
1053 pio_irq_disable (ep
->bEndpointAddress
);
1057 /* dequeue JUST ONE request */
1058 static int pxa2xx_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1060 struct pxa2xx_ep
*ep
;
1061 struct pxa2xx_request
*req
;
1062 unsigned long flags
;
1064 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1065 if (!_ep
|| ep
->ep
.name
== ep0name
)
1068 local_irq_save(flags
);
1070 /* make sure it's actually queued on this endpoint */
1071 list_for_each_entry (req
, &ep
->queue
, queue
) {
1072 if (&req
->req
== _req
)
1075 if (&req
->req
!= _req
) {
1076 local_irq_restore(flags
);
1081 if (ep
->dma
>= 0 && ep
->queue
.next
== &req
->queue
&& !ep
->stopped
) {
1083 done(ep
, req
, -ECONNRESET
);
1085 if (!list_empty(&ep
->queue
)) {
1086 req
= list_entry(ep
->queue
.next
,
1087 struct pxa2xx_request
, queue
);
1092 done(ep
, req
, -ECONNRESET
);
1094 local_irq_restore(flags
);
1098 /*-------------------------------------------------------------------------*/
1100 static int pxa2xx_ep_set_halt(struct usb_ep
*_ep
, int value
)
1102 struct pxa2xx_ep
*ep
;
1103 unsigned long flags
;
1105 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1107 || (!ep
->desc
&& ep
->ep
.name
!= ep0name
))
1108 || ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
1109 DMSG("%s, bad ep\n", __FUNCTION__
);
1113 /* this path (reset toggle+halt) is needed to implement
1114 * SET_INTERFACE on normal hardware. but it can't be
1115 * done from software on the PXA UDC, and the hardware
1116 * forgets to do it as part of SET_INTERFACE automagic.
1118 DMSG("only host can clear %s halt\n", _ep
->name
);
1122 local_irq_save(flags
);
1124 if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0
1125 && ((*ep
->reg_udccs
& UDCCS_BI_TFS
) == 0
1126 || !list_empty(&ep
->queue
))) {
1127 local_irq_restore(flags
);
1131 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1132 *ep
->reg_udccs
= UDCCS_BI_FST
|UDCCS_BI_FTF
;
1134 /* ep0 needs special care */
1136 start_watchdog(ep
->dev
);
1137 ep
->dev
->req_pending
= 0;
1138 ep
->dev
->ep0state
= EP0_STALL
;
1140 /* and bulk/intr endpoints like dropping stalls too */
1143 for (i
= 0; i
< 1000; i
+= 20) {
1144 if (*ep
->reg_udccs
& UDCCS_BI_SST
)
1149 local_irq_restore(flags
);
1151 DBG(DBG_VERBOSE
, "%s halt\n", _ep
->name
);
1155 static int pxa2xx_ep_fifo_status(struct usb_ep
*_ep
)
1157 struct pxa2xx_ep
*ep
;
1159 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1161 DMSG("%s, bad ep\n", __FUNCTION__
);
1164 /* pxa can't report unclaimed bytes from IN fifos */
1165 if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0)
1167 if (ep
->dev
->gadget
.speed
== USB_SPEED_UNKNOWN
1168 || (*ep
->reg_udccs
& UDCCS_BO_RFS
) == 0)
1171 return (*ep
->reg_ubcr
& 0xfff) + 1;
1174 static void pxa2xx_ep_fifo_flush(struct usb_ep
*_ep
)
1176 struct pxa2xx_ep
*ep
;
1178 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1179 if (!_ep
|| ep
->ep
.name
== ep0name
|| !list_empty(&ep
->queue
)) {
1180 DMSG("%s, bad ep\n", __FUNCTION__
);
1184 /* toggle and halt bits stay unchanged */
1186 /* for OUT, just read and discard the FIFO contents. */
1187 if ((ep
->bEndpointAddress
& USB_DIR_IN
) == 0) {
1188 while (((*ep
->reg_udccs
) & UDCCS_BO_RNE
) != 0)
1189 (void) *ep
->reg_uddr
;
1193 /* most IN status is the same, but ISO can't stall */
1194 *ep
->reg_udccs
= UDCCS_BI_TPC
|UDCCS_BI_FTF
|UDCCS_BI_TUR
1195 | (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
)
1200 static struct usb_ep_ops pxa2xx_ep_ops
= {
1201 .enable
= pxa2xx_ep_enable
,
1202 .disable
= pxa2xx_ep_disable
,
1204 .alloc_request
= pxa2xx_ep_alloc_request
,
1205 .free_request
= pxa2xx_ep_free_request
,
1207 .alloc_buffer
= pxa2xx_ep_alloc_buffer
,
1208 .free_buffer
= pxa2xx_ep_free_buffer
,
1210 .queue
= pxa2xx_ep_queue
,
1211 .dequeue
= pxa2xx_ep_dequeue
,
1213 .set_halt
= pxa2xx_ep_set_halt
,
1214 .fifo_status
= pxa2xx_ep_fifo_status
,
1215 .fifo_flush
= pxa2xx_ep_fifo_flush
,
1219 /* ---------------------------------------------------------------------------
1220 * device-scoped parts of the api to the usb controller hardware
1221 * ---------------------------------------------------------------------------
1224 static int pxa2xx_udc_get_frame(struct usb_gadget
*_gadget
)
1226 return ((UFNRH
& 0x07) << 8) | (UFNRL
& 0xff);
1229 static int pxa2xx_udc_wakeup(struct usb_gadget
*_gadget
)
1231 /* host may not have enabled remote wakeup */
1232 if ((UDCCS0
& UDCCS0_DRWF
) == 0)
1233 return -EHOSTUNREACH
;
1234 udc_set_mask_UDCCR(UDCCR_RSM
);
1238 static void stop_activity(struct pxa2xx_udc
*, struct usb_gadget_driver
*);
1239 static void udc_enable (struct pxa2xx_udc
*);
1240 static void udc_disable(struct pxa2xx_udc
*);
1242 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1245 static int pullup(struct pxa2xx_udc
*udc
, int is_active
)
1247 is_active
= is_active
&& udc
->vbus
&& udc
->pullup
;
1248 DMSG("%s\n", is_active
? "active" : "inactive");
1252 if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
1253 DMSG("disconnect %s\n", udc
->driver
1254 ? udc
->driver
->driver
.name
1256 stop_activity(udc
, udc
->driver
);
1263 /* VBUS reporting logically comes from a transceiver */
1264 static int pxa2xx_udc_vbus_session(struct usb_gadget
*_gadget
, int is_active
)
1266 struct pxa2xx_udc
*udc
;
1268 udc
= container_of(_gadget
, struct pxa2xx_udc
, gadget
);
1269 udc
->vbus
= is_active
= (is_active
!= 0);
1270 DMSG("vbus %s\n", is_active
? "supplied" : "inactive");
1271 pullup(udc
, is_active
);
1275 /* drivers may have software control over D+ pullup */
1276 static int pxa2xx_udc_pullup(struct usb_gadget
*_gadget
, int is_active
)
1278 struct pxa2xx_udc
*udc
;
1280 udc
= container_of(_gadget
, struct pxa2xx_udc
, gadget
);
1282 /* not all boards support pullup control */
1283 if (!udc
->mach
->udc_command
)
1286 is_active
= (is_active
!= 0);
1287 udc
->pullup
= is_active
;
1288 pullup(udc
, is_active
);
1292 static const struct usb_gadget_ops pxa2xx_udc_ops
= {
1293 .get_frame
= pxa2xx_udc_get_frame
,
1294 .wakeup
= pxa2xx_udc_wakeup
,
1295 .vbus_session
= pxa2xx_udc_vbus_session
,
1296 .pullup
= pxa2xx_udc_pullup
,
1298 // .vbus_draw ... boards may consume current from VBUS, up to
1299 // 100-500mA based on config. the 500uA suspend ceiling means
1300 // that exclusively vbus-powered PXA designs violate USB specs.
1303 /*-------------------------------------------------------------------------*/
1305 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1307 static const char proc_node_name
[] = "driver/udc";
1310 udc_proc_read(char *page
, char **start
, off_t off
, int count
,
1311 int *eof
, void *_dev
)
1314 struct pxa2xx_udc
*dev
= _dev
;
1316 unsigned size
= count
;
1317 unsigned long flags
;
1324 local_irq_save(flags
);
1326 /* basic device status */
1327 t
= scnprintf(next
, size
, DRIVER_DESC
"\n"
1328 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1329 driver_name
, DRIVER_VERSION SIZE_STR DMASTR
,
1330 dev
->driver
? dev
->driver
->driver
.name
: "(none)",
1331 is_vbus_present() ? "full speed" : "disconnected");
1335 /* registers for device and ep0 */
1336 t
= scnprintf(next
, size
,
1337 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1338 UICR1
, UICR0
, USIR1
, USIR0
, UFNRH
, UFNRL
);
1343 t
= scnprintf(next
, size
,
1344 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp
,
1345 (tmp
& UDCCR_REM
) ? " rem" : "",
1346 (tmp
& UDCCR_RSTIR
) ? " rstir" : "",
1347 (tmp
& UDCCR_SRM
) ? " srm" : "",
1348 (tmp
& UDCCR_SUSIR
) ? " susir" : "",
1349 (tmp
& UDCCR_RESIR
) ? " resir" : "",
1350 (tmp
& UDCCR_RSM
) ? " rsm" : "",
1351 (tmp
& UDCCR_UDA
) ? " uda" : "",
1352 (tmp
& UDCCR_UDE
) ? " ude" : "");
1357 t
= scnprintf(next
, size
,
1358 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp
,
1359 (tmp
& UDCCS0_SA
) ? " sa" : "",
1360 (tmp
& UDCCS0_RNE
) ? " rne" : "",
1361 (tmp
& UDCCS0_FST
) ? " fst" : "",
1362 (tmp
& UDCCS0_SST
) ? " sst" : "",
1363 (tmp
& UDCCS0_DRWF
) ? " dwrf" : "",
1364 (tmp
& UDCCS0_FTF
) ? " ftf" : "",
1365 (tmp
& UDCCS0_IPR
) ? " ipr" : "",
1366 (tmp
& UDCCS0_OPR
) ? " opr" : "");
1372 t
= scnprintf(next
, size
,
1373 "udccfr %02X =%s%s\n", tmp
,
1374 (tmp
& UDCCFR_AREN
) ? " aren" : "",
1375 (tmp
& UDCCFR_ACM
) ? " acm" : "");
1380 if (!is_vbus_present() || !dev
->driver
)
1383 t
= scnprintf(next
, size
, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1384 dev
->stats
.write
.bytes
, dev
->stats
.write
.ops
,
1385 dev
->stats
.read
.bytes
, dev
->stats
.read
.ops
,
1390 /* dump endpoint queues */
1391 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1392 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1393 struct pxa2xx_request
*req
;
1397 const struct usb_endpoint_descriptor
*d
;
1402 tmp
= *dev
->ep
[i
].reg_udccs
;
1403 t
= scnprintf(next
, size
,
1404 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1405 ep
->ep
.name
, le16_to_cpu (d
->wMaxPacketSize
),
1406 (ep
->dma
>= 0) ? "dma" : "pio", tmp
,
1407 ep
->pio_irqs
, ep
->dma_irqs
);
1408 /* TODO translate all five groups of udccs bits! */
1410 } else /* ep0 should only have one transfer queued */
1411 t
= scnprintf(next
, size
, "ep0 max 16 pio irqs %lu\n",
1413 if (t
<= 0 || t
> size
)
1418 if (list_empty(&ep
->queue
)) {
1419 t
= scnprintf(next
, size
, "\t(nothing queued)\n");
1420 if (t
<= 0 || t
> size
)
1426 list_for_each_entry(req
, &ep
->queue
, queue
) {
1428 if (ep
->dma
>= 0 && req
->queue
.prev
== &ep
->queue
)
1429 t
= scnprintf(next
, size
,
1430 "\treq %p len %d/%d "
1431 "buf %p (dma%d dcmd %08x)\n",
1432 &req
->req
, req
->req
.actual
,
1433 req
->req
.length
, req
->req
.buf
,
1434 ep
->dma
, DCMD(ep
->dma
)
1435 // low 13 bits == bytes-to-go
1439 t
= scnprintf(next
, size
,
1440 "\treq %p len %d/%d buf %p\n",
1441 &req
->req
, req
->req
.actual
,
1442 req
->req
.length
, req
->req
.buf
);
1443 if (t
<= 0 || t
> size
)
1451 local_irq_restore(flags
);
1453 return count
- size
;
1456 #define create_proc_files() \
1457 create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1458 #define remove_proc_files() \
1459 remove_proc_entry(proc_node_name, NULL)
1461 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
1463 #define create_proc_files() do {} while (0)
1464 #define remove_proc_files() do {} while (0)
1466 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
1468 /* "function" sysfs attribute */
1470 show_function (struct device
*_dev
, struct device_attribute
*attr
, char *buf
)
1472 struct pxa2xx_udc
*dev
= dev_get_drvdata (_dev
);
1475 || !dev
->driver
->function
1476 || strlen (dev
->driver
->function
) > PAGE_SIZE
)
1478 return scnprintf (buf
, PAGE_SIZE
, "%s\n", dev
->driver
->function
);
1480 static DEVICE_ATTR (function
, S_IRUGO
, show_function
, NULL
);
1482 /*-------------------------------------------------------------------------*/
1485 * udc_disable - disable USB device controller
1487 static void udc_disable(struct pxa2xx_udc
*dev
)
1489 /* block all irqs */
1490 udc_set_mask_UDCCR(UDCCR_SRM
|UDCCR_REM
);
1491 UICR0
= UICR1
= 0xff;
1494 /* if hardware supports it, disconnect from usb */
1497 udc_clear_mask_UDCCR(UDCCR_UDE
);
1499 #ifdef CONFIG_ARCH_PXA
1500 /* Disable clock for USB device */
1501 pxa_set_cken(CKEN11_USB
, 0);
1505 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1511 * udc_reinit - initialize software state
1513 static void udc_reinit(struct pxa2xx_udc
*dev
)
1517 /* device/ep0 records init */
1518 INIT_LIST_HEAD (&dev
->gadget
.ep_list
);
1519 INIT_LIST_HEAD (&dev
->gadget
.ep0
->ep_list
);
1520 dev
->ep0state
= EP0_IDLE
;
1522 /* basic endpoint records init */
1523 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1524 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1527 list_add_tail (&ep
->ep
.ep_list
, &dev
->gadget
.ep_list
);
1531 INIT_LIST_HEAD (&ep
->queue
);
1532 ep
->pio_irqs
= ep
->dma_irqs
= 0;
1535 /* the rest was statically initialized, and is read-only */
1538 /* until it's enabled, this UDC should be completely invisible
1541 static void udc_enable (struct pxa2xx_udc
*dev
)
1543 udc_clear_mask_UDCCR(UDCCR_UDE
);
1545 #ifdef CONFIG_ARCH_PXA
1546 /* Enable clock for USB device */
1547 pxa_set_cken(CKEN11_USB
, 1);
1551 /* try to clear these bits before we enable the udc */
1552 udc_ack_int_UDCCR(UDCCR_SUSIR
|/*UDCCR_RSTIR|*/UDCCR_RESIR
);
1555 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1556 dev
->stats
.irqs
= 0;
1559 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1561 * - if RESET is already in progress, ack interrupt
1562 * - unmask reset interrupt
1564 udc_set_mask_UDCCR(UDCCR_UDE
);
1565 if (!(UDCCR
& UDCCR_UDA
))
1566 udc_ack_int_UDCCR(UDCCR_RSTIR
);
1568 if (dev
->has_cfr
/* UDC_RES2 is defined */) {
1569 /* pxa255 (a0+) can avoid a set_config race that could
1570 * prevent gadget drivers from configuring correctly
1572 UDCCFR
= UDCCFR_ACM
| UDCCFR_MB1
;
1574 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1575 * which could result in missing packets and interrupts.
1576 * supposedly one bit per endpoint, controlling whether it
1577 * double buffers or not; ACM/AREN bits fit into the holes.
1578 * zero bits (like USIR0_IRx) disable double buffering.
1584 #ifdef DISABLE_TEST_MODE
1585 /* "test mode" seems to have become the default in later chip
1586 * revs, preventing double buffering (and invalidating docs).
1587 * this EXPERIMENT enables it for bulk endpoints by tweaking
1588 * undefined/reserved register bits (that other drivers clear).
1589 * Belcarra code comments noted this usage.
1591 if (fifo_mode
& 1) { /* IN endpoints */
1592 UDC_RES1
|= USIR0_IR1
|USIR0_IR6
;
1593 UDC_RES2
|= USIR1_IR11
;
1595 if (fifo_mode
& 2) { /* OUT endpoints */
1596 UDC_RES1
|= USIR0_IR2
|USIR0_IR7
;
1597 UDC_RES2
|= USIR1_IR12
;
1601 /* enable suspend/resume and reset irqs */
1602 udc_clear_mask_UDCCR(UDCCR_SRM
| UDCCR_REM
);
1604 /* enable ep0 irqs */
1605 UICR0
&= ~UICR0_IM0
;
1607 /* if hardware supports it, pullup D+ and wait for reset */
1612 /* when a driver is successfully registered, it will receive
1613 * control requests including set_configuration(), which enables
1614 * non-control requests. then usb traffic follows until a
1615 * disconnect is reported. then a host may connect again, or
1616 * the driver might get unbound.
1618 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
1620 struct pxa2xx_udc
*dev
= the_controller
;
1624 || driver
->speed
< USB_SPEED_FULL
1627 || !driver
->disconnect
1635 /* first hook up the driver ... */
1636 dev
->driver
= driver
;
1637 dev
->gadget
.dev
.driver
= &driver
->driver
;
1640 device_add (&dev
->gadget
.dev
);
1641 retval
= driver
->bind(&dev
->gadget
);
1643 DMSG("bind to driver %s --> error %d\n",
1644 driver
->driver
.name
, retval
);
1645 device_del (&dev
->gadget
.dev
);
1648 dev
->gadget
.dev
.driver
= NULL
;
1651 device_create_file(dev
->dev
, &dev_attr_function
);
1653 /* ... then enable host detection and ep0; and we're ready
1654 * for set_configuration as well as eventual disconnect.
1656 DMSG("registered gadget driver '%s'\n", driver
->driver
.name
);
1661 EXPORT_SYMBOL(usb_gadget_register_driver
);
1664 stop_activity(struct pxa2xx_udc
*dev
, struct usb_gadget_driver
*driver
)
1668 /* don't disconnect drivers more than once */
1669 if (dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1671 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1673 /* prevent new request submissions, kill any outstanding requests */
1674 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1675 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1678 nuke(ep
, -ESHUTDOWN
);
1680 del_timer_sync(&dev
->timer
);
1682 /* report disconnect; the driver is already quiesced */
1685 driver
->disconnect(&dev
->gadget
);
1687 /* re-init driver-visible data structures */
1691 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1693 struct pxa2xx_udc
*dev
= the_controller
;
1697 if (!driver
|| driver
!= dev
->driver
)
1700 local_irq_disable();
1702 stop_activity(dev
, driver
);
1705 driver
->unbind(&dev
->gadget
);
1708 device_del (&dev
->gadget
.dev
);
1709 device_remove_file(dev
->dev
, &dev_attr_function
);
1711 DMSG("unregistered gadget driver '%s'\n", driver
->driver
.name
);
1715 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1718 /*-------------------------------------------------------------------------*/
1720 #ifdef CONFIG_ARCH_LUBBOCK
1722 /* Lubbock has separate connect and disconnect irqs. More typical designs
1723 * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1727 lubbock_vbus_irq(int irq
, void *_dev
, struct pt_regs
*r
)
1729 struct pxa2xx_udc
*dev
= _dev
;
1733 HEX_DISPLAY(dev
->stats
.irqs
);
1735 case LUBBOCK_USB_IRQ
:
1738 disable_irq(LUBBOCK_USB_IRQ
);
1739 enable_irq(LUBBOCK_USB_DISC_IRQ
);
1741 case LUBBOCK_USB_DISC_IRQ
:
1744 disable_irq(LUBBOCK_USB_DISC_IRQ
);
1745 enable_irq(LUBBOCK_USB_IRQ
);
1751 pxa2xx_udc_vbus_session(&dev
->gadget
, vbus
);
1758 udc_vbus_irq(int irq
, void *_dev
, struct pt_regs
*r
)
1760 struct pxa2xx_udc
*dev
= _dev
;
1761 int vbus
= pxa_gpio_get(dev
->mach
->gpio_vbus
);
1763 pxa2xx_udc_vbus_session(&dev
->gadget
, vbus
);
1768 /*-------------------------------------------------------------------------*/
1770 static inline void clear_ep_state (struct pxa2xx_udc
*dev
)
1774 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1775 * fifos, and pending transactions mustn't be continued in any case.
1777 for (i
= 1; i
< PXA_UDC_NUM_ENDPOINTS
; i
++)
1778 nuke(&dev
->ep
[i
], -ECONNABORTED
);
1781 static void udc_watchdog(unsigned long _dev
)
1783 struct pxa2xx_udc
*dev
= (void *)_dev
;
1785 local_irq_disable();
1786 if (dev
->ep0state
== EP0_STALL
1787 && (UDCCS0
& UDCCS0_FST
) == 0
1788 && (UDCCS0
& UDCCS0_SST
) == 0) {
1789 UDCCS0
= UDCCS0_FST
|UDCCS0_FTF
;
1790 DBG(DBG_VERBOSE
, "ep0 re-stall\n");
1791 start_watchdog(dev
);
1796 static void handle_ep0 (struct pxa2xx_udc
*dev
)
1798 u32 udccs0
= UDCCS0
;
1799 struct pxa2xx_ep
*ep
= &dev
->ep
[0];
1800 struct pxa2xx_request
*req
;
1802 struct usb_ctrlrequest r
;
1807 if (list_empty(&ep
->queue
))
1810 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
1812 /* clear stall status */
1813 if (udccs0
& UDCCS0_SST
) {
1815 UDCCS0
= UDCCS0_SST
;
1816 del_timer(&dev
->timer
);
1820 /* previous request unfinished? non-error iff back-to-back ... */
1821 if ((udccs0
& UDCCS0_SA
) != 0 && dev
->ep0state
!= EP0_IDLE
) {
1823 del_timer(&dev
->timer
);
1827 switch (dev
->ep0state
) {
1829 /* late-breaking status? */
1832 /* start control request? */
1833 if (likely((udccs0
& (UDCCS0_OPR
|UDCCS0_SA
|UDCCS0_RNE
))
1834 == (UDCCS0_OPR
|UDCCS0_SA
|UDCCS0_RNE
))) {
1839 /* read SETUP packet */
1840 for (i
= 0; i
< 8; i
++) {
1841 if (unlikely(!(UDCCS0
& UDCCS0_RNE
))) {
1843 DMSG("SETUP %d!\n", i
);
1846 u
.raw
[i
] = (u8
) UDDR0
;
1848 if (unlikely((UDCCS0
& UDCCS0_RNE
) != 0))
1852 DBG(DBG_VERBOSE
, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1853 u
.r
.bRequestType
, u
.r
.bRequest
,
1854 le16_to_cpu(u
.r
.wValue
),
1855 le16_to_cpu(u
.r
.wIndex
),
1856 le16_to_cpu(u
.r
.wLength
));
1858 /* cope with automagic for some standard requests. */
1859 dev
->req_std
= (u
.r
.bRequestType
& USB_TYPE_MASK
)
1860 == USB_TYPE_STANDARD
;
1861 dev
->req_config
= 0;
1862 dev
->req_pending
= 1;
1863 switch (u
.r
.bRequest
) {
1864 /* hardware restricts gadget drivers here! */
1865 case USB_REQ_SET_CONFIGURATION
:
1866 if (u
.r
.bRequestType
== USB_RECIP_DEVICE
) {
1867 /* reflect hardware's automagic
1868 * up to the gadget driver.
1871 dev
->req_config
= 1;
1872 clear_ep_state(dev
);
1873 /* if !has_cfr, there's no synch
1874 * else use AREN (later) not SA|OPR
1875 * USIR0_IR0 acts edge sensitive
1879 /* ... and here, even more ... */
1880 case USB_REQ_SET_INTERFACE
:
1881 if (u
.r
.bRequestType
== USB_RECIP_INTERFACE
) {
1882 /* udc hardware is broken by design:
1883 * - altsetting may only be zero;
1884 * - hw resets all interfaces' eps;
1885 * - ep reset doesn't include halt(?).
1887 DMSG("broken set_interface (%d/%d)\n",
1888 le16_to_cpu(u
.r
.wIndex
),
1889 le16_to_cpu(u
.r
.wValue
));
1893 /* hardware was supposed to hide this */
1894 case USB_REQ_SET_ADDRESS
:
1895 if (u
.r
.bRequestType
== USB_RECIP_DEVICE
) {
1896 ep0start(dev
, 0, "address");
1902 if (u
.r
.bRequestType
& USB_DIR_IN
)
1903 dev
->ep0state
= EP0_IN_DATA_PHASE
;
1905 dev
->ep0state
= EP0_OUT_DATA_PHASE
;
1907 i
= dev
->driver
->setup(&dev
->gadget
, &u
.r
);
1909 /* hardware automagic preventing STALL... */
1910 if (dev
->req_config
) {
1911 /* hardware sometimes neglects to tell
1912 * tell us about config change events,
1913 * so later ones may fail...
1915 WARN("config change %02x fail %d?\n",
1918 /* TODO experiment: if has_cfr,
1919 * hardware didn't ACK; maybe we
1920 * could actually STALL!
1923 DBG(DBG_VERBOSE
, "protocol STALL, "
1924 "%02x err %d\n", UDCCS0
, i
);
1926 /* the watchdog timer helps deal with cases
1927 * where udc seems to clear FST wrongly, and
1928 * then NAKs instead of STALLing.
1930 ep0start(dev
, UDCCS0_FST
|UDCCS0_FTF
, "stall");
1931 start_watchdog(dev
);
1932 dev
->ep0state
= EP0_STALL
;
1934 /* deferred i/o == no response yet */
1935 } else if (dev
->req_pending
) {
1936 if (likely(dev
->ep0state
== EP0_IN_DATA_PHASE
1937 || dev
->req_std
|| u
.r
.wLength
))
1938 ep0start(dev
, 0, "defer");
1940 ep0start(dev
, UDCCS0_IPR
, "defer/IPR");
1943 /* expect at least one data or status stage irq */
1946 } else if (likely((udccs0
& (UDCCS0_OPR
|UDCCS0_SA
))
1947 == (UDCCS0_OPR
|UDCCS0_SA
))) {
1950 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1951 * still observed on a pxa255 a0.
1953 DBG(DBG_VERBOSE
, "e131\n");
1956 /* read SETUP data, but don't trust it too much */
1957 for (i
= 0; i
< 8; i
++)
1958 u
.raw
[i
] = (u8
) UDDR0
;
1959 if ((u
.r
.bRequestType
& USB_RECIP_MASK
)
1962 if (u
.word
[0] == 0 && u
.word
[1] == 0)
1966 /* some random early IRQ:
1969 * - OPR got set, without SA (likely status stage)
1971 UDCCS0
= udccs0
& (UDCCS0_SA
|UDCCS0_OPR
);
1974 case EP0_IN_DATA_PHASE
: /* GET_DESCRIPTOR etc */
1975 if (udccs0
& UDCCS0_OPR
) {
1976 UDCCS0
= UDCCS0_OPR
|UDCCS0_FTF
;
1977 DBG(DBG_VERBOSE
, "ep0in premature status\n");
1981 } else /* irq was IPR clearing */ {
1983 /* this IN packet might finish the request */
1984 (void) write_ep0_fifo(ep
, req
);
1985 } /* else IN token before response was written */
1988 case EP0_OUT_DATA_PHASE
: /* SET_DESCRIPTOR etc */
1989 if (udccs0
& UDCCS0_OPR
) {
1991 /* this OUT packet might finish the request */
1992 if (read_ep0_fifo(ep
, req
))
1994 /* else more OUT packets expected */
1995 } /* else OUT token before read was issued */
1996 } else /* irq was IPR clearing */ {
1997 DBG(DBG_VERBOSE
, "ep0out premature status\n");
2006 /* ack control-IN status (maybe in-zlp was skipped)
2007 * also appears after some config change events.
2009 if (udccs0
& UDCCS0_OPR
)
2010 UDCCS0
= UDCCS0_OPR
;
2014 UDCCS0
= UDCCS0_FST
;
2020 static void handle_ep(struct pxa2xx_ep
*ep
)
2022 struct pxa2xx_request
*req
;
2023 int is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
2029 if (likely (!list_empty(&ep
->queue
)))
2030 req
= list_entry(ep
->queue
.next
,
2031 struct pxa2xx_request
, queue
);
2035 // TODO check FST handling
2037 udccs
= *ep
->reg_udccs
;
2038 if (unlikely(is_in
)) { /* irq from TPC, SST, or (ISO) TUR */
2040 if (likely(ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
))
2041 tmp
|= UDCCS_BI_SST
;
2044 *ep
->reg_udccs
= tmp
;
2045 if (req
&& likely ((udccs
& UDCCS_BI_TFS
) != 0))
2046 completed
= write_fifo(ep
, req
);
2048 } else { /* irq from RPC (or for ISO, ROF) */
2049 if (likely(ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
))
2050 tmp
= UDCCS_BO_SST
| UDCCS_BO_DME
;
2052 tmp
= UDCCS_IO_ROF
| UDCCS_IO_DME
;
2055 *ep
->reg_udccs
= tmp
;
2057 /* fifos can hold packets, ready for reading... */
2060 // TODO didn't yet debug out-dma. this approach assumes
2061 // the worst about short packets and RPC; it might be better.
2063 if (likely(ep
->dma
>= 0)) {
2064 if (!(udccs
& UDCCS_BO_RSP
)) {
2065 *ep
->reg_udccs
= UDCCS_BO_RPC
;
2071 completed
= read_fifo(ep
, req
);
2073 pio_irq_disable (ep
->bEndpointAddress
);
2076 } while (completed
);
2080 * pxa2xx_udc_irq - interrupt handler
2082 * avoid delays in ep0 processing. the control handshaking isn't always
2083 * under software control (pxa250c0 and the pxa255 are better), and delays
2084 * could cause usb protocol errors.
2087 pxa2xx_udc_irq(int irq
, void *_dev
, struct pt_regs
*r
)
2089 struct pxa2xx_udc
*dev
= _dev
;
2093 HEX_DISPLAY(dev
->stats
.irqs
);
2099 /* SUSpend Interrupt Request */
2100 if (unlikely(udccr
& UDCCR_SUSIR
)) {
2101 udc_ack_int_UDCCR(UDCCR_SUSIR
);
2103 DBG(DBG_VERBOSE
, "USB suspend%s\n", is_vbus_present()
2104 ? "" : "+disconnect");
2106 if (!is_vbus_present())
2107 stop_activity(dev
, dev
->driver
);
2108 else if (dev
->gadget
.speed
!= USB_SPEED_UNKNOWN
2110 && dev
->driver
->suspend
)
2111 dev
->driver
->suspend(&dev
->gadget
);
2115 /* RESume Interrupt Request */
2116 if (unlikely(udccr
& UDCCR_RESIR
)) {
2117 udc_ack_int_UDCCR(UDCCR_RESIR
);
2119 DBG(DBG_VERBOSE
, "USB resume\n");
2121 if (dev
->gadget
.speed
!= USB_SPEED_UNKNOWN
2123 && dev
->driver
->resume
2124 && is_vbus_present())
2125 dev
->driver
->resume(&dev
->gadget
);
2128 /* ReSeT Interrupt Request - USB reset */
2129 if (unlikely(udccr
& UDCCR_RSTIR
)) {
2130 udc_ack_int_UDCCR(UDCCR_RSTIR
);
2133 if ((UDCCR
& UDCCR_UDA
) == 0) {
2134 DBG(DBG_VERBOSE
, "USB reset start\n");
2136 /* reset driver and endpoints,
2137 * in case that's not yet done
2139 stop_activity (dev
, dev
->driver
);
2142 DBG(DBG_VERBOSE
, "USB reset end\n");
2143 dev
->gadget
.speed
= USB_SPEED_FULL
;
2145 memset(&dev
->stats
, 0, sizeof dev
->stats
);
2146 /* driver and endpoints are still reset */
2150 u32 usir0
= USIR0
& ~UICR0
;
2151 u32 usir1
= USIR1
& ~UICR1
;
2154 if (unlikely (!usir0
&& !usir1
))
2157 DBG(DBG_VERY_NOISY
, "irq %02x.%02x\n", usir1
, usir0
);
2159 /* control traffic */
2160 if (usir0
& USIR0_IR0
) {
2161 dev
->ep
[0].pio_irqs
++;
2166 /* endpoint data transfers */
2167 for (i
= 0; i
< 8; i
++) {
2170 if (i
&& (usir0
& tmp
)) {
2171 handle_ep(&dev
->ep
[i
]);
2176 handle_ep(&dev
->ep
[i
+8]);
2183 /* we could also ask for 1 msec SOF (SIR) interrupts */
2189 /*-------------------------------------------------------------------------*/
2191 static void nop_release (struct device
*dev
)
2193 DMSG("%s %s\n", __FUNCTION__
, dev
->bus_id
);
2196 /* this uses load-time allocation and initialization (instead of
2197 * doing it at run-time) to save code, eliminate fault paths, and
2198 * be more obviously correct.
2200 static struct pxa2xx_udc memory
= {
2202 .ops
= &pxa2xx_udc_ops
,
2203 .ep0
= &memory
.ep
[0].ep
,
2204 .name
= driver_name
,
2207 .release
= nop_release
,
2211 /* control endpoint */
2215 .ops
= &pxa2xx_ep_ops
,
2216 .maxpacket
= EP0_FIFO_SIZE
,
2219 .reg_udccs
= &UDCCS0
,
2223 /* first group of endpoints */
2226 .name
= "ep1in-bulk",
2227 .ops
= &pxa2xx_ep_ops
,
2228 .maxpacket
= BULK_FIFO_SIZE
,
2231 .fifo_size
= BULK_FIFO_SIZE
,
2232 .bEndpointAddress
= USB_DIR_IN
| 1,
2233 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2234 .reg_udccs
= &UDCCS1
,
2240 .name
= "ep2out-bulk",
2241 .ops
= &pxa2xx_ep_ops
,
2242 .maxpacket
= BULK_FIFO_SIZE
,
2245 .fifo_size
= BULK_FIFO_SIZE
,
2246 .bEndpointAddress
= 2,
2247 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2248 .reg_udccs
= &UDCCS2
,
2253 #ifndef CONFIG_USB_PXA2XX_SMALL
2256 .name
= "ep3in-iso",
2257 .ops
= &pxa2xx_ep_ops
,
2258 .maxpacket
= ISO_FIFO_SIZE
,
2261 .fifo_size
= ISO_FIFO_SIZE
,
2262 .bEndpointAddress
= USB_DIR_IN
| 3,
2263 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2264 .reg_udccs
= &UDCCS3
,
2270 .name
= "ep4out-iso",
2271 .ops
= &pxa2xx_ep_ops
,
2272 .maxpacket
= ISO_FIFO_SIZE
,
2275 .fifo_size
= ISO_FIFO_SIZE
,
2276 .bEndpointAddress
= 4,
2277 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2278 .reg_udccs
= &UDCCS4
,
2285 .name
= "ep5in-int",
2286 .ops
= &pxa2xx_ep_ops
,
2287 .maxpacket
= INT_FIFO_SIZE
,
2290 .fifo_size
= INT_FIFO_SIZE
,
2291 .bEndpointAddress
= USB_DIR_IN
| 5,
2292 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2293 .reg_udccs
= &UDCCS5
,
2297 /* second group of endpoints */
2300 .name
= "ep6in-bulk",
2301 .ops
= &pxa2xx_ep_ops
,
2302 .maxpacket
= BULK_FIFO_SIZE
,
2305 .fifo_size
= BULK_FIFO_SIZE
,
2306 .bEndpointAddress
= USB_DIR_IN
| 6,
2307 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2308 .reg_udccs
= &UDCCS6
,
2314 .name
= "ep7out-bulk",
2315 .ops
= &pxa2xx_ep_ops
,
2316 .maxpacket
= BULK_FIFO_SIZE
,
2319 .fifo_size
= BULK_FIFO_SIZE
,
2320 .bEndpointAddress
= 7,
2321 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2322 .reg_udccs
= &UDCCS7
,
2329 .name
= "ep8in-iso",
2330 .ops
= &pxa2xx_ep_ops
,
2331 .maxpacket
= ISO_FIFO_SIZE
,
2334 .fifo_size
= ISO_FIFO_SIZE
,
2335 .bEndpointAddress
= USB_DIR_IN
| 8,
2336 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2337 .reg_udccs
= &UDCCS8
,
2343 .name
= "ep9out-iso",
2344 .ops
= &pxa2xx_ep_ops
,
2345 .maxpacket
= ISO_FIFO_SIZE
,
2348 .fifo_size
= ISO_FIFO_SIZE
,
2349 .bEndpointAddress
= 9,
2350 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2351 .reg_udccs
= &UDCCS9
,
2358 .name
= "ep10in-int",
2359 .ops
= &pxa2xx_ep_ops
,
2360 .maxpacket
= INT_FIFO_SIZE
,
2363 .fifo_size
= INT_FIFO_SIZE
,
2364 .bEndpointAddress
= USB_DIR_IN
| 10,
2365 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2366 .reg_udccs
= &UDCCS10
,
2367 .reg_uddr
= &UDDR10
,
2370 /* third group of endpoints */
2373 .name
= "ep11in-bulk",
2374 .ops
= &pxa2xx_ep_ops
,
2375 .maxpacket
= BULK_FIFO_SIZE
,
2378 .fifo_size
= BULK_FIFO_SIZE
,
2379 .bEndpointAddress
= USB_DIR_IN
| 11,
2380 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2381 .reg_udccs
= &UDCCS11
,
2382 .reg_uddr
= &UDDR11
,
2387 .name
= "ep12out-bulk",
2388 .ops
= &pxa2xx_ep_ops
,
2389 .maxpacket
= BULK_FIFO_SIZE
,
2392 .fifo_size
= BULK_FIFO_SIZE
,
2393 .bEndpointAddress
= 12,
2394 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2395 .reg_udccs
= &UDCCS12
,
2396 .reg_ubcr
= &UBCR12
,
2397 .reg_uddr
= &UDDR12
,
2402 .name
= "ep13in-iso",
2403 .ops
= &pxa2xx_ep_ops
,
2404 .maxpacket
= ISO_FIFO_SIZE
,
2407 .fifo_size
= ISO_FIFO_SIZE
,
2408 .bEndpointAddress
= USB_DIR_IN
| 13,
2409 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2410 .reg_udccs
= &UDCCS13
,
2411 .reg_uddr
= &UDDR13
,
2416 .name
= "ep14out-iso",
2417 .ops
= &pxa2xx_ep_ops
,
2418 .maxpacket
= ISO_FIFO_SIZE
,
2421 .fifo_size
= ISO_FIFO_SIZE
,
2422 .bEndpointAddress
= 14,
2423 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2424 .reg_udccs
= &UDCCS14
,
2425 .reg_ubcr
= &UBCR14
,
2426 .reg_uddr
= &UDDR14
,
2431 .name
= "ep15in-int",
2432 .ops
= &pxa2xx_ep_ops
,
2433 .maxpacket
= INT_FIFO_SIZE
,
2436 .fifo_size
= INT_FIFO_SIZE
,
2437 .bEndpointAddress
= USB_DIR_IN
| 15,
2438 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2439 .reg_udccs
= &UDCCS15
,
2440 .reg_uddr
= &UDDR15
,
2442 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2445 #define CP15R0_VENDOR_MASK 0xffffe000
2447 #if defined(CONFIG_ARCH_PXA)
2448 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2450 #elif defined(CONFIG_ARCH_IXP4XX)
2451 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2455 #define CP15R0_PROD_MASK 0x000003f0
2456 #define PXA25x 0x00000100 /* and PXA26x */
2457 #define PXA210 0x00000120
2459 #define CP15R0_REV_MASK 0x0000000f
2461 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2463 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2464 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2465 #define PXA250_B2 0x00000104
2466 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2467 #define PXA250_B0 0x00000102
2468 #define PXA250_A1 0x00000101
2469 #define PXA250_A0 0x00000100
2471 #define PXA210_C0 0x00000125
2472 #define PXA210_B2 0x00000124
2473 #define PXA210_B1 0x00000123
2474 #define PXA210_B0 0x00000122
2475 #define IXP425_A0 0x000001c1
2476 #define IXP465_AD 0x00000200
2479 * probe - binds to the platform device
2481 static int __init
pxa2xx_udc_probe(struct platform_device
*pdev
)
2483 struct pxa2xx_udc
*dev
= &memory
;
2484 int retval
, out_dma
= 1, vbus_irq
;
2487 /* insist on Intel/ARM/XScale */
2488 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev
));
2489 if ((chiprev
& CP15R0_VENDOR_MASK
) != CP15R0_XSCALE_VALUE
) {
2490 printk(KERN_ERR
"%s: not XScale!\n", driver_name
);
2494 /* trigger chiprev-specific logic */
2495 switch (chiprev
& CP15R0_PRODREV_MASK
) {
2496 #if defined(CONFIG_ARCH_PXA)
2502 /* A0/A1 "not released"; ep 13, 15 unusable */
2504 case PXA250_B2
: case PXA210_B2
:
2505 case PXA250_B1
: case PXA210_B1
:
2506 case PXA250_B0
: case PXA210_B0
:
2509 case PXA250_C0
: case PXA210_C0
:
2511 #elif defined(CONFIG_ARCH_IXP4XX)
2520 printk(KERN_ERR
"%s: unrecognized processor: %08x\n",
2521 driver_name
, chiprev
);
2522 /* iop3xx, ixp4xx, ... */
2526 pr_debug("%s: IRQ %d%s%s%s\n", driver_name
, IRQ_USB
,
2527 dev
->has_cfr
? "" : " (!cfr)",
2528 out_dma
? "" : " (broken dma-out)",
2536 /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2538 DMSG("disabled OUT dma\n");
2539 dev
->ep
[ 2].reg_drcmr
= dev
->ep
[ 4].reg_drcmr
= 0;
2540 dev
->ep
[ 7].reg_drcmr
= dev
->ep
[ 9].reg_drcmr
= 0;
2541 dev
->ep
[12].reg_drcmr
= dev
->ep
[14].reg_drcmr
= 0;
2545 /* other non-static parts of init */
2546 dev
->dev
= &pdev
->dev
;
2547 dev
->mach
= pdev
->dev
.platform_data
;
2548 if (dev
->mach
->gpio_vbus
) {
2549 vbus_irq
= IRQ_GPIO(dev
->mach
->gpio_vbus
& GPIO_MD_MASK_NR
);
2550 pxa_gpio_mode((dev
->mach
->gpio_vbus
& GPIO_MD_MASK_NR
)
2552 set_irq_type(vbus_irq
, IRQT_BOTHEDGE
);
2555 if (dev
->mach
->gpio_pullup
)
2556 pxa_gpio_mode((dev
->mach
->gpio_pullup
& GPIO_MD_MASK_NR
)
2557 | GPIO_OUT
| GPIO_DFLT_LOW
);
2559 init_timer(&dev
->timer
);
2560 dev
->timer
.function
= udc_watchdog
;
2561 dev
->timer
.data
= (unsigned long) dev
;
2563 device_initialize(&dev
->gadget
.dev
);
2564 dev
->gadget
.dev
.parent
= &pdev
->dev
;
2565 dev
->gadget
.dev
.dma_mask
= pdev
->dev
.dma_mask
;
2567 the_controller
= dev
;
2568 platform_set_drvdata(pdev
, dev
);
2573 dev
->vbus
= is_vbus_present();
2575 /* irq setup after old hardware state is cleaned up */
2576 retval
= request_irq(IRQ_USB
, pxa2xx_udc_irq
,
2577 IRQF_DISABLED
, driver_name
, dev
);
2579 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2580 driver_name
, IRQ_USB
, retval
);
2585 #ifdef CONFIG_ARCH_LUBBOCK
2586 if (machine_is_lubbock()) {
2587 retval
= request_irq(LUBBOCK_USB_DISC_IRQ
,
2589 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
2592 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2593 driver_name
, LUBBOCK_USB_DISC_IRQ
, retval
);
2595 free_irq(IRQ_USB
, dev
);
2598 retval
= request_irq(LUBBOCK_USB_IRQ
,
2600 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
2603 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2604 driver_name
, LUBBOCK_USB_IRQ
, retval
);
2605 free_irq(LUBBOCK_USB_DISC_IRQ
, dev
);
2609 /* with U-Boot (but not BLOB), hex is off by default */
2610 HEX_DISPLAY(dev
->stats
.irqs
);
2611 LUB_DISC_BLNK_LED
&= 0xff;
2616 retval
= request_irq(vbus_irq
, udc_vbus_irq
,
2617 SA_INTERRUPT
| SA_SAMPLE_RANDOM
,
2620 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2621 driver_name
, vbus_irq
, retval
);
2622 free_irq(IRQ_USB
, dev
);
2626 create_proc_files();
2631 static void pxa2xx_udc_shutdown(struct platform_device
*_dev
)
2636 static int __exit
pxa2xx_udc_remove(struct platform_device
*pdev
)
2638 struct pxa2xx_udc
*dev
= platform_get_drvdata(pdev
);
2641 remove_proc_files();
2642 usb_gadget_unregister_driver(dev
->driver
);
2645 free_irq(IRQ_USB
, dev
);
2648 #ifdef CONFIG_ARCH_LUBBOCK
2649 if (machine_is_lubbock()) {
2650 free_irq(LUBBOCK_USB_DISC_IRQ
, dev
);
2651 free_irq(LUBBOCK_USB_IRQ
, dev
);
2654 if (dev
->mach
->gpio_vbus
)
2655 free_irq(IRQ_GPIO(dev
->mach
->gpio_vbus
), dev
);
2656 platform_set_drvdata(pdev
, NULL
);
2657 the_controller
= NULL
;
2661 /*-------------------------------------------------------------------------*/
2665 /* USB suspend (controlled by the host) and system suspend (controlled
2666 * by the PXA) don't necessarily work well together. If USB is active,
2667 * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2668 * mode, or any deeper PM saving state.
2670 * For now, we punt and forcibly disconnect from the USB host when PXA
2671 * enters any suspend state. While we're disconnected, we always disable
2672 * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2673 * Boards without software pullup control shouldn't use those states.
2674 * VBUS IRQs should probably be ignored so that the PXA device just acts
2675 * "dead" to USB hosts until system resume.
2677 static int pxa2xx_udc_suspend(struct platform_device
*dev
, pm_message_t state
)
2679 struct pxa2xx_udc
*udc
= platform_get_drvdata(dev
);
2681 if (!udc
->mach
->udc_command
)
2682 WARN("USB host won't detect disconnect!\n");
2688 static int pxa2xx_udc_resume(struct platform_device
*dev
)
2690 struct pxa2xx_udc
*udc
= platform_get_drvdata(dev
);
2698 #define pxa2xx_udc_suspend NULL
2699 #define pxa2xx_udc_resume NULL
2702 /*-------------------------------------------------------------------------*/
2704 static struct platform_driver udc_driver
= {
2705 .probe
= pxa2xx_udc_probe
,
2706 .shutdown
= pxa2xx_udc_shutdown
,
2707 .remove
= __exit_p(pxa2xx_udc_remove
),
2708 .suspend
= pxa2xx_udc_suspend
,
2709 .resume
= pxa2xx_udc_resume
,
2711 .owner
= THIS_MODULE
,
2712 .name
= "pxa2xx-udc",
2716 static int __init
udc_init(void)
2718 printk(KERN_INFO
"%s: version %s\n", driver_name
, DRIVER_VERSION
);
2719 return platform_driver_register(&udc_driver
);
2721 module_init(udc_init
);
2723 static void __exit
udc_exit(void)
2725 platform_driver_unregister(&udc_driver
);
2727 module_exit(udc_exit
);
2729 MODULE_DESCRIPTION(DRIVER_DESC
);
2730 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2731 MODULE_LICENSE("GPL");