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igb: Simplify how we populate the RSS key
[linux-2.6/cjktty.git] / include / linux / pci.h
blob5faa8310eec9ea02df6618345eb299cdee74d26b
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_D3COLD_WAIT 100
138 #define PCI_PM_BUS_WAIT 50
139
140 /** The pci_channel state describes connectivity between the CPU and
141 * the pci device. If some PCI bus between here and the pci device
142 * has crashed or locked up, this info is reflected here.
143 */
144 typedef unsigned int __bitwise pci_channel_state_t;
145
146 enum pci_channel_state {
147 /* I/O channel is in normal state */
148 pci_channel_io_normal = (__force pci_channel_state_t) 1,
149
150 /* I/O to channel is blocked */
151 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
152
153 /* PCI card is dead */
154 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
155 };
156
157 typedef unsigned int __bitwise pcie_reset_state_t;
158
159 enum pcie_reset_state {
160 /* Reset is NOT asserted (Use to deassert reset) */
161 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
162
163 /* Use #PERST to reset PCI-E device */
164 pcie_warm_reset = (__force pcie_reset_state_t) 2,
165
166 /* Use PCI-E Hot Reset to reset device */
167 pcie_hot_reset = (__force pcie_reset_state_t) 3
168 };
169
170 typedef unsigned short __bitwise pci_dev_flags_t;
171 enum pci_dev_flags {
172 /* INTX_DISABLE in PCI_COMMAND register disables MSI
173 * generation too.
174 */
175 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
176 /* Device configuration is irrevocably lost if disabled into D3 */
177 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
178 /* Provide indication device is assigned by a Virtual Machine Manager */
179 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
180 };
181
182 enum pci_irq_reroute_variant {
183 INTEL_IRQ_REROUTE_VARIANT = 1,
184 MAX_IRQ_REROUTE_VARIANTS = 3
185 };
186
187 typedef unsigned short __bitwise pci_bus_flags_t;
188 enum pci_bus_flags {
189 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
190 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
191 };
192
193 /* Based on the PCI Hotplug Spec, but some values are made up by us */
194 enum pci_bus_speed {
195 PCI_SPEED_33MHz = 0x00,
196 PCI_SPEED_66MHz = 0x01,
197 PCI_SPEED_66MHz_PCIX = 0x02,
198 PCI_SPEED_100MHz_PCIX = 0x03,
199 PCI_SPEED_133MHz_PCIX = 0x04,
200 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
201 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
202 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
203 PCI_SPEED_66MHz_PCIX_266 = 0x09,
204 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
205 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
206 AGP_UNKNOWN = 0x0c,
207 AGP_1X = 0x0d,
208 AGP_2X = 0x0e,
209 AGP_4X = 0x0f,
210 AGP_8X = 0x10,
211 PCI_SPEED_66MHz_PCIX_533 = 0x11,
212 PCI_SPEED_100MHz_PCIX_533 = 0x12,
213 PCI_SPEED_133MHz_PCIX_533 = 0x13,
214 PCIE_SPEED_2_5GT = 0x14,
215 PCIE_SPEED_5_0GT = 0x15,
216 PCIE_SPEED_8_0GT = 0x16,
217 PCI_SPEED_UNKNOWN = 0xff,
218 };
219
220 struct pci_cap_saved_data {
221 char cap_nr;
222 unsigned int size;
223 u32 data[0];
224 };
225
226 struct pci_cap_saved_state {
227 struct hlist_node next;
228 struct pci_cap_saved_data cap;
229 };
230
231 struct pcie_link_state;
232 struct pci_vpd;
233 struct pci_sriov;
234 struct pci_ats;
235
236 /*
237 * The pci_dev structure is used to describe PCI devices.
238 */
239 struct pci_dev {
240 struct list_head bus_list; /* node in per-bus list */
241 struct pci_bus *bus; /* bus this device is on */
242 struct pci_bus *subordinate; /* bus this device bridges to */
243
244 void *sysdata; /* hook for sys-specific extension */
245 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
246 struct pci_slot *slot; /* Physical slot this device is in */
247
248 unsigned int devfn; /* encoded device & function index */
249 unsigned short vendor;
250 unsigned short device;
251 unsigned short subsystem_vendor;
252 unsigned short subsystem_device;
253 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
254 u8 revision; /* PCI revision, low byte of class word */
255 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
256 u8 pcie_cap; /* PCI-E capability offset */
257 u8 pcie_type:4; /* PCI-E device/port type */
258 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
259 u8 rom_base_reg; /* which config register controls the ROM */
260 u8 pin; /* which interrupt pin this device uses */
261
262 struct pci_driver *driver; /* which driver has allocated this device */
263 u64 dma_mask; /* Mask of the bits of bus address this
264 device implements. Normally this is
265 0xffffffff. You only need to change
266 this if your device has broken DMA
267 or supports 64-bit transfers. */
268
269 struct device_dma_parameters dma_parms;
270
271 pci_power_t current_state; /* Current operating state. In ACPI-speak,
272 this is D0-D3, D0 being fully functional,
273 and D3 being off. */
274 int pm_cap; /* PM capability offset in the
275 configuration space */
276 unsigned int pme_support:5; /* Bitmask of states from which PME#
277 can be generated */
278 unsigned int pme_interrupt:1;
279 unsigned int pme_poll:1; /* Poll device's PME status bit */
280 unsigned int d1_support:1; /* Low power state D1 is supported */
281 unsigned int d2_support:1; /* Low power state D2 is supported */
282 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
283 unsigned int no_d3cold:1; /* D3cold is forbidden */
284 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
285 unsigned int mmio_always_on:1; /* disallow turning off io/mem
286 decoding during bar sizing */
287 unsigned int wakeup_prepared:1;
288 unsigned int runtime_d3cold:1; /* whether go through runtime
289 D3cold, not set for devices
290 powered on/off by the
291 corresponding bridge */
292 unsigned int d3_delay; /* D3->D0 transition time in ms */
293 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
294
295 #ifdef CONFIG_PCIEASPM
296 struct pcie_link_state *link_state; /* ASPM link state. */
297 #endif
298
299 pci_channel_state_t error_state; /* current connectivity state */
300 struct device dev; /* Generic device interface */
301
302 int cfg_size; /* Size of configuration space */
303
304 /*
305 * Instead of touching interrupt line and base address registers
306 * directly, use the values stored here. They might be different!
307 */
308 unsigned int irq;
309 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
310
311 /* These fields are used by common fixups */
312 unsigned int transparent:1; /* Transparent PCI bridge */
313 unsigned int multifunction:1;/* Part of multi-function device */
314 /* keep track of device state */
315 unsigned int is_added:1;
316 unsigned int is_busmaster:1; /* device is busmaster */
317 unsigned int no_msi:1; /* device may not use msi */
318 unsigned int block_cfg_access:1; /* config space access is blocked */
319 unsigned int broken_parity_status:1; /* Device generates false positive parity */
320 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
321 unsigned int msi_enabled:1;
322 unsigned int msix_enabled:1;
323 unsigned int ari_enabled:1; /* ARI forwarding */
324 unsigned int is_managed:1;
325 unsigned int is_pcie:1; /* Obsolete. Will be removed.
326 Use pci_is_pcie() instead */
327 unsigned int needs_freset:1; /* Dev requires fundamental reset */
328 unsigned int state_saved:1;
329 unsigned int is_physfn:1;
330 unsigned int is_virtfn:1;
331 unsigned int reset_fn:1;
332 unsigned int is_hotplug_bridge:1;
333 unsigned int __aer_firmware_first_valid:1;
334 unsigned int __aer_firmware_first:1;
335 unsigned int broken_intx_masking:1;
336 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
337 pci_dev_flags_t dev_flags;
338 atomic_t enable_cnt; /* pci_enable_device has been called */
339
340 u32 saved_config_space[16]; /* config space saved at suspend time */
341 struct hlist_head saved_cap_space;
342 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
343 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
344 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
345 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
346 #ifdef CONFIG_PCI_MSI
347 struct list_head msi_list;
348 struct kset *msi_kset;
349 #endif
350 struct pci_vpd *vpd;
351 #ifdef CONFIG_PCI_ATS
352 union {
353 struct pci_sriov *sriov; /* SR-IOV capability related */
354 struct pci_dev *physfn; /* the PF this VF is associated with */
355 };
356 struct pci_ats *ats; /* Address Translation Service */
357 #endif
358 };
359
360 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
361 {
362 #ifdef CONFIG_PCI_IOV
363 if (dev->is_virtfn)
364 dev = dev->physfn;
365 #endif
366
367 return dev;
368 }
369
370 extern struct pci_dev *alloc_pci_dev(void);
371
372 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
373 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
374 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
375
376 static inline int pci_channel_offline(struct pci_dev *pdev)
377 {
378 return (pdev->error_state != pci_channel_io_normal);
379 }
380
381 extern struct resource busn_resource;
382
383 struct pci_host_bridge_window {
384 struct list_head list;
385 struct resource *res; /* host bridge aperture (CPU address) */
386 resource_size_t offset; /* bus address + offset = CPU address */
387 };
388
389 struct pci_host_bridge {
390 struct device dev;
391 struct pci_bus *bus; /* root bus */
392 struct list_head windows; /* pci_host_bridge_windows */
393 void (*release_fn)(struct pci_host_bridge *);
394 void *release_data;
395 };
396
397 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
398 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
399 void (*release_fn)(struct pci_host_bridge *),
400 void *release_data);
401
402 /*
403 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
404 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
405 * buses below host bridges or subtractive decode bridges) go in the list.
406 * Use pci_bus_for_each_resource() to iterate through all the resources.
407 */
408
409 /*
410 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
411 * and there's no way to program the bridge with the details of the window.
412 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
413 * decode bit set, because they are explicit and can be programmed with _SRS.
414 */
415 #define PCI_SUBTRACTIVE_DECODE 0x1
416
417 struct pci_bus_resource {
418 struct list_head list;
419 struct resource *res;
420 unsigned int flags;
421 };
422
423 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
424
425 struct pci_bus {
426 struct list_head node; /* node in list of buses */
427 struct pci_bus *parent; /* parent bus this bridge is on */
428 struct list_head children; /* list of child buses */
429 struct list_head devices; /* list of devices on this bus */
430 struct pci_dev *self; /* bridge device as seen by parent */
431 struct list_head slots; /* list of slots on this bus */
432 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
433 struct list_head resources; /* address space routed to this bus */
434 struct resource busn_res; /* bus numbers routed to this bus */
435
436 struct pci_ops *ops; /* configuration access functions */
437 void *sysdata; /* hook for sys-specific extension */
438 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
439
440 unsigned char number; /* bus number */
441 unsigned char primary; /* number of primary bridge */
442 unsigned char max_bus_speed; /* enum pci_bus_speed */
443 unsigned char cur_bus_speed; /* enum pci_bus_speed */
444
445 char name[48];
446
447 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
448 pci_bus_flags_t bus_flags; /* Inherited by child busses */
449 struct device *bridge;
450 struct device dev;
451 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
452 struct bin_attribute *legacy_mem; /* legacy mem */
453 unsigned int is_added:1;
454 };
455
456 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
457 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
458
459 /*
460 * Returns true if the pci bus is root (behind host-pci bridge),
461 * false otherwise
462 */
463 static inline bool pci_is_root_bus(struct pci_bus *pbus)
464 {
465 return !(pbus->parent);
466 }
467
468 #ifdef CONFIG_PCI_MSI
469 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
470 {
471 return pci_dev->msi_enabled || pci_dev->msix_enabled;
472 }
473 #else
474 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
475 #endif
476
477 /*
478 * Error values that may be returned by PCI functions.
479 */
480 #define PCIBIOS_SUCCESSFUL 0x00
481 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
482 #define PCIBIOS_BAD_VENDOR_ID 0x83
483 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
484 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
485 #define PCIBIOS_SET_FAILED 0x88
486 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
487
488 /*
489 * Translate above to generic errno for passing back through non-pci.
490 */
491 static inline int pcibios_err_to_errno(int err)
492 {
493 if (err <= PCIBIOS_SUCCESSFUL)
494 return err; /* Assume already errno */
495
496 switch (err) {
497 case PCIBIOS_FUNC_NOT_SUPPORTED:
498 return -ENOENT;
499 case PCIBIOS_BAD_VENDOR_ID:
500 return -EINVAL;
501 case PCIBIOS_DEVICE_NOT_FOUND:
502 return -ENODEV;
503 case PCIBIOS_BAD_REGISTER_NUMBER:
504 return -EFAULT;
505 case PCIBIOS_SET_FAILED:
506 return -EIO;
507 case PCIBIOS_BUFFER_TOO_SMALL:
508 return -ENOSPC;
509 }
510
511 return -ENOTTY;
512 }
513
514 /* Low-level architecture-dependent routines */
515
516 struct pci_ops {
517 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
518 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
519 };
520
521 /*
522 * ACPI needs to be able to access PCI config space before we've done a
523 * PCI bus scan and created pci_bus structures.
524 */
525 extern int raw_pci_read(unsigned int domain, unsigned int bus,
526 unsigned int devfn, int reg, int len, u32 *val);
527 extern int raw_pci_write(unsigned int domain, unsigned int bus,
528 unsigned int devfn, int reg, int len, u32 val);
529
530 struct pci_bus_region {
531 resource_size_t start;
532 resource_size_t end;
533 };
534
535 struct pci_dynids {
536 spinlock_t lock; /* protects list, index */
537 struct list_head list; /* for IDs added at runtime */
538 };
539
540 /* ---------------------------------------------------------------- */
541 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
542 * a set of callbacks in struct pci_error_handlers, then that device driver
543 * will be notified of PCI bus errors, and will be driven to recovery
544 * when an error occurs.
545 */
546
547 typedef unsigned int __bitwise pci_ers_result_t;
548
549 enum pci_ers_result {
550 /* no result/none/not supported in device driver */
551 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
552
553 /* Device driver can recover without slot reset */
554 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
555
556 /* Device driver wants slot to be reset. */
557 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
558
559 /* Device has completely failed, is unrecoverable */
560 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
561
562 /* Device driver is fully recovered and operational */
563 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
564 };
565
566 /* PCI bus error event callbacks */
567 struct pci_error_handlers {
568 /* PCI bus error detected on this device */
569 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
570 enum pci_channel_state error);
571
572 /* MMIO has been re-enabled, but not DMA */
573 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
574
575 /* PCI Express link has been reset */
576 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
577
578 /* PCI slot has been reset */
579 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
580
581 /* Device driver may resume normal operations */
582 void (*resume)(struct pci_dev *dev);
583 };
584
585 /* ---------------------------------------------------------------- */
586
587 struct module;
588 struct pci_driver {
589 struct list_head node;
590 const char *name;
591 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
592 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
593 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
594 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
595 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
596 int (*resume_early) (struct pci_dev *dev);
597 int (*resume) (struct pci_dev *dev); /* Device woken up */
598 void (*shutdown) (struct pci_dev *dev);
599 struct pci_error_handlers *err_handler;
600 struct device_driver driver;
601 struct pci_dynids dynids;
602 };
603
604 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
605
606 /**
607 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
608 * @_table: device table name
609 *
610 * This macro is used to create a struct pci_device_id array (a device table)
611 * in a generic manner.
612 */
613 #define DEFINE_PCI_DEVICE_TABLE(_table) \
614 const struct pci_device_id _table[] __devinitconst
615
616 /**
617 * PCI_DEVICE - macro used to describe a specific pci device
618 * @vend: the 16 bit PCI Vendor ID
619 * @dev: the 16 bit PCI Device ID
620 *
621 * This macro is used to create a struct pci_device_id that matches a
622 * specific device. The subvendor and subdevice fields will be set to
623 * PCI_ANY_ID.
624 */
625 #define PCI_DEVICE(vend,dev) \
626 .vendor = (vend), .device = (dev), \
627 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
628
629 /**
630 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
631 * @dev_class: the class, subclass, prog-if triple for this device
632 * @dev_class_mask: the class mask for this device
633 *
634 * This macro is used to create a struct pci_device_id that matches a
635 * specific PCI class. The vendor, device, subvendor, and subdevice
636 * fields will be set to PCI_ANY_ID.
637 */
638 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
639 .class = (dev_class), .class_mask = (dev_class_mask), \
640 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
641 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
642
643 /**
644 * PCI_VDEVICE - macro used to describe a specific pci device in short form
645 * @vendor: the vendor name
646 * @device: the 16 bit PCI Device ID
647 *
648 * This macro is used to create a struct pci_device_id that matches a
649 * specific PCI device. The subvendor, and subdevice fields will be set
650 * to PCI_ANY_ID. The macro allows the next field to follow as the device
651 * private data.
652 */
653
654 #define PCI_VDEVICE(vendor, device) \
655 PCI_VENDOR_ID_##vendor, (device), \
656 PCI_ANY_ID, PCI_ANY_ID, 0, 0
657
658 /* these external functions are only available when PCI support is enabled */
659 #ifdef CONFIG_PCI
660
661 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
662
663 enum pcie_bus_config_types {
664 PCIE_BUS_TUNE_OFF,
665 PCIE_BUS_SAFE,
666 PCIE_BUS_PERFORMANCE,
667 PCIE_BUS_PEER2PEER,
668 };
669
670 extern enum pcie_bus_config_types pcie_bus_config;
671
672 extern struct bus_type pci_bus_type;
673
674 /* Do NOT directly access these two variables, unless you are arch specific pci
675 * code, or pci core code. */
676 extern struct list_head pci_root_buses; /* list of all known PCI buses */
677 /* Some device drivers need know if pci is initiated */
678 extern int no_pci_devices(void);
679
680 void pcibios_fixup_bus(struct pci_bus *);
681 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
682 /* Architecture specific versions may override this (weak) */
683 char *pcibios_setup(char *str);
684
685 /* Used only when drivers/pci/setup.c is used */
686 resource_size_t pcibios_align_resource(void *, const struct resource *,
687 resource_size_t,
688 resource_size_t);
689 void pcibios_update_irq(struct pci_dev *, int irq);
690
691 /* Weak but can be overriden by arch */
692 void pci_fixup_cardbus(struct pci_bus *);
693
694 /* Generic PCI functions used internally */
695
696 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
697 struct resource *res);
698 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
699 struct pci_bus_region *region);
700 void pcibios_scan_specific_bus(int busn);
701 extern struct pci_bus *pci_find_bus(int domain, int busnr);
702 void pci_bus_add_devices(const struct pci_bus *bus);
703 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
704 struct pci_ops *ops, void *sysdata);
705 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
706 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
707 struct pci_ops *ops, void *sysdata,
708 struct list_head *resources);
709 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
710 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
711 void pci_bus_release_busn_res(struct pci_bus *b);
712 struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
713 struct pci_ops *ops, void *sysdata,
714 struct list_head *resources);
715 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
716 int busnr);
717 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
718 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
719 const char *name,
720 struct hotplug_slot *hotplug);
721 void pci_destroy_slot(struct pci_slot *slot);
722 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
723 int pci_scan_slot(struct pci_bus *bus, int devfn);
724 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
725 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
726 unsigned int pci_scan_child_bus(struct pci_bus *bus);
727 int __must_check pci_bus_add_device(struct pci_dev *dev);
728 void pci_read_bridge_bases(struct pci_bus *child);
729 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
730 struct resource *res);
731 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
732 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
733 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
734 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
735 extern void pci_dev_put(struct pci_dev *dev);
736 extern void pci_remove_bus(struct pci_bus *b);
737 extern void __pci_remove_bus_device(struct pci_dev *dev);
738 extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
739 extern void pci_stop_bus_device(struct pci_dev *dev);
740 void pci_setup_cardbus(struct pci_bus *bus);
741 extern void pci_sort_breadthfirst(void);
742 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
743 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
744 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
745
746 /* Generic PCI functions exported to card drivers */
747
748 enum pci_lost_interrupt_reason {
749 PCI_LOST_IRQ_NO_INFORMATION = 0,
750 PCI_LOST_IRQ_DISABLE_MSI,
751 PCI_LOST_IRQ_DISABLE_MSIX,
752 PCI_LOST_IRQ_DISABLE_ACPI,
753 };
754 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
755 int pci_find_capability(struct pci_dev *dev, int cap);
756 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
757 int pci_find_ext_capability(struct pci_dev *dev, int cap);
758 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
759 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
760 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
761
762 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
763 struct pci_dev *from);
764 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
765 unsigned int ss_vendor, unsigned int ss_device,
766 struct pci_dev *from);
767 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
768 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
769 unsigned int devfn);
770 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
771 unsigned int devfn)
772 {
773 return pci_get_domain_bus_and_slot(0, bus, devfn);
774 }
775 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
776 int pci_dev_present(const struct pci_device_id *ids);
777
778 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
779 int where, u8 *val);
780 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
781 int where, u16 *val);
782 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
783 int where, u32 *val);
784 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
785 int where, u8 val);
786 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
787 int where, u16 val);
788 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
789 int where, u32 val);
790 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
791
792 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
793 {
794 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
795 }
796 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
797 {
798 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
799 }
800 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
801 u32 *val)
802 {
803 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
804 }
805 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
806 {
807 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
808 }
809 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
810 {
811 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
812 }
813 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
814 u32 val)
815 {
816 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
817 }
818
819 /* user-space driven config access */
820 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
821 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
822 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
823 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
824 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
825 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
826
827 int __must_check pci_enable_device(struct pci_dev *dev);
828 int __must_check pci_enable_device_io(struct pci_dev *dev);
829 int __must_check pci_enable_device_mem(struct pci_dev *dev);
830 int __must_check pci_reenable_device(struct pci_dev *);
831 int __must_check pcim_enable_device(struct pci_dev *pdev);
832 void pcim_pin_device(struct pci_dev *pdev);
833
834 static inline int pci_is_enabled(struct pci_dev *pdev)
835 {
836 return (atomic_read(&pdev->enable_cnt) > 0);
837 }
838
839 static inline int pci_is_managed(struct pci_dev *pdev)
840 {
841 return pdev->is_managed;
842 }
843
844 void pci_disable_device(struct pci_dev *dev);
845
846 extern unsigned int pcibios_max_latency;
847 void pci_set_master(struct pci_dev *dev);
848 void pci_clear_master(struct pci_dev *dev);
849
850 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
851 int pci_set_cacheline_size(struct pci_dev *dev);
852 #define HAVE_PCI_SET_MWI
853 int __must_check pci_set_mwi(struct pci_dev *dev);
854 int pci_try_set_mwi(struct pci_dev *dev);
855 void pci_clear_mwi(struct pci_dev *dev);
856 void pci_intx(struct pci_dev *dev, int enable);
857 bool pci_intx_mask_supported(struct pci_dev *dev);
858 bool pci_check_and_mask_intx(struct pci_dev *dev);
859 bool pci_check_and_unmask_intx(struct pci_dev *dev);
860 void pci_msi_off(struct pci_dev *dev);
861 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
862 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
863 int pcix_get_max_mmrbc(struct pci_dev *dev);
864 int pcix_get_mmrbc(struct pci_dev *dev);
865 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
866 int pcie_get_readrq(struct pci_dev *dev);
867 int pcie_set_readrq(struct pci_dev *dev, int rq);
868 int pcie_get_mps(struct pci_dev *dev);
869 int pcie_set_mps(struct pci_dev *dev, int mps);
870 int __pci_reset_function(struct pci_dev *dev);
871 int __pci_reset_function_locked(struct pci_dev *dev);
872 int pci_reset_function(struct pci_dev *dev);
873 void pci_update_resource(struct pci_dev *dev, int resno);
874 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
875 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
876 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
877
878 /* ROM control related routines */
879 int pci_enable_rom(struct pci_dev *pdev);
880 void pci_disable_rom(struct pci_dev *pdev);
881 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
882 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
883 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
884
885 /* Power management related routines */
886 int pci_save_state(struct pci_dev *dev);
887 void pci_restore_state(struct pci_dev *dev);
888 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
889 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
890 int pci_load_and_free_saved_state(struct pci_dev *dev,
891 struct pci_saved_state **state);
892 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
893 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
894 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
895 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
896 void pci_pme_active(struct pci_dev *dev, bool enable);
897 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
898 bool runtime, bool enable);
899 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
900 pci_power_t pci_target_state(struct pci_dev *dev);
901 int pci_prepare_to_sleep(struct pci_dev *dev);
902 int pci_back_from_sleep(struct pci_dev *dev);
903 bool pci_dev_run_wake(struct pci_dev *dev);
904 bool pci_check_pme_status(struct pci_dev *dev);
905 void pci_pme_wakeup_bus(struct pci_bus *bus);
906
907 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
908 bool enable)
909 {
910 return __pci_enable_wake(dev, state, false, enable);
911 }
912
913 #define PCI_EXP_IDO_REQUEST (1<<0)
914 #define PCI_EXP_IDO_COMPLETION (1<<1)
915 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
916 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
917
918 enum pci_obff_signal_type {
919 PCI_EXP_OBFF_SIGNAL_L0 = 0,
920 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
921 };
922 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
923 void pci_disable_obff(struct pci_dev *dev);
924
925 int pci_enable_ltr(struct pci_dev *dev);
926 void pci_disable_ltr(struct pci_dev *dev);
927 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
928
929 /* For use by arch with custom probe code */
930 void set_pcie_port_type(struct pci_dev *pdev);
931 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
932
933 /* Functions for PCI Hotplug drivers to use */
934 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
935 #ifdef CONFIG_HOTPLUG
936 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
937 unsigned int pci_rescan_bus(struct pci_bus *bus);
938 #endif
939
940 /* Vital product data routines */
941 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
942 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
943 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
944
945 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
946 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
947 void pci_bus_assign_resources(const struct pci_bus *bus);
948 void pci_bus_size_bridges(struct pci_bus *bus);
949 int pci_claim_resource(struct pci_dev *, int);
950 void pci_assign_unassigned_resources(void);
951 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
952 void pdev_enable_device(struct pci_dev *);
953 int pci_enable_resources(struct pci_dev *, int mask);
954 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
955 int (*)(const struct pci_dev *, u8, u8));
956 #define HAVE_PCI_REQ_REGIONS 2
957 int __must_check pci_request_regions(struct pci_dev *, const char *);
958 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
959 void pci_release_regions(struct pci_dev *);
960 int __must_check pci_request_region(struct pci_dev *, int, const char *);
961 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
962 void pci_release_region(struct pci_dev *, int);
963 int pci_request_selected_regions(struct pci_dev *, int, const char *);
964 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
965 void pci_release_selected_regions(struct pci_dev *, int);
966
967 /* drivers/pci/bus.c */
968 void pci_add_resource(struct list_head *resources, struct resource *res);
969 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
970 resource_size_t offset);
971 void pci_free_resource_list(struct list_head *resources);
972 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
973 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
974 void pci_bus_remove_resources(struct pci_bus *bus);
975
976 #define pci_bus_for_each_resource(bus, res, i) \
977 for (i = 0; \
978 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
979 i++)
980
981 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
982 struct resource *res, resource_size_t size,
983 resource_size_t align, resource_size_t min,
984 unsigned int type_mask,
985 resource_size_t (*alignf)(void *,
986 const struct resource *,
987 resource_size_t,
988 resource_size_t),
989 void *alignf_data);
990 void pci_enable_bridges(struct pci_bus *bus);
991
992 /* Proper probing supporting hot-pluggable devices */
993 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
994 const char *mod_name);
995
996 /*
997 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
998 */
999 #define pci_register_driver(driver) \
1000 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1001
1002 void pci_unregister_driver(struct pci_driver *dev);
1003
1004 /**
1005 * module_pci_driver() - Helper macro for registering a PCI driver
1006 * @__pci_driver: pci_driver struct
1007 *
1008 * Helper macro for PCI drivers which do not do anything special in module
1009 * init/exit. This eliminates a lot of boilerplate. Each module may only
1010 * use this macro once, and calling it replaces module_init() and module_exit()
1011 */
1012 #define module_pci_driver(__pci_driver) \
1013 module_driver(__pci_driver, pci_register_driver, \
1014 pci_unregister_driver)
1015
1016 void pci_stop_and_remove_behind_bridge(struct pci_dev *dev);
1017 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1018 int pci_add_dynid(struct pci_driver *drv,
1019 unsigned int vendor, unsigned int device,
1020 unsigned int subvendor, unsigned int subdevice,
1021 unsigned int class, unsigned int class_mask,
1022 unsigned long driver_data);
1023 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1024 struct pci_dev *dev);
1025 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1026 int pass);
1027
1028 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1029 void *userdata);
1030 int pci_cfg_space_size_ext(struct pci_dev *dev);
1031 int pci_cfg_space_size(struct pci_dev *dev);
1032 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1033 void pci_setup_bridge(struct pci_bus *bus);
1034
1035 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1036 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1037
1038 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1039 unsigned int command_bits, u32 flags);
1040 /* kmem_cache style wrapper around pci_alloc_consistent() */
1041
1042 #include <linux/pci-dma.h>
1043 #include <linux/dmapool.h>
1044
1045 #define pci_pool dma_pool
1046 #define pci_pool_create(name, pdev, size, align, allocation) \
1047 dma_pool_create(name, &pdev->dev, size, align, allocation)
1048 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1049 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1050 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1051
1052 enum pci_dma_burst_strategy {
1053 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1054 strategy_parameter is N/A */
1055 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1056 byte boundaries */
1057 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1058 strategy_parameter byte boundaries */
1059 };
1060
1061 struct msix_entry {
1062 u32 vector; /* kernel uses to write allocated vector */
1063 u16 entry; /* driver uses to specify entry, OS writes */
1064 };
1065
1066
1067 #ifndef CONFIG_PCI_MSI
1068 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1069 {
1070 return -1;
1071 }
1072
1073 static inline void pci_msi_shutdown(struct pci_dev *dev)
1074 { }
1075 static inline void pci_disable_msi(struct pci_dev *dev)
1076 { }
1077
1078 static inline int pci_msix_table_size(struct pci_dev *dev)
1079 {
1080 return 0;
1081 }
1082 static inline int pci_enable_msix(struct pci_dev *dev,
1083 struct msix_entry *entries, int nvec)
1084 {
1085 return -1;
1086 }
1087
1088 static inline void pci_msix_shutdown(struct pci_dev *dev)
1089 { }
1090 static inline void pci_disable_msix(struct pci_dev *dev)
1091 { }
1092
1093 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1094 { }
1095
1096 static inline void pci_restore_msi_state(struct pci_dev *dev)
1097 { }
1098 static inline int pci_msi_enabled(void)
1099 {
1100 return 0;
1101 }
1102 #else
1103 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1104 extern void pci_msi_shutdown(struct pci_dev *dev);
1105 extern void pci_disable_msi(struct pci_dev *dev);
1106 extern int pci_msix_table_size(struct pci_dev *dev);
1107 extern int pci_enable_msix(struct pci_dev *dev,
1108 struct msix_entry *entries, int nvec);
1109 extern void pci_msix_shutdown(struct pci_dev *dev);
1110 extern void pci_disable_msix(struct pci_dev *dev);
1111 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1112 extern void pci_restore_msi_state(struct pci_dev *dev);
1113 extern int pci_msi_enabled(void);
1114 #endif
1115
1116 #ifdef CONFIG_PCIEPORTBUS
1117 extern bool pcie_ports_disabled;
1118 extern bool pcie_ports_auto;
1119 #else
1120 #define pcie_ports_disabled true
1121 #define pcie_ports_auto false
1122 #endif
1123
1124 #ifndef CONFIG_PCIEASPM
1125 static inline int pcie_aspm_enabled(void) { return 0; }
1126 static inline bool pcie_aspm_support_enabled(void) { return false; }
1127 #else
1128 extern int pcie_aspm_enabled(void);
1129 extern bool pcie_aspm_support_enabled(void);
1130 #endif
1131
1132 #ifdef CONFIG_PCIEAER
1133 void pci_no_aer(void);
1134 bool pci_aer_available(void);
1135 #else
1136 static inline void pci_no_aer(void) { }
1137 static inline bool pci_aer_available(void) { return false; }
1138 #endif
1139
1140 #ifndef CONFIG_PCIE_ECRC
1141 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1142 {
1143 return;
1144 }
1145 static inline void pcie_ecrc_get_policy(char *str) {};
1146 #else
1147 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1148 extern void pcie_ecrc_get_policy(char *str);
1149 #endif
1150
1151 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1152
1153 #ifdef CONFIG_HT_IRQ
1154 /* The functions a driver should call */
1155 int ht_create_irq(struct pci_dev *dev, int idx);
1156 void ht_destroy_irq(unsigned int irq);
1157 #endif /* CONFIG_HT_IRQ */
1158
1159 extern void pci_cfg_access_lock(struct pci_dev *dev);
1160 extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1161 extern void pci_cfg_access_unlock(struct pci_dev *dev);
1162
1163 /*
1164 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1165 * a PCI domain is defined to be a set of PCI busses which share
1166 * configuration space.
1167 */
1168 #ifdef CONFIG_PCI_DOMAINS
1169 extern int pci_domains_supported;
1170 #else
1171 enum { pci_domains_supported = 0 };
1172 static inline int pci_domain_nr(struct pci_bus *bus)
1173 {
1174 return 0;
1175 }
1176
1177 static inline int pci_proc_domain(struct pci_bus *bus)
1178 {
1179 return 0;
1180 }
1181 #endif /* CONFIG_PCI_DOMAINS */
1182
1183 /* some architectures require additional setup to direct VGA traffic */
1184 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1185 unsigned int command_bits, u32 flags);
1186 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1187
1188 #else /* CONFIG_PCI is not enabled */
1189
1190 /*
1191 * If the system does not have PCI, clearly these return errors. Define
1192 * these as simple inline functions to avoid hair in drivers.
1193 */
1194
1195 #define _PCI_NOP(o, s, t) \
1196 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1197 int where, t val) \
1198 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1199
1200 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1201 _PCI_NOP(o, word, u16 x) \
1202 _PCI_NOP(o, dword, u32 x)
1203 _PCI_NOP_ALL(read, *)
1204 _PCI_NOP_ALL(write,)
1205
1206 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1207 unsigned int device,
1208 struct pci_dev *from)
1209 {
1210 return NULL;
1211 }
1212
1213 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1214 unsigned int device,
1215 unsigned int ss_vendor,
1216 unsigned int ss_device,
1217 struct pci_dev *from)
1218 {
1219 return NULL;
1220 }
1221
1222 static inline struct pci_dev *pci_get_class(unsigned int class,
1223 struct pci_dev *from)
1224 {
1225 return NULL;
1226 }
1227
1228 #define pci_dev_present(ids) (0)
1229 #define no_pci_devices() (1)
1230 #define pci_dev_put(dev) do { } while (0)
1231
1232 static inline void pci_set_master(struct pci_dev *dev)
1233 { }
1234
1235 static inline int pci_enable_device(struct pci_dev *dev)
1236 {
1237 return -EIO;
1238 }
1239
1240 static inline void pci_disable_device(struct pci_dev *dev)
1241 { }
1242
1243 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1244 {
1245 return -EIO;
1246 }
1247
1248 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1249 {
1250 return -EIO;
1251 }
1252
1253 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1254 unsigned int size)
1255 {
1256 return -EIO;
1257 }
1258
1259 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1260 unsigned long mask)
1261 {
1262 return -EIO;
1263 }
1264
1265 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1266 {
1267 return -EBUSY;
1268 }
1269
1270 static inline int __pci_register_driver(struct pci_driver *drv,
1271 struct module *owner)
1272 {
1273 return 0;
1274 }
1275
1276 static inline int pci_register_driver(struct pci_driver *drv)
1277 {
1278 return 0;
1279 }
1280
1281 static inline void pci_unregister_driver(struct pci_driver *drv)
1282 { }
1283
1284 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1285 {
1286 return 0;
1287 }
1288
1289 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1290 int cap)
1291 {
1292 return 0;
1293 }
1294
1295 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1296 {
1297 return 0;
1298 }
1299
1300 /* Power management related routines */
1301 static inline int pci_save_state(struct pci_dev *dev)
1302 {
1303 return 0;
1304 }
1305
1306 static inline void pci_restore_state(struct pci_dev *dev)
1307 { }
1308
1309 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1310 {
1311 return 0;
1312 }
1313
1314 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1315 {
1316 return 0;
1317 }
1318
1319 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1320 pm_message_t state)
1321 {
1322 return PCI_D0;
1323 }
1324
1325 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1326 int enable)
1327 {
1328 return 0;
1329 }
1330
1331 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1332 {
1333 }
1334
1335 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1336 {
1337 }
1338
1339 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1340 {
1341 return 0;
1342 }
1343
1344 static inline void pci_disable_obff(struct pci_dev *dev)
1345 {
1346 }
1347
1348 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1349 {
1350 return -EIO;
1351 }
1352
1353 static inline void pci_release_regions(struct pci_dev *dev)
1354 { }
1355
1356 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1357
1358 static inline void pci_block_cfg_access(struct pci_dev *dev)
1359 { }
1360
1361 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1362 { return 0; }
1363
1364 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1365 { }
1366
1367 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1368 { return NULL; }
1369
1370 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1371 unsigned int devfn)
1372 { return NULL; }
1373
1374 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1375 unsigned int devfn)
1376 { return NULL; }
1377
1378 static inline int pci_domain_nr(struct pci_bus *bus)
1379 { return 0; }
1380
1381 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1382 { return NULL; }
1383
1384 #define dev_is_pci(d) (false)
1385 #define dev_is_pf(d) (false)
1386 #define dev_num_vf(d) (0)
1387 #endif /* CONFIG_PCI */
1388
1389 /* Include architecture-dependent settings and functions */
1390
1391 #include <asm/pci.h>
1392
1393 #ifndef PCIBIOS_MAX_MEM_32
1394 #define PCIBIOS_MAX_MEM_32 (-1)
1395 #endif
1396
1397 /* these helpers provide future and backwards compatibility
1398 * for accessing popular PCI BAR info */
1399 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1400 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1401 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1402 #define pci_resource_len(dev,bar) \
1403 ((pci_resource_start((dev), (bar)) == 0 && \
1404 pci_resource_end((dev), (bar)) == \
1405 pci_resource_start((dev), (bar))) ? 0 : \
1406 \
1407 (pci_resource_end((dev), (bar)) - \
1408 pci_resource_start((dev), (bar)) + 1))
1409
1410 /* Similar to the helpers above, these manipulate per-pci_dev
1411 * driver-specific data. They are really just a wrapper around
1412 * the generic device structure functions of these calls.
1413 */
1414 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1415 {
1416 return dev_get_drvdata(&pdev->dev);
1417 }
1418
1419 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1420 {
1421 dev_set_drvdata(&pdev->dev, data);
1422 }
1423
1424 /* If you want to know what to call your pci_dev, ask this function.
1425 * Again, it's a wrapper around the generic device.
1426 */
1427 static inline const char *pci_name(const struct pci_dev *pdev)
1428 {
1429 return dev_name(&pdev->dev);
1430 }
1431
1432
1433 /* Some archs don't want to expose struct resource to userland as-is
1434 * in sysfs and /proc
1435 */
1436 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1437 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1438 const struct resource *rsrc, resource_size_t *start,
1439 resource_size_t *end)
1440 {
1441 *start = rsrc->start;
1442 *end = rsrc->end;
1443 }
1444 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1445
1446
1447 /*
1448 * The world is not perfect and supplies us with broken PCI devices.
1449 * For at least a part of these bugs we need a work-around, so both
1450 * generic (drivers/pci/quirks.c) and per-architecture code can define
1451 * fixup hooks to be called for particular buggy devices.
1452 */
1453
1454 struct pci_fixup {
1455 u16 vendor; /* You can use PCI_ANY_ID here of course */
1456 u16 device; /* You can use PCI_ANY_ID here of course */
1457 u32 class; /* You can use PCI_ANY_ID here too */
1458 unsigned int class_shift; /* should be 0, 8, 16 */
1459 void (*hook)(struct pci_dev *dev);
1460 };
1461
1462 enum pci_fixup_pass {
1463 pci_fixup_early, /* Before probing BARs */
1464 pci_fixup_header, /* After reading configuration header */
1465 pci_fixup_final, /* Final phase of device fixups */
1466 pci_fixup_enable, /* pci_enable_device() time */
1467 pci_fixup_resume, /* pci_device_resume() */
1468 pci_fixup_suspend, /* pci_device_suspend */
1469 pci_fixup_resume_early, /* pci_device_resume_early() */
1470 };
1471
1472 /* Anonymous variables would be nice... */
1473 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1474 class_shift, hook) \
1475 static const struct pci_fixup const __pci_fixup_##name __used \
1476 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1477 = { vendor, device, class, class_shift, hook };
1478
1479 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1480 class_shift, hook) \
1481 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1482 vendor##device##hook, vendor, device, class, class_shift, hook)
1483 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1484 class_shift, hook) \
1485 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1486 vendor##device##hook, vendor, device, class, class_shift, hook)
1487 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1488 class_shift, hook) \
1489 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1490 vendor##device##hook, vendor, device, class, class_shift, hook)
1491 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1492 class_shift, hook) \
1493 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1494 vendor##device##hook, vendor, device, class, class_shift, hook)
1495 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1496 class_shift, hook) \
1497 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1498 resume##vendor##device##hook, vendor, device, class, \
1499 class_shift, hook)
1500 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1501 class_shift, hook) \
1502 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1503 resume_early##vendor##device##hook, vendor, device, \
1504 class, class_shift, hook)
1505 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1506 class_shift, hook) \
1507 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1508 suspend##vendor##device##hook, vendor, device, class, \
1509 class_shift, hook)
1510
1511 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1512 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1513 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1514 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1515 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1516 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1517 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1518 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1519 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1520 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1521 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1522 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1523 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1524 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1525 resume##vendor##device##hook, vendor, device, \
1526 PCI_ANY_ID, 0, hook)
1527 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1528 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1529 resume_early##vendor##device##hook, vendor, device, \
1530 PCI_ANY_ID, 0, hook)
1531 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1532 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1533 suspend##vendor##device##hook, vendor, device, \
1534 PCI_ANY_ID, 0, hook)
1535
1536 #ifdef CONFIG_PCI_QUIRKS
1537 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1538 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1539 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1540 #else
1541 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1542 struct pci_dev *dev) {}
1543 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1544 {
1545 return pci_dev_get(dev);
1546 }
1547 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1548 u16 acs_flags)
1549 {
1550 return -ENOTTY;
1551 }
1552 #endif
1553
1554 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1555 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1556 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1557 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1558 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1559 const char *name);
1560 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1561
1562 extern int pci_pci_problems;
1563 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1564 #define PCIPCI_TRITON 2
1565 #define PCIPCI_NATOMA 4
1566 #define PCIPCI_VIAETBF 8
1567 #define PCIPCI_VSFX 16
1568 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1569 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1570
1571 extern unsigned long pci_cardbus_io_size;
1572 extern unsigned long pci_cardbus_mem_size;
1573 extern u8 __devinitdata pci_dfl_cache_line_size;
1574 extern u8 pci_cache_line_size;
1575
1576 extern unsigned long pci_hotplug_io_size;
1577 extern unsigned long pci_hotplug_mem_size;
1578
1579 /* Architecture specific versions may override these (weak) */
1580 int pcibios_add_platform_entries(struct pci_dev *dev);
1581 void pcibios_disable_device(struct pci_dev *dev);
1582 void pcibios_set_master(struct pci_dev *dev);
1583 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1584 enum pcie_reset_state state);
1585
1586 #ifdef CONFIG_PCI_MMCONFIG
1587 extern void __init pci_mmcfg_early_init(void);
1588 extern void __init pci_mmcfg_late_init(void);
1589 #else
1590 static inline void pci_mmcfg_early_init(void) { }
1591 static inline void pci_mmcfg_late_init(void) { }
1592 #endif
1593
1594 int pci_ext_cfg_avail(struct pci_dev *dev);
1595
1596 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1597
1598 #ifdef CONFIG_PCI_IOV
1599 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1600 extern void pci_disable_sriov(struct pci_dev *dev);
1601 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1602 extern int pci_num_vf(struct pci_dev *dev);
1603 #else
1604 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1605 {
1606 return -ENODEV;
1607 }
1608 static inline void pci_disable_sriov(struct pci_dev *dev)
1609 {
1610 }
1611 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1612 {
1613 return IRQ_NONE;
1614 }
1615 static inline int pci_num_vf(struct pci_dev *dev)
1616 {
1617 return 0;
1618 }
1619 #endif
1620
1621 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1622 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1623 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1624 #endif
1625
1626 /**
1627 * pci_pcie_cap - get the saved PCIe capability offset
1628 * @dev: PCI device
1629 *
1630 * PCIe capability offset is calculated at PCI device initialization
1631 * time and saved in the data structure. This function returns saved
1632 * PCIe capability offset. Using this instead of pci_find_capability()
1633 * reduces unnecessary search in the PCI configuration space. If you
1634 * need to calculate PCIe capability offset from raw device for some
1635 * reasons, please use pci_find_capability() instead.
1636 */
1637 static inline int pci_pcie_cap(struct pci_dev *dev)
1638 {
1639 return dev->pcie_cap;
1640 }
1641
1642 /**
1643 * pci_is_pcie - check if the PCI device is PCI Express capable
1644 * @dev: PCI device
1645 *
1646 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1647 */
1648 static inline bool pci_is_pcie(struct pci_dev *dev)
1649 {
1650 return !!pci_pcie_cap(dev);
1651 }
1652
1653 void pci_request_acs(void);
1654 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1655 bool pci_acs_path_enabled(struct pci_dev *start,
1656 struct pci_dev *end, u16 acs_flags);
1657
1658 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1659 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1660
1661 /* Large Resource Data Type Tag Item Names */
1662 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1663 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1664 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1665
1666 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1667 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1668 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1669
1670 /* Small Resource Data Type Tag Item Names */
1671 #define PCI_VPD_STIN_END 0x78 /* End */
1672
1673 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1674
1675 #define PCI_VPD_SRDT_TIN_MASK 0x78
1676 #define PCI_VPD_SRDT_LEN_MASK 0x07
1677
1678 #define PCI_VPD_LRDT_TAG_SIZE 3
1679 #define PCI_VPD_SRDT_TAG_SIZE 1
1680
1681 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1682
1683 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1684 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1685 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1686 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1687
1688 /**
1689 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1690 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1691 *
1692 * Returns the extracted Large Resource Data Type length.
1693 */
1694 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1695 {
1696 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1697 }
1698
1699 /**
1700 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1701 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1702 *
1703 * Returns the extracted Small Resource Data Type length.
1704 */
1705 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1706 {
1707 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1708 }
1709
1710 /**
1711 * pci_vpd_info_field_size - Extracts the information field length
1712 * @lrdt: Pointer to the beginning of an information field header
1713 *
1714 * Returns the extracted information field length.
1715 */
1716 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1717 {
1718 return info_field[2];
1719 }
1720
1721 /**
1722 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1723 * @buf: Pointer to buffered vpd data
1724 * @off: The offset into the buffer at which to begin the search
1725 * @len: The length of the vpd buffer
1726 * @rdt: The Resource Data Type to search for
1727 *
1728 * Returns the index where the Resource Data Type was found or
1729 * -ENOENT otherwise.
1730 */
1731 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1732
1733 /**
1734 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1735 * @buf: Pointer to buffered vpd data
1736 * @off: The offset into the buffer at which to begin the search
1737 * @len: The length of the buffer area, relative to off, in which to search
1738 * @kw: The keyword to search for
1739 *
1740 * Returns the index where the information field keyword was found or
1741 * -ENOENT otherwise.
1742 */
1743 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1744 unsigned int len, const char *kw);
1745
1746 /* PCI <-> OF binding helpers */
1747 #ifdef CONFIG_OF
1748 struct device_node;
1749 extern void pci_set_of_node(struct pci_dev *dev);
1750 extern void pci_release_of_node(struct pci_dev *dev);
1751 extern void pci_set_bus_of_node(struct pci_bus *bus);
1752 extern void pci_release_bus_of_node(struct pci_bus *bus);
1753
1754 /* Arch may override this (weak) */
1755 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1756
1757 static inline struct device_node *
1758 pci_device_to_OF_node(const struct pci_dev *pdev)
1759 {
1760 return pdev ? pdev->dev.of_node : NULL;
1761 }
1762
1763 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1764 {
1765 return bus ? bus->dev.of_node : NULL;
1766 }
1767
1768 #else /* CONFIG_OF */
1769 static inline void pci_set_of_node(struct pci_dev *dev) { }
1770 static inline void pci_release_of_node(struct pci_dev *dev) { }
1771 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1772 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1773 #endif /* CONFIG_OF */
1774
1775 #ifdef CONFIG_EEH
1776 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1777 {
1778 return pdev->dev.archdata.edev;
1779 }
1780 #endif
1781
1782 /**
1783 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1784 * @pdev: the PCI device
1785 *
1786 * if the device is PCIE, return NULL
1787 * if the device isn't connected to a PCIe bridge (that is its parent is a
1788 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1789 * parent
1790 */
1791 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1792
1793 #endif /* __KERNEL__ */
1794 #endif /* LINUX_PCI_H */
CJK support for tty framebuffer vt