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Linux 3.9-rc4
[linux-2.6/cjktty.git] / drivers / net / phy / marvell.c
blob22dec9c7ef05d7480e87b575605e2240f4476a20
1 /*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/spinlock.h>
27 #include <linux/mm.h>
28 #include <linux/module.h>
29 #include <linux/mii.h>
30 #include <linux/ethtool.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/of.h>
34
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 #include <asm/uaccess.h>
38
39 #define MII_MARVELL_PHY_PAGE 22
40
41 #define MII_M1011_IEVENT 0x13
42 #define MII_M1011_IEVENT_CLEAR 0x0000
43
44 #define MII_M1011_IMASK 0x12
45 #define MII_M1011_IMASK_INIT 0x6400
46 #define MII_M1011_IMASK_CLEAR 0x0000
47
48 #define MII_M1011_PHY_SCR 0x10
49 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
50
51 #define MII_M1145_PHY_EXT_CR 0x14
52 #define MII_M1145_RGMII_RX_DELAY 0x0080
53 #define MII_M1145_RGMII_TX_DELAY 0x0002
54
55 #define MII_M1111_PHY_LED_CONTROL 0x18
56 #define MII_M1111_PHY_LED_DIRECT 0x4100
57 #define MII_M1111_PHY_LED_COMBINE 0x411c
58 #define MII_M1111_PHY_EXT_CR 0x14
59 #define MII_M1111_RX_DELAY 0x80
60 #define MII_M1111_TX_DELAY 0x2
61 #define MII_M1111_PHY_EXT_SR 0x1b
62
63 #define MII_M1111_HWCFG_MODE_MASK 0xf
64 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
65 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
66 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
67 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
68 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
69 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
70
71 #define MII_M1111_COPPER 0
72 #define MII_M1111_FIBER 1
73
74 #define MII_88E1121_PHY_MSCR_PAGE 2
75 #define MII_88E1121_PHY_MSCR_REG 21
76 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
77 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
78 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
79
80 #define MII_88E1318S_PHY_MSCR1_REG 16
81 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
82
83 #define MII_88E1121_PHY_LED_CTRL 16
84 #define MII_88E1121_PHY_LED_PAGE 3
85 #define MII_88E1121_PHY_LED_DEF 0x0030
86
87 #define MII_M1011_PHY_STATUS 0x11
88 #define MII_M1011_PHY_STATUS_1000 0x8000
89 #define MII_M1011_PHY_STATUS_100 0x4000
90 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
91 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
92 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
93 #define MII_M1011_PHY_STATUS_LINK 0x0400
94
95
96 MODULE_DESCRIPTION("Marvell PHY driver");
97 MODULE_AUTHOR("Andy Fleming");
98 MODULE_LICENSE("GPL");
99
100 static int marvell_ack_interrupt(struct phy_device *phydev)
101 {
102 int err;
103
104 /* Clear the interrupts by reading the reg */
105 err = phy_read(phydev, MII_M1011_IEVENT);
106
107 if (err < 0)
108 return err;
109
110 return 0;
111 }
112
113 static int marvell_config_intr(struct phy_device *phydev)
114 {
115 int err;
116
117 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
118 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
119 else
120 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
121
122 return err;
123 }
124
125 static int marvell_config_aneg(struct phy_device *phydev)
126 {
127 int err;
128
129 /* The Marvell PHY has an errata which requires
130 * that certain registers get written in order
131 * to restart autonegotiation */
132 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
133
134 if (err < 0)
135 return err;
136
137 err = phy_write(phydev, 0x1d, 0x1f);
138 if (err < 0)
139 return err;
140
141 err = phy_write(phydev, 0x1e, 0x200c);
142 if (err < 0)
143 return err;
144
145 err = phy_write(phydev, 0x1d, 0x5);
146 if (err < 0)
147 return err;
148
149 err = phy_write(phydev, 0x1e, 0);
150 if (err < 0)
151 return err;
152
153 err = phy_write(phydev, 0x1e, 0x100);
154 if (err < 0)
155 return err;
156
157 err = phy_write(phydev, MII_M1011_PHY_SCR,
158 MII_M1011_PHY_SCR_AUTO_CROSS);
159 if (err < 0)
160 return err;
161
162 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
163 MII_M1111_PHY_LED_DIRECT);
164 if (err < 0)
165 return err;
166
167 err = genphy_config_aneg(phydev);
168 if (err < 0)
169 return err;
170
171 if (phydev->autoneg != AUTONEG_ENABLE) {
172 int bmcr;
173
174 /*
175 * A write to speed/duplex bits (that is performed by
176 * genphy_config_aneg() call above) must be followed by
177 * a software reset. Otherwise, the write has no effect.
178 */
179 bmcr = phy_read(phydev, MII_BMCR);
180 if (bmcr < 0)
181 return bmcr;
182
183 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
184 if (err < 0)
185 return err;
186 }
187
188 return 0;
189 }
190
191 #ifdef CONFIG_OF_MDIO
192 /*
193 * Set and/or override some configuration registers based on the
194 * marvell,reg-init property stored in the of_node for the phydev.
195 *
196 * marvell,reg-init = <reg-page reg mask value>,...;
197 *
198 * There may be one or more sets of <reg-page reg mask value>:
199 *
200 * reg-page: which register bank to use.
201 * reg: the register.
202 * mask: if non-zero, ANDed with existing register value.
203 * value: ORed with the masked value and written to the regiser.
204 *
205 */
206 static int marvell_of_reg_init(struct phy_device *phydev)
207 {
208 const __be32 *paddr;
209 int len, i, saved_page, current_page, page_changed, ret;
210
211 if (!phydev->dev.of_node)
212 return 0;
213
214 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
215 if (!paddr || len < (4 * sizeof(*paddr)))
216 return 0;
217
218 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
219 if (saved_page < 0)
220 return saved_page;
221 page_changed = 0;
222 current_page = saved_page;
223
224 ret = 0;
225 len /= sizeof(*paddr);
226 for (i = 0; i < len - 3; i += 4) {
227 u16 reg_page = be32_to_cpup(paddr + i);
228 u16 reg = be32_to_cpup(paddr + i + 1);
229 u16 mask = be32_to_cpup(paddr + i + 2);
230 u16 val_bits = be32_to_cpup(paddr + i + 3);
231 int val;
232
233 if (reg_page != current_page) {
234 current_page = reg_page;
235 page_changed = 1;
236 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
237 if (ret < 0)
238 goto err;
239 }
240
241 val = 0;
242 if (mask) {
243 val = phy_read(phydev, reg);
244 if (val < 0) {
245 ret = val;
246 goto err;
247 }
248 val &= mask;
249 }
250 val |= val_bits;
251
252 ret = phy_write(phydev, reg, val);
253 if (ret < 0)
254 goto err;
255
256 }
257 err:
258 if (page_changed) {
259 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
260 if (ret == 0)
261 ret = i;
262 }
263 return ret;
264 }
265 #else
266 static int marvell_of_reg_init(struct phy_device *phydev)
267 {
268 return 0;
269 }
270 #endif /* CONFIG_OF_MDIO */
271
272 static int m88e1121_config_aneg(struct phy_device *phydev)
273 {
274 int err, oldpage, mscr;
275
276 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
277
278 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
279 MII_88E1121_PHY_MSCR_PAGE);
280 if (err < 0)
281 return err;
282
283 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
284 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
285 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
286 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
287
288 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
289 MII_88E1121_PHY_MSCR_DELAY_MASK;
290
291 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
292 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
293 MII_88E1121_PHY_MSCR_TX_DELAY);
294 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
295 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
296 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
297 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
298
299 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
300 if (err < 0)
301 return err;
302 }
303
304 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
305
306 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
307 if (err < 0)
308 return err;
309
310 err = phy_write(phydev, MII_M1011_PHY_SCR,
311 MII_M1011_PHY_SCR_AUTO_CROSS);
312 if (err < 0)
313 return err;
314
315 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
316
317 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
318 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
319 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
320
321 err = genphy_config_aneg(phydev);
322
323 return err;
324 }
325
326 static int m88e1318_config_aneg(struct phy_device *phydev)
327 {
328 int err, oldpage, mscr;
329
330 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
331
332 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
333 MII_88E1121_PHY_MSCR_PAGE);
334 if (err < 0)
335 return err;
336
337 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
338 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
339
340 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
341 if (err < 0)
342 return err;
343
344 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
345 if (err < 0)
346 return err;
347
348 return m88e1121_config_aneg(phydev);
349 }
350
351 static int m88e1111_config_init(struct phy_device *phydev)
352 {
353 int err;
354 int temp;
355
356 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
357 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
358 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
359 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
360
361 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
362 if (temp < 0)
363 return temp;
364
365 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
366 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
367 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
368 temp &= ~MII_M1111_TX_DELAY;
369 temp |= MII_M1111_RX_DELAY;
370 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
371 temp &= ~MII_M1111_RX_DELAY;
372 temp |= MII_M1111_TX_DELAY;
373 }
374
375 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
376 if (err < 0)
377 return err;
378
379 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
380 if (temp < 0)
381 return temp;
382
383 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
384
385 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
386 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
387 else
388 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
389
390 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
391 if (err < 0)
392 return err;
393 }
394
395 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
396 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
397 if (temp < 0)
398 return temp;
399
400 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
401 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
402 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
403
404 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
405 if (err < 0)
406 return err;
407 }
408
409 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
410 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
411 if (temp < 0)
412 return temp;
413 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
414 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
415 if (err < 0)
416 return err;
417
418 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
419 if (temp < 0)
420 return temp;
421 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
422 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
423 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
424 if (err < 0)
425 return err;
426
427 /* soft reset */
428 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
429 if (err < 0)
430 return err;
431 do
432 temp = phy_read(phydev, MII_BMCR);
433 while (temp & BMCR_RESET);
434
435 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
436 if (temp < 0)
437 return temp;
438 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
439 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
440 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
441 if (err < 0)
442 return err;
443 }
444
445 err = marvell_of_reg_init(phydev);
446 if (err < 0)
447 return err;
448
449 return phy_write(phydev, MII_BMCR, BMCR_RESET);
450 }
451
452 static int m88e1118_config_aneg(struct phy_device *phydev)
453 {
454 int err;
455
456 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
457 if (err < 0)
458 return err;
459
460 err = phy_write(phydev, MII_M1011_PHY_SCR,
461 MII_M1011_PHY_SCR_AUTO_CROSS);
462 if (err < 0)
463 return err;
464
465 err = genphy_config_aneg(phydev);
466 return 0;
467 }
468
469 static int m88e1118_config_init(struct phy_device *phydev)
470 {
471 int err;
472
473 /* Change address */
474 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
475 if (err < 0)
476 return err;
477
478 /* Enable 1000 Mbit */
479 err = phy_write(phydev, 0x15, 0x1070);
480 if (err < 0)
481 return err;
482
483 /* Change address */
484 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
485 if (err < 0)
486 return err;
487
488 /* Adjust LED Control */
489 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
490 err = phy_write(phydev, 0x10, 0x1100);
491 else
492 err = phy_write(phydev, 0x10, 0x021e);
493 if (err < 0)
494 return err;
495
496 err = marvell_of_reg_init(phydev);
497 if (err < 0)
498 return err;
499
500 /* Reset address */
501 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
502 if (err < 0)
503 return err;
504
505 return phy_write(phydev, MII_BMCR, BMCR_RESET);
506 }
507
508 static int m88e1149_config_init(struct phy_device *phydev)
509 {
510 int err;
511
512 /* Change address */
513 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
514 if (err < 0)
515 return err;
516
517 /* Enable 1000 Mbit */
518 err = phy_write(phydev, 0x15, 0x1048);
519 if (err < 0)
520 return err;
521
522 err = marvell_of_reg_init(phydev);
523 if (err < 0)
524 return err;
525
526 /* Reset address */
527 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
528 if (err < 0)
529 return err;
530
531 return phy_write(phydev, MII_BMCR, BMCR_RESET);
532 }
533
534 static int m88e1145_config_init(struct phy_device *phydev)
535 {
536 int err;
537
538 /* Take care of errata E0 & E1 */
539 err = phy_write(phydev, 0x1d, 0x001b);
540 if (err < 0)
541 return err;
542
543 err = phy_write(phydev, 0x1e, 0x418f);
544 if (err < 0)
545 return err;
546
547 err = phy_write(phydev, 0x1d, 0x0016);
548 if (err < 0)
549 return err;
550
551 err = phy_write(phydev, 0x1e, 0xa2da);
552 if (err < 0)
553 return err;
554
555 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
556 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
557 if (temp < 0)
558 return temp;
559
560 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
561
562 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
563 if (err < 0)
564 return err;
565
566 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
567 err = phy_write(phydev, 0x1d, 0x0012);
568 if (err < 0)
569 return err;
570
571 temp = phy_read(phydev, 0x1e);
572 if (temp < 0)
573 return temp;
574
575 temp &= 0xf03f;
576 temp |= 2 << 9; /* 36 ohm */
577 temp |= 2 << 6; /* 39 ohm */
578
579 err = phy_write(phydev, 0x1e, temp);
580 if (err < 0)
581 return err;
582
583 err = phy_write(phydev, 0x1d, 0x3);
584 if (err < 0)
585 return err;
586
587 err = phy_write(phydev, 0x1e, 0x8000);
588 if (err < 0)
589 return err;
590 }
591 }
592
593 err = marvell_of_reg_init(phydev);
594 if (err < 0)
595 return err;
596
597 return 0;
598 }
599
600 /* marvell_read_status
601 *
602 * Generic status code does not detect Fiber correctly!
603 * Description:
604 * Check the link, then figure out the current state
605 * by comparing what we advertise with what the link partner
606 * advertises. Start by checking the gigabit possibilities,
607 * then move on to 10/100.
608 */
609 static int marvell_read_status(struct phy_device *phydev)
610 {
611 int adv;
612 int err;
613 int lpa;
614 int status = 0;
615
616 /* Update the link, but return if there
617 * was an error */
618 err = genphy_update_link(phydev);
619 if (err)
620 return err;
621
622 if (AUTONEG_ENABLE == phydev->autoneg) {
623 status = phy_read(phydev, MII_M1011_PHY_STATUS);
624 if (status < 0)
625 return status;
626
627 lpa = phy_read(phydev, MII_LPA);
628 if (lpa < 0)
629 return lpa;
630
631 adv = phy_read(phydev, MII_ADVERTISE);
632 if (adv < 0)
633 return adv;
634
635 lpa &= adv;
636
637 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
638 phydev->duplex = DUPLEX_FULL;
639 else
640 phydev->duplex = DUPLEX_HALF;
641
642 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
643 phydev->pause = phydev->asym_pause = 0;
644
645 switch (status) {
646 case MII_M1011_PHY_STATUS_1000:
647 phydev->speed = SPEED_1000;
648 break;
649
650 case MII_M1011_PHY_STATUS_100:
651 phydev->speed = SPEED_100;
652 break;
653
654 default:
655 phydev->speed = SPEED_10;
656 break;
657 }
658
659 if (phydev->duplex == DUPLEX_FULL) {
660 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
661 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
662 }
663 } else {
664 int bmcr = phy_read(phydev, MII_BMCR);
665
666 if (bmcr < 0)
667 return bmcr;
668
669 if (bmcr & BMCR_FULLDPLX)
670 phydev->duplex = DUPLEX_FULL;
671 else
672 phydev->duplex = DUPLEX_HALF;
673
674 if (bmcr & BMCR_SPEED1000)
675 phydev->speed = SPEED_1000;
676 else if (bmcr & BMCR_SPEED100)
677 phydev->speed = SPEED_100;
678 else
679 phydev->speed = SPEED_10;
680
681 phydev->pause = phydev->asym_pause = 0;
682 }
683
684 return 0;
685 }
686
687 static int m88e1121_did_interrupt(struct phy_device *phydev)
688 {
689 int imask;
690
691 imask = phy_read(phydev, MII_M1011_IEVENT);
692
693 if (imask & MII_M1011_IMASK_INIT)
694 return 1;
695
696 return 0;
697 }
698
699 static struct phy_driver marvell_drivers[] = {
700 {
701 .phy_id = MARVELL_PHY_ID_88E1101,
702 .phy_id_mask = MARVELL_PHY_ID_MASK,
703 .name = "Marvell 88E1101",
704 .features = PHY_GBIT_FEATURES,
705 .flags = PHY_HAS_INTERRUPT,
706 .config_aneg = &marvell_config_aneg,
707 .read_status = &genphy_read_status,
708 .ack_interrupt = &marvell_ack_interrupt,
709 .config_intr = &marvell_config_intr,
710 .driver = { .owner = THIS_MODULE },
711 },
712 {
713 .phy_id = MARVELL_PHY_ID_88E1112,
714 .phy_id_mask = MARVELL_PHY_ID_MASK,
715 .name = "Marvell 88E1112",
716 .features = PHY_GBIT_FEATURES,
717 .flags = PHY_HAS_INTERRUPT,
718 .config_init = &m88e1111_config_init,
719 .config_aneg = &marvell_config_aneg,
720 .read_status = &genphy_read_status,
721 .ack_interrupt = &marvell_ack_interrupt,
722 .config_intr = &marvell_config_intr,
723 .driver = { .owner = THIS_MODULE },
724 },
725 {
726 .phy_id = MARVELL_PHY_ID_88E1111,
727 .phy_id_mask = MARVELL_PHY_ID_MASK,
728 .name = "Marvell 88E1111",
729 .features = PHY_GBIT_FEATURES,
730 .flags = PHY_HAS_INTERRUPT,
731 .config_init = &m88e1111_config_init,
732 .config_aneg = &marvell_config_aneg,
733 .read_status = &marvell_read_status,
734 .ack_interrupt = &marvell_ack_interrupt,
735 .config_intr = &marvell_config_intr,
736 .driver = { .owner = THIS_MODULE },
737 },
738 {
739 .phy_id = MARVELL_PHY_ID_88E1118,
740 .phy_id_mask = MARVELL_PHY_ID_MASK,
741 .name = "Marvell 88E1118",
742 .features = PHY_GBIT_FEATURES,
743 .flags = PHY_HAS_INTERRUPT,
744 .config_init = &m88e1118_config_init,
745 .config_aneg = &m88e1118_config_aneg,
746 .read_status = &genphy_read_status,
747 .ack_interrupt = &marvell_ack_interrupt,
748 .config_intr = &marvell_config_intr,
749 .driver = {.owner = THIS_MODULE,},
750 },
751 {
752 .phy_id = MARVELL_PHY_ID_88E1121R,
753 .phy_id_mask = MARVELL_PHY_ID_MASK,
754 .name = "Marvell 88E1121R",
755 .features = PHY_GBIT_FEATURES,
756 .flags = PHY_HAS_INTERRUPT,
757 .config_aneg = &m88e1121_config_aneg,
758 .read_status = &marvell_read_status,
759 .ack_interrupt = &marvell_ack_interrupt,
760 .config_intr = &marvell_config_intr,
761 .did_interrupt = &m88e1121_did_interrupt,
762 .driver = { .owner = THIS_MODULE },
763 },
764 {
765 .phy_id = MARVELL_PHY_ID_88E1318S,
766 .phy_id_mask = MARVELL_PHY_ID_MASK,
767 .name = "Marvell 88E1318S",
768 .features = PHY_GBIT_FEATURES,
769 .flags = PHY_HAS_INTERRUPT,
770 .config_aneg = &m88e1318_config_aneg,
771 .read_status = &marvell_read_status,
772 .ack_interrupt = &marvell_ack_interrupt,
773 .config_intr = &marvell_config_intr,
774 .did_interrupt = &m88e1121_did_interrupt,
775 .driver = { .owner = THIS_MODULE },
776 },
777 {
778 .phy_id = MARVELL_PHY_ID_88E1145,
779 .phy_id_mask = MARVELL_PHY_ID_MASK,
780 .name = "Marvell 88E1145",
781 .features = PHY_GBIT_FEATURES,
782 .flags = PHY_HAS_INTERRUPT,
783 .config_init = &m88e1145_config_init,
784 .config_aneg = &marvell_config_aneg,
785 .read_status = &genphy_read_status,
786 .ack_interrupt = &marvell_ack_interrupt,
787 .config_intr = &marvell_config_intr,
788 .driver = { .owner = THIS_MODULE },
789 },
790 {
791 .phy_id = MARVELL_PHY_ID_88E1149R,
792 .phy_id_mask = MARVELL_PHY_ID_MASK,
793 .name = "Marvell 88E1149R",
794 .features = PHY_GBIT_FEATURES,
795 .flags = PHY_HAS_INTERRUPT,
796 .config_init = &m88e1149_config_init,
797 .config_aneg = &m88e1118_config_aneg,
798 .read_status = &genphy_read_status,
799 .ack_interrupt = &marvell_ack_interrupt,
800 .config_intr = &marvell_config_intr,
801 .driver = { .owner = THIS_MODULE },
802 },
803 {
804 .phy_id = MARVELL_PHY_ID_88E1240,
805 .phy_id_mask = MARVELL_PHY_ID_MASK,
806 .name = "Marvell 88E1240",
807 .features = PHY_GBIT_FEATURES,
808 .flags = PHY_HAS_INTERRUPT,
809 .config_init = &m88e1111_config_init,
810 .config_aneg = &marvell_config_aneg,
811 .read_status = &genphy_read_status,
812 .ack_interrupt = &marvell_ack_interrupt,
813 .config_intr = &marvell_config_intr,
814 .driver = { .owner = THIS_MODULE },
815 },
816 };
817
818 static int __init marvell_init(void)
819 {
820 return phy_drivers_register(marvell_drivers,
821 ARRAY_SIZE(marvell_drivers));
822 }
823
824 static void __exit marvell_exit(void)
825 {
826 phy_drivers_unregister(marvell_drivers,
827 ARRAY_SIZE(marvell_drivers));
828 }
829
830 module_init(marvell_init);
831 module_exit(marvell_exit);
832
833 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
834 { 0x01410c60, 0xfffffff0 },
835 { 0x01410c90, 0xfffffff0 },
836 { 0x01410cc0, 0xfffffff0 },
837 { 0x01410e10, 0xfffffff0 },
838 { 0x01410cb0, 0xfffffff0 },
839 { 0x01410cd0, 0xfffffff0 },
840 { 0x01410e50, 0xfffffff0 },
841 { 0x01410e30, 0xfffffff0 },
842 { 0x01410e90, 0xfffffff0 },
843 { }
844 };
845
846 MODULE_DEVICE_TABLE(mdio, marvell_tbl);
CJK support for tty framebuffer vt