2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
37 #include <linux/slab.h>
39 #include <linux/tcp.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.30"
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 63
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
81 static const u32 default_msg
=
82 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
83 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
86 static int debug
= -1; /* defaults above */
87 module_param(debug
, int, 0);
88 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly
= 128;
91 module_param(copybreak
, int, 0);
92 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
94 static int disable_msi
= 0;
95 module_param(disable_msi
, int, 0);
96 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
98 static int legacy_pme
= 0;
99 module_param(legacy_pme
, int, 0);
100 MODULE_PARM_DESC(legacy_pme
, "Legacy power management");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4381) }, /* 88E8059 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4382) }, /* 88E8079 */
148 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
150 /* Avoid conditionals by using array */
151 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
152 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
153 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
155 static void sky2_set_multicast(struct net_device
*dev
);
156 static irqreturn_t
sky2_intr(int irq
, void *dev_id
);
158 /* Access to PHY via serial interconnect */
159 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
163 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
164 gma_write16(hw
, port
, GM_SMI_CTRL
,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
167 for (i
= 0; i
< PHY_RETRIES
; i
++) {
168 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
172 if (!(ctrl
& GM_SMI_CT_BUSY
))
178 dev_warn(&hw
->pdev
->dev
, "%s: phy write timeout\n", hw
->dev
[port
]->name
);
182 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
186 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
190 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
191 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
193 for (i
= 0; i
< PHY_RETRIES
; i
++) {
194 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
198 if (ctrl
& GM_SMI_CT_RD_VAL
) {
199 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
206 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
209 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
213 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
216 __gm_phy_read(hw
, port
, reg
, &v
);
221 static void sky2_power_on(struct sky2_hw
*hw
)
223 /* switch power to VCC (WA for VAUX problem) */
224 sky2_write8(hw
, B0_POWER_CTRL
,
225 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
227 /* disable Core Clock Division, */
228 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
230 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> CHIP_REV_YU_XL_A1
)
231 /* enable bits are inverted */
232 sky2_write8(hw
, B2_Y2_CLK_GATE
,
233 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
234 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
235 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
237 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
239 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
242 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
244 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
245 /* set all bits to 0 except bits 15..12 and 8 */
246 reg
&= P_ASPM_CONTROL_MSK
;
247 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
249 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
250 /* set all bits to 0 except bits 28 & 27 */
251 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
252 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
254 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
256 sky2_write16(hw
, B0_CTST
, Y2_HW_WOL_ON
);
258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg
= sky2_read32(hw
, B2_GP_IO
);
260 reg
|= GLB_GPIO_STAT_RACE_DIS
;
261 sky2_write32(hw
, B2_GP_IO
, reg
);
263 sky2_read32(hw
, B2_GP_IO
);
266 /* Turn on "driver loaded" LED */
267 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_ON
);
270 static void sky2_power_aux(struct sky2_hw
*hw
)
272 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> CHIP_REV_YU_XL_A1
)
273 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
275 /* enable bits are inverted */
276 sky2_write8(hw
, B2_Y2_CLK_GATE
,
277 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
278 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
279 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
281 /* switch power to VAUX if supported and PME from D3cold */
282 if ( (sky2_read32(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
283 pci_pme_capable(hw
->pdev
, PCI_D3cold
))
284 sky2_write8(hw
, B0_POWER_CTRL
,
285 (PC_VAUX_ENA
| PC_VCC_ENA
|
286 PC_VAUX_ON
| PC_VCC_OFF
));
288 /* turn off "driver loaded LED" */
289 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_OFF
);
292 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
296 /* disable all GMAC IRQ's */
297 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
299 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
300 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
301 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
302 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
304 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
305 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
306 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
309 /* flow control to advertise bits */
310 static const u16 copper_fc_adv
[] = {
312 [FC_TX
] = PHY_M_AN_ASP
,
313 [FC_RX
] = PHY_M_AN_PC
,
314 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
317 /* flow control to advertise bits when using 1000BaseX */
318 static const u16 fiber_fc_adv
[] = {
319 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
320 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
321 [FC_RX
] = PHY_M_P_SYM_MD_X
,
322 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
325 /* flow control to GMA disable bits */
326 static const u16 gm_fc_disable
[] = {
327 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
328 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
329 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
334 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
336 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
337 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
339 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
340 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
341 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
343 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
345 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
347 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
348 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
349 /* set downshift counter to 3x and enable downshift */
350 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
352 /* set master & slave downshift counter to 1x */
353 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
355 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
358 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
359 if (sky2_is_copper(hw
)) {
360 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
361 /* enable automatic crossover */
362 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
364 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
365 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
368 /* Enable Class A driver for FE+ A0 */
369 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
370 spec
|= PHY_M_FESC_SEL_CL_A
;
371 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
374 /* disable energy detect */
375 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
377 /* enable automatic crossover */
378 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
380 /* downshift on PHY 88E1112 and 88E1149 is changed */
381 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
382 (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
383 /* set downshift counter to 3x and enable downshift */
384 ctrl
&= ~PHY_M_PC_DSC_MSK
;
385 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
389 /* workaround for deviation #4.88 (CRC errors) */
390 /* disable Automatic Crossover */
392 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
395 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
397 /* special setup for PHY 88E1112 Fiber */
398 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
399 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
401 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
402 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
403 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
404 ctrl
&= ~PHY_M_MAC_MD_MSK
;
405 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
406 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
408 if (hw
->pmd_type
== 'P') {
409 /* select page 1 to access Fiber registers */
410 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
412 /* for SFP-module set SIGDET polarity to low */
413 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
414 ctrl
|= PHY_M_FIB_SIGD_POL
;
415 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
418 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
426 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) {
427 if (sky2_is_copper(hw
)) {
428 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
429 ct1000
|= PHY_M_1000C_AFD
;
430 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
431 ct1000
|= PHY_M_1000C_AHD
;
432 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
433 adv
|= PHY_M_AN_100_FD
;
434 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
435 adv
|= PHY_M_AN_100_HD
;
436 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
437 adv
|= PHY_M_AN_10_FD
;
438 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
439 adv
|= PHY_M_AN_10_HD
;
441 } else { /* special defines for FIBER (88E1040S only) */
442 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
443 adv
|= PHY_M_AN_1000X_AFD
;
444 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
445 adv
|= PHY_M_AN_1000X_AHD
;
448 /* Restart Auto-negotiation */
449 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
451 /* forced speed/duplex settings */
452 ct1000
= PHY_M_1000C_MSE
;
454 /* Disable auto update for duplex flow control and duplex */
455 reg
|= GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_SPD_DIS
;
457 switch (sky2
->speed
) {
459 ctrl
|= PHY_CT_SP1000
;
460 reg
|= GM_GPCR_SPEED_1000
;
463 ctrl
|= PHY_CT_SP100
;
464 reg
|= GM_GPCR_SPEED_100
;
468 if (sky2
->duplex
== DUPLEX_FULL
) {
469 reg
|= GM_GPCR_DUP_FULL
;
470 ctrl
|= PHY_CT_DUP_MD
;
471 } else if (sky2
->speed
< SPEED_1000
)
472 sky2
->flow_mode
= FC_NONE
;
475 if (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
) {
476 if (sky2_is_copper(hw
))
477 adv
|= copper_fc_adv
[sky2
->flow_mode
];
479 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
481 reg
|= GM_GPCR_AU_FCT_DIS
;
482 reg
|= gm_fc_disable
[sky2
->flow_mode
];
484 /* Forward pause packets to GMAC? */
485 if (sky2
->flow_mode
& FC_RX
)
486 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
488 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
491 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
493 if (hw
->flags
& SKY2_HW_GIGABIT
)
494 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
496 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
497 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
499 /* Setup Phy LED's */
500 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
503 switch (hw
->chip_id
) {
504 case CHIP_ID_YUKON_FE
:
505 /* on 88E3082 these bits are at 11..9 (shifted left) */
506 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
508 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
510 /* delete ACT LED control bits */
511 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
512 /* change ACT LED control to blink mode */
513 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
514 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
517 case CHIP_ID_YUKON_FE_P
:
518 /* Enable Link Partner Next Page */
519 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
520 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
522 /* disable Energy Detect and enable scrambler */
523 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
524 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
526 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
527 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
528 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
529 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
531 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
534 case CHIP_ID_YUKON_XL
:
535 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
537 /* select page 3 to access LED control register */
538 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
540 /* set LED Function Control register */
541 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
542 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
543 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
544 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
545 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
547 /* set Polarity Control register */
548 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
549 (PHY_M_POLC_LS1_P_MIX(4) |
550 PHY_M_POLC_IS0_P_MIX(4) |
551 PHY_M_POLC_LOS_CTRL(2) |
552 PHY_M_POLC_INIT_CTRL(2) |
553 PHY_M_POLC_STA1_CTRL(2) |
554 PHY_M_POLC_STA0_CTRL(2)));
556 /* restore page register */
557 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
560 case CHIP_ID_YUKON_EC_U
:
561 case CHIP_ID_YUKON_EX
:
562 case CHIP_ID_YUKON_SUPR
:
563 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
565 /* select page 3 to access LED control register */
566 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
568 /* set LED Function Control register */
569 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
570 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
571 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
572 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
573 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
575 /* set Blink Rate in LED Timer Control Register */
576 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
577 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
578 /* restore page register */
579 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
583 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
584 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
586 /* turn off the Rx LED (LED_RX) */
587 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
590 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
591 /* apply fixes in PHY AFE */
592 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
594 /* increase differential signal amplitude in 10BASE-T */
595 gm_phy_write(hw
, port
, 0x18, 0xaa99);
596 gm_phy_write(hw
, port
, 0x17, 0x2011);
598 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
599 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
600 gm_phy_write(hw
, port
, 0x18, 0xa204);
601 gm_phy_write(hw
, port
, 0x17, 0x2002);
604 /* set page register to 0 */
605 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
606 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
607 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
608 /* apply workaround for integrated resistors calibration */
609 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
610 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
611 } else if (hw
->chip_id
== CHIP_ID_YUKON_OPT
&& hw
->chip_rev
== 0) {
612 /* apply fixes in PHY AFE */
613 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00ff);
615 /* apply RDAC termination workaround */
616 gm_phy_write(hw
, port
, 24, 0x2800);
617 gm_phy_write(hw
, port
, 23, 0x2001);
619 /* set page register back to 0 */
620 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
621 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
622 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
623 /* no effect on Yukon-XL */
624 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
626 if (!(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) ||
627 sky2
->speed
== SPEED_100
) {
628 /* turn on 100 Mbps LED (LED_LINK100) */
629 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
633 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
635 } else if (hw
->chip_id
== CHIP_ID_YUKON_PRM
&&
636 (sky2_read8(hw
, B2_MAC_CFG
) & 0xf) == 0x7) {
638 /* This a phy register setup workaround copied from vendor driver. */
639 static const struct {
645 /* { 0x155, 0x130b },*/
651 /* { 0x154, 0x2f39 },*/
655 /* { 0x158, 0x1223 },*/
662 /* Start Workaround for OptimaEEE Rev.Z0 */
663 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00fb);
665 gm_phy_write(hw
, port
, 1, 0x4099);
666 gm_phy_write(hw
, port
, 3, 0x1120);
667 gm_phy_write(hw
, port
, 11, 0x113c);
668 gm_phy_write(hw
, port
, 14, 0x8100);
669 gm_phy_write(hw
, port
, 15, 0x112a);
670 gm_phy_write(hw
, port
, 17, 0x1008);
672 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00fc);
673 gm_phy_write(hw
, port
, 1, 0x20b0);
675 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00ff);
677 for (i
= 0; i
< ARRAY_SIZE(eee_afe
); i
++) {
678 /* apply AFE settings */
679 gm_phy_write(hw
, port
, 17, eee_afe
[i
].val
);
680 gm_phy_write(hw
, port
, 16, eee_afe
[i
].reg
| 1u<<13);
683 /* End Workaround for OptimaEEE */
684 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
686 /* Enable 10Base-Te (EEE) */
687 if (hw
->chip_id
>= CHIP_ID_YUKON_PRM
) {
688 reg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
689 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
,
690 reg
| PHY_M_10B_TE_ENABLE
);
694 /* Enable phy interrupt on auto-negotiation complete (or link up) */
695 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
696 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
698 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
701 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
702 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
704 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
708 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
709 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
710 reg1
&= ~phy_power
[port
];
712 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> CHIP_REV_YU_XL_A1
)
713 reg1
|= coma_mode
[port
];
715 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
716 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
717 sky2_pci_read32(hw
, PCI_DEV_REG1
);
719 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
720 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
721 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
722 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
725 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
730 /* release GPHY Control reset */
731 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
733 /* release GMAC reset */
734 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
736 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
737 /* select page 2 to access MAC control register */
738 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
740 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
741 /* allow GMII Power Down */
742 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
743 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
745 /* set page register back to 0 */
746 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
749 /* setup General Purpose Control Register */
750 gma_write16(hw
, port
, GM_GP_CTRL
,
751 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
|
752 GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_FCT_DIS
|
755 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
756 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
757 /* select page 2 to access MAC control register */
758 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
760 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
761 /* enable Power Down */
762 ctrl
|= PHY_M_PC_POW_D_ENA
;
763 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
765 /* set page register back to 0 */
766 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
769 /* set IEEE compatible Power Down Mode (dev. #4.99) */
770 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
773 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
774 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
775 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
776 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
777 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
780 /* configure IPG according to used link speed */
781 static void sky2_set_ipg(struct sky2_port
*sky2
)
785 reg
= gma_read16(sky2
->hw
, sky2
->port
, GM_SERIAL_MODE
);
786 reg
&= ~GM_SMOD_IPG_MSK
;
787 if (sky2
->speed
> SPEED_100
)
788 reg
|= IPG_DATA_VAL(IPG_DATA_DEF_1000
);
790 reg
|= IPG_DATA_VAL(IPG_DATA_DEF_10_100
);
791 gma_write16(sky2
->hw
, sky2
->port
, GM_SERIAL_MODE
, reg
);
795 static void sky2_enable_rx_tx(struct sky2_port
*sky2
)
797 struct sky2_hw
*hw
= sky2
->hw
;
798 unsigned port
= sky2
->port
;
801 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
802 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
803 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
806 /* Force a renegotiation */
807 static void sky2_phy_reinit(struct sky2_port
*sky2
)
809 spin_lock_bh(&sky2
->phy_lock
);
810 sky2_phy_init(sky2
->hw
, sky2
->port
);
811 sky2_enable_rx_tx(sky2
);
812 spin_unlock_bh(&sky2
->phy_lock
);
815 /* Put device in state to listen for Wake On Lan */
816 static void sky2_wol_init(struct sky2_port
*sky2
)
818 struct sky2_hw
*hw
= sky2
->hw
;
819 unsigned port
= sky2
->port
;
820 enum flow_control save_mode
;
823 /* Bring hardware out of reset */
824 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
825 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
827 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
828 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
831 * sky2_reset will re-enable on resume
833 save_mode
= sky2
->flow_mode
;
834 ctrl
= sky2
->advertising
;
836 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
837 sky2
->flow_mode
= FC_NONE
;
839 spin_lock_bh(&sky2
->phy_lock
);
840 sky2_phy_power_up(hw
, port
);
841 sky2_phy_init(hw
, port
);
842 spin_unlock_bh(&sky2
->phy_lock
);
844 sky2
->flow_mode
= save_mode
;
845 sky2
->advertising
= ctrl
;
847 /* Set GMAC to no flow control and auto update for speed/duplex */
848 gma_write16(hw
, port
, GM_GP_CTRL
,
849 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
850 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
852 /* Set WOL address */
853 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
854 sky2
->netdev
->dev_addr
, ETH_ALEN
);
856 /* Turn on appropriate WOL control bits */
857 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
859 if (sky2
->wol
& WAKE_PHY
)
860 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
862 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
864 if (sky2
->wol
& WAKE_MAGIC
)
865 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
867 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;
869 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
870 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
872 /* Disable PiG firmware */
873 sky2_write16(hw
, B0_CTST
, Y2_HW_WOL_OFF
);
875 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
877 u32 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
878 reg1
|= PCI_Y2_PME_LEGACY
;
879 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
883 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
884 sky2_read32(hw
, B0_CTST
);
887 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
889 struct net_device
*dev
= hw
->dev
[port
];
891 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
892 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
893 hw
->chip_id
>= CHIP_ID_YUKON_FE_P
) {
894 /* Yukon-Extreme B0 and further Extreme devices */
895 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
896 } else if (dev
->mtu
> ETH_DATA_LEN
) {
897 /* set Tx GMAC FIFO Almost Empty Threshold */
898 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
899 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
901 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
903 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
906 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
908 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
912 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
914 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
915 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
917 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
919 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&&
920 hw
->chip_rev
== CHIP_REV_YU_XL_A0
&&
922 /* WA DEV_472 -- looks like crossed wires on port 2 */
923 /* clear GMAC 1 Control reset */
924 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
926 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
927 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
928 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
929 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
930 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
933 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
935 /* Enable Transmit FIFO Underrun */
936 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
938 spin_lock_bh(&sky2
->phy_lock
);
939 sky2_phy_power_up(hw
, port
);
940 sky2_phy_init(hw
, port
);
941 spin_unlock_bh(&sky2
->phy_lock
);
944 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
945 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
947 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
948 gma_read16(hw
, port
, i
);
949 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
951 /* transmit control */
952 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
954 /* receive control reg: unicast + multicast + no FCS */
955 gma_write16(hw
, port
, GM_RX_CTRL
,
956 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
958 /* transmit flow control */
959 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
961 /* transmit parameter */
962 gma_write16(hw
, port
, GM_TX_PARAM
,
963 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
964 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
965 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
966 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
968 /* serial mode register */
969 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
970 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF_1000
);
972 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
973 reg
|= GM_SMOD_JUMBO_ENA
;
975 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
976 hw
->chip_rev
== CHIP_REV_YU_EC_U_B1
)
977 reg
|= GM_NEW_FLOW_CTRL
;
979 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
981 /* virtual address for data */
982 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
984 /* physical address: used for pause frames */
985 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
987 /* ignore counter overflows */
988 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
989 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
990 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
992 /* Configure Rx MAC FIFO */
993 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
994 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
995 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
996 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
997 rx_reg
|= GMF_RX_OVER_ON
;
999 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
1001 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
1002 /* Hardware errata - clear flush mask */
1003 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
1005 /* Flush Rx MAC FIFO on any flow control or error */
1006 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
1009 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1010 reg
= RX_GMF_FL_THR_DEF
+ 1;
1011 /* Another magic mystery workaround from sk98lin */
1012 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
1013 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
1015 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
1017 /* Configure Tx MAC FIFO */
1018 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
1019 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
1021 /* On chips without ram buffer, pause is controlled by MAC level */
1022 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
1023 /* Pause threshold is scaled by 8 in bytes */
1024 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
1025 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
1029 sky2_write16(hw
, SK_REG(port
, RX_GMF_UP_THR
), reg
);
1030 sky2_write16(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768 / 8);
1032 sky2_set_tx_stfwd(hw
, port
);
1035 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
1036 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
1037 /* disable dynamic watermark */
1038 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
1039 reg
&= ~TX_DYN_WM_ENA
;
1040 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
1044 /* Assign Ram Buffer allocation to queue */
1045 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
1049 /* convert from K bytes to qwords used for hw register */
1052 end
= start
+ space
- 1;
1054 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
1055 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
1056 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
1057 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
1058 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
1060 if (q
== Q_R1
|| q
== Q_R2
) {
1061 u32 tp
= space
- space
/4;
1063 /* On receive queue's set the thresholds
1064 * give receiver priority when > 3/4 full
1065 * send pause when down to 2K
1067 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
1068 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
1070 tp
= space
- 2048/8;
1071 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
1072 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
1074 /* Enable store & forward on Tx queue's because
1075 * Tx FIFO is only 1K on Yukon
1077 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
1080 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
1081 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
1084 /* Setup Bus Memory Interface */
1085 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
1087 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
1088 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
1089 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
1090 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
1093 /* Setup prefetch unit registers. This is the interface between
1094 * hardware and driver list elements
1096 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
1097 dma_addr_t addr
, u32 last
)
1099 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1100 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
1101 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), upper_32_bits(addr
));
1102 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), lower_32_bits(addr
));
1103 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
1104 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
1106 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
1109 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
, u16
*slot
)
1111 struct sky2_tx_le
*le
= sky2
->tx_le
+ *slot
;
1113 *slot
= RING_NEXT(*slot
, sky2
->tx_ring_size
);
1118 static void tx_init(struct sky2_port
*sky2
)
1120 struct sky2_tx_le
*le
;
1122 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1123 sky2
->tx_tcpsum
= 0;
1124 sky2
->tx_last_mss
= 0;
1125 netdev_reset_queue(sky2
->netdev
);
1127 le
= get_tx_le(sky2
, &sky2
->tx_prod
);
1129 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1130 sky2
->tx_last_upper
= 0;
1133 /* Update chip's next pointer */
1134 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1136 /* Make sure write' to descriptors are complete before we tell hardware */
1138 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1140 /* Synchronize I/O on since next processor may write to tail */
1145 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1147 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1148 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1153 static unsigned sky2_get_rx_threshold(struct sky2_port
*sky2
)
1157 /* Space needed for frame data + headers rounded up */
1158 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1160 /* Stopping point for hardware truncation */
1161 return (size
- 8) / sizeof(u32
);
1164 static unsigned sky2_get_rx_data_size(struct sky2_port
*sky2
)
1166 struct rx_ring_info
*re
;
1169 /* Space needed for frame data + headers rounded up */
1170 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1172 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1173 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1175 /* Compute residue after pages */
1176 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1178 /* Optimize to handle small packets and headers */
1179 if (size
< copybreak
)
1181 if (size
< ETH_HLEN
)
1187 /* Build description to hardware for one receive segment */
1188 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1189 dma_addr_t map
, unsigned len
)
1191 struct sky2_rx_le
*le
;
1193 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1194 le
= sky2_next_rx(sky2
);
1195 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1196 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1199 le
= sky2_next_rx(sky2
);
1200 le
->addr
= cpu_to_le32(lower_32_bits(map
));
1201 le
->length
= cpu_to_le16(len
);
1202 le
->opcode
= op
| HW_OWNER
;
1205 /* Build description to hardware for one possibly fragmented skb */
1206 static void sky2_rx_submit(struct sky2_port
*sky2
,
1207 const struct rx_ring_info
*re
)
1211 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1213 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1214 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1218 static int sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1221 struct sk_buff
*skb
= re
->skb
;
1224 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1225 if (pci_dma_mapping_error(pdev
, re
->data_addr
))
1228 dma_unmap_len_set(re
, data_size
, size
);
1230 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1231 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1233 re
->frag_addr
[i
] = skb_frag_dma_map(&pdev
->dev
, frag
, 0,
1234 skb_frag_size(frag
),
1237 if (dma_mapping_error(&pdev
->dev
, re
->frag_addr
[i
]))
1238 goto map_page_error
;
1244 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1245 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
1246 PCI_DMA_FROMDEVICE
);
1249 pci_unmap_single(pdev
, re
->data_addr
, dma_unmap_len(re
, data_size
),
1250 PCI_DMA_FROMDEVICE
);
1253 if (net_ratelimit())
1254 dev_warn(&pdev
->dev
, "%s: rx mapping error\n",
1259 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1261 struct sk_buff
*skb
= re
->skb
;
1264 pci_unmap_single(pdev
, re
->data_addr
, dma_unmap_len(re
, data_size
),
1265 PCI_DMA_FROMDEVICE
);
1267 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1268 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1269 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
1270 PCI_DMA_FROMDEVICE
);
1273 /* Tell chip where to start receive checksum.
1274 * Actually has two checksums, but set both same to avoid possible byte
1277 static void rx_set_checksum(struct sky2_port
*sky2
)
1279 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1281 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1283 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1285 sky2_write32(sky2
->hw
,
1286 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1287 (sky2
->netdev
->features
& NETIF_F_RXCSUM
)
1288 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1292 * Fixed initial key as seed to RSS.
1294 static const uint32_t rss_init_key
[10] = {
1295 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43,
1296 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30
1299 /* Enable/disable receive hash calculation (RSS) */
1300 static void rx_set_rss(struct net_device
*dev
, netdev_features_t features
)
1302 struct sky2_port
*sky2
= netdev_priv(dev
);
1303 struct sky2_hw
*hw
= sky2
->hw
;
1306 /* Supports IPv6 and other modes */
1307 if (hw
->flags
& SKY2_HW_NEW_LE
) {
1309 sky2_write32(hw
, SK_REG(sky2
->port
, RSS_CFG
), HASH_ALL
);
1312 /* Program RSS initial values */
1313 if (features
& NETIF_F_RXHASH
) {
1314 for (i
= 0; i
< nkeys
; i
++)
1315 sky2_write32(hw
, SK_REG(sky2
->port
, RSS_KEY
+ i
* 4),
1318 /* Need to turn on (undocumented) flag to make hashing work */
1319 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
),
1322 sky2_write32(hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1323 BMU_ENA_RX_RSS_HASH
);
1325 sky2_write32(hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1326 BMU_DIS_RX_RSS_HASH
);
1330 * The RX Stop command will not work for Yukon-2 if the BMU does not
1331 * reach the end of packet and since we can't make sure that we have
1332 * incoming data, we must reset the BMU while it is not doing a DMA
1333 * transfer. Since it is possible that the RX path is still active,
1334 * the RX RAM buffer will be stopped first, so any possible incoming
1335 * data will not trigger a DMA. After the RAM buffer is stopped, the
1336 * BMU is polled until any DMA in progress is ended and only then it
1339 static void sky2_rx_stop(struct sky2_port
*sky2
)
1341 struct sky2_hw
*hw
= sky2
->hw
;
1342 unsigned rxq
= rxqaddr
[sky2
->port
];
1345 /* disable the RAM Buffer receive queue */
1346 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1348 for (i
= 0; i
< 0xffff; i
++)
1349 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1350 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1353 netdev_warn(sky2
->netdev
, "receiver stop failed\n");
1355 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1357 /* reset the Rx prefetch unit */
1358 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1362 /* Clean out receive buffer area, assumes receiver hardware stopped */
1363 static void sky2_rx_clean(struct sky2_port
*sky2
)
1367 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1368 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1369 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1372 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1379 /* Basic MII support */
1380 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1382 struct mii_ioctl_data
*data
= if_mii(ifr
);
1383 struct sky2_port
*sky2
= netdev_priv(dev
);
1384 struct sky2_hw
*hw
= sky2
->hw
;
1385 int err
= -EOPNOTSUPP
;
1387 if (!netif_running(dev
))
1388 return -ENODEV
; /* Phy still in reset */
1392 data
->phy_id
= PHY_ADDR_MARV
;
1398 spin_lock_bh(&sky2
->phy_lock
);
1399 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1400 spin_unlock_bh(&sky2
->phy_lock
);
1402 data
->val_out
= val
;
1407 spin_lock_bh(&sky2
->phy_lock
);
1408 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1410 spin_unlock_bh(&sky2
->phy_lock
);
1416 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1418 static void sky2_vlan_mode(struct net_device
*dev
, netdev_features_t features
)
1420 struct sky2_port
*sky2
= netdev_priv(dev
);
1421 struct sky2_hw
*hw
= sky2
->hw
;
1422 u16 port
= sky2
->port
;
1424 if (features
& NETIF_F_HW_VLAN_RX
)
1425 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1428 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1431 if (features
& NETIF_F_HW_VLAN_TX
) {
1432 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1435 dev
->vlan_features
|= SKY2_VLAN_OFFLOADS
;
1437 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1440 /* Can't do transmit offload of vlan without hw vlan */
1441 dev
->vlan_features
&= ~SKY2_VLAN_OFFLOADS
;
1445 /* Amount of required worst case padding in rx buffer */
1446 static inline unsigned sky2_rx_pad(const struct sky2_hw
*hw
)
1448 return (hw
->flags
& SKY2_HW_RAM_BUFFER
) ? 8 : 2;
1452 * Allocate an skb for receiving. If the MTU is large enough
1453 * make the skb non-linear with a fragment list of pages.
1455 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
, gfp_t gfp
)
1457 struct sk_buff
*skb
;
1460 skb
= __netdev_alloc_skb(sky2
->netdev
,
1461 sky2
->rx_data_size
+ sky2_rx_pad(sky2
->hw
),
1466 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1467 unsigned char *start
;
1469 * Workaround for a bug in FIFO that cause hang
1470 * if the FIFO if the receive buffer is not 64 byte aligned.
1471 * The buffer returned from netdev_alloc_skb is
1472 * aligned except if slab debugging is enabled.
1474 start
= PTR_ALIGN(skb
->data
, 8);
1475 skb_reserve(skb
, start
- skb
->data
);
1477 skb_reserve(skb
, NET_IP_ALIGN
);
1479 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1480 struct page
*page
= alloc_page(gfp
);
1484 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1494 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1496 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1499 static int sky2_alloc_rx_skbs(struct sky2_port
*sky2
)
1501 struct sky2_hw
*hw
= sky2
->hw
;
1504 sky2
->rx_data_size
= sky2_get_rx_data_size(sky2
);
1507 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1508 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1510 re
->skb
= sky2_rx_alloc(sky2
, GFP_KERNEL
);
1514 if (sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
)) {
1515 dev_kfree_skb(re
->skb
);
1524 * Setup receiver buffer pool.
1525 * Normal case this ends up creating one list element for skb
1526 * in the receive ring. Worst case if using large MTU and each
1527 * allocation falls on a different 64 bit region, that results
1528 * in 6 list elements per ring entry.
1529 * One element is used for checksum enable/disable, and one
1530 * extra to avoid wrap.
1532 static void sky2_rx_start(struct sky2_port
*sky2
)
1534 struct sky2_hw
*hw
= sky2
->hw
;
1535 struct rx_ring_info
*re
;
1536 unsigned rxq
= rxqaddr
[sky2
->port
];
1539 sky2
->rx_put
= sky2
->rx_next
= 0;
1542 /* On PCI express lowering the watermark gives better performance */
1543 if (pci_is_pcie(hw
->pdev
))
1544 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1546 /* These chips have no ram buffer?
1547 * MAC Rx RAM Read is controlled by hardware */
1548 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1549 hw
->chip_rev
> CHIP_REV_YU_EC_U_A0
)
1550 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1552 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1554 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1555 rx_set_checksum(sky2
);
1557 if (!(hw
->flags
& SKY2_HW_RSS_BROKEN
))
1558 rx_set_rss(sky2
->netdev
, sky2
->netdev
->features
);
1560 /* submit Rx ring */
1561 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1562 re
= sky2
->rx_ring
+ i
;
1563 sky2_rx_submit(sky2
, re
);
1567 * The receiver hangs if it receives frames larger than the
1568 * packet buffer. As a workaround, truncate oversize frames, but
1569 * the register is limited to 9 bits, so if you do frames > 2052
1570 * you better get the MTU right!
1572 thresh
= sky2_get_rx_threshold(sky2
);
1574 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1576 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1577 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1580 /* Tell chip about available buffers */
1581 sky2_rx_update(sky2
, rxq
);
1583 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
1584 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
1586 * Disable flushing of non ASF packets;
1587 * must be done after initializing the BMUs;
1588 * drivers without ASF support should do this too, otherwise
1589 * it may happen that they cannot run on ASF devices;
1590 * remember that the MAC FIFO isn't reset during initialization.
1592 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_MACSEC_FLUSH_OFF
);
1595 if (hw
->chip_id
>= CHIP_ID_YUKON_SUPR
) {
1596 /* Enable RX Home Address & Routing Header checksum fix */
1597 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_FL_CTRL
),
1598 RX_IPV6_SA_MOB_ENA
| RX_IPV6_DA_MOB_ENA
);
1600 /* Enable TX Home Address & Routing Header checksum fix */
1601 sky2_write32(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_TEST
),
1602 TBMU_TEST_HOME_ADD_FIX_EN
| TBMU_TEST_ROUTING_ADD_FIX_EN
);
1606 static int sky2_alloc_buffers(struct sky2_port
*sky2
)
1608 struct sky2_hw
*hw
= sky2
->hw
;
1610 /* must be power of 2 */
1611 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1612 sky2
->tx_ring_size
*
1613 sizeof(struct sky2_tx_le
),
1618 sky2
->tx_ring
= kcalloc(sky2
->tx_ring_size
, sizeof(struct tx_ring_info
),
1623 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1627 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1629 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1634 return sky2_alloc_rx_skbs(sky2
);
1639 static void sky2_free_buffers(struct sky2_port
*sky2
)
1641 struct sky2_hw
*hw
= sky2
->hw
;
1643 sky2_rx_clean(sky2
);
1646 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1647 sky2
->rx_le
, sky2
->rx_le_map
);
1651 pci_free_consistent(hw
->pdev
,
1652 sky2
->tx_ring_size
* sizeof(struct sky2_tx_le
),
1653 sky2
->tx_le
, sky2
->tx_le_map
);
1656 kfree(sky2
->tx_ring
);
1657 kfree(sky2
->rx_ring
);
1659 sky2
->tx_ring
= NULL
;
1660 sky2
->rx_ring
= NULL
;
1663 static void sky2_hw_up(struct sky2_port
*sky2
)
1665 struct sky2_hw
*hw
= sky2
->hw
;
1666 unsigned port
= sky2
->port
;
1669 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1674 * On dual port PCI-X card, there is an problem where status
1675 * can be received out of order due to split transactions
1677 if (otherdev
&& netif_running(otherdev
) &&
1678 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1681 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1682 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1683 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1686 sky2_mac_init(hw
, port
);
1688 /* Register is number of 4K blocks on internal RAM buffer. */
1689 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1693 netdev_dbg(sky2
->netdev
, "ram buffer %dK\n", ramsize
);
1695 rxspace
= ramsize
/ 2;
1697 rxspace
= 8 + (2*(ramsize
- 16))/3;
1699 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1700 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1702 /* Make sure SyncQ is disabled */
1703 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1707 sky2_qset(hw
, txqaddr
[port
]);
1709 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1710 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1711 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1713 /* Set almost empty threshold */
1714 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1715 hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1716 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1718 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1719 sky2
->tx_ring_size
- 1);
1721 sky2_vlan_mode(sky2
->netdev
, sky2
->netdev
->features
);
1722 netdev_update_features(sky2
->netdev
);
1724 sky2_rx_start(sky2
);
1727 /* Setup device IRQ and enable napi to process */
1728 static int sky2_setup_irq(struct sky2_hw
*hw
, const char *name
)
1730 struct pci_dev
*pdev
= hw
->pdev
;
1733 err
= request_irq(pdev
->irq
, sky2_intr
,
1734 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
1737 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
1739 hw
->flags
|= SKY2_HW_IRQ_SETUP
;
1741 napi_enable(&hw
->napi
);
1742 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
1743 sky2_read32(hw
, B0_IMSK
);
1750 /* Bring up network interface. */
1751 static int sky2_open(struct net_device
*dev
)
1753 struct sky2_port
*sky2
= netdev_priv(dev
);
1754 struct sky2_hw
*hw
= sky2
->hw
;
1755 unsigned port
= sky2
->port
;
1759 netif_carrier_off(dev
);
1761 err
= sky2_alloc_buffers(sky2
);
1765 /* With single port, IRQ is setup when device is brought up */
1766 if (hw
->ports
== 1 && (err
= sky2_setup_irq(hw
, dev
->name
)))
1771 /* Enable interrupts from phy/mac for port */
1772 imask
= sky2_read32(hw
, B0_IMSK
);
1774 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
||
1775 hw
->chip_id
== CHIP_ID_YUKON_PRM
||
1776 hw
->chip_id
== CHIP_ID_YUKON_OP_2
)
1777 imask
|= Y2_IS_PHY_QLNK
; /* enable PHY Quick Link */
1779 imask
|= portirq_msk
[port
];
1780 sky2_write32(hw
, B0_IMSK
, imask
);
1781 sky2_read32(hw
, B0_IMSK
);
1783 netif_info(sky2
, ifup
, dev
, "enabling interface\n");
1788 sky2_free_buffers(sky2
);
1792 /* Modular subtraction in ring */
1793 static inline int tx_inuse(const struct sky2_port
*sky2
)
1795 return (sky2
->tx_prod
- sky2
->tx_cons
) & (sky2
->tx_ring_size
- 1);
1798 /* Number of list elements available for next tx */
1799 static inline int tx_avail(const struct sky2_port
*sky2
)
1801 return sky2
->tx_pending
- tx_inuse(sky2
);
1804 /* Estimate of number of transmit list elements required */
1805 static unsigned tx_le_req(const struct sk_buff
*skb
)
1809 count
= (skb_shinfo(skb
)->nr_frags
+ 1)
1810 * (sizeof(dma_addr_t
) / sizeof(u32
));
1812 if (skb_is_gso(skb
))
1814 else if (sizeof(dma_addr_t
) == sizeof(u32
))
1815 ++count
; /* possible vlan */
1817 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1823 static void sky2_tx_unmap(struct pci_dev
*pdev
, struct tx_ring_info
*re
)
1825 if (re
->flags
& TX_MAP_SINGLE
)
1826 pci_unmap_single(pdev
, dma_unmap_addr(re
, mapaddr
),
1827 dma_unmap_len(re
, maplen
),
1829 else if (re
->flags
& TX_MAP_PAGE
)
1830 pci_unmap_page(pdev
, dma_unmap_addr(re
, mapaddr
),
1831 dma_unmap_len(re
, maplen
),
1837 * Put one packet in ring for transmit.
1838 * A single packet can generate multiple list elements, and
1839 * the number of ring elements will probably be less than the number
1840 * of list elements used.
1842 static netdev_tx_t
sky2_xmit_frame(struct sk_buff
*skb
,
1843 struct net_device
*dev
)
1845 struct sky2_port
*sky2
= netdev_priv(dev
);
1846 struct sky2_hw
*hw
= sky2
->hw
;
1847 struct sky2_tx_le
*le
= NULL
;
1848 struct tx_ring_info
*re
;
1856 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1857 return NETDEV_TX_BUSY
;
1859 len
= skb_headlen(skb
);
1860 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1862 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1865 slot
= sky2
->tx_prod
;
1866 netif_printk(sky2
, tx_queued
, KERN_DEBUG
, dev
,
1867 "tx queued, slot %u, len %d\n", slot
, skb
->len
);
1869 /* Send high bits if needed */
1870 upper
= upper_32_bits(mapping
);
1871 if (upper
!= sky2
->tx_last_upper
) {
1872 le
= get_tx_le(sky2
, &slot
);
1873 le
->addr
= cpu_to_le32(upper
);
1874 sky2
->tx_last_upper
= upper
;
1875 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1878 /* Check for TCP Segmentation Offload */
1879 mss
= skb_shinfo(skb
)->gso_size
;
1882 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1883 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1885 if (mss
!= sky2
->tx_last_mss
) {
1886 le
= get_tx_le(sky2
, &slot
);
1887 le
->addr
= cpu_to_le32(mss
);
1889 if (hw
->flags
& SKY2_HW_NEW_LE
)
1890 le
->opcode
= OP_MSS
| HW_OWNER
;
1892 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1893 sky2
->tx_last_mss
= mss
;
1899 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1900 if (vlan_tx_tag_present(skb
)) {
1902 le
= get_tx_le(sky2
, &slot
);
1904 le
->opcode
= OP_VLAN
|HW_OWNER
;
1906 le
->opcode
|= OP_VLAN
;
1907 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1911 /* Handle TCP checksum offload */
1912 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1913 /* On Yukon EX (some versions) encoding change. */
1914 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1915 ctrl
|= CALSUM
; /* auto checksum */
1917 const unsigned offset
= skb_transport_offset(skb
);
1920 tcpsum
= offset
<< 16; /* sum start */
1921 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1923 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1924 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1927 if (tcpsum
!= sky2
->tx_tcpsum
) {
1928 sky2
->tx_tcpsum
= tcpsum
;
1930 le
= get_tx_le(sky2
, &slot
);
1931 le
->addr
= cpu_to_le32(tcpsum
);
1932 le
->length
= 0; /* initial checksum value */
1933 le
->ctrl
= 1; /* one packet */
1934 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1939 re
= sky2
->tx_ring
+ slot
;
1940 re
->flags
= TX_MAP_SINGLE
;
1941 dma_unmap_addr_set(re
, mapaddr
, mapping
);
1942 dma_unmap_len_set(re
, maplen
, len
);
1944 le
= get_tx_le(sky2
, &slot
);
1945 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1946 le
->length
= cpu_to_le16(len
);
1948 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1951 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1952 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1954 mapping
= skb_frag_dma_map(&hw
->pdev
->dev
, frag
, 0,
1955 skb_frag_size(frag
), DMA_TO_DEVICE
);
1957 if (dma_mapping_error(&hw
->pdev
->dev
, mapping
))
1958 goto mapping_unwind
;
1960 upper
= upper_32_bits(mapping
);
1961 if (upper
!= sky2
->tx_last_upper
) {
1962 le
= get_tx_le(sky2
, &slot
);
1963 le
->addr
= cpu_to_le32(upper
);
1964 sky2
->tx_last_upper
= upper
;
1965 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1968 re
= sky2
->tx_ring
+ slot
;
1969 re
->flags
= TX_MAP_PAGE
;
1970 dma_unmap_addr_set(re
, mapaddr
, mapping
);
1971 dma_unmap_len_set(re
, maplen
, skb_frag_size(frag
));
1973 le
= get_tx_le(sky2
, &slot
);
1974 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1975 le
->length
= cpu_to_le16(skb_frag_size(frag
));
1977 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1983 sky2
->tx_prod
= slot
;
1985 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1986 netif_stop_queue(dev
);
1988 netdev_sent_queue(dev
, skb
->len
);
1989 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1991 return NETDEV_TX_OK
;
1994 for (i
= sky2
->tx_prod
; i
!= slot
; i
= RING_NEXT(i
, sky2
->tx_ring_size
)) {
1995 re
= sky2
->tx_ring
+ i
;
1997 sky2_tx_unmap(hw
->pdev
, re
);
2001 if (net_ratelimit())
2002 dev_warn(&hw
->pdev
->dev
, "%s: tx mapping error\n", dev
->name
);
2004 return NETDEV_TX_OK
;
2008 * Free ring elements from starting at tx_cons until "done"
2011 * 1. The hardware will tell us about partial completion of multi-part
2012 * buffers so make sure not to free skb to early.
2013 * 2. This may run in parallel start_xmit because the it only
2014 * looks at the tail of the queue of FIFO (tx_cons), not
2015 * the head (tx_prod)
2017 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
2019 struct net_device
*dev
= sky2
->netdev
;
2021 unsigned int bytes_compl
= 0, pkts_compl
= 0;
2023 BUG_ON(done
>= sky2
->tx_ring_size
);
2025 for (idx
= sky2
->tx_cons
; idx
!= done
;
2026 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
2027 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
2028 struct sk_buff
*skb
= re
->skb
;
2030 sky2_tx_unmap(sky2
->hw
->pdev
, re
);
2033 netif_printk(sky2
, tx_done
, KERN_DEBUG
, dev
,
2034 "tx done %u\n", idx
);
2037 bytes_compl
+= skb
->len
;
2040 dev_kfree_skb_any(skb
);
2042 sky2
->tx_next
= RING_NEXT(idx
, sky2
->tx_ring_size
);
2046 sky2
->tx_cons
= idx
;
2049 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
2051 u64_stats_update_begin(&sky2
->tx_stats
.syncp
);
2052 sky2
->tx_stats
.packets
+= pkts_compl
;
2053 sky2
->tx_stats
.bytes
+= bytes_compl
;
2054 u64_stats_update_end(&sky2
->tx_stats
.syncp
);
2057 static void sky2_tx_reset(struct sky2_hw
*hw
, unsigned port
)
2059 /* Disable Force Sync bit and Enable Alloc bit */
2060 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
2061 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2063 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2064 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2065 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2067 /* Reset the PCI FIFO of the async Tx queue */
2068 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
2069 BMU_RST_SET
| BMU_FIFO_RST
);
2071 /* Reset the Tx prefetch units */
2072 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
2075 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2076 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2078 sky2_read32(hw
, B0_CTST
);
2081 static void sky2_hw_down(struct sky2_port
*sky2
)
2083 struct sky2_hw
*hw
= sky2
->hw
;
2084 unsigned port
= sky2
->port
;
2087 /* Force flow control off */
2088 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2090 /* Stop transmitter */
2091 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
2092 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
2094 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2095 RB_RST_SET
| RB_DIS_OP_MD
);
2097 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2098 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
2099 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
2101 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2103 /* Workaround shared GMAC reset */
2104 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 &&
2105 port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
2106 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2108 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2110 /* Force any delayed status interrupt and NAPI */
2111 sky2_write32(hw
, STAT_LEV_TIMER_CNT
, 0);
2112 sky2_write32(hw
, STAT_TX_TIMER_CNT
, 0);
2113 sky2_write32(hw
, STAT_ISR_TIMER_CNT
, 0);
2114 sky2_read8(hw
, STAT_ISR_TIMER_CTRL
);
2118 spin_lock_bh(&sky2
->phy_lock
);
2119 sky2_phy_power_down(hw
, port
);
2120 spin_unlock_bh(&sky2
->phy_lock
);
2122 sky2_tx_reset(hw
, port
);
2124 /* Free any pending frames stuck in HW queue */
2125 sky2_tx_complete(sky2
, sky2
->tx_prod
);
2128 /* Network shutdown */
2129 static int sky2_close(struct net_device
*dev
)
2131 struct sky2_port
*sky2
= netdev_priv(dev
);
2132 struct sky2_hw
*hw
= sky2
->hw
;
2134 /* Never really got started! */
2138 netif_info(sky2
, ifdown
, dev
, "disabling interface\n");
2140 if (hw
->ports
== 1) {
2141 sky2_write32(hw
, B0_IMSK
, 0);
2142 sky2_read32(hw
, B0_IMSK
);
2144 napi_disable(&hw
->napi
);
2145 free_irq(hw
->pdev
->irq
, hw
);
2146 hw
->flags
&= ~SKY2_HW_IRQ_SETUP
;
2150 /* Disable port IRQ */
2151 imask
= sky2_read32(hw
, B0_IMSK
);
2152 imask
&= ~portirq_msk
[sky2
->port
];
2153 sky2_write32(hw
, B0_IMSK
, imask
);
2154 sky2_read32(hw
, B0_IMSK
);
2156 synchronize_irq(hw
->pdev
->irq
);
2157 napi_synchronize(&hw
->napi
);
2162 sky2_free_buffers(sky2
);
2167 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
2169 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
2172 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
2173 if (aux
& PHY_M_PS_SPEED_100
)
2179 switch (aux
& PHY_M_PS_SPEED_MSK
) {
2180 case PHY_M_PS_SPEED_1000
:
2182 case PHY_M_PS_SPEED_100
:
2189 static void sky2_link_up(struct sky2_port
*sky2
)
2191 struct sky2_hw
*hw
= sky2
->hw
;
2192 unsigned port
= sky2
->port
;
2193 static const char *fc_name
[] = {
2202 sky2_enable_rx_tx(sky2
);
2204 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
2206 netif_carrier_on(sky2
->netdev
);
2208 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
2210 /* Turn on link LED */
2211 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
2212 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
2214 netif_info(sky2
, link
, sky2
->netdev
,
2215 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2217 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
2218 fc_name
[sky2
->flow_status
]);
2221 static void sky2_link_down(struct sky2_port
*sky2
)
2223 struct sky2_hw
*hw
= sky2
->hw
;
2224 unsigned port
= sky2
->port
;
2227 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
2229 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2230 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2231 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2233 netif_carrier_off(sky2
->netdev
);
2235 /* Turn off link LED */
2236 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
2238 netif_info(sky2
, link
, sky2
->netdev
, "Link is down\n");
2240 sky2_phy_init(hw
, port
);
2243 static enum flow_control
sky2_flow(int rx
, int tx
)
2246 return tx
? FC_BOTH
: FC_RX
;
2248 return tx
? FC_TX
: FC_NONE
;
2251 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
2253 struct sky2_hw
*hw
= sky2
->hw
;
2254 unsigned port
= sky2
->port
;
2257 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2258 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
2259 if (lpa
& PHY_M_AN_RF
) {
2260 netdev_err(sky2
->netdev
, "remote fault\n");
2264 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
2265 netdev_err(sky2
->netdev
, "speed/duplex mismatch\n");
2269 sky2
->speed
= sky2_phy_speed(hw
, aux
);
2270 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2272 /* Since the pause result bits seem to in different positions on
2273 * different chips. look at registers.
2275 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
2276 /* Shift for bits in fiber PHY */
2277 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
2278 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
2280 if (advert
& ADVERTISE_1000XPAUSE
)
2281 advert
|= ADVERTISE_PAUSE_CAP
;
2282 if (advert
& ADVERTISE_1000XPSE_ASYM
)
2283 advert
|= ADVERTISE_PAUSE_ASYM
;
2284 if (lpa
& LPA_1000XPAUSE
)
2285 lpa
|= LPA_PAUSE_CAP
;
2286 if (lpa
& LPA_1000XPAUSE_ASYM
)
2287 lpa
|= LPA_PAUSE_ASYM
;
2290 sky2
->flow_status
= FC_NONE
;
2291 if (advert
& ADVERTISE_PAUSE_CAP
) {
2292 if (lpa
& LPA_PAUSE_CAP
)
2293 sky2
->flow_status
= FC_BOTH
;
2294 else if (advert
& ADVERTISE_PAUSE_ASYM
)
2295 sky2
->flow_status
= FC_RX
;
2296 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
2297 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
2298 sky2
->flow_status
= FC_TX
;
2301 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
&&
2302 !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
2303 sky2
->flow_status
= FC_NONE
;
2305 if (sky2
->flow_status
& FC_TX
)
2306 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2308 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2313 /* Interrupt from PHY */
2314 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2316 struct net_device
*dev
= hw
->dev
[port
];
2317 struct sky2_port
*sky2
= netdev_priv(dev
);
2318 u16 istatus
, phystat
;
2320 if (!netif_running(dev
))
2323 spin_lock(&sky2
->phy_lock
);
2324 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2325 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2327 netif_info(sky2
, intr
, sky2
->netdev
, "phy interrupt status 0x%x 0x%x\n",
2330 if (istatus
& PHY_M_IS_AN_COMPL
) {
2331 if (sky2_autoneg_done(sky2
, phystat
) == 0 &&
2332 !netif_carrier_ok(dev
))
2337 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2338 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2340 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2342 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2344 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2345 if (phystat
& PHY_M_PS_LINK_UP
)
2348 sky2_link_down(sky2
);
2351 spin_unlock(&sky2
->phy_lock
);
2354 /* Special quick link interrupt (Yukon-2 Optima only) */
2355 static void sky2_qlink_intr(struct sky2_hw
*hw
)
2357 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[0]);
2362 imask
= sky2_read32(hw
, B0_IMSK
);
2363 imask
&= ~Y2_IS_PHY_QLNK
;
2364 sky2_write32(hw
, B0_IMSK
, imask
);
2366 /* reset PHY Link Detect */
2367 phy
= sky2_pci_read16(hw
, PSM_CONFIG_REG4
);
2368 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2369 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, phy
| 1);
2370 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2375 /* Transmit timeout is only called if we are running, carrier is up
2376 * and tx queue is full (stopped).
2378 static void sky2_tx_timeout(struct net_device
*dev
)
2380 struct sky2_port
*sky2
= netdev_priv(dev
);
2381 struct sky2_hw
*hw
= sky2
->hw
;
2383 netif_err(sky2
, timer
, dev
, "tx timeout\n");
2385 netdev_printk(KERN_DEBUG
, dev
, "transmit ring %u .. %u report=%u done=%u\n",
2386 sky2
->tx_cons
, sky2
->tx_prod
,
2387 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2388 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2390 /* can't restart safely under softirq */
2391 schedule_work(&hw
->restart_work
);
2394 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2396 struct sky2_port
*sky2
= netdev_priv(dev
);
2397 struct sky2_hw
*hw
= sky2
->hw
;
2398 unsigned port
= sky2
->port
;
2403 /* MTU size outside the spec */
2404 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2407 /* MTU > 1500 on yukon FE and FE+ not allowed */
2408 if (new_mtu
> ETH_DATA_LEN
&&
2409 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2410 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2413 if (!netif_running(dev
)) {
2415 netdev_update_features(dev
);
2419 imask
= sky2_read32(hw
, B0_IMSK
);
2420 sky2_write32(hw
, B0_IMSK
, 0);
2422 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2423 napi_disable(&hw
->napi
);
2424 netif_tx_disable(dev
);
2426 synchronize_irq(hw
->pdev
->irq
);
2428 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2429 sky2_set_tx_stfwd(hw
, port
);
2431 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2432 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2434 sky2_rx_clean(sky2
);
2437 netdev_update_features(dev
);
2439 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) | GM_SMOD_VLAN_ENA
;
2440 if (sky2
->speed
> SPEED_100
)
2441 mode
|= IPG_DATA_VAL(IPG_DATA_DEF_1000
);
2443 mode
|= IPG_DATA_VAL(IPG_DATA_DEF_10_100
);
2445 if (dev
->mtu
> ETH_DATA_LEN
)
2446 mode
|= GM_SMOD_JUMBO_ENA
;
2448 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2450 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2452 err
= sky2_alloc_rx_skbs(sky2
);
2454 sky2_rx_start(sky2
);
2456 sky2_rx_clean(sky2
);
2457 sky2_write32(hw
, B0_IMSK
, imask
);
2459 sky2_read32(hw
, B0_Y2_SP_LISR
);
2460 napi_enable(&hw
->napi
);
2465 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2467 netif_wake_queue(dev
);
2473 static inline bool needs_copy(const struct rx_ring_info
*re
,
2476 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2477 /* Some architectures need the IP header to be aligned */
2478 if (!IS_ALIGNED(re
->data_addr
+ ETH_HLEN
, sizeof(u32
)))
2481 return length
< copybreak
;
2484 /* For small just reuse existing skb for next receive */
2485 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2486 const struct rx_ring_info
*re
,
2489 struct sk_buff
*skb
;
2491 skb
= netdev_alloc_skb_ip_align(sky2
->netdev
, length
);
2493 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2494 length
, PCI_DMA_FROMDEVICE
);
2495 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2496 skb
->ip_summed
= re
->skb
->ip_summed
;
2497 skb
->csum
= re
->skb
->csum
;
2498 skb
->rxhash
= re
->skb
->rxhash
;
2499 skb
->vlan_tci
= re
->skb
->vlan_tci
;
2501 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2502 length
, PCI_DMA_FROMDEVICE
);
2503 re
->skb
->vlan_tci
= 0;
2504 re
->skb
->rxhash
= 0;
2505 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2506 skb_put(skb
, length
);
2511 /* Adjust length of skb with fragments to match received data */
2512 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2513 unsigned int length
)
2518 /* put header into skb */
2519 size
= min(length
, hdr_space
);
2524 num_frags
= skb_shinfo(skb
)->nr_frags
;
2525 for (i
= 0; i
< num_frags
; i
++) {
2526 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2529 /* don't need this page */
2530 __skb_frag_unref(frag
);
2531 --skb_shinfo(skb
)->nr_frags
;
2533 size
= min(length
, (unsigned) PAGE_SIZE
);
2535 skb_frag_size_set(frag
, size
);
2536 skb
->data_len
+= size
;
2537 skb
->truesize
+= PAGE_SIZE
;
2544 /* Normal packet - take skb from ring element and put in a new one */
2545 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2546 struct rx_ring_info
*re
,
2547 unsigned int length
)
2549 struct sk_buff
*skb
;
2550 struct rx_ring_info nre
;
2551 unsigned hdr_space
= sky2
->rx_data_size
;
2553 nre
.skb
= sky2_rx_alloc(sky2
, GFP_ATOMIC
);
2554 if (unlikely(!nre
.skb
))
2557 if (sky2_rx_map_skb(sky2
->hw
->pdev
, &nre
, hdr_space
))
2561 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2562 prefetch(skb
->data
);
2565 if (skb_shinfo(skb
)->nr_frags
)
2566 skb_put_frags(skb
, hdr_space
, length
);
2568 skb_put(skb
, length
);
2572 dev_kfree_skb(nre
.skb
);
2578 * Receive one packet.
2579 * For larger packets, get new buffer.
2581 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2582 u16 length
, u32 status
)
2584 struct sky2_port
*sky2
= netdev_priv(dev
);
2585 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2586 struct sk_buff
*skb
= NULL
;
2587 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2589 netif_printk(sky2
, rx_status
, KERN_DEBUG
, dev
,
2590 "rx slot %u status 0x%x len %d\n",
2591 sky2
->rx_next
, status
, length
);
2593 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2594 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2596 if (vlan_tx_tag_present(re
->skb
))
2597 count
-= VLAN_HLEN
; /* Account for vlan tag */
2599 /* This chip has hardware problems that generates bogus status.
2600 * So do only marginal checking and expect higher level protocols
2601 * to handle crap frames.
2603 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2604 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2608 if (status
& GMR_FS_ANY_ERR
)
2611 if (!(status
& GMR_FS_RX_OK
))
2614 /* if length reported by DMA does not match PHY, packet was truncated */
2615 if (length
!= count
)
2619 if (needs_copy(re
, length
))
2620 skb
= receive_copy(sky2
, re
, length
);
2622 skb
= receive_new(sky2
, re
, length
);
2624 dev
->stats
.rx_dropped
+= (skb
== NULL
);
2627 sky2_rx_submit(sky2
, re
);
2632 ++dev
->stats
.rx_errors
;
2634 if (net_ratelimit())
2635 netif_info(sky2
, rx_err
, dev
,
2636 "rx error, status 0x%x length %d\n", status
, length
);
2641 /* Transmit complete */
2642 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2644 struct sky2_port
*sky2
= netdev_priv(dev
);
2646 if (netif_running(dev
)) {
2647 sky2_tx_complete(sky2
, last
);
2649 /* Wake unless it's detached, and called e.g. from sky2_close() */
2650 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
2651 netif_wake_queue(dev
);
2655 static inline void sky2_skb_rx(const struct sky2_port
*sky2
,
2656 struct sk_buff
*skb
)
2658 if (skb
->ip_summed
== CHECKSUM_NONE
)
2659 netif_receive_skb(skb
);
2661 napi_gro_receive(&sky2
->hw
->napi
, skb
);
2664 static inline void sky2_rx_done(struct sky2_hw
*hw
, unsigned port
,
2665 unsigned packets
, unsigned bytes
)
2667 struct net_device
*dev
= hw
->dev
[port
];
2668 struct sky2_port
*sky2
= netdev_priv(dev
);
2673 u64_stats_update_begin(&sky2
->rx_stats
.syncp
);
2674 sky2
->rx_stats
.packets
+= packets
;
2675 sky2
->rx_stats
.bytes
+= bytes
;
2676 u64_stats_update_end(&sky2
->rx_stats
.syncp
);
2678 dev
->last_rx
= jiffies
;
2679 sky2_rx_update(netdev_priv(dev
), rxqaddr
[port
]);
2682 static void sky2_rx_checksum(struct sky2_port
*sky2
, u32 status
)
2684 /* If this happens then driver assuming wrong format for chip type */
2685 BUG_ON(sky2
->hw
->flags
& SKY2_HW_NEW_LE
);
2687 /* Both checksum counters are programmed to start at
2688 * the same offset, so unless there is a problem they
2689 * should match. This failure is an early indication that
2690 * hardware receive checksumming won't work.
2692 if (likely((u16
)(status
>> 16) == (u16
)status
)) {
2693 struct sk_buff
*skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2694 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2695 skb
->csum
= le16_to_cpu(status
);
2697 dev_notice(&sky2
->hw
->pdev
->dev
,
2698 "%s: receive checksum problem (status = %#x)\n",
2699 sky2
->netdev
->name
, status
);
2701 /* Disable checksum offload
2702 * It will be reenabled on next ndo_set_features, but if it's
2703 * really broken, will get disabled again
2705 sky2
->netdev
->features
&= ~NETIF_F_RXCSUM
;
2706 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2711 static void sky2_rx_tag(struct sky2_port
*sky2
, u16 length
)
2713 struct sk_buff
*skb
;
2715 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2716 __vlan_hwaccel_put_tag(skb
, be16_to_cpu(length
));
2719 static void sky2_rx_hash(struct sky2_port
*sky2
, u32 status
)
2721 struct sk_buff
*skb
;
2723 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2724 skb
->rxhash
= le32_to_cpu(status
);
2727 /* Process status response ring */
2728 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2731 unsigned int total_bytes
[2] = { 0 };
2732 unsigned int total_packets
[2] = { 0 };
2736 struct sky2_port
*sky2
;
2737 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2739 struct net_device
*dev
;
2740 struct sk_buff
*skb
;
2743 u8 opcode
= le
->opcode
;
2745 if (!(opcode
& HW_OWNER
))
2748 hw
->st_idx
= RING_NEXT(hw
->st_idx
, hw
->st_size
);
2750 port
= le
->css
& CSS_LINK_BIT
;
2751 dev
= hw
->dev
[port
];
2752 sky2
= netdev_priv(dev
);
2753 length
= le16_to_cpu(le
->length
);
2754 status
= le32_to_cpu(le
->status
);
2757 switch (opcode
& ~HW_OWNER
) {
2759 total_packets
[port
]++;
2760 total_bytes
[port
] += length
;
2762 skb
= sky2_receive(dev
, length
, status
);
2766 /* This chip reports checksum status differently */
2767 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2768 if ((dev
->features
& NETIF_F_RXCSUM
) &&
2769 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2770 (le
->css
& CSS_TCPUDPCSOK
))
2771 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2773 skb
->ip_summed
= CHECKSUM_NONE
;
2776 skb
->protocol
= eth_type_trans(skb
, dev
);
2777 sky2_skb_rx(sky2
, skb
);
2779 /* Stop after net poll weight */
2780 if (++work_done
>= to_do
)
2785 sky2_rx_tag(sky2
, length
);
2789 sky2_rx_tag(sky2
, length
);
2792 if (likely(dev
->features
& NETIF_F_RXCSUM
))
2793 sky2_rx_checksum(sky2
, status
);
2797 sky2_rx_hash(sky2
, status
);
2801 /* TX index reports status for both ports */
2802 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2804 sky2_tx_done(hw
->dev
[1],
2805 ((status
>> 24) & 0xff)
2806 | (u16
)(length
& 0xf) << 8);
2810 if (net_ratelimit())
2811 pr_warning("unknown status opcode 0x%x\n", opcode
);
2813 } while (hw
->st_idx
!= idx
);
2815 /* Fully processed status ring so clear irq */
2816 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2819 sky2_rx_done(hw
, 0, total_packets
[0], total_bytes
[0]);
2820 sky2_rx_done(hw
, 1, total_packets
[1], total_bytes
[1]);
2825 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2827 struct net_device
*dev
= hw
->dev
[port
];
2829 if (net_ratelimit())
2830 netdev_info(dev
, "hw error interrupt status 0x%x\n", status
);
2832 if (status
& Y2_IS_PAR_RD1
) {
2833 if (net_ratelimit())
2834 netdev_err(dev
, "ram data read parity error\n");
2836 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2839 if (status
& Y2_IS_PAR_WR1
) {
2840 if (net_ratelimit())
2841 netdev_err(dev
, "ram data write parity error\n");
2843 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2846 if (status
& Y2_IS_PAR_MAC1
) {
2847 if (net_ratelimit())
2848 netdev_err(dev
, "MAC parity error\n");
2849 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2852 if (status
& Y2_IS_PAR_RX1
) {
2853 if (net_ratelimit())
2854 netdev_err(dev
, "RX parity error\n");
2855 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2858 if (status
& Y2_IS_TCP_TXA1
) {
2859 if (net_ratelimit())
2860 netdev_err(dev
, "TCP segmentation error\n");
2861 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2865 static void sky2_hw_intr(struct sky2_hw
*hw
)
2867 struct pci_dev
*pdev
= hw
->pdev
;
2868 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2869 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2873 if (status
& Y2_IS_TIST_OV
)
2874 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2876 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2879 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2880 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2881 if (net_ratelimit())
2882 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2885 sky2_pci_write16(hw
, PCI_STATUS
,
2886 pci_err
| PCI_STATUS_ERROR_BITS
);
2887 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2890 if (status
& Y2_IS_PCI_EXP
) {
2891 /* PCI-Express uncorrectable Error occurred */
2894 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2895 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2896 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2898 if (net_ratelimit())
2899 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2901 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2902 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2905 if (status
& Y2_HWE_L1_MASK
)
2906 sky2_hw_error(hw
, 0, status
);
2908 if (status
& Y2_HWE_L1_MASK
)
2909 sky2_hw_error(hw
, 1, status
);
2912 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2914 struct net_device
*dev
= hw
->dev
[port
];
2915 struct sky2_port
*sky2
= netdev_priv(dev
);
2916 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2918 netif_info(sky2
, intr
, dev
, "mac interrupt status 0x%x\n", status
);
2920 if (status
& GM_IS_RX_CO_OV
)
2921 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2923 if (status
& GM_IS_TX_CO_OV
)
2924 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2926 if (status
& GM_IS_RX_FF_OR
) {
2927 ++dev
->stats
.rx_fifo_errors
;
2928 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2931 if (status
& GM_IS_TX_FF_UR
) {
2932 ++dev
->stats
.tx_fifo_errors
;
2933 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2937 /* This should never happen it is a bug. */
2938 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
, u16 q
)
2940 struct net_device
*dev
= hw
->dev
[port
];
2941 u16 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2943 dev_err(&hw
->pdev
->dev
, "%s: descriptor error q=%#x get=%u put=%u\n",
2944 dev
->name
, (unsigned) q
, (unsigned) idx
,
2945 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2947 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2950 static int sky2_rx_hung(struct net_device
*dev
)
2952 struct sky2_port
*sky2
= netdev_priv(dev
);
2953 struct sky2_hw
*hw
= sky2
->hw
;
2954 unsigned port
= sky2
->port
;
2955 unsigned rxq
= rxqaddr
[port
];
2956 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2957 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2958 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2959 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2961 /* If idle and MAC or PCI is stuck */
2962 if (sky2
->check
.last
== dev
->last_rx
&&
2963 ((mac_rp
== sky2
->check
.mac_rp
&&
2964 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2965 /* Check if the PCI RX hang */
2966 (fifo_rp
== sky2
->check
.fifo_rp
&&
2967 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2968 netdev_printk(KERN_DEBUG
, dev
,
2969 "hung mac %d:%d fifo %d (%d:%d)\n",
2970 mac_lev
, mac_rp
, fifo_lev
,
2971 fifo_rp
, sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2974 sky2
->check
.last
= dev
->last_rx
;
2975 sky2
->check
.mac_rp
= mac_rp
;
2976 sky2
->check
.mac_lev
= mac_lev
;
2977 sky2
->check
.fifo_rp
= fifo_rp
;
2978 sky2
->check
.fifo_lev
= fifo_lev
;
2983 static void sky2_watchdog(unsigned long arg
)
2985 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2987 /* Check for lost IRQ once a second */
2988 if (sky2_read32(hw
, B0_ISRC
)) {
2989 napi_schedule(&hw
->napi
);
2993 for (i
= 0; i
< hw
->ports
; i
++) {
2994 struct net_device
*dev
= hw
->dev
[i
];
2995 if (!netif_running(dev
))
2999 /* For chips with Rx FIFO, check if stuck */
3000 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
3001 sky2_rx_hung(dev
)) {
3002 netdev_info(dev
, "receiver hang detected\n");
3003 schedule_work(&hw
->restart_work
);
3012 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
3015 /* Hardware/software error handling */
3016 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
3018 if (net_ratelimit())
3019 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
3021 if (status
& Y2_IS_HW_ERR
)
3024 if (status
& Y2_IS_IRQ_MAC1
)
3025 sky2_mac_intr(hw
, 0);
3027 if (status
& Y2_IS_IRQ_MAC2
)
3028 sky2_mac_intr(hw
, 1);
3030 if (status
& Y2_IS_CHK_RX1
)
3031 sky2_le_error(hw
, 0, Q_R1
);
3033 if (status
& Y2_IS_CHK_RX2
)
3034 sky2_le_error(hw
, 1, Q_R2
);
3036 if (status
& Y2_IS_CHK_TXA1
)
3037 sky2_le_error(hw
, 0, Q_XA1
);
3039 if (status
& Y2_IS_CHK_TXA2
)
3040 sky2_le_error(hw
, 1, Q_XA2
);
3043 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
3045 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
3046 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
3050 if (unlikely(status
& Y2_IS_ERROR
))
3051 sky2_err_intr(hw
, status
);
3053 if (status
& Y2_IS_IRQ_PHY1
)
3054 sky2_phy_intr(hw
, 0);
3056 if (status
& Y2_IS_IRQ_PHY2
)
3057 sky2_phy_intr(hw
, 1);
3059 if (status
& Y2_IS_PHY_QLNK
)
3060 sky2_qlink_intr(hw
);
3062 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
3063 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
3065 if (work_done
>= work_limit
)
3069 napi_complete(napi
);
3070 sky2_read32(hw
, B0_Y2_SP_LISR
);
3076 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
3078 struct sky2_hw
*hw
= dev_id
;
3081 /* Reading this mask interrupts as side effect */
3082 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3083 if (status
== 0 || status
== ~0) {
3084 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3088 prefetch(&hw
->st_le
[hw
->st_idx
]);
3090 napi_schedule(&hw
->napi
);
3095 #ifdef CONFIG_NET_POLL_CONTROLLER
3096 static void sky2_netpoll(struct net_device
*dev
)
3098 struct sky2_port
*sky2
= netdev_priv(dev
);
3100 napi_schedule(&sky2
->hw
->napi
);
3104 /* Chip internal frequency for clock calculations */
3105 static u32
sky2_mhz(const struct sky2_hw
*hw
)
3107 switch (hw
->chip_id
) {
3108 case CHIP_ID_YUKON_EC
:
3109 case CHIP_ID_YUKON_EC_U
:
3110 case CHIP_ID_YUKON_EX
:
3111 case CHIP_ID_YUKON_SUPR
:
3112 case CHIP_ID_YUKON_UL_2
:
3113 case CHIP_ID_YUKON_OPT
:
3114 case CHIP_ID_YUKON_PRM
:
3115 case CHIP_ID_YUKON_OP_2
:
3118 case CHIP_ID_YUKON_FE
:
3121 case CHIP_ID_YUKON_FE_P
:
3124 case CHIP_ID_YUKON_XL
:
3132 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
3134 return sky2_mhz(hw
) * us
;
3137 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
3139 return clk
/ sky2_mhz(hw
);
3143 static int sky2_init(struct sky2_hw
*hw
)
3147 /* Enable all clocks and check for bad PCI access */
3148 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
3150 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
3152 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
3153 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
3155 switch (hw
->chip_id
) {
3156 case CHIP_ID_YUKON_XL
:
3157 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
3158 if (hw
->chip_rev
< CHIP_REV_YU_XL_A2
)
3159 hw
->flags
|= SKY2_HW_RSS_BROKEN
;
3162 case CHIP_ID_YUKON_EC_U
:
3163 hw
->flags
= SKY2_HW_GIGABIT
3165 | SKY2_HW_ADV_POWER_CTL
;
3168 case CHIP_ID_YUKON_EX
:
3169 hw
->flags
= SKY2_HW_GIGABIT
3172 | SKY2_HW_ADV_POWER_CTL
3173 | SKY2_HW_RSS_CHKSUM
;
3175 /* New transmit checksum */
3176 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
3177 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
3180 case CHIP_ID_YUKON_EC
:
3181 /* This rev is really old, and requires untested workarounds */
3182 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
3183 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
3186 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_RSS_BROKEN
;
3189 case CHIP_ID_YUKON_FE
:
3190 hw
->flags
= SKY2_HW_RSS_BROKEN
;
3193 case CHIP_ID_YUKON_FE_P
:
3194 hw
->flags
= SKY2_HW_NEWER_PHY
3196 | SKY2_HW_AUTO_TX_SUM
3197 | SKY2_HW_ADV_POWER_CTL
;
3199 /* The workaround for status conflicts VLAN tag detection. */
3200 if (hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
3201 hw
->flags
|= SKY2_HW_VLAN_BROKEN
| SKY2_HW_RSS_CHKSUM
;
3204 case CHIP_ID_YUKON_SUPR
:
3205 hw
->flags
= SKY2_HW_GIGABIT
3208 | SKY2_HW_AUTO_TX_SUM
3209 | SKY2_HW_ADV_POWER_CTL
;
3211 if (hw
->chip_rev
== CHIP_REV_YU_SU_A0
)
3212 hw
->flags
|= SKY2_HW_RSS_CHKSUM
;
3215 case CHIP_ID_YUKON_UL_2
:
3216 hw
->flags
= SKY2_HW_GIGABIT
3217 | SKY2_HW_ADV_POWER_CTL
;
3220 case CHIP_ID_YUKON_OPT
:
3221 case CHIP_ID_YUKON_PRM
:
3222 case CHIP_ID_YUKON_OP_2
:
3223 hw
->flags
= SKY2_HW_GIGABIT
3225 | SKY2_HW_ADV_POWER_CTL
;
3229 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
3234 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
3235 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
3236 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
3239 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
3240 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
3241 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
3245 if (sky2_read8(hw
, B2_E_0
))
3246 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
3251 static void sky2_reset(struct sky2_hw
*hw
)
3253 struct pci_dev
*pdev
= hw
->pdev
;
3256 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
3259 if (hw
->chip_id
== CHIP_ID_YUKON_EX
3260 || hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3261 sky2_write32(hw
, CPU_WDOG
, 0);
3262 status
= sky2_read16(hw
, HCU_CCSR
);
3263 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
3264 HCU_CCSR_UC_STATE_MSK
);
3266 * CPU clock divider shouldn't be used because
3267 * - ASF firmware may malfunction
3268 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3270 status
&= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK
;
3271 sky2_write16(hw
, HCU_CCSR
, status
);
3272 sky2_write32(hw
, CPU_WDOG
, 0);
3274 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
3275 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
3278 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3279 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
3281 /* allow writes to PCI config */
3282 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3284 /* clear PCI errors, if any */
3285 status
= sky2_pci_read16(hw
, PCI_STATUS
);
3286 status
|= PCI_STATUS_ERROR_BITS
;
3287 sky2_pci_write16(hw
, PCI_STATUS
, status
);
3289 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3291 if (pci_is_pcie(pdev
)) {
3292 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
3295 /* If error bit is stuck on ignore it */
3296 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
3297 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
3299 hwe_mask
|= Y2_IS_PCI_EXP
;
3303 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3305 for (i
= 0; i
< hw
->ports
; i
++) {
3306 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3307 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3309 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
3310 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
3311 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
3312 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
3317 if (hw
->chip_id
== CHIP_ID_YUKON_SUPR
&& hw
->chip_rev
> CHIP_REV_YU_SU_B0
) {
3318 /* enable MACSec clock gating */
3319 sky2_pci_write32(hw
, PCI_DEV_REG3
, P_CLK_MACSEC_DIS
);
3322 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
||
3323 hw
->chip_id
== CHIP_ID_YUKON_PRM
||
3324 hw
->chip_id
== CHIP_ID_YUKON_OP_2
) {
3327 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
&& hw
->chip_rev
== 0) {
3328 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3329 sky2_write32(hw
, Y2_PEX_PHY_DATA
, (0x80UL
<< 16) | (1 << 7));
3331 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3334 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3335 sky2_write32(hw
, Y2_PEX_PHY_DATA
, PEX_DB_ACCESS
| (0x08UL
<< 16));
3337 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3341 reg
<<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE
;
3342 reg
|= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT
;
3344 /* reset PHY Link Detect */
3345 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3346 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, reg
);
3348 /* check if PSMv2 was running before */
3349 reg
= sky2_pci_read16(hw
, PSM_CONFIG_REG3
);
3350 if (reg
& PCI_EXP_LNKCTL_ASPMC
)
3351 /* restore the PCIe Link Control register */
3352 sky2_pci_write16(hw
, pdev
->pcie_cap
+ PCI_EXP_LNKCTL
,
3355 if (hw
->chip_id
== CHIP_ID_YUKON_PRM
&&
3356 hw
->chip_rev
== CHIP_REV_YU_PRM_A0
) {
3357 /* change PHY Interrupt polarity to low active */
3358 reg
= sky2_read16(hw
, GPHY_CTRL
);
3359 sky2_write16(hw
, GPHY_CTRL
, reg
| GPC_INTPOL
);
3361 /* adapt HW for low active PHY Interrupt */
3362 reg
= sky2_read16(hw
, Y2_CFG_SPC
+ PCI_LDO_CTRL
);
3363 sky2_write16(hw
, Y2_CFG_SPC
+ PCI_LDO_CTRL
, reg
| PHY_M_UNDOC1
);
3366 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3368 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3369 sky2_write32(hw
, Y2_PEX_PHY_DATA
, PEX_DB_ACCESS
| (0x08UL
<< 16));
3372 /* Clear I2C IRQ noise */
3373 sky2_write32(hw
, B2_I2C_IRQ
, 1);
3375 /* turn off hardware timer (unused) */
3376 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3377 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3379 /* Turn off descriptor polling */
3380 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
3382 /* Turn off receive timestamp */
3383 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
3384 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3386 /* enable the Tx Arbiters */
3387 for (i
= 0; i
< hw
->ports
; i
++)
3388 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3390 /* Initialize ram interface */
3391 for (i
= 0; i
< hw
->ports
; i
++) {
3392 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
3394 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
3395 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
3396 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
3397 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
3398 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
3399 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
3400 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
3401 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
3402 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
3403 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
3404 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
3405 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
3408 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
3410 for (i
= 0; i
< hw
->ports
; i
++)
3411 sky2_gmac_reset(hw
, i
);
3413 memset(hw
->st_le
, 0, hw
->st_size
* sizeof(struct sky2_status_le
));
3416 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
3417 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
3419 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
3420 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
3422 /* Set the list last index */
3423 sky2_write16(hw
, STAT_LAST_IDX
, hw
->st_size
- 1);
3425 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
3426 sky2_write8(hw
, STAT_FIFO_WM
, 16);
3428 /* set Status-FIFO ISR watermark */
3429 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
3430 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
3432 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
3434 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
3435 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
3436 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
3438 /* enable status unit */
3439 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
3441 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3442 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3443 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3446 /* Take device down (offline).
3447 * Equivalent to doing dev_stop() but this does not
3448 * inform upper layers of the transition.
3450 static void sky2_detach(struct net_device
*dev
)
3452 if (netif_running(dev
)) {
3454 netif_device_detach(dev
); /* stop txq */
3455 netif_tx_unlock(dev
);
3460 /* Bring device back after doing sky2_detach */
3461 static int sky2_reattach(struct net_device
*dev
)
3465 if (netif_running(dev
)) {
3466 err
= sky2_open(dev
);
3468 netdev_info(dev
, "could not restart %d\n", err
);
3471 netif_device_attach(dev
);
3472 sky2_set_multicast(dev
);
3479 static void sky2_all_down(struct sky2_hw
*hw
)
3483 if (hw
->flags
& SKY2_HW_IRQ_SETUP
) {
3484 sky2_read32(hw
, B0_IMSK
);
3485 sky2_write32(hw
, B0_IMSK
, 0);
3487 synchronize_irq(hw
->pdev
->irq
);
3488 napi_disable(&hw
->napi
);
3491 for (i
= 0; i
< hw
->ports
; i
++) {
3492 struct net_device
*dev
= hw
->dev
[i
];
3493 struct sky2_port
*sky2
= netdev_priv(dev
);
3495 if (!netif_running(dev
))
3498 netif_carrier_off(dev
);
3499 netif_tx_disable(dev
);
3504 static void sky2_all_up(struct sky2_hw
*hw
)
3506 u32 imask
= Y2_IS_BASE
;
3509 for (i
= 0; i
< hw
->ports
; i
++) {
3510 struct net_device
*dev
= hw
->dev
[i
];
3511 struct sky2_port
*sky2
= netdev_priv(dev
);
3513 if (!netif_running(dev
))
3517 sky2_set_multicast(dev
);
3518 imask
|= portirq_msk
[i
];
3519 netif_wake_queue(dev
);
3522 if (hw
->flags
& SKY2_HW_IRQ_SETUP
) {
3523 sky2_write32(hw
, B0_IMSK
, imask
);
3524 sky2_read32(hw
, B0_IMSK
);
3525 sky2_read32(hw
, B0_Y2_SP_LISR
);
3526 napi_enable(&hw
->napi
);
3530 static void sky2_restart(struct work_struct
*work
)
3532 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
3543 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3545 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3548 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3550 const struct sky2_port
*sky2
= netdev_priv(dev
);
3552 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3553 wol
->wolopts
= sky2
->wol
;
3556 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3558 struct sky2_port
*sky2
= netdev_priv(dev
);
3559 struct sky2_hw
*hw
= sky2
->hw
;
3560 bool enable_wakeup
= false;
3563 if ((wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
)) ||
3564 !device_can_wakeup(&hw
->pdev
->dev
))
3567 sky2
->wol
= wol
->wolopts
;
3569 for (i
= 0; i
< hw
->ports
; i
++) {
3570 struct net_device
*dev
= hw
->dev
[i
];
3571 struct sky2_port
*sky2
= netdev_priv(dev
);
3574 enable_wakeup
= true;
3576 device_set_wakeup_enable(&hw
->pdev
->dev
, enable_wakeup
);
3581 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3583 if (sky2_is_copper(hw
)) {
3584 u32 modes
= SUPPORTED_10baseT_Half
3585 | SUPPORTED_10baseT_Full
3586 | SUPPORTED_100baseT_Half
3587 | SUPPORTED_100baseT_Full
;
3589 if (hw
->flags
& SKY2_HW_GIGABIT
)
3590 modes
|= SUPPORTED_1000baseT_Half
3591 | SUPPORTED_1000baseT_Full
;
3594 return SUPPORTED_1000baseT_Half
3595 | SUPPORTED_1000baseT_Full
;
3598 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3600 struct sky2_port
*sky2
= netdev_priv(dev
);
3601 struct sky2_hw
*hw
= sky2
->hw
;
3603 ecmd
->transceiver
= XCVR_INTERNAL
;
3604 ecmd
->supported
= sky2_supported_modes(hw
);
3605 ecmd
->phy_address
= PHY_ADDR_MARV
;
3606 if (sky2_is_copper(hw
)) {
3607 ecmd
->port
= PORT_TP
;
3608 ethtool_cmd_speed_set(ecmd
, sky2
->speed
);
3609 ecmd
->supported
|= SUPPORTED_Autoneg
| SUPPORTED_TP
;
3611 ethtool_cmd_speed_set(ecmd
, SPEED_1000
);
3612 ecmd
->port
= PORT_FIBRE
;
3613 ecmd
->supported
|= SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
3616 ecmd
->advertising
= sky2
->advertising
;
3617 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
3618 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3619 ecmd
->duplex
= sky2
->duplex
;
3623 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3625 struct sky2_port
*sky2
= netdev_priv(dev
);
3626 const struct sky2_hw
*hw
= sky2
->hw
;
3627 u32 supported
= sky2_supported_modes(hw
);
3629 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3630 if (ecmd
->advertising
& ~supported
)
3633 if (sky2_is_copper(hw
))
3634 sky2
->advertising
= ecmd
->advertising
|
3638 sky2
->advertising
= ecmd
->advertising
|
3642 sky2
->flags
|= SKY2_FLAG_AUTO_SPEED
;
3647 u32 speed
= ethtool_cmd_speed(ecmd
);
3651 if (ecmd
->duplex
== DUPLEX_FULL
)
3652 setting
= SUPPORTED_1000baseT_Full
;
3653 else if (ecmd
->duplex
== DUPLEX_HALF
)
3654 setting
= SUPPORTED_1000baseT_Half
;
3659 if (ecmd
->duplex
== DUPLEX_FULL
)
3660 setting
= SUPPORTED_100baseT_Full
;
3661 else if (ecmd
->duplex
== DUPLEX_HALF
)
3662 setting
= SUPPORTED_100baseT_Half
;
3668 if (ecmd
->duplex
== DUPLEX_FULL
)
3669 setting
= SUPPORTED_10baseT_Full
;
3670 else if (ecmd
->duplex
== DUPLEX_HALF
)
3671 setting
= SUPPORTED_10baseT_Half
;
3679 if ((setting
& supported
) == 0)
3682 sky2
->speed
= speed
;
3683 sky2
->duplex
= ecmd
->duplex
;
3684 sky2
->flags
&= ~SKY2_FLAG_AUTO_SPEED
;
3687 if (netif_running(dev
)) {
3688 sky2_phy_reinit(sky2
);
3689 sky2_set_multicast(dev
);
3695 static void sky2_get_drvinfo(struct net_device
*dev
,
3696 struct ethtool_drvinfo
*info
)
3698 struct sky2_port
*sky2
= netdev_priv(dev
);
3700 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
3701 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
3702 strlcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
),
3703 sizeof(info
->bus_info
));
3706 static const struct sky2_stat
{
3707 char name
[ETH_GSTRING_LEN
];
3710 { "tx_bytes", GM_TXO_OK_HI
},
3711 { "rx_bytes", GM_RXO_OK_HI
},
3712 { "tx_broadcast", GM_TXF_BC_OK
},
3713 { "rx_broadcast", GM_RXF_BC_OK
},
3714 { "tx_multicast", GM_TXF_MC_OK
},
3715 { "rx_multicast", GM_RXF_MC_OK
},
3716 { "tx_unicast", GM_TXF_UC_OK
},
3717 { "rx_unicast", GM_RXF_UC_OK
},
3718 { "tx_mac_pause", GM_TXF_MPAUSE
},
3719 { "rx_mac_pause", GM_RXF_MPAUSE
},
3720 { "collisions", GM_TXF_COL
},
3721 { "late_collision",GM_TXF_LAT_COL
},
3722 { "aborted", GM_TXF_ABO_COL
},
3723 { "single_collisions", GM_TXF_SNG_COL
},
3724 { "multi_collisions", GM_TXF_MUL_COL
},
3726 { "rx_short", GM_RXF_SHT
},
3727 { "rx_runt", GM_RXE_FRAG
},
3728 { "rx_64_byte_packets", GM_RXF_64B
},
3729 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3730 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3731 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3732 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3733 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3734 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3735 { "rx_too_long", GM_RXF_LNG_ERR
},
3736 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3737 { "rx_jabber", GM_RXF_JAB_PKT
},
3738 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3740 { "tx_64_byte_packets", GM_TXF_64B
},
3741 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3742 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3743 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3744 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3745 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3746 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3747 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3750 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3752 struct sky2_port
*sky2
= netdev_priv(netdev
);
3753 return sky2
->msg_enable
;
3756 static int sky2_nway_reset(struct net_device
*dev
)
3758 struct sky2_port
*sky2
= netdev_priv(dev
);
3760 if (!netif_running(dev
) || !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
))
3763 sky2_phy_reinit(sky2
);
3764 sky2_set_multicast(dev
);
3769 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3771 struct sky2_hw
*hw
= sky2
->hw
;
3772 unsigned port
= sky2
->port
;
3775 data
[0] = get_stats64(hw
, port
, GM_TXO_OK_LO
);
3776 data
[1] = get_stats64(hw
, port
, GM_RXO_OK_LO
);
3778 for (i
= 2; i
< count
; i
++)
3779 data
[i
] = get_stats32(hw
, port
, sky2_stats
[i
].offset
);
3782 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3784 struct sky2_port
*sky2
= netdev_priv(netdev
);
3785 sky2
->msg_enable
= value
;
3788 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3792 return ARRAY_SIZE(sky2_stats
);
3798 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3799 struct ethtool_stats
*stats
, u64
* data
)
3801 struct sky2_port
*sky2
= netdev_priv(dev
);
3803 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3806 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3810 switch (stringset
) {
3812 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3813 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3814 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3819 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3821 struct sky2_port
*sky2
= netdev_priv(dev
);
3822 struct sky2_hw
*hw
= sky2
->hw
;
3823 unsigned port
= sky2
->port
;
3824 const struct sockaddr
*addr
= p
;
3826 if (!is_valid_ether_addr(addr
->sa_data
))
3827 return -EADDRNOTAVAIL
;
3829 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3830 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3831 dev
->dev_addr
, ETH_ALEN
);
3832 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3833 dev
->dev_addr
, ETH_ALEN
);
3835 /* virtual address for data */
3836 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3838 /* physical address: used for pause frames */
3839 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3844 static inline void sky2_add_filter(u8 filter
[8], const u8
*addr
)
3848 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3849 filter
[bit
>> 3] |= 1 << (bit
& 7);
3852 static void sky2_set_multicast(struct net_device
*dev
)
3854 struct sky2_port
*sky2
= netdev_priv(dev
);
3855 struct sky2_hw
*hw
= sky2
->hw
;
3856 unsigned port
= sky2
->port
;
3857 struct netdev_hw_addr
*ha
;
3861 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3863 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3864 memset(filter
, 0, sizeof(filter
));
3866 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3867 reg
|= GM_RXCR_UCF_ENA
;
3869 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3870 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3871 else if (dev
->flags
& IFF_ALLMULTI
)
3872 memset(filter
, 0xff, sizeof(filter
));
3873 else if (netdev_mc_empty(dev
) && !rx_pause
)
3874 reg
&= ~GM_RXCR_MCF_ENA
;
3876 reg
|= GM_RXCR_MCF_ENA
;
3879 sky2_add_filter(filter
, pause_mc_addr
);
3881 netdev_for_each_mc_addr(ha
, dev
)
3882 sky2_add_filter(filter
, ha
->addr
);
3885 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3886 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3887 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3888 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3889 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3890 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3891 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3892 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3894 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3897 static struct rtnl_link_stats64
*sky2_get_stats(struct net_device
*dev
,
3898 struct rtnl_link_stats64
*stats
)
3900 struct sky2_port
*sky2
= netdev_priv(dev
);
3901 struct sky2_hw
*hw
= sky2
->hw
;
3902 unsigned port
= sky2
->port
;
3904 u64 _bytes
, _packets
;
3907 start
= u64_stats_fetch_begin_bh(&sky2
->rx_stats
.syncp
);
3908 _bytes
= sky2
->rx_stats
.bytes
;
3909 _packets
= sky2
->rx_stats
.packets
;
3910 } while (u64_stats_fetch_retry_bh(&sky2
->rx_stats
.syncp
, start
));
3912 stats
->rx_packets
= _packets
;
3913 stats
->rx_bytes
= _bytes
;
3916 start
= u64_stats_fetch_begin_bh(&sky2
->tx_stats
.syncp
);
3917 _bytes
= sky2
->tx_stats
.bytes
;
3918 _packets
= sky2
->tx_stats
.packets
;
3919 } while (u64_stats_fetch_retry_bh(&sky2
->tx_stats
.syncp
, start
));
3921 stats
->tx_packets
= _packets
;
3922 stats
->tx_bytes
= _bytes
;
3924 stats
->multicast
= get_stats32(hw
, port
, GM_RXF_MC_OK
)
3925 + get_stats32(hw
, port
, GM_RXF_BC_OK
);
3927 stats
->collisions
= get_stats32(hw
, port
, GM_TXF_COL
);
3929 stats
->rx_length_errors
= get_stats32(hw
, port
, GM_RXF_LNG_ERR
);
3930 stats
->rx_crc_errors
= get_stats32(hw
, port
, GM_RXF_FCS_ERR
);
3931 stats
->rx_frame_errors
= get_stats32(hw
, port
, GM_RXF_SHT
)
3932 + get_stats32(hw
, port
, GM_RXE_FRAG
);
3933 stats
->rx_over_errors
= get_stats32(hw
, port
, GM_RXE_FIFO_OV
);
3935 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
3936 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
3937 stats
->tx_fifo_errors
= dev
->stats
.tx_fifo_errors
;
3942 /* Can have one global because blinking is controlled by
3943 * ethtool and that is always under RTNL mutex
3945 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3947 struct sky2_hw
*hw
= sky2
->hw
;
3948 unsigned port
= sky2
->port
;
3950 spin_lock_bh(&sky2
->phy_lock
);
3951 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3952 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3953 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3955 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3956 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3960 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3961 PHY_M_LEDC_LOS_CTRL(8) |
3962 PHY_M_LEDC_INIT_CTRL(8) |
3963 PHY_M_LEDC_STA1_CTRL(8) |
3964 PHY_M_LEDC_STA0_CTRL(8));
3967 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3968 PHY_M_LEDC_LOS_CTRL(9) |
3969 PHY_M_LEDC_INIT_CTRL(9) |
3970 PHY_M_LEDC_STA1_CTRL(9) |
3971 PHY_M_LEDC_STA0_CTRL(9));
3974 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3975 PHY_M_LEDC_LOS_CTRL(0xa) |
3976 PHY_M_LEDC_INIT_CTRL(0xa) |
3977 PHY_M_LEDC_STA1_CTRL(0xa) |
3978 PHY_M_LEDC_STA0_CTRL(0xa));
3981 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3982 PHY_M_LEDC_LOS_CTRL(1) |
3983 PHY_M_LEDC_INIT_CTRL(8) |
3984 PHY_M_LEDC_STA1_CTRL(7) |
3985 PHY_M_LEDC_STA0_CTRL(7));
3988 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3990 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3991 PHY_M_LED_MO_DUP(mode
) |
3992 PHY_M_LED_MO_10(mode
) |
3993 PHY_M_LED_MO_100(mode
) |
3994 PHY_M_LED_MO_1000(mode
) |
3995 PHY_M_LED_MO_RX(mode
) |
3996 PHY_M_LED_MO_TX(mode
));
3998 spin_unlock_bh(&sky2
->phy_lock
);
4001 /* blink LED's for finding board */
4002 static int sky2_set_phys_id(struct net_device
*dev
,
4003 enum ethtool_phys_id_state state
)
4005 struct sky2_port
*sky2
= netdev_priv(dev
);
4008 case ETHTOOL_ID_ACTIVE
:
4009 return 1; /* cycle on/off once per second */
4010 case ETHTOOL_ID_INACTIVE
:
4011 sky2_led(sky2
, MO_LED_NORM
);
4014 sky2_led(sky2
, MO_LED_ON
);
4016 case ETHTOOL_ID_OFF
:
4017 sky2_led(sky2
, MO_LED_OFF
);
4024 static void sky2_get_pauseparam(struct net_device
*dev
,
4025 struct ethtool_pauseparam
*ecmd
)
4027 struct sky2_port
*sky2
= netdev_priv(dev
);
4029 switch (sky2
->flow_mode
) {
4031 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
4034 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
4037 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
4040 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
4043 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
)
4044 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
4047 static int sky2_set_pauseparam(struct net_device
*dev
,
4048 struct ethtool_pauseparam
*ecmd
)
4050 struct sky2_port
*sky2
= netdev_priv(dev
);
4052 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
4053 sky2
->flags
|= SKY2_FLAG_AUTO_PAUSE
;
4055 sky2
->flags
&= ~SKY2_FLAG_AUTO_PAUSE
;
4057 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
4059 if (netif_running(dev
))
4060 sky2_phy_reinit(sky2
);
4065 static int sky2_get_coalesce(struct net_device
*dev
,
4066 struct ethtool_coalesce
*ecmd
)
4068 struct sky2_port
*sky2
= netdev_priv(dev
);
4069 struct sky2_hw
*hw
= sky2
->hw
;
4071 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
4072 ecmd
->tx_coalesce_usecs
= 0;
4074 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
4075 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
4077 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
4079 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
4080 ecmd
->rx_coalesce_usecs
= 0;
4082 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
4083 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
4085 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
4087 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
4088 ecmd
->rx_coalesce_usecs_irq
= 0;
4090 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
4091 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
4094 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
4099 /* Note: this affect both ports */
4100 static int sky2_set_coalesce(struct net_device
*dev
,
4101 struct ethtool_coalesce
*ecmd
)
4103 struct sky2_port
*sky2
= netdev_priv(dev
);
4104 struct sky2_hw
*hw
= sky2
->hw
;
4105 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
4107 if (ecmd
->tx_coalesce_usecs
> tmax
||
4108 ecmd
->rx_coalesce_usecs
> tmax
||
4109 ecmd
->rx_coalesce_usecs_irq
> tmax
)
4112 if (ecmd
->tx_max_coalesced_frames
>= sky2
->tx_ring_size
-1)
4114 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
4116 if (ecmd
->rx_max_coalesced_frames_irq
> RX_MAX_PENDING
)
4119 if (ecmd
->tx_coalesce_usecs
== 0)
4120 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
4122 sky2_write32(hw
, STAT_TX_TIMER_INI
,
4123 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
4124 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
4126 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
4128 if (ecmd
->rx_coalesce_usecs
== 0)
4129 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
4131 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
4132 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
4133 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
4135 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
4137 if (ecmd
->rx_coalesce_usecs_irq
== 0)
4138 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
4140 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
4141 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
4142 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
4144 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
4149 * Hardware is limited to min of 128 and max of 2048 for ring size
4150 * and rounded up to next power of two
4151 * to avoid division in modulus calclation
4153 static unsigned long roundup_ring_size(unsigned long pending
)
4155 return max(128ul, roundup_pow_of_two(pending
+1));
4158 static void sky2_get_ringparam(struct net_device
*dev
,
4159 struct ethtool_ringparam
*ering
)
4161 struct sky2_port
*sky2
= netdev_priv(dev
);
4163 ering
->rx_max_pending
= RX_MAX_PENDING
;
4164 ering
->tx_max_pending
= TX_MAX_PENDING
;
4166 ering
->rx_pending
= sky2
->rx_pending
;
4167 ering
->tx_pending
= sky2
->tx_pending
;
4170 static int sky2_set_ringparam(struct net_device
*dev
,
4171 struct ethtool_ringparam
*ering
)
4173 struct sky2_port
*sky2
= netdev_priv(dev
);
4175 if (ering
->rx_pending
> RX_MAX_PENDING
||
4176 ering
->rx_pending
< 8 ||
4177 ering
->tx_pending
< TX_MIN_PENDING
||
4178 ering
->tx_pending
> TX_MAX_PENDING
)
4183 sky2
->rx_pending
= ering
->rx_pending
;
4184 sky2
->tx_pending
= ering
->tx_pending
;
4185 sky2
->tx_ring_size
= roundup_ring_size(sky2
->tx_pending
);
4187 return sky2_reattach(dev
);
4190 static int sky2_get_regs_len(struct net_device
*dev
)
4195 static int sky2_reg_access_ok(struct sky2_hw
*hw
, unsigned int b
)
4197 /* This complicated switch statement is to make sure and
4198 * only access regions that are unreserved.
4199 * Some blocks are only valid on dual port cards.
4203 case 5: /* Tx Arbiter 2 */
4205 case 14 ... 15: /* TX2 */
4206 case 17: case 19: /* Ram Buffer 2 */
4207 case 22 ... 23: /* Tx Ram Buffer 2 */
4208 case 25: /* Rx MAC Fifo 1 */
4209 case 27: /* Tx MAC Fifo 2 */
4210 case 31: /* GPHY 2 */
4211 case 40 ... 47: /* Pattern Ram 2 */
4212 case 52: case 54: /* TCP Segmentation 2 */
4213 case 112 ... 116: /* GMAC 2 */
4214 return hw
->ports
> 1;
4216 case 0: /* Control */
4217 case 2: /* Mac address */
4218 case 4: /* Tx Arbiter 1 */
4219 case 7: /* PCI express reg */
4221 case 12 ... 13: /* TX1 */
4222 case 16: case 18:/* Rx Ram Buffer 1 */
4223 case 20 ... 21: /* Tx Ram Buffer 1 */
4224 case 24: /* Rx MAC Fifo 1 */
4225 case 26: /* Tx MAC Fifo 1 */
4226 case 28 ... 29: /* Descriptor and status unit */
4227 case 30: /* GPHY 1*/
4228 case 32 ... 39: /* Pattern Ram 1 */
4229 case 48: case 50: /* TCP Segmentation 1 */
4230 case 56 ... 60: /* PCI space */
4231 case 80 ... 84: /* GMAC 1 */
4240 * Returns copy of control register region
4241 * Note: ethtool_get_regs always provides full size (16k) buffer
4243 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
4246 const struct sky2_port
*sky2
= netdev_priv(dev
);
4247 const void __iomem
*io
= sky2
->hw
->regs
;
4252 for (b
= 0; b
< 128; b
++) {
4253 /* skip poisonous diagnostic ram region in block 3 */
4255 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
4256 else if (sky2_reg_access_ok(sky2
->hw
, b
))
4257 memcpy_fromio(p
, io
, 128);
4266 static int sky2_get_eeprom_len(struct net_device
*dev
)
4268 struct sky2_port
*sky2
= netdev_priv(dev
);
4269 struct sky2_hw
*hw
= sky2
->hw
;
4272 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4273 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4276 static int sky2_vpd_wait(const struct sky2_hw
*hw
, int cap
, u16 busy
)
4278 unsigned long start
= jiffies
;
4280 while ( (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
) == busy
) {
4281 /* Can take up to 10.6 ms for write */
4282 if (time_after(jiffies
, start
+ HZ
/4)) {
4283 dev_err(&hw
->pdev
->dev
, "VPD cycle timed out\n");
4292 static int sky2_vpd_read(struct sky2_hw
*hw
, int cap
, void *data
,
4293 u16 offset
, size_t length
)
4297 while (length
> 0) {
4300 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
4301 rc
= sky2_vpd_wait(hw
, cap
, 0);
4305 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
4307 memcpy(data
, &val
, min(sizeof(val
), length
));
4308 offset
+= sizeof(u32
);
4309 data
+= sizeof(u32
);
4310 length
-= sizeof(u32
);
4316 static int sky2_vpd_write(struct sky2_hw
*hw
, int cap
, const void *data
,
4317 u16 offset
, unsigned int length
)
4322 for (i
= 0; i
< length
; i
+= sizeof(u32
)) {
4323 u32 val
= *(u32
*)(data
+ i
);
4325 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
4326 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
4328 rc
= sky2_vpd_wait(hw
, cap
, PCI_VPD_ADDR_F
);
4335 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4338 struct sky2_port
*sky2
= netdev_priv(dev
);
4339 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4344 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
4346 return sky2_vpd_read(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4349 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4352 struct sky2_port
*sky2
= netdev_priv(dev
);
4353 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4358 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
4361 /* Partial writes not supported */
4362 if ((eeprom
->offset
& 3) || (eeprom
->len
& 3))
4365 return sky2_vpd_write(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4368 static netdev_features_t
sky2_fix_features(struct net_device
*dev
,
4369 netdev_features_t features
)
4371 const struct sky2_port
*sky2
= netdev_priv(dev
);
4372 const struct sky2_hw
*hw
= sky2
->hw
;
4374 /* In order to do Jumbo packets on these chips, need to turn off the
4375 * transmit store/forward. Therefore checksum offload won't work.
4377 if (dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
4378 netdev_info(dev
, "checksum offload not possible with jumbo frames\n");
4379 features
&= ~(NETIF_F_TSO
|NETIF_F_SG
|NETIF_F_ALL_CSUM
);
4382 /* Some hardware requires receive checksum for RSS to work. */
4383 if ( (features
& NETIF_F_RXHASH
) &&
4384 !(features
& NETIF_F_RXCSUM
) &&
4385 (sky2
->hw
->flags
& SKY2_HW_RSS_CHKSUM
)) {
4386 netdev_info(dev
, "receive hashing forces receive checksum\n");
4387 features
|= NETIF_F_RXCSUM
;
4393 static int sky2_set_features(struct net_device
*dev
, netdev_features_t features
)
4395 struct sky2_port
*sky2
= netdev_priv(dev
);
4396 netdev_features_t changed
= dev
->features
^ features
;
4398 if ((changed
& NETIF_F_RXCSUM
) &&
4399 !(sky2
->hw
->flags
& SKY2_HW_NEW_LE
)) {
4400 sky2_write32(sky2
->hw
,
4401 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
4402 (features
& NETIF_F_RXCSUM
)
4403 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
4406 if (changed
& NETIF_F_RXHASH
)
4407 rx_set_rss(dev
, features
);
4409 if (changed
& (NETIF_F_HW_VLAN_TX
|NETIF_F_HW_VLAN_RX
))
4410 sky2_vlan_mode(dev
, features
);
4415 static const struct ethtool_ops sky2_ethtool_ops
= {
4416 .get_settings
= sky2_get_settings
,
4417 .set_settings
= sky2_set_settings
,
4418 .get_drvinfo
= sky2_get_drvinfo
,
4419 .get_wol
= sky2_get_wol
,
4420 .set_wol
= sky2_set_wol
,
4421 .get_msglevel
= sky2_get_msglevel
,
4422 .set_msglevel
= sky2_set_msglevel
,
4423 .nway_reset
= sky2_nway_reset
,
4424 .get_regs_len
= sky2_get_regs_len
,
4425 .get_regs
= sky2_get_regs
,
4426 .get_link
= ethtool_op_get_link
,
4427 .get_eeprom_len
= sky2_get_eeprom_len
,
4428 .get_eeprom
= sky2_get_eeprom
,
4429 .set_eeprom
= sky2_set_eeprom
,
4430 .get_strings
= sky2_get_strings
,
4431 .get_coalesce
= sky2_get_coalesce
,
4432 .set_coalesce
= sky2_set_coalesce
,
4433 .get_ringparam
= sky2_get_ringparam
,
4434 .set_ringparam
= sky2_set_ringparam
,
4435 .get_pauseparam
= sky2_get_pauseparam
,
4436 .set_pauseparam
= sky2_set_pauseparam
,
4437 .set_phys_id
= sky2_set_phys_id
,
4438 .get_sset_count
= sky2_get_sset_count
,
4439 .get_ethtool_stats
= sky2_get_ethtool_stats
,
4442 #ifdef CONFIG_SKY2_DEBUG
4444 static struct dentry
*sky2_debug
;
4448 * Read and parse the first part of Vital Product Data
4450 #define VPD_SIZE 128
4451 #define VPD_MAGIC 0x82
4453 static const struct vpd_tag
{
4457 { "PN", "Part Number" },
4458 { "EC", "Engineering Level" },
4459 { "MN", "Manufacturer" },
4460 { "SN", "Serial Number" },
4461 { "YA", "Asset Tag" },
4462 { "VL", "First Error Log Message" },
4463 { "VF", "Second Error Log Message" },
4464 { "VB", "Boot Agent ROM Configuration" },
4465 { "VE", "EFI UNDI Configuration" },
4468 static void sky2_show_vpd(struct seq_file
*seq
, struct sky2_hw
*hw
)
4476 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4477 vpd_size
= 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4479 seq_printf(seq
, "%s Product Data\n", pci_name(hw
->pdev
));
4480 buf
= kmalloc(vpd_size
, GFP_KERNEL
);
4482 seq_puts(seq
, "no memory!\n");
4486 if (pci_read_vpd(hw
->pdev
, 0, vpd_size
, buf
) < 0) {
4487 seq_puts(seq
, "VPD read failed\n");
4491 if (buf
[0] != VPD_MAGIC
) {
4492 seq_printf(seq
, "VPD tag mismatch: %#x\n", buf
[0]);
4496 if (len
== 0 || len
> vpd_size
- 4) {
4497 seq_printf(seq
, "Invalid id length: %d\n", len
);
4501 seq_printf(seq
, "%.*s\n", len
, buf
+ 3);
4504 while (offs
< vpd_size
- 4) {
4507 if (!memcmp("RW", buf
+ offs
, 2)) /* end marker */
4509 len
= buf
[offs
+ 2];
4510 if (offs
+ len
+ 3 >= vpd_size
)
4513 for (i
= 0; i
< ARRAY_SIZE(vpd_tags
); i
++) {
4514 if (!memcmp(vpd_tags
[i
].tag
, buf
+ offs
, 2)) {
4515 seq_printf(seq
, " %s: %.*s\n",
4516 vpd_tags
[i
].label
, len
, buf
+ offs
+ 3);
4526 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
4528 struct net_device
*dev
= seq
->private;
4529 const struct sky2_port
*sky2
= netdev_priv(dev
);
4530 struct sky2_hw
*hw
= sky2
->hw
;
4531 unsigned port
= sky2
->port
;
4535 sky2_show_vpd(seq
, hw
);
4537 seq_printf(seq
, "\nIRQ src=%x mask=%x control=%x\n",
4538 sky2_read32(hw
, B0_ISRC
),
4539 sky2_read32(hw
, B0_IMSK
),
4540 sky2_read32(hw
, B0_Y2_SP_ICR
));
4542 if (!netif_running(dev
)) {
4543 seq_printf(seq
, "network not running\n");
4547 napi_disable(&hw
->napi
);
4548 last
= sky2_read16(hw
, STAT_PUT_IDX
);
4550 seq_printf(seq
, "Status ring %u\n", hw
->st_size
);
4551 if (hw
->st_idx
== last
)
4552 seq_puts(seq
, "Status ring (empty)\n");
4554 seq_puts(seq
, "Status ring\n");
4555 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< hw
->st_size
;
4556 idx
= RING_NEXT(idx
, hw
->st_size
)) {
4557 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
4558 seq_printf(seq
, "[%d] %#x %d %#x\n",
4559 idx
, le
->opcode
, le
->length
, le
->status
);
4561 seq_puts(seq
, "\n");
4564 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
4565 sky2
->tx_cons
, sky2
->tx_prod
,
4566 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
4567 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
4569 /* Dump contents of tx ring */
4571 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< sky2
->tx_ring_size
;
4572 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
4573 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
4574 u32 a
= le32_to_cpu(le
->addr
);
4577 seq_printf(seq
, "%u:", idx
);
4580 switch (le
->opcode
& ~HW_OWNER
) {
4582 seq_printf(seq
, " %#x:", a
);
4585 seq_printf(seq
, " mtu=%d", a
);
4588 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
4591 seq_printf(seq
, " csum=%#x", a
);
4594 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
4597 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
4600 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
4603 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
4604 a
, le16_to_cpu(le
->length
));
4607 if (le
->ctrl
& EOP
) {
4608 seq_putc(seq
, '\n');
4613 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
4614 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
4615 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
4616 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
4618 sky2_read32(hw
, B0_Y2_SP_LISR
);
4619 napi_enable(&hw
->napi
);
4623 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
4625 return single_open(file
, sky2_debug_show
, inode
->i_private
);
4628 static const struct file_operations sky2_debug_fops
= {
4629 .owner
= THIS_MODULE
,
4630 .open
= sky2_debug_open
,
4632 .llseek
= seq_lseek
,
4633 .release
= single_release
,
4637 * Use network device events to create/remove/rename
4638 * debugfs file entries
4640 static int sky2_device_event(struct notifier_block
*unused
,
4641 unsigned long event
, void *ptr
)
4643 struct net_device
*dev
= ptr
;
4644 struct sky2_port
*sky2
= netdev_priv(dev
);
4646 if (dev
->netdev_ops
->ndo_open
!= sky2_open
|| !sky2_debug
)
4650 case NETDEV_CHANGENAME
:
4651 if (sky2
->debugfs
) {
4652 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
4653 sky2_debug
, dev
->name
);
4657 case NETDEV_GOING_DOWN
:
4658 if (sky2
->debugfs
) {
4659 netdev_printk(KERN_DEBUG
, dev
, "remove debugfs\n");
4660 debugfs_remove(sky2
->debugfs
);
4661 sky2
->debugfs
= NULL
;
4666 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
4669 if (IS_ERR(sky2
->debugfs
))
4670 sky2
->debugfs
= NULL
;
4676 static struct notifier_block sky2_notifier
= {
4677 .notifier_call
= sky2_device_event
,
4681 static __init
void sky2_debug_init(void)
4685 ent
= debugfs_create_dir("sky2", NULL
);
4686 if (!ent
|| IS_ERR(ent
))
4690 register_netdevice_notifier(&sky2_notifier
);
4693 static __exit
void sky2_debug_cleanup(void)
4696 unregister_netdevice_notifier(&sky2_notifier
);
4697 debugfs_remove(sky2_debug
);
4703 #define sky2_debug_init()
4704 #define sky2_debug_cleanup()
4707 /* Two copies of network device operations to handle special case of
4708 not allowing netpoll on second port */
4709 static const struct net_device_ops sky2_netdev_ops
[2] = {
4711 .ndo_open
= sky2_open
,
4712 .ndo_stop
= sky2_close
,
4713 .ndo_start_xmit
= sky2_xmit_frame
,
4714 .ndo_do_ioctl
= sky2_ioctl
,
4715 .ndo_validate_addr
= eth_validate_addr
,
4716 .ndo_set_mac_address
= sky2_set_mac_address
,
4717 .ndo_set_rx_mode
= sky2_set_multicast
,
4718 .ndo_change_mtu
= sky2_change_mtu
,
4719 .ndo_fix_features
= sky2_fix_features
,
4720 .ndo_set_features
= sky2_set_features
,
4721 .ndo_tx_timeout
= sky2_tx_timeout
,
4722 .ndo_get_stats64
= sky2_get_stats
,
4723 #ifdef CONFIG_NET_POLL_CONTROLLER
4724 .ndo_poll_controller
= sky2_netpoll
,
4728 .ndo_open
= sky2_open
,
4729 .ndo_stop
= sky2_close
,
4730 .ndo_start_xmit
= sky2_xmit_frame
,
4731 .ndo_do_ioctl
= sky2_ioctl
,
4732 .ndo_validate_addr
= eth_validate_addr
,
4733 .ndo_set_mac_address
= sky2_set_mac_address
,
4734 .ndo_set_rx_mode
= sky2_set_multicast
,
4735 .ndo_change_mtu
= sky2_change_mtu
,
4736 .ndo_fix_features
= sky2_fix_features
,
4737 .ndo_set_features
= sky2_set_features
,
4738 .ndo_tx_timeout
= sky2_tx_timeout
,
4739 .ndo_get_stats64
= sky2_get_stats
,
4743 /* Initialize network device */
4744 static struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
, unsigned port
,
4745 int highmem
, int wol
)
4747 struct sky2_port
*sky2
;
4748 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4753 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4754 dev
->irq
= hw
->pdev
->irq
;
4755 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4756 dev
->watchdog_timeo
= TX_WATCHDOG
;
4757 dev
->netdev_ops
= &sky2_netdev_ops
[port
];
4759 sky2
= netdev_priv(dev
);
4762 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4764 /* Auto speed and flow control */
4765 sky2
->flags
= SKY2_FLAG_AUTO_SPEED
| SKY2_FLAG_AUTO_PAUSE
;
4766 if (hw
->chip_id
!= CHIP_ID_YUKON_XL
)
4767 dev
->hw_features
|= NETIF_F_RXCSUM
;
4769 sky2
->flow_mode
= FC_BOTH
;
4773 sky2
->advertising
= sky2_supported_modes(hw
);
4776 spin_lock_init(&sky2
->phy_lock
);
4778 sky2
->tx_pending
= TX_DEF_PENDING
;
4779 sky2
->tx_ring_size
= roundup_ring_size(TX_DEF_PENDING
);
4780 sky2
->rx_pending
= RX_DEF_PENDING
;
4782 hw
->dev
[port
] = dev
;
4786 dev
->hw_features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_TSO
;
4789 dev
->features
|= NETIF_F_HIGHDMA
;
4791 /* Enable receive hashing unless hardware is known broken */
4792 if (!(hw
->flags
& SKY2_HW_RSS_BROKEN
))
4793 dev
->hw_features
|= NETIF_F_RXHASH
;
4795 if (!(hw
->flags
& SKY2_HW_VLAN_BROKEN
)) {
4796 dev
->hw_features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4797 dev
->vlan_features
|= SKY2_VLAN_OFFLOADS
;
4800 dev
->features
|= dev
->hw_features
;
4802 /* read the mac address */
4803 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4808 static void sky2_show_addr(struct net_device
*dev
)
4810 const struct sky2_port
*sky2
= netdev_priv(dev
);
4812 netif_info(sky2
, probe
, dev
, "addr %pM\n", dev
->dev_addr
);
4815 /* Handle software interrupt used during MSI test */
4816 static irqreturn_t
sky2_test_intr(int irq
, void *dev_id
)
4818 struct sky2_hw
*hw
= dev_id
;
4819 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4824 if (status
& Y2_IS_IRQ_SW
) {
4825 hw
->flags
|= SKY2_HW_USE_MSI
;
4826 wake_up(&hw
->msi_wait
);
4827 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4829 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4834 /* Test interrupt path by forcing a a software IRQ */
4835 static int sky2_test_msi(struct sky2_hw
*hw
)
4837 struct pci_dev
*pdev
= hw
->pdev
;
4840 init_waitqueue_head(&hw
->msi_wait
);
4842 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4844 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4848 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4850 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4851 sky2_read8(hw
, B0_CTST
);
4853 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4855 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4856 /* MSI test failed, go back to INTx mode */
4857 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4858 "switching to INTx mode.\n");
4861 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4864 sky2_write32(hw
, B0_IMSK
, 0);
4865 sky2_read32(hw
, B0_IMSK
);
4867 free_irq(pdev
->irq
, hw
);
4872 /* This driver supports yukon2 chipset only */
4873 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4875 const char *name
[] = {
4877 "EC Ultra", /* 0xb4 */
4878 "Extreme", /* 0xb5 */
4882 "Supreme", /* 0xb9 */
4884 "Unknown", /* 0xbb */
4885 "Optima", /* 0xbc */
4886 "OptimaEEE", /* 0xbd */
4887 "Optima 2", /* 0xbe */
4890 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
<= CHIP_ID_YUKON_OP_2
)
4891 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4893 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4897 static int sky2_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
4899 struct net_device
*dev
, *dev1
;
4901 int err
, using_dac
= 0, wol_default
;
4905 err
= pci_enable_device(pdev
);
4907 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4911 /* Get configuration information
4912 * Note: only regular PCI config access once to test for HW issues
4913 * other PCI access through shared memory for speed and to
4914 * avoid MMCONFIG problems.
4916 err
= pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
4918 dev_err(&pdev
->dev
, "PCI read config failed\n");
4919 goto err_out_disable
;
4923 dev_err(&pdev
->dev
, "PCI configuration read error\n");
4925 goto err_out_disable
;
4928 err
= pci_request_regions(pdev
, DRV_NAME
);
4930 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4931 goto err_out_disable
;
4934 pci_set_master(pdev
);
4936 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4937 !(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
4939 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4941 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4942 "for consistent allocations\n");
4943 goto err_out_free_regions
;
4946 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4948 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4949 goto err_out_free_regions
;
4955 /* The sk98lin vendor driver uses hardware byte swapping but
4956 * this driver uses software swapping.
4958 reg
&= ~PCI_REV_DESC
;
4959 err
= pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
4961 dev_err(&pdev
->dev
, "PCI write config failed\n");
4962 goto err_out_free_regions
;
4966 wol_default
= device_may_wakeup(&pdev
->dev
) ? WAKE_MAGIC
: 0;
4970 hw
= kzalloc(sizeof(*hw
) + strlen(DRV_NAME
"@pci:")
4971 + strlen(pci_name(pdev
)) + 1, GFP_KERNEL
);
4973 goto err_out_free_regions
;
4976 sprintf(hw
->irq_name
, DRV_NAME
"@pci:%s", pci_name(pdev
));
4978 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4980 dev_err(&pdev
->dev
, "cannot map device registers\n");
4981 goto err_out_free_hw
;
4984 err
= sky2_init(hw
);
4986 goto err_out_iounmap
;
4988 /* ring for status responses */
4989 hw
->st_size
= hw
->ports
* roundup_pow_of_two(3*RX_MAX_PENDING
+ TX_MAX_PENDING
);
4990 hw
->st_le
= pci_alloc_consistent(pdev
, hw
->st_size
* sizeof(struct sky2_status_le
),
4997 dev_info(&pdev
->dev
, "Yukon-2 %s chip revision %d\n",
4998 sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)), hw
->chip_rev
);
5002 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
5005 goto err_out_free_pci
;
5008 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
5009 err
= sky2_test_msi(hw
);
5011 pci_disable_msi(pdev
);
5012 if (err
!= -EOPNOTSUPP
)
5013 goto err_out_free_netdev
;
5017 err
= register_netdev(dev
);
5019 dev_err(&pdev
->dev
, "cannot register net device\n");
5020 goto err_out_free_netdev
;
5023 netif_carrier_off(dev
);
5025 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
5027 sky2_show_addr(dev
);
5029 if (hw
->ports
> 1) {
5030 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
5033 goto err_out_unregister
;
5036 err
= register_netdev(dev1
);
5038 dev_err(&pdev
->dev
, "cannot register second net device\n");
5039 goto err_out_free_dev1
;
5042 err
= sky2_setup_irq(hw
, hw
->irq_name
);
5044 goto err_out_unregister_dev1
;
5046 sky2_show_addr(dev1
);
5049 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
5050 INIT_WORK(&hw
->restart_work
, sky2_restart
);
5052 pci_set_drvdata(pdev
, hw
);
5053 pdev
->d3_delay
= 150;
5057 err_out_unregister_dev1
:
5058 unregister_netdev(dev1
);
5062 unregister_netdev(dev
);
5063 err_out_free_netdev
:
5064 if (hw
->flags
& SKY2_HW_USE_MSI
)
5065 pci_disable_msi(pdev
);
5068 pci_free_consistent(pdev
, hw
->st_size
* sizeof(struct sky2_status_le
),
5069 hw
->st_le
, hw
->st_dma
);
5071 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
5076 err_out_free_regions
:
5077 pci_release_regions(pdev
);
5079 pci_disable_device(pdev
);
5081 pci_set_drvdata(pdev
, NULL
);
5085 static void sky2_remove(struct pci_dev
*pdev
)
5087 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
5093 del_timer_sync(&hw
->watchdog_timer
);
5094 cancel_work_sync(&hw
->restart_work
);
5096 for (i
= hw
->ports
-1; i
>= 0; --i
)
5097 unregister_netdev(hw
->dev
[i
]);
5099 sky2_write32(hw
, B0_IMSK
, 0);
5100 sky2_read32(hw
, B0_IMSK
);
5104 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
5105 sky2_read8(hw
, B0_CTST
);
5107 if (hw
->ports
> 1) {
5108 napi_disable(&hw
->napi
);
5109 free_irq(pdev
->irq
, hw
);
5112 if (hw
->flags
& SKY2_HW_USE_MSI
)
5113 pci_disable_msi(pdev
);
5114 pci_free_consistent(pdev
, hw
->st_size
* sizeof(struct sky2_status_le
),
5115 hw
->st_le
, hw
->st_dma
);
5116 pci_release_regions(pdev
);
5117 pci_disable_device(pdev
);
5119 for (i
= hw
->ports
-1; i
>= 0; --i
)
5120 free_netdev(hw
->dev
[i
]);
5125 pci_set_drvdata(pdev
, NULL
);
5128 static int sky2_suspend(struct device
*dev
)
5130 struct pci_dev
*pdev
= to_pci_dev(dev
);
5131 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
5137 del_timer_sync(&hw
->watchdog_timer
);
5138 cancel_work_sync(&hw
->restart_work
);
5143 for (i
= 0; i
< hw
->ports
; i
++) {
5144 struct net_device
*dev
= hw
->dev
[i
];
5145 struct sky2_port
*sky2
= netdev_priv(dev
);
5148 sky2_wol_init(sky2
);
5157 #ifdef CONFIG_PM_SLEEP
5158 static int sky2_resume(struct device
*dev
)
5160 struct pci_dev
*pdev
= to_pci_dev(dev
);
5161 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
5167 /* Re-enable all clocks */
5168 err
= pci_write_config_dword(pdev
, PCI_DEV_REG3
, 0);
5170 dev_err(&pdev
->dev
, "PCI write config failed\n");
5182 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
5183 pci_disable_device(pdev
);
5187 static SIMPLE_DEV_PM_OPS(sky2_pm_ops
, sky2_suspend
, sky2_resume
);
5188 #define SKY2_PM_OPS (&sky2_pm_ops)
5192 #define SKY2_PM_OPS NULL
5195 static void sky2_shutdown(struct pci_dev
*pdev
)
5197 sky2_suspend(&pdev
->dev
);
5198 pci_wake_from_d3(pdev
, device_may_wakeup(&pdev
->dev
));
5199 pci_set_power_state(pdev
, PCI_D3hot
);
5202 static struct pci_driver sky2_driver
= {
5204 .id_table
= sky2_id_table
,
5205 .probe
= sky2_probe
,
5206 .remove
= sky2_remove
,
5207 .shutdown
= sky2_shutdown
,
5208 .driver
.pm
= SKY2_PM_OPS
,
5211 static int __init
sky2_init_module(void)
5213 pr_info("driver version " DRV_VERSION
"\n");
5216 return pci_register_driver(&sky2_driver
);
5219 static void __exit
sky2_cleanup_module(void)
5221 pci_unregister_driver(&sky2_driver
);
5222 sky2_debug_cleanup();
5225 module_init(sky2_init_module
);
5226 module_exit(sky2_cleanup_module
);
5228 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5229 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5230 MODULE_LICENSE("GPL");
5231 MODULE_VERSION(DRV_VERSION
);