2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
39 #include <asm/emulated_ops.h>
40 #include <asm/pgtable.h>
41 #include <asm/uaccess.h>
43 #include <asm/machdep.h>
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
62 #include <asm/debug.h>
64 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
65 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
66 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
67 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
68 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
69 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
70 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
71 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
73 EXPORT_SYMBOL(__debugger
);
74 EXPORT_SYMBOL(__debugger_ipi
);
75 EXPORT_SYMBOL(__debugger_bpt
);
76 EXPORT_SYMBOL(__debugger_sstep
);
77 EXPORT_SYMBOL(__debugger_iabr_match
);
78 EXPORT_SYMBOL(__debugger_break_match
);
79 EXPORT_SYMBOL(__debugger_fault_handler
);
82 /* Transactional Memory trap debug */
84 #define TM_DEBUG(x...) printk(KERN_INFO x)
86 #define TM_DEBUG(x...) do { } while(0)
90 * Trap & Exception support
93 #ifdef CONFIG_PMAC_BACKLIGHT
94 static void pmac_backlight_unblank(void)
96 mutex_lock(&pmac_backlight_mutex
);
98 struct backlight_properties
*props
;
100 props
= &pmac_backlight
->props
;
101 props
->brightness
= props
->max_brightness
;
102 props
->power
= FB_BLANK_UNBLANK
;
103 backlight_update_status(pmac_backlight
);
105 mutex_unlock(&pmac_backlight_mutex
);
108 static inline void pmac_backlight_unblank(void) { }
111 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
112 static int die_owner
= -1;
113 static unsigned int die_nest_count
;
114 static int die_counter
;
116 static unsigned __kprobes
long oops_begin(struct pt_regs
*regs
)
126 /* racy, but better than risking deadlock. */
127 raw_local_irq_save(flags
);
128 cpu
= smp_processor_id();
129 if (!arch_spin_trylock(&die_lock
)) {
130 if (cpu
== die_owner
)
131 /* nested oops. should stop eventually */;
133 arch_spin_lock(&die_lock
);
139 if (machine_is(powermac
))
140 pmac_backlight_unblank();
144 static void __kprobes
oops_end(unsigned long flags
, struct pt_regs
*regs
,
149 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
154 /* Nest count reaches zero, release the lock. */
155 arch_spin_unlock(&die_lock
);
156 raw_local_irq_restore(flags
);
158 crash_fadump(regs
, "die oops");
161 * A system reset (0x100) is a request to dump, so we always send
162 * it through the crashdump code.
164 if (kexec_should_crash(current
) || (TRAP(regs
) == 0x100)) {
168 * We aren't the primary crash CPU. We need to send it
169 * to a holding pattern to avoid it ending up in the panic
172 crash_kexec_secondary(regs
);
179 * While our oops output is serialised by a spinlock, output
180 * from panic() called below can race and corrupt it. If we
181 * know we are going to panic, delay for 1 second so we have a
182 * chance to get clean backtraces from all CPUs that are oopsing.
184 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
185 is_global_init(current
)) {
186 mdelay(MSEC_PER_SEC
);
190 panic("Fatal exception in interrupt");
192 panic("Fatal exception");
196 static int __kprobes
__die(const char *str
, struct pt_regs
*regs
, long err
)
198 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
199 #ifdef CONFIG_PREEMPT
203 printk("SMP NR_CPUS=%d ", NR_CPUS
);
205 #ifdef CONFIG_DEBUG_PAGEALLOC
206 printk("DEBUG_PAGEALLOC ");
211 printk("%s\n", ppc_md
.name
? ppc_md
.name
: "");
213 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
222 void die(const char *str
, struct pt_regs
*regs
, long err
)
224 unsigned long flags
= oops_begin(regs
);
226 if (__die(str
, regs
, err
))
228 oops_end(flags
, regs
, err
);
231 void user_single_step_siginfo(struct task_struct
*tsk
,
232 struct pt_regs
*regs
, siginfo_t
*info
)
234 memset(info
, 0, sizeof(*info
));
235 info
->si_signo
= SIGTRAP
;
236 info
->si_code
= TRAP_TRACE
;
237 info
->si_addr
= (void __user
*)regs
->nip
;
240 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
243 const char fmt32
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
244 "at %08lx nip %08lx lr %08lx code %x\n";
245 const char fmt64
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
246 "at %016lx nip %016lx lr %016lx code %x\n";
248 if (!user_mode(regs
)) {
249 die("Exception in kernel mode", regs
, signr
);
253 if (show_unhandled_signals
&& unhandled_signal(current
, signr
)) {
254 printk_ratelimited(regs
->msr
& MSR_64BIT
? fmt64
: fmt32
,
255 current
->comm
, current
->pid
, signr
,
256 addr
, regs
->nip
, regs
->link
, code
);
259 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
262 current
->thread
.trap_nr
= code
;
263 memset(&info
, 0, sizeof(info
));
264 info
.si_signo
= signr
;
266 info
.si_addr
= (void __user
*) addr
;
267 force_sig_info(signr
, &info
, current
);
271 void system_reset_exception(struct pt_regs
*regs
)
273 /* See if any machine dependent calls */
274 if (ppc_md
.system_reset_exception
) {
275 if (ppc_md
.system_reset_exception(regs
))
279 die("System Reset", regs
, SIGABRT
);
281 /* Must die if the interrupt is not recoverable */
282 if (!(regs
->msr
& MSR_RI
))
283 panic("Unrecoverable System Reset");
285 /* What should we do here? We could issue a shutdown or hard reset. */
290 * I/O accesses can cause machine checks on powermacs.
291 * Check if the NIP corresponds to the address of a sync
292 * instruction for which there is an entry in the exception
294 * Note that the 601 only takes a machine check on TEA
295 * (transfer error ack) signal assertion, and does not
296 * set any of the top 16 bits of SRR1.
299 static inline int check_io_access(struct pt_regs
*regs
)
302 unsigned long msr
= regs
->msr
;
303 const struct exception_table_entry
*entry
;
304 unsigned int *nip
= (unsigned int *)regs
->nip
;
306 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
307 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
309 * Check that it's a sync instruction, or somewhere
310 * in the twi; isync; nop sequence that inb/inw/inl uses.
311 * As the address is in the exception table
312 * we should be able to read the instr there.
313 * For the debug message, we look at the preceding
316 if (*nip
== 0x60000000) /* nop */
318 else if (*nip
== 0x4c00012c) /* isync */
320 if (*nip
== 0x7c0004ac || (*nip
>> 26) == 3) {
325 rb
= (*nip
>> 11) & 0x1f;
326 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
327 (*nip
& 0x100)? "OUT to": "IN from",
328 regs
->gpr
[rb
] - _IO_BASE
, nip
);
330 regs
->nip
= entry
->fixup
;
334 #endif /* CONFIG_PPC32 */
338 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
339 /* On 4xx, the reason for the machine check or program exception
341 #define get_reason(regs) ((regs)->dsisr)
342 #ifndef CONFIG_FSL_BOOKE
343 #define get_mc_reason(regs) ((regs)->dsisr)
345 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
347 #define REASON_FP ESR_FP
348 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
349 #define REASON_PRIVILEGED ESR_PPR
350 #define REASON_TRAP ESR_PTR
352 /* single-step stuff */
353 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
354 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
357 /* On non-4xx, the reason for the machine check or program
358 exception is in the MSR. */
359 #define get_reason(regs) ((regs)->msr)
360 #define get_mc_reason(regs) ((regs)->msr)
361 #define REASON_TM 0x200000
362 #define REASON_FP 0x100000
363 #define REASON_ILLEGAL 0x80000
364 #define REASON_PRIVILEGED 0x40000
365 #define REASON_TRAP 0x20000
367 #define single_stepping(regs) ((regs)->msr & MSR_SE)
368 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
371 #if defined(CONFIG_4xx)
372 int machine_check_4xx(struct pt_regs
*regs
)
374 unsigned long reason
= get_mc_reason(regs
);
376 if (reason
& ESR_IMCP
) {
377 printk("Instruction");
378 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
381 printk(" machine check in kernel mode.\n");
386 int machine_check_440A(struct pt_regs
*regs
)
388 unsigned long reason
= get_mc_reason(regs
);
390 printk("Machine check in kernel mode.\n");
391 if (reason
& ESR_IMCP
){
392 printk("Instruction Synchronous Machine Check exception\n");
393 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
396 u32 mcsr
= mfspr(SPRN_MCSR
);
398 printk("Instruction Read PLB Error\n");
400 printk("Data Read PLB Error\n");
402 printk("Data Write PLB Error\n");
403 if (mcsr
& MCSR_TLBP
)
404 printk("TLB Parity Error\n");
405 if (mcsr
& MCSR_ICP
){
406 flush_instruction_cache();
407 printk("I-Cache Parity Error\n");
409 if (mcsr
& MCSR_DCSP
)
410 printk("D-Cache Search Parity Error\n");
411 if (mcsr
& MCSR_DCFP
)
412 printk("D-Cache Flush Parity Error\n");
413 if (mcsr
& MCSR_IMPE
)
414 printk("Machine Check exception is imprecise\n");
417 mtspr(SPRN_MCSR
, mcsr
);
422 int machine_check_47x(struct pt_regs
*regs
)
424 unsigned long reason
= get_mc_reason(regs
);
427 printk(KERN_ERR
"Machine check in kernel mode.\n");
428 if (reason
& ESR_IMCP
) {
430 "Instruction Synchronous Machine Check exception\n");
431 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
434 mcsr
= mfspr(SPRN_MCSR
);
436 printk(KERN_ERR
"Instruction Read PLB Error\n");
438 printk(KERN_ERR
"Data Read PLB Error\n");
440 printk(KERN_ERR
"Data Write PLB Error\n");
441 if (mcsr
& MCSR_TLBP
)
442 printk(KERN_ERR
"TLB Parity Error\n");
443 if (mcsr
& MCSR_ICP
) {
444 flush_instruction_cache();
445 printk(KERN_ERR
"I-Cache Parity Error\n");
447 if (mcsr
& MCSR_DCSP
)
448 printk(KERN_ERR
"D-Cache Search Parity Error\n");
449 if (mcsr
& PPC47x_MCSR_GPR
)
450 printk(KERN_ERR
"GPR Parity Error\n");
451 if (mcsr
& PPC47x_MCSR_FPR
)
452 printk(KERN_ERR
"FPR Parity Error\n");
453 if (mcsr
& PPC47x_MCSR_IPR
)
454 printk(KERN_ERR
"Machine Check exception is imprecise\n");
457 mtspr(SPRN_MCSR
, mcsr
);
461 #elif defined(CONFIG_E500)
462 int machine_check_e500mc(struct pt_regs
*regs
)
464 unsigned long mcsr
= mfspr(SPRN_MCSR
);
465 unsigned long reason
= mcsr
;
468 if (reason
& MCSR_LD
) {
469 recoverable
= fsl_rio_mcheck_exception(regs
);
470 if (recoverable
== 1)
474 printk("Machine check in kernel mode.\n");
475 printk("Caused by (from MCSR=%lx): ", reason
);
477 if (reason
& MCSR_MCP
)
478 printk("Machine Check Signal\n");
480 if (reason
& MCSR_ICPERR
) {
481 printk("Instruction Cache Parity Error\n");
484 * This is recoverable by invalidating the i-cache.
486 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
487 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
491 * This will generally be accompanied by an instruction
492 * fetch error report -- only treat MCSR_IF as fatal
493 * if it wasn't due to an L1 parity error.
498 if (reason
& MCSR_DCPERR_MC
) {
499 printk("Data Cache Parity Error\n");
502 * In write shadow mode we auto-recover from the error, but it
503 * may still get logged and cause a machine check. We should
504 * only treat the non-write shadow case as non-recoverable.
506 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
510 if (reason
& MCSR_L2MMU_MHIT
) {
511 printk("Hit on multiple TLB entries\n");
515 if (reason
& MCSR_NMI
)
516 printk("Non-maskable interrupt\n");
518 if (reason
& MCSR_IF
) {
519 printk("Instruction Fetch Error Report\n");
523 if (reason
& MCSR_LD
) {
524 printk("Load Error Report\n");
528 if (reason
& MCSR_ST
) {
529 printk("Store Error Report\n");
533 if (reason
& MCSR_LDG
) {
534 printk("Guarded Load Error Report\n");
538 if (reason
& MCSR_TLBSYNC
)
539 printk("Simultaneous tlbsync operations\n");
541 if (reason
& MCSR_BSL2_ERR
) {
542 printk("Level 2 Cache Error\n");
546 if (reason
& MCSR_MAV
) {
549 addr
= mfspr(SPRN_MCAR
);
550 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
552 printk("Machine Check %s Address: %#llx\n",
553 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
557 mtspr(SPRN_MCSR
, mcsr
);
558 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
561 int machine_check_e500(struct pt_regs
*regs
)
563 unsigned long reason
= get_mc_reason(regs
);
565 if (reason
& MCSR_BUS_RBERR
) {
566 if (fsl_rio_mcheck_exception(regs
))
570 printk("Machine check in kernel mode.\n");
571 printk("Caused by (from MCSR=%lx): ", reason
);
573 if (reason
& MCSR_MCP
)
574 printk("Machine Check Signal\n");
575 if (reason
& MCSR_ICPERR
)
576 printk("Instruction Cache Parity Error\n");
577 if (reason
& MCSR_DCP_PERR
)
578 printk("Data Cache Push Parity Error\n");
579 if (reason
& MCSR_DCPERR
)
580 printk("Data Cache Parity Error\n");
581 if (reason
& MCSR_BUS_IAERR
)
582 printk("Bus - Instruction Address Error\n");
583 if (reason
& MCSR_BUS_RAERR
)
584 printk("Bus - Read Address Error\n");
585 if (reason
& MCSR_BUS_WAERR
)
586 printk("Bus - Write Address Error\n");
587 if (reason
& MCSR_BUS_IBERR
)
588 printk("Bus - Instruction Data Error\n");
589 if (reason
& MCSR_BUS_RBERR
)
590 printk("Bus - Read Data Bus Error\n");
591 if (reason
& MCSR_BUS_WBERR
)
592 printk("Bus - Read Data Bus Error\n");
593 if (reason
& MCSR_BUS_IPERR
)
594 printk("Bus - Instruction Parity Error\n");
595 if (reason
& MCSR_BUS_RPERR
)
596 printk("Bus - Read Parity Error\n");
601 int machine_check_generic(struct pt_regs
*regs
)
605 #elif defined(CONFIG_E200)
606 int machine_check_e200(struct pt_regs
*regs
)
608 unsigned long reason
= get_mc_reason(regs
);
610 printk("Machine check in kernel mode.\n");
611 printk("Caused by (from MCSR=%lx): ", reason
);
613 if (reason
& MCSR_MCP
)
614 printk("Machine Check Signal\n");
615 if (reason
& MCSR_CP_PERR
)
616 printk("Cache Push Parity Error\n");
617 if (reason
& MCSR_CPERR
)
618 printk("Cache Parity Error\n");
619 if (reason
& MCSR_EXCP_ERR
)
620 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
621 if (reason
& MCSR_BUS_IRERR
)
622 printk("Bus - Read Bus Error on instruction fetch\n");
623 if (reason
& MCSR_BUS_DRERR
)
624 printk("Bus - Read Bus Error on data load\n");
625 if (reason
& MCSR_BUS_WRERR
)
626 printk("Bus - Write Bus Error on buffered store or cache line push\n");
631 int machine_check_generic(struct pt_regs
*regs
)
633 unsigned long reason
= get_mc_reason(regs
);
635 printk("Machine check in kernel mode.\n");
636 printk("Caused by (from SRR1=%lx): ", reason
);
637 switch (reason
& 0x601F0000) {
639 printk("Machine check signal\n");
641 case 0: /* for 601 */
643 case 0x140000: /* 7450 MSS error and TEA */
644 printk("Transfer error ack signal\n");
647 printk("Data parity error signal\n");
650 printk("Address parity error signal\n");
653 printk("L1 Data Cache error\n");
656 printk("L1 Instruction Cache error\n");
659 printk("L2 data cache parity error\n");
662 printk("Unknown values in msr\n");
666 #endif /* everything else */
668 void machine_check_exception(struct pt_regs
*regs
)
672 __get_cpu_var(irq_stat
).mce_exceptions
++;
674 /* See if any machine dependent calls. In theory, we would want
675 * to call the CPU first, and call the ppc_md. one if the CPU
676 * one returns a positive number. However there is existing code
677 * that assumes the board gets a first chance, so let's keep it
678 * that way for now and fix things later. --BenH.
680 if (ppc_md
.machine_check_exception
)
681 recover
= ppc_md
.machine_check_exception(regs
);
682 else if (cur_cpu_spec
->machine_check
)
683 recover
= cur_cpu_spec
->machine_check(regs
);
688 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
689 /* the qspan pci read routines can cause machine checks -- Cort
691 * yuck !!! that totally needs to go away ! There are better ways
692 * to deal with that than having a wart in the mcheck handler.
695 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
699 if (debugger_fault_handler(regs
))
702 if (check_io_access(regs
))
705 die("Machine check", regs
, SIGBUS
);
707 /* Must die if the interrupt is not recoverable */
708 if (!(regs
->msr
& MSR_RI
))
709 panic("Unrecoverable Machine check");
712 void SMIException(struct pt_regs
*regs
)
714 die("System Management Interrupt", regs
, SIGABRT
);
717 void unknown_exception(struct pt_regs
*regs
)
719 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
720 regs
->nip
, regs
->msr
, regs
->trap
);
722 _exception(SIGTRAP
, regs
, 0, 0);
725 void instruction_breakpoint_exception(struct pt_regs
*regs
)
727 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
728 5, SIGTRAP
) == NOTIFY_STOP
)
730 if (debugger_iabr_match(regs
))
732 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
735 void RunModeException(struct pt_regs
*regs
)
737 _exception(SIGTRAP
, regs
, 0, 0);
740 void __kprobes
single_step_exception(struct pt_regs
*regs
)
742 clear_single_step(regs
);
744 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
745 5, SIGTRAP
) == NOTIFY_STOP
)
747 if (debugger_sstep(regs
))
750 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
754 * After we have successfully emulated an instruction, we have to
755 * check if the instruction was being single-stepped, and if so,
756 * pretend we got a single-step exception. This was pointed out
757 * by Kumar Gala. -- paulus
759 static void emulate_single_step(struct pt_regs
*regs
)
761 if (single_stepping(regs
))
762 single_step_exception(regs
);
765 static inline int __parse_fpscr(unsigned long fpscr
)
769 /* Invalid operation */
770 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
774 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
778 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
782 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
786 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
792 static void parse_fpe(struct pt_regs
*regs
)
796 flush_fp_to_thread(current
);
798 code
= __parse_fpscr(current
->thread
.fpscr
.val
);
800 _exception(SIGFPE
, regs
, code
, regs
->nip
);
804 * Illegal instruction emulation support. Originally written to
805 * provide the PVR to user applications using the mfspr rd, PVR.
806 * Return non-zero if we can't emulate, or -EFAULT if the associated
807 * memory access caused an access fault. Return zero on success.
809 * There are a couple of ways to do this, either "decode" the instruction
810 * or directly match lots of bits. In this case, matching lots of
811 * bits is faster and easier.
814 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
816 u8 rT
= (instword
>> 21) & 0x1f;
817 u8 rA
= (instword
>> 16) & 0x1f;
818 u8 NB_RB
= (instword
>> 11) & 0x1f;
823 /* Early out if we are an invalid form of lswx */
824 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
825 if ((rT
== rA
) || (rT
== NB_RB
))
828 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
830 switch (instword
& PPC_INST_STRING_MASK
) {
834 num_bytes
= regs
->xer
& 0x7f;
838 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
844 while (num_bytes
!= 0)
847 u32 shift
= 8 * (3 - (pos
& 0x3));
849 switch ((instword
& PPC_INST_STRING_MASK
)) {
852 if (get_user(val
, (u8 __user
*)EA
))
854 /* first time updating this reg,
858 regs
->gpr
[rT
] |= val
<< shift
;
862 val
= regs
->gpr
[rT
] >> shift
;
863 if (put_user(val
, (u8 __user
*)EA
))
867 /* move EA to next address */
871 /* manage our position within the register */
882 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
887 ra
= (instword
>> 16) & 0x1f;
888 rs
= (instword
>> 21) & 0x1f;
891 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
892 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
893 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
899 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
901 u8 rT
= (instword
>> 21) & 0x1f;
902 u8 rA
= (instword
>> 16) & 0x1f;
903 u8 rB
= (instword
>> 11) & 0x1f;
904 u8 BC
= (instword
>> 6) & 0x1f;
908 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
909 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
911 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
916 static int emulate_instruction(struct pt_regs
*regs
)
921 if (!user_mode(regs
) || (regs
->msr
& MSR_LE
))
923 CHECK_FULL_REGS(regs
);
925 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
928 /* Emulate the mfspr rD, PVR. */
929 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
930 PPC_WARN_EMULATED(mfpvr
, regs
);
931 rd
= (instword
>> 21) & 0x1f;
932 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
936 /* Emulating the dcba insn is just a no-op. */
937 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
938 PPC_WARN_EMULATED(dcba
, regs
);
942 /* Emulate the mcrxr insn. */
943 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
944 int shift
= (instword
>> 21) & 0x1c;
945 unsigned long msk
= 0xf0000000UL
>> shift
;
947 PPC_WARN_EMULATED(mcrxr
, regs
);
948 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
949 regs
->xer
&= ~0xf0000000UL
;
953 /* Emulate load/store string insn. */
954 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
955 PPC_WARN_EMULATED(string
, regs
);
956 return emulate_string_inst(regs
, instword
);
959 /* Emulate the popcntb (Population Count Bytes) instruction. */
960 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
961 PPC_WARN_EMULATED(popcntb
, regs
);
962 return emulate_popcntb_inst(regs
, instword
);
965 /* Emulate isel (Integer Select) instruction */
966 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
967 PPC_WARN_EMULATED(isel
, regs
);
968 return emulate_isel(regs
, instword
);
972 /* Emulate the mfspr rD, DSCR. */
973 if (((instword
& PPC_INST_MFSPR_DSCR_MASK
) == PPC_INST_MFSPR_DSCR
) &&
974 cpu_has_feature(CPU_FTR_DSCR
)) {
975 PPC_WARN_EMULATED(mfdscr
, regs
);
976 rd
= (instword
>> 21) & 0x1f;
977 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
980 /* Emulate the mtspr DSCR, rD. */
981 if (((instword
& PPC_INST_MTSPR_DSCR_MASK
) == PPC_INST_MTSPR_DSCR
) &&
982 cpu_has_feature(CPU_FTR_DSCR
)) {
983 PPC_WARN_EMULATED(mtdscr
, regs
);
984 rd
= (instword
>> 21) & 0x1f;
985 current
->thread
.dscr
= regs
->gpr
[rd
];
986 current
->thread
.dscr_inherit
= 1;
987 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
995 int is_valid_bugaddr(unsigned long addr
)
997 return is_kernel_addr(addr
);
1000 void __kprobes
program_check_exception(struct pt_regs
*regs
)
1002 unsigned int reason
= get_reason(regs
);
1003 extern int do_mathemu(struct pt_regs
*regs
);
1005 /* We can now get here via a FP Unavailable exception if the core
1006 * has no FPU, in that case the reason flags will be 0 */
1008 if (reason
& REASON_FP
) {
1009 /* IEEE FP exception */
1013 if (reason
& REASON_TRAP
) {
1014 /* Debugger is first in line to stop recursive faults in
1015 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1016 if (debugger_bpt(regs
))
1019 /* trap exception */
1020 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1024 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1025 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1029 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1032 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1033 if (reason
& REASON_TM
) {
1034 /* This is a TM "Bad Thing Exception" program check.
1036 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1037 * transition in TM states.
1038 * - A trechkpt is attempted when transactional.
1039 * - A treclaim is attempted when non transactional.
1040 * - A tend is illegally attempted.
1041 * - writing a TM SPR when transactional.
1043 if (!user_mode(regs
) &&
1044 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1048 /* If usermode caused this, it's done something illegal and
1049 * gets a SIGILL slap on the wrist. We call it an illegal
1050 * operand to distinguish from the instruction just being bad
1051 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1052 * illegal /placement/ of a valid instruction.
1054 if (user_mode(regs
)) {
1055 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1058 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1059 "at %lx (msr 0x%x)\n", regs
->nip
, reason
);
1060 die("Unrecoverable exception", regs
, SIGABRT
);
1065 /* We restore the interrupt state now */
1066 if (!arch_irq_disabled_regs(regs
))
1069 #ifdef CONFIG_MATH_EMULATION
1070 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1071 * but there seems to be a hardware bug on the 405GP (RevD)
1072 * that means ESR is sometimes set incorrectly - either to
1073 * ESR_DST (!?) or 0. In the process of chasing this with the
1074 * hardware people - not sure if it can happen on any illegal
1075 * instruction or only on FP instructions, whether there is a
1076 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
1077 switch (do_mathemu(regs
)) {
1079 emulate_single_step(regs
);
1083 code
= __parse_fpscr(current
->thread
.fpscr
.val
);
1084 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1088 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1091 /* fall through on any other errors */
1092 #endif /* CONFIG_MATH_EMULATION */
1094 /* Try to emulate it if we should. */
1095 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1096 switch (emulate_instruction(regs
)) {
1099 emulate_single_step(regs
);
1102 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1107 if (reason
& REASON_PRIVILEGED
)
1108 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1110 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1113 void alignment_exception(struct pt_regs
*regs
)
1115 int sig
, code
, fixed
= 0;
1117 /* We restore the interrupt state now */
1118 if (!arch_irq_disabled_regs(regs
))
1121 /* we don't implement logging of alignment exceptions */
1122 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1123 fixed
= fix_alignment(regs
);
1126 regs
->nip
+= 4; /* skip over emulated instruction */
1127 emulate_single_step(regs
);
1131 /* Operand address was bad */
1132 if (fixed
== -EFAULT
) {
1139 if (user_mode(regs
))
1140 _exception(sig
, regs
, code
, regs
->dar
);
1142 bad_page_fault(regs
, regs
->dar
, sig
);
1145 void StackOverflow(struct pt_regs
*regs
)
1147 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1148 current
, regs
->gpr
[1]);
1151 panic("kernel stack overflow");
1154 void nonrecoverable_exception(struct pt_regs
*regs
)
1156 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
1157 regs
->nip
, regs
->msr
);
1159 die("nonrecoverable exception", regs
, SIGKILL
);
1162 void trace_syscall(struct pt_regs
*regs
)
1164 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1165 current
, task_pid_nr(current
), regs
->nip
, regs
->link
, regs
->gpr
[0],
1166 regs
->ccr
&0x10000000?"Error=":"", regs
->gpr
[3], print_tainted());
1169 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1171 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1172 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1173 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1176 void altivec_unavailable_exception(struct pt_regs
*regs
)
1178 if (user_mode(regs
)) {
1179 /* A user program has executed an altivec instruction,
1180 but this kernel doesn't support altivec. */
1181 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1185 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1186 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1187 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1190 void vsx_unavailable_exception(struct pt_regs
*regs
)
1192 if (user_mode(regs
)) {
1193 /* A user program has executed an vsx instruction,
1194 but this kernel doesn't support vsx. */
1195 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1199 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1200 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1201 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1204 void tm_unavailable_exception(struct pt_regs
*regs
)
1206 /* We restore the interrupt state now */
1207 if (!arch_irq_disabled_regs(regs
))
1210 /* Currently we never expect a TMU exception. Catch
1211 * this and kill the process!
1213 printk(KERN_EMERG
"Unexpected TM unavailable exception at %lx "
1215 regs
->nip
, regs
->msr
);
1217 if (user_mode(regs
)) {
1218 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1222 die("Unexpected TM unavailable exception", regs
, SIGABRT
);
1225 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1227 extern void do_load_up_fpu(struct pt_regs
*regs
);
1229 void fp_unavailable_tm(struct pt_regs
*regs
)
1231 /* Note: This does not handle any kind of FP laziness. */
1233 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1234 regs
->nip
, regs
->msr
);
1237 /* We can only have got here if the task started using FP after
1238 * beginning the transaction. So, the transactional regs are just a
1239 * copy of the checkpointed ones. But, we still need to recheckpoint
1240 * as we're enabling FP for the process; it will return, abort the
1241 * transaction, and probably retry but now with FP enabled. So the
1242 * checkpointed FP registers need to be loaded.
1244 tm_reclaim(¤t
->thread
, current
->thread
.regs
->msr
,
1246 /* Reclaim didn't save out any FPRs to transact_fprs. */
1248 /* Enable FP for the task: */
1249 regs
->msr
|= (MSR_FP
| current
->thread
.fpexc_mode
);
1251 /* This loads and recheckpoints the FP registers from
1252 * thread.fpr[]. They will remain in registers after the
1253 * checkpoint so we don't need to reload them after.
1255 tm_recheckpoint(¤t
->thread
, regs
->msr
);
1258 #ifdef CONFIG_ALTIVEC
1259 extern void do_load_up_altivec(struct pt_regs
*regs
);
1261 void altivec_unavailable_tm(struct pt_regs
*regs
)
1263 /* See the comments in fp_unavailable_tm(). This function operates
1267 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1269 regs
->nip
, regs
->msr
);
1271 tm_reclaim(¤t
->thread
, current
->thread
.regs
->msr
,
1273 regs
->msr
|= MSR_VEC
;
1274 tm_recheckpoint(¤t
->thread
, regs
->msr
);
1275 current
->thread
.used_vr
= 1;
1280 void vsx_unavailable_tm(struct pt_regs
*regs
)
1282 /* See the comments in fp_unavailable_tm(). This works similarly,
1283 * though we're loading both FP and VEC registers in here.
1285 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1286 * regs. Either way, set MSR_VSX.
1289 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1291 regs
->nip
, regs
->msr
);
1294 /* This reclaims FP and/or VR regs if they're already enabled */
1295 tm_reclaim(¤t
->thread
, current
->thread
.regs
->msr
,
1298 regs
->msr
|= MSR_VEC
| MSR_FP
| current
->thread
.fpexc_mode
|
1300 /* This loads & recheckpoints FP and VRs. */
1301 tm_recheckpoint(¤t
->thread
, regs
->msr
);
1302 current
->thread
.used_vsr
= 1;
1305 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1307 void performance_monitor_exception(struct pt_regs
*regs
)
1309 __get_cpu_var(irq_stat
).pmu_irqs
++;
1315 void SoftwareEmulation(struct pt_regs
*regs
)
1317 extern int do_mathemu(struct pt_regs
*);
1318 extern int Soft_emulate_8xx(struct pt_regs
*);
1319 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1323 CHECK_FULL_REGS(regs
);
1325 if (!user_mode(regs
)) {
1327 die("Kernel Mode Software FPU Emulation", regs
, SIGFPE
);
1330 #ifdef CONFIG_MATH_EMULATION
1331 errcode
= do_mathemu(regs
);
1333 PPC_WARN_EMULATED(math
, regs
);
1337 emulate_single_step(regs
);
1341 code
= __parse_fpscr(current
->thread
.fpscr
.val
);
1342 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1346 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1349 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1353 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1354 errcode
= Soft_emulate_8xx(regs
);
1356 PPC_WARN_EMULATED(8xx
, regs
);
1360 emulate_single_step(regs
);
1363 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1366 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1370 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1373 #endif /* CONFIG_8xx */
1375 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1376 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1380 * Determine the cause of the debug event, clear the
1381 * event flags and send a trap to the handler. Torez
1383 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1384 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1385 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1386 current
->thread
.dbcr2
&= ~DBCR2_DAC12MODE
;
1388 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
, TRAP_HWBKPT
,
1391 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1392 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1393 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
, TRAP_HWBKPT
,
1396 } else if (debug_status
& DBSR_IAC1
) {
1397 current
->thread
.dbcr0
&= ~DBCR0_IAC1
;
1398 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1399 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
, TRAP_HWBKPT
,
1402 } else if (debug_status
& DBSR_IAC2
) {
1403 current
->thread
.dbcr0
&= ~DBCR0_IAC2
;
1404 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
, TRAP_HWBKPT
,
1407 } else if (debug_status
& DBSR_IAC3
) {
1408 current
->thread
.dbcr0
&= ~DBCR0_IAC3
;
1409 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1410 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
, TRAP_HWBKPT
,
1413 } else if (debug_status
& DBSR_IAC4
) {
1414 current
->thread
.dbcr0
&= ~DBCR0_IAC4
;
1415 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
, TRAP_HWBKPT
,
1420 * At the point this routine was called, the MSR(DE) was turned off.
1421 * Check all other debug flags and see if that bit needs to be turned
1424 if (DBCR_ACTIVE_EVENTS(current
->thread
.dbcr0
, current
->thread
.dbcr1
))
1425 regs
->msr
|= MSR_DE
;
1427 /* Make sure the IDM flag is off */
1428 current
->thread
.dbcr0
&= ~DBCR0_IDM
;
1431 mtspr(SPRN_DBCR0
, current
->thread
.dbcr0
);
1434 void __kprobes
DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1436 current
->thread
.dbsr
= debug_status
;
1438 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1439 * on server, it stops on the target of the branch. In order to simulate
1440 * the server behaviour, we thus restart right away with a single step
1441 * instead of stopping here when hitting a BT
1443 if (debug_status
& DBSR_BT
) {
1444 regs
->msr
&= ~MSR_DE
;
1447 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1448 /* Clear the BT event */
1449 mtspr(SPRN_DBSR
, DBSR_BT
);
1451 /* Do the single step trick only when coming from userspace */
1452 if (user_mode(regs
)) {
1453 current
->thread
.dbcr0
&= ~DBCR0_BT
;
1454 current
->thread
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1455 regs
->msr
|= MSR_DE
;
1459 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1460 5, SIGTRAP
) == NOTIFY_STOP
) {
1463 if (debugger_sstep(regs
))
1465 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1466 regs
->msr
&= ~MSR_DE
;
1468 /* Disable instruction completion */
1469 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1470 /* Clear the instruction completion event */
1471 mtspr(SPRN_DBSR
, DBSR_IC
);
1473 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1474 5, SIGTRAP
) == NOTIFY_STOP
) {
1478 if (debugger_sstep(regs
))
1481 if (user_mode(regs
)) {
1482 current
->thread
.dbcr0
&= ~DBCR0_IC
;
1483 if (DBCR_ACTIVE_EVENTS(current
->thread
.dbcr0
,
1484 current
->thread
.dbcr1
))
1485 regs
->msr
|= MSR_DE
;
1487 /* Make sure the IDM bit is off */
1488 current
->thread
.dbcr0
&= ~DBCR0_IDM
;
1491 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1493 handle_debug(regs
, debug_status
);
1495 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1497 #if !defined(CONFIG_TAU_INT)
1498 void TAUException(struct pt_regs
*regs
)
1500 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1501 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1503 #endif /* CONFIG_INT_TAU */
1505 #ifdef CONFIG_ALTIVEC
1506 void altivec_assist_exception(struct pt_regs
*regs
)
1510 if (!user_mode(regs
)) {
1511 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1512 " at %lx\n", regs
->nip
);
1513 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1516 flush_altivec_to_thread(current
);
1518 PPC_WARN_EMULATED(altivec
, regs
);
1519 err
= emulate_altivec(regs
);
1521 regs
->nip
+= 4; /* skip emulated instruction */
1522 emulate_single_step(regs
);
1526 if (err
== -EFAULT
) {
1527 /* got an error reading the instruction */
1528 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1530 /* didn't recognize the instruction */
1531 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1532 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1533 "in %s at %lx\n", current
->comm
, regs
->nip
);
1534 current
->thread
.vscr
.u
[3] |= 0x10000;
1537 #endif /* CONFIG_ALTIVEC */
1540 void vsx_assist_exception(struct pt_regs
*regs
)
1542 if (!user_mode(regs
)) {
1543 printk(KERN_EMERG
"VSX assist exception in kernel mode"
1544 " at %lx\n", regs
->nip
);
1545 die("Kernel VSX assist exception", regs
, SIGILL
);
1548 flush_vsx_to_thread(current
);
1549 printk(KERN_INFO
"VSX assist not supported at %lx\n", regs
->nip
);
1550 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1552 #endif /* CONFIG_VSX */
1554 #ifdef CONFIG_FSL_BOOKE
1555 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1556 unsigned long error_code
)
1558 /* We treat cache locking instructions from the user
1559 * as priv ops, in the future we could try to do
1562 if (error_code
& (ESR_DLK
|ESR_ILK
))
1563 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1566 #endif /* CONFIG_FSL_BOOKE */
1569 void SPEFloatingPointException(struct pt_regs
*regs
)
1571 extern int do_spe_mathemu(struct pt_regs
*regs
);
1572 unsigned long spefscr
;
1577 flush_spe_to_thread(current
);
1579 spefscr
= current
->thread
.spefscr
;
1580 fpexc_mode
= current
->thread
.fpexc_mode
;
1582 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
1585 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
1588 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
1590 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
1593 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
1596 err
= do_spe_mathemu(regs
);
1598 regs
->nip
+= 4; /* skip emulated instruction */
1599 emulate_single_step(regs
);
1603 if (err
== -EFAULT
) {
1604 /* got an error reading the instruction */
1605 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1606 } else if (err
== -EINVAL
) {
1607 /* didn't recognize the instruction */
1608 printk(KERN_ERR
"unrecognized spe instruction "
1609 "in %s at %lx\n", current
->comm
, regs
->nip
);
1611 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1617 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
1619 extern int speround_handler(struct pt_regs
*regs
);
1623 if (regs
->msr
& MSR_SPE
)
1624 giveup_spe(current
);
1628 err
= speround_handler(regs
);
1630 regs
->nip
+= 4; /* skip emulated instruction */
1631 emulate_single_step(regs
);
1635 if (err
== -EFAULT
) {
1636 /* got an error reading the instruction */
1637 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1638 } else if (err
== -EINVAL
) {
1639 /* didn't recognize the instruction */
1640 printk(KERN_ERR
"unrecognized spe instruction "
1641 "in %s at %lx\n", current
->comm
, regs
->nip
);
1643 _exception(SIGFPE
, regs
, 0, regs
->nip
);
1650 * We enter here if we get an unrecoverable exception, that is, one
1651 * that happened at a point where the RI (recoverable interrupt) bit
1652 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1653 * we therefore lost state by taking this exception.
1655 void unrecoverable_exception(struct pt_regs
*regs
)
1657 printk(KERN_EMERG
"Unrecoverable exception %lx at %lx\n",
1658 regs
->trap
, regs
->nip
);
1659 die("Unrecoverable exception", regs
, SIGABRT
);
1662 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1664 * Default handler for a Watchdog exception,
1665 * spins until a reboot occurs
1667 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
1669 /* Generic WatchdogHandler, implement your own */
1670 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
1674 void WatchdogException(struct pt_regs
*regs
)
1676 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
1677 WatchdogHandler(regs
);
1682 * We enter here if we discover during exception entry that we are
1683 * running in supervisor mode with a userspace value in the stack pointer.
1685 void kernel_bad_stack(struct pt_regs
*regs
)
1687 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
1688 regs
->gpr
[1], regs
->nip
);
1689 die("Bad kernel stack pointer", regs
, SIGABRT
);
1692 void __init
trap_init(void)
1697 #ifdef CONFIG_PPC_EMULATED_STATS
1699 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1701 struct ppc_emulated ppc_emulated
= {
1702 #ifdef CONFIG_ALTIVEC
1703 WARN_EMULATED_SETUP(altivec
),
1705 WARN_EMULATED_SETUP(dcba
),
1706 WARN_EMULATED_SETUP(dcbz
),
1707 WARN_EMULATED_SETUP(fp_pair
),
1708 WARN_EMULATED_SETUP(isel
),
1709 WARN_EMULATED_SETUP(mcrxr
),
1710 WARN_EMULATED_SETUP(mfpvr
),
1711 WARN_EMULATED_SETUP(multiple
),
1712 WARN_EMULATED_SETUP(popcntb
),
1713 WARN_EMULATED_SETUP(spe
),
1714 WARN_EMULATED_SETUP(string
),
1715 WARN_EMULATED_SETUP(unaligned
),
1716 #ifdef CONFIG_MATH_EMULATION
1717 WARN_EMULATED_SETUP(math
),
1718 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1719 WARN_EMULATED_SETUP(8xx
),
1722 WARN_EMULATED_SETUP(vsx
),
1725 WARN_EMULATED_SETUP(mfdscr
),
1726 WARN_EMULATED_SETUP(mtdscr
),
1730 u32 ppc_warn_emulated
;
1732 void ppc_warn_emulated_print(const char *type
)
1734 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
1738 static int __init
ppc_warn_emulated_init(void)
1740 struct dentry
*dir
, *d
;
1742 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
1744 if (!powerpc_debugfs_root
)
1747 dir
= debugfs_create_dir("emulated_instructions",
1748 powerpc_debugfs_root
);
1752 d
= debugfs_create_u32("do_warn", S_IRUGO
| S_IWUSR
, dir
,
1753 &ppc_warn_emulated
);
1757 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
1758 d
= debugfs_create_u32(entries
[i
].name
, S_IRUGO
| S_IWUSR
, dir
,
1759 (u32
*)&entries
[i
].val
.counter
);
1767 debugfs_remove_recursive(dir
);
1771 device_initcall(ppc_warn_emulated_init
);
1773 #endif /* CONFIG_PPC_EMULATED_STATS */