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ASoC: TWL4030: Helper to check chip default registers
[linux-2.6/cjktty.git] / sound / soc / codecs / twl4030.c
blob30b7bbaf6aed5bf6c67f3cf1458110893dff31b3
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x00, /* REG_CODEC_MODE (0x1) */
46 0x00, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x00, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0f, /* REG_ATXL1PGA (0xA) */
55 0x0f, /* REG_ATXR1PGA (0xB) */
56 0x0f, /* REG_AVTXL2PGA (0xC) */
57 0x0f, /* REG_AVTXR2PGA (0xD) */
58 0x00, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x3f, /* REG_ARXR1PGA (0x10) */
61 0x3f, /* REG_ARXL1PGA (0x11) */
62 0x3f, /* REG_ARXR2PGA (0x12) */
63 0x3f, /* REG_ARXL2PGA (0x13) */
64 0x25, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x00, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x55, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x00, /* REG_HS_SEL (0x22) */
79 0x00, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x05, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x13, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x79, /* REG_DTMF_TONOFF (0x35) */
98 0x11, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x06, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x32, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
119 };
120
121 /* codec private data */
122 struct twl4030_priv {
123 struct snd_soc_codec codec;
124
125 unsigned int codec_powered;
126
127 /* reference counts of AIF/APLL users */
128 unsigned int apll_enabled;
129
130 struct snd_pcm_substream *master_substream;
131 struct snd_pcm_substream *slave_substream;
132
133 unsigned int configured;
134 unsigned int rate;
135 unsigned int sample_bits;
136 unsigned int channels;
137
138 unsigned int sysclk;
139
140 /* Output (with associated amp) states */
141 u8 hsl_enabled, hsr_enabled;
142 u8 earpiece_enabled;
143 u8 predrivel_enabled, predriver_enabled;
144 u8 carkitl_enabled, carkitr_enabled;
145 };
146
147 /*
148 * read twl4030 register cache
149 */
150 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
151 unsigned int reg)
152 {
153 u8 *cache = codec->reg_cache;
154
155 if (reg >= TWL4030_CACHEREGNUM)
156 return -EIO;
157
158 return cache[reg];
159 }
160
161 /*
162 * write twl4030 register cache
163 */
164 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
165 u8 reg, u8 value)
166 {
167 u8 *cache = codec->reg_cache;
168
169 if (reg >= TWL4030_CACHEREGNUM)
170 return;
171 cache[reg] = value;
172 }
173
174 /*
175 * write to the twl4030 register space
176 */
177 static int twl4030_write(struct snd_soc_codec *codec,
178 unsigned int reg, unsigned int value)
179 {
180 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
181 int write_to_reg = 0;
182
183 twl4030_write_reg_cache(codec, reg, value);
184 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
185 /* Decide if the given register can be written */
186 switch (reg) {
187 case TWL4030_REG_EAR_CTL:
188 if (twl4030->earpiece_enabled)
189 write_to_reg = 1;
190 break;
191 case TWL4030_REG_PREDL_CTL:
192 if (twl4030->predrivel_enabled)
193 write_to_reg = 1;
194 break;
195 case TWL4030_REG_PREDR_CTL:
196 if (twl4030->predriver_enabled)
197 write_to_reg = 1;
198 break;
199 case TWL4030_REG_PRECKL_CTL:
200 if (twl4030->carkitl_enabled)
201 write_to_reg = 1;
202 break;
203 case TWL4030_REG_PRECKR_CTL:
204 if (twl4030->carkitr_enabled)
205 write_to_reg = 1;
206 break;
207 case TWL4030_REG_HS_GAIN_SET:
208 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
209 write_to_reg = 1;
210 break;
211 default:
212 /* All other register can be written */
213 write_to_reg = 1;
214 break;
215 }
216 if (write_to_reg)
217 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
218 value, reg);
219 }
220 return 0;
221 }
222
223 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
224 {
225 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
226 int mode;
227
228 if (enable == twl4030->codec_powered)
229 return;
230
231 if (enable)
232 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
233 else
234 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
235
236 if (mode >= 0) {
237 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
238 twl4030->codec_powered = enable;
239 }
240
241 /* REVISIT: this delay is present in TI sample drivers */
242 /* but there seems to be no TRM requirement for it */
243 udelay(10);
244 }
245
246 static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
247 {
248 int i, difference = 0;
249 u8 val;
250
251 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
252 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
253 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
254 if (val != twl4030_reg[i]) {
255 difference++;
256 dev_dbg(codec->dev,
257 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
258 i, val, twl4030_reg[i]);
259 }
260 }
261 dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
262 difference, difference ? "Not OK" : "OK");
263 }
264
265 static void twl4030_init_chip(struct platform_device *pdev)
266 {
267 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
268 struct twl4030_setup_data *setup = socdev->codec_data;
269 struct snd_soc_codec *codec = socdev->card->codec;
270 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
271 u8 reg, byte;
272 int i = 0;
273
274 /* Check defaults, if instructed before anything else */
275 if (setup && setup->check_defaults)
276 twl4030_check_defaults(codec);
277
278 /* Refresh APLL_CTL register from HW */
279 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
280 TWL4030_REG_APLL_CTL);
281 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
282
283 /* anti-pop when changing analog gain */
284 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
285 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
286 reg | TWL4030_SMOOTH_ANAVOL_EN);
287
288 twl4030_write(codec, TWL4030_REG_OPTION,
289 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
290 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
291
292 /* Machine dependent setup */
293 if (!setup)
294 return;
295
296 /* Configuration for headset ramp delay from setup data */
297 if (setup->sysclk != twl4030->sysclk)
298 dev_warn(codec->dev,
299 "Mismatch in APLL mclk: %u (configured: %u)\n",
300 setup->sysclk, twl4030->sysclk);
301
302 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
303 reg &= ~TWL4030_RAMP_DELAY;
304 reg |= (setup->ramp_delay_value << 2);
305 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
306
307 /* initiate offset cancellation */
308 twl4030_codec_enable(codec, 1);
309
310 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
311 reg &= ~TWL4030_OFFSET_CNCL_SEL;
312 reg |= setup->offset_cncl_path;
313 twl4030_write(codec, TWL4030_REG_ANAMICL,
314 reg | TWL4030_CNCL_OFFSET_START);
315
316 /* wait for offset cancellation to complete */
317 do {
318 /* this takes a little while, so don't slam i2c */
319 udelay(2000);
320 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
321 TWL4030_REG_ANAMICL);
322 } while ((i++ < 100) &&
323 ((byte & TWL4030_CNCL_OFFSET_START) ==
324 TWL4030_CNCL_OFFSET_START));
325
326 /* Make sure that the reg_cache has the same value as the HW */
327 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
328
329 twl4030_codec_enable(codec, 0);
330 }
331
332 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
333 {
334 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
335 int status = -1;
336
337 if (enable) {
338 twl4030->apll_enabled++;
339 if (twl4030->apll_enabled == 1)
340 status = twl4030_codec_enable_resource(
341 TWL4030_CODEC_RES_APLL);
342 } else {
343 twl4030->apll_enabled--;
344 if (!twl4030->apll_enabled)
345 status = twl4030_codec_disable_resource(
346 TWL4030_CODEC_RES_APLL);
347 }
348
349 if (status >= 0)
350 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
351 }
352
353 /* Earpiece */
354 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
355 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
356 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
357 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
358 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
359 };
360
361 /* PreDrive Left */
362 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
366 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
367 };
368
369 /* PreDrive Right */
370 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
371 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
372 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
373 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
374 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
375 };
376
377 /* Headset Left */
378 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
379 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
380 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
381 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
382 };
383
384 /* Headset Right */
385 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
386 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
387 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
388 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
389 };
390
391 /* Carkit Left */
392 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
393 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
394 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
395 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
396 };
397
398 /* Carkit Right */
399 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
400 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
401 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
402 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
403 };
404
405 /* Handsfree Left */
406 static const char *twl4030_handsfreel_texts[] =
407 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
408
409 static const struct soc_enum twl4030_handsfreel_enum =
410 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
411 ARRAY_SIZE(twl4030_handsfreel_texts),
412 twl4030_handsfreel_texts);
413
414 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
415 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
416
417 /* Handsfree Left virtual mute */
418 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
419 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
420
421 /* Handsfree Right */
422 static const char *twl4030_handsfreer_texts[] =
423 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
424
425 static const struct soc_enum twl4030_handsfreer_enum =
426 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
427 ARRAY_SIZE(twl4030_handsfreer_texts),
428 twl4030_handsfreer_texts);
429
430 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
431 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
432
433 /* Handsfree Right virtual mute */
434 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
435 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
436
437 /* Vibra */
438 /* Vibra audio path selection */
439 static const char *twl4030_vibra_texts[] =
440 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
441
442 static const struct soc_enum twl4030_vibra_enum =
443 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
444 ARRAY_SIZE(twl4030_vibra_texts),
445 twl4030_vibra_texts);
446
447 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
448 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
449
450 /* Vibra path selection: local vibrator (PWM) or audio driven */
451 static const char *twl4030_vibrapath_texts[] =
452 {"Local vibrator", "Audio"};
453
454 static const struct soc_enum twl4030_vibrapath_enum =
455 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
456 ARRAY_SIZE(twl4030_vibrapath_texts),
457 twl4030_vibrapath_texts);
458
459 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
460 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
461
462 /* Left analog microphone selection */
463 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
464 SOC_DAPM_SINGLE("Main Mic Capture Switch",
465 TWL4030_REG_ANAMICL, 0, 1, 0),
466 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
467 TWL4030_REG_ANAMICL, 1, 1, 0),
468 SOC_DAPM_SINGLE("AUXL Capture Switch",
469 TWL4030_REG_ANAMICL, 2, 1, 0),
470 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
471 TWL4030_REG_ANAMICL, 3, 1, 0),
472 };
473
474 /* Right analog microphone selection */
475 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
476 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
477 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
478 };
479
480 /* TX1 L/R Analog/Digital microphone selection */
481 static const char *twl4030_micpathtx1_texts[] =
482 {"Analog", "Digimic0"};
483
484 static const struct soc_enum twl4030_micpathtx1_enum =
485 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
486 ARRAY_SIZE(twl4030_micpathtx1_texts),
487 twl4030_micpathtx1_texts);
488
489 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
490 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
491
492 /* TX2 L/R Analog/Digital microphone selection */
493 static const char *twl4030_micpathtx2_texts[] =
494 {"Analog", "Digimic1"};
495
496 static const struct soc_enum twl4030_micpathtx2_enum =
497 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
498 ARRAY_SIZE(twl4030_micpathtx2_texts),
499 twl4030_micpathtx2_texts);
500
501 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
502 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
503
504 /* Analog bypass for AudioR1 */
505 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
506 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
507
508 /* Analog bypass for AudioL1 */
509 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
510 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
511
512 /* Analog bypass for AudioR2 */
513 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
514 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
515
516 /* Analog bypass for AudioL2 */
517 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
518 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
519
520 /* Analog bypass for Voice */
521 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
522 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
523
524 /* Digital bypass gain, 0 mutes the bypass */
525 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
526 TLV_DB_RANGE_HEAD(2),
527 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
528 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
529 };
530
531 /* Digital bypass left (TX1L -> RX2L) */
532 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
533 SOC_DAPM_SINGLE_TLV("Volume",
534 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
535 twl4030_dapm_dbypass_tlv);
536
537 /* Digital bypass right (TX1R -> RX2R) */
538 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
539 SOC_DAPM_SINGLE_TLV("Volume",
540 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
541 twl4030_dapm_dbypass_tlv);
542
543 /*
544 * Voice Sidetone GAIN volume control:
545 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
546 */
547 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
548
549 /* Digital bypass voice: sidetone (VUL -> VDL)*/
550 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
551 SOC_DAPM_SINGLE_TLV("Volume",
552 TWL4030_REG_VSTPGA, 0, 0x29, 0,
553 twl4030_dapm_dbypassv_tlv);
554
555 static int micpath_event(struct snd_soc_dapm_widget *w,
556 struct snd_kcontrol *kcontrol, int event)
557 {
558 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
559 unsigned char adcmicsel, micbias_ctl;
560
561 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
562 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
563 /* Prepare the bits for the given TX path:
564 * shift_l == 0: TX1 microphone path
565 * shift_l == 2: TX2 microphone path */
566 if (e->shift_l) {
567 /* TX2 microphone path */
568 if (adcmicsel & TWL4030_TX2IN_SEL)
569 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
570 else
571 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
572 } else {
573 /* TX1 microphone path */
574 if (adcmicsel & TWL4030_TX1IN_SEL)
575 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
576 else
577 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
578 }
579
580 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
581
582 return 0;
583 }
584
585 /*
586 * Output PGA builder:
587 * Handle the muting and unmuting of the given output (turning off the
588 * amplifier associated with the output pin)
589 * On mute bypass the reg_cache and write 0 to the register
590 * On unmute: restore the register content from the reg_cache
591 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
592 */
593 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
594 static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
595 struct snd_kcontrol *kcontrol, int event) \
596 { \
597 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
598 \
599 switch (event) { \
600 case SND_SOC_DAPM_POST_PMU: \
601 twl4030->pin_name##_enabled = 1; \
602 twl4030_write(w->codec, reg, \
603 twl4030_read_reg_cache(w->codec, reg)); \
604 break; \
605 case SND_SOC_DAPM_POST_PMD: \
606 twl4030->pin_name##_enabled = 0; \
607 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
608 0, reg); \
609 break; \
610 } \
611 return 0; \
612 }
613
614 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
615 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
616 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
617 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
618 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
619
620 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
621 {
622 unsigned char hs_ctl;
623
624 hs_ctl = twl4030_read_reg_cache(codec, reg);
625
626 if (ramp) {
627 /* HF ramp-up */
628 hs_ctl |= TWL4030_HF_CTL_REF_EN;
629 twl4030_write(codec, reg, hs_ctl);
630 udelay(10);
631 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
632 twl4030_write(codec, reg, hs_ctl);
633 udelay(40);
634 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
635 hs_ctl |= TWL4030_HF_CTL_HB_EN;
636 twl4030_write(codec, reg, hs_ctl);
637 } else {
638 /* HF ramp-down */
639 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
640 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
641 twl4030_write(codec, reg, hs_ctl);
642 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
643 twl4030_write(codec, reg, hs_ctl);
644 udelay(40);
645 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
646 twl4030_write(codec, reg, hs_ctl);
647 }
648 }
649
650 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
651 struct snd_kcontrol *kcontrol, int event)
652 {
653 switch (event) {
654 case SND_SOC_DAPM_POST_PMU:
655 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
656 break;
657 case SND_SOC_DAPM_POST_PMD:
658 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
659 break;
660 }
661 return 0;
662 }
663
664 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
665 struct snd_kcontrol *kcontrol, int event)
666 {
667 switch (event) {
668 case SND_SOC_DAPM_POST_PMU:
669 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
670 break;
671 case SND_SOC_DAPM_POST_PMD:
672 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
673 break;
674 }
675 return 0;
676 }
677
678 static int vibramux_event(struct snd_soc_dapm_widget *w,
679 struct snd_kcontrol *kcontrol, int event)
680 {
681 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
682 return 0;
683 }
684
685 static int apll_event(struct snd_soc_dapm_widget *w,
686 struct snd_kcontrol *kcontrol, int event)
687 {
688 switch (event) {
689 case SND_SOC_DAPM_PRE_PMU:
690 twl4030_apll_enable(w->codec, 1);
691 break;
692 case SND_SOC_DAPM_POST_PMD:
693 twl4030_apll_enable(w->codec, 0);
694 break;
695 }
696 return 0;
697 }
698
699 static int aif_event(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *kcontrol, int event)
701 {
702 u8 audio_if;
703
704 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
705 switch (event) {
706 case SND_SOC_DAPM_PRE_PMU:
707 /* Enable AIF */
708 /* enable the PLL before we use it to clock the DAI */
709 twl4030_apll_enable(w->codec, 1);
710
711 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
712 audio_if | TWL4030_AIF_EN);
713 break;
714 case SND_SOC_DAPM_POST_PMD:
715 /* disable the DAI before we stop it's source PLL */
716 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
717 audio_if & ~TWL4030_AIF_EN);
718 twl4030_apll_enable(w->codec, 0);
719 break;
720 }
721 return 0;
722 }
723
724 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
725 {
726 struct snd_soc_device *socdev = codec->socdev;
727 struct twl4030_setup_data *setup = socdev->codec_data;
728
729 unsigned char hs_gain, hs_pop;
730 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
731 /* Base values for ramp delay calculation: 2^19 - 2^26 */
732 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
733 8388608, 16777216, 33554432, 67108864};
734
735 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
736 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
737
738 /* Enable external mute control, this dramatically reduces
739 * the pop-noise */
740 if (setup && setup->hs_extmute) {
741 if (setup->set_hs_extmute) {
742 setup->set_hs_extmute(1);
743 } else {
744 hs_pop |= TWL4030_EXTMUTE;
745 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
746 }
747 }
748
749 if (ramp) {
750 /* Headset ramp-up according to the TRM */
751 hs_pop |= TWL4030_VMID_EN;
752 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
753 /* Actually write to the register */
754 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
755 hs_gain,
756 TWL4030_REG_HS_GAIN_SET);
757 hs_pop |= TWL4030_RAMP_EN;
758 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
759 /* Wait ramp delay time + 1, so the VMID can settle */
760 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
761 twl4030->sysclk) + 1);
762 } else {
763 /* Headset ramp-down _not_ according to
764 * the TRM, but in a way that it is working */
765 hs_pop &= ~TWL4030_RAMP_EN;
766 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
767 /* Wait ramp delay time + 1, so the VMID can settle */
768 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
769 twl4030->sysclk) + 1);
770 /* Bypass the reg_cache to mute the headset */
771 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
772 hs_gain & (~0x0f),
773 TWL4030_REG_HS_GAIN_SET);
774
775 hs_pop &= ~TWL4030_VMID_EN;
776 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
777 }
778
779 /* Disable external mute */
780 if (setup && setup->hs_extmute) {
781 if (setup->set_hs_extmute) {
782 setup->set_hs_extmute(0);
783 } else {
784 hs_pop &= ~TWL4030_EXTMUTE;
785 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
786 }
787 }
788 }
789
790 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
791 struct snd_kcontrol *kcontrol, int event)
792 {
793 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
794
795 switch (event) {
796 case SND_SOC_DAPM_POST_PMU:
797 /* Do the ramp-up only once */
798 if (!twl4030->hsr_enabled)
799 headset_ramp(w->codec, 1);
800
801 twl4030->hsl_enabled = 1;
802 break;
803 case SND_SOC_DAPM_POST_PMD:
804 /* Do the ramp-down only if both headsetL/R is disabled */
805 if (!twl4030->hsr_enabled)
806 headset_ramp(w->codec, 0);
807
808 twl4030->hsl_enabled = 0;
809 break;
810 }
811 return 0;
812 }
813
814 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
815 struct snd_kcontrol *kcontrol, int event)
816 {
817 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
818
819 switch (event) {
820 case SND_SOC_DAPM_POST_PMU:
821 /* Do the ramp-up only once */
822 if (!twl4030->hsl_enabled)
823 headset_ramp(w->codec, 1);
824
825 twl4030->hsr_enabled = 1;
826 break;
827 case SND_SOC_DAPM_POST_PMD:
828 /* Do the ramp-down only if both headsetL/R is disabled */
829 if (!twl4030->hsl_enabled)
830 headset_ramp(w->codec, 0);
831
832 twl4030->hsr_enabled = 0;
833 break;
834 }
835 return 0;
836 }
837
838 /*
839 * Some of the gain controls in TWL (mostly those which are associated with
840 * the outputs) are implemented in an interesting way:
841 * 0x0 : Power down (mute)
842 * 0x1 : 6dB
843 * 0x2 : 0 dB
844 * 0x3 : -6 dB
845 * Inverting not going to help with these.
846 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
847 */
848 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
849 xinvert, tlv_array) \
850 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
851 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
852 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
853 .tlv.p = (tlv_array), \
854 .info = snd_soc_info_volsw, \
855 .get = snd_soc_get_volsw_twl4030, \
856 .put = snd_soc_put_volsw_twl4030, \
857 .private_value = (unsigned long)&(struct soc_mixer_control) \
858 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
859 .max = xmax, .invert = xinvert} }
860 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
861 xinvert, tlv_array) \
862 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
863 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
864 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
865 .tlv.p = (tlv_array), \
866 .info = snd_soc_info_volsw_2r, \
867 .get = snd_soc_get_volsw_r2_twl4030,\
868 .put = snd_soc_put_volsw_r2_twl4030, \
869 .private_value = (unsigned long)&(struct soc_mixer_control) \
870 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
871 .rshift = xshift, .max = xmax, .invert = xinvert} }
872 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
873 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
874 xinvert, tlv_array)
875
876 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
877 struct snd_ctl_elem_value *ucontrol)
878 {
879 struct soc_mixer_control *mc =
880 (struct soc_mixer_control *)kcontrol->private_value;
881 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
882 unsigned int reg = mc->reg;
883 unsigned int shift = mc->shift;
884 unsigned int rshift = mc->rshift;
885 int max = mc->max;
886 int mask = (1 << fls(max)) - 1;
887
888 ucontrol->value.integer.value[0] =
889 (snd_soc_read(codec, reg) >> shift) & mask;
890 if (ucontrol->value.integer.value[0])
891 ucontrol->value.integer.value[0] =
892 max + 1 - ucontrol->value.integer.value[0];
893
894 if (shift != rshift) {
895 ucontrol->value.integer.value[1] =
896 (snd_soc_read(codec, reg) >> rshift) & mask;
897 if (ucontrol->value.integer.value[1])
898 ucontrol->value.integer.value[1] =
899 max + 1 - ucontrol->value.integer.value[1];
900 }
901
902 return 0;
903 }
904
905 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
906 struct snd_ctl_elem_value *ucontrol)
907 {
908 struct soc_mixer_control *mc =
909 (struct soc_mixer_control *)kcontrol->private_value;
910 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
911 unsigned int reg = mc->reg;
912 unsigned int shift = mc->shift;
913 unsigned int rshift = mc->rshift;
914 int max = mc->max;
915 int mask = (1 << fls(max)) - 1;
916 unsigned short val, val2, val_mask;
917
918 val = (ucontrol->value.integer.value[0] & mask);
919
920 val_mask = mask << shift;
921 if (val)
922 val = max + 1 - val;
923 val = val << shift;
924 if (shift != rshift) {
925 val2 = (ucontrol->value.integer.value[1] & mask);
926 val_mask |= mask << rshift;
927 if (val2)
928 val2 = max + 1 - val2;
929 val |= val2 << rshift;
930 }
931 return snd_soc_update_bits(codec, reg, val_mask, val);
932 }
933
934 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
935 struct snd_ctl_elem_value *ucontrol)
936 {
937 struct soc_mixer_control *mc =
938 (struct soc_mixer_control *)kcontrol->private_value;
939 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
940 unsigned int reg = mc->reg;
941 unsigned int reg2 = mc->rreg;
942 unsigned int shift = mc->shift;
943 int max = mc->max;
944 int mask = (1<<fls(max))-1;
945
946 ucontrol->value.integer.value[0] =
947 (snd_soc_read(codec, reg) >> shift) & mask;
948 ucontrol->value.integer.value[1] =
949 (snd_soc_read(codec, reg2) >> shift) & mask;
950
951 if (ucontrol->value.integer.value[0])
952 ucontrol->value.integer.value[0] =
953 max + 1 - ucontrol->value.integer.value[0];
954 if (ucontrol->value.integer.value[1])
955 ucontrol->value.integer.value[1] =
956 max + 1 - ucontrol->value.integer.value[1];
957
958 return 0;
959 }
960
961 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
962 struct snd_ctl_elem_value *ucontrol)
963 {
964 struct soc_mixer_control *mc =
965 (struct soc_mixer_control *)kcontrol->private_value;
966 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
967 unsigned int reg = mc->reg;
968 unsigned int reg2 = mc->rreg;
969 unsigned int shift = mc->shift;
970 int max = mc->max;
971 int mask = (1 << fls(max)) - 1;
972 int err;
973 unsigned short val, val2, val_mask;
974
975 val_mask = mask << shift;
976 val = (ucontrol->value.integer.value[0] & mask);
977 val2 = (ucontrol->value.integer.value[1] & mask);
978
979 if (val)
980 val = max + 1 - val;
981 if (val2)
982 val2 = max + 1 - val2;
983
984 val = val << shift;
985 val2 = val2 << shift;
986
987 err = snd_soc_update_bits(codec, reg, val_mask, val);
988 if (err < 0)
989 return err;
990
991 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
992 return err;
993 }
994
995 /* Codec operation modes */
996 static const char *twl4030_op_modes_texts[] = {
997 "Option 2 (voice/audio)", "Option 1 (audio)"
998 };
999
1000 static const struct soc_enum twl4030_op_modes_enum =
1001 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1002 ARRAY_SIZE(twl4030_op_modes_texts),
1003 twl4030_op_modes_texts);
1004
1005 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
1006 struct snd_ctl_elem_value *ucontrol)
1007 {
1008 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1009 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1010 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1011 unsigned short val;
1012 unsigned short mask, bitmask;
1013
1014 if (twl4030->configured) {
1015 printk(KERN_ERR "twl4030 operation mode cannot be "
1016 "changed on-the-fly\n");
1017 return -EBUSY;
1018 }
1019
1020 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1021 ;
1022 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1023 return -EINVAL;
1024
1025 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1026 mask = (bitmask - 1) << e->shift_l;
1027 if (e->shift_l != e->shift_r) {
1028 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1029 return -EINVAL;
1030 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1031 mask |= (bitmask - 1) << e->shift_r;
1032 }
1033
1034 return snd_soc_update_bits(codec, e->reg, mask, val);
1035 }
1036
1037 /*
1038 * FGAIN volume control:
1039 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1040 */
1041 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
1042
1043 /*
1044 * CGAIN volume control:
1045 * 0 dB to 12 dB in 6 dB steps
1046 * value 2 and 3 means 12 dB
1047 */
1048 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1049
1050 /*
1051 * Voice Downlink GAIN volume control:
1052 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1053 */
1054 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1055
1056 /*
1057 * Analog playback gain
1058 * -24 dB to 12 dB in 2 dB steps
1059 */
1060 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
1061
1062 /*
1063 * Gain controls tied to outputs
1064 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1065 */
1066 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1067
1068 /*
1069 * Gain control for earpiece amplifier
1070 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1071 */
1072 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1073
1074 /*
1075 * Capture gain after the ADCs
1076 * from 0 dB to 31 dB in 1 dB steps
1077 */
1078 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1079
1080 /*
1081 * Gain control for input amplifiers
1082 * 0 dB to 30 dB in 6 dB steps
1083 */
1084 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1085
1086 /* AVADC clock priority */
1087 static const char *twl4030_avadc_clk_priority_texts[] = {
1088 "Voice high priority", "HiFi high priority"
1089 };
1090
1091 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1092 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1093 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1094 twl4030_avadc_clk_priority_texts);
1095
1096 static const char *twl4030_rampdelay_texts[] = {
1097 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1098 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1099 "3495/2581/1748 ms"
1100 };
1101
1102 static const struct soc_enum twl4030_rampdelay_enum =
1103 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1104 ARRAY_SIZE(twl4030_rampdelay_texts),
1105 twl4030_rampdelay_texts);
1106
1107 /* Vibra H-bridge direction mode */
1108 static const char *twl4030_vibradirmode_texts[] = {
1109 "Vibra H-bridge direction", "Audio data MSB",
1110 };
1111
1112 static const struct soc_enum twl4030_vibradirmode_enum =
1113 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1114 ARRAY_SIZE(twl4030_vibradirmode_texts),
1115 twl4030_vibradirmode_texts);
1116
1117 /* Vibra H-bridge direction */
1118 static const char *twl4030_vibradir_texts[] = {
1119 "Positive polarity", "Negative polarity",
1120 };
1121
1122 static const struct soc_enum twl4030_vibradir_enum =
1123 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1124 ARRAY_SIZE(twl4030_vibradir_texts),
1125 twl4030_vibradir_texts);
1126
1127 /* Digimic Left and right swapping */
1128 static const char *twl4030_digimicswap_texts[] = {
1129 "Not swapped", "Swapped",
1130 };
1131
1132 static const struct soc_enum twl4030_digimicswap_enum =
1133 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1134 ARRAY_SIZE(twl4030_digimicswap_texts),
1135 twl4030_digimicswap_texts);
1136
1137 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1138 /* Codec operation mode control */
1139 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1140 snd_soc_get_enum_double,
1141 snd_soc_put_twl4030_opmode_enum_double),
1142
1143 /* Common playback gain controls */
1144 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1145 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1146 0, 0x3f, 0, digital_fine_tlv),
1147 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1148 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1149 0, 0x3f, 0, digital_fine_tlv),
1150
1151 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1152 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1153 6, 0x2, 0, digital_coarse_tlv),
1154 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1155 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1156 6, 0x2, 0, digital_coarse_tlv),
1157
1158 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1159 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1160 3, 0x12, 1, analog_tlv),
1161 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1162 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1163 3, 0x12, 1, analog_tlv),
1164 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1165 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1166 1, 1, 0),
1167 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1168 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1169 1, 1, 0),
1170
1171 /* Common voice downlink gain controls */
1172 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1173 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1174
1175 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1176 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1177
1178 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1179 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1180
1181 /* Separate output gain controls */
1182 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1183 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1184 4, 3, 0, output_tvl),
1185
1186 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1187 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1188
1189 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1190 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1191 4, 3, 0, output_tvl),
1192
1193 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
1194 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
1195
1196 /* Common capture gain controls */
1197 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1198 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1199 0, 0x1f, 0, digital_capture_tlv),
1200 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1201 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1202 0, 0x1f, 0, digital_capture_tlv),
1203
1204 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1205 0, 3, 5, 0, input_gain_tlv),
1206
1207 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1208
1209 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1210
1211 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1212 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1213
1214 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1215 };
1216
1217 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1218 /* Left channel inputs */
1219 SND_SOC_DAPM_INPUT("MAINMIC"),
1220 SND_SOC_DAPM_INPUT("HSMIC"),
1221 SND_SOC_DAPM_INPUT("AUXL"),
1222 SND_SOC_DAPM_INPUT("CARKITMIC"),
1223 /* Right channel inputs */
1224 SND_SOC_DAPM_INPUT("SUBMIC"),
1225 SND_SOC_DAPM_INPUT("AUXR"),
1226 /* Digital microphones (Stereo) */
1227 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1228 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1229
1230 /* Outputs */
1231 SND_SOC_DAPM_OUTPUT("EARPIECE"),
1232 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1233 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1234 SND_SOC_DAPM_OUTPUT("HSOL"),
1235 SND_SOC_DAPM_OUTPUT("HSOR"),
1236 SND_SOC_DAPM_OUTPUT("CARKITL"),
1237 SND_SOC_DAPM_OUTPUT("CARKITR"),
1238 SND_SOC_DAPM_OUTPUT("HFL"),
1239 SND_SOC_DAPM_OUTPUT("HFR"),
1240 SND_SOC_DAPM_OUTPUT("VIBRA"),
1241
1242 /* AIF and APLL clocks for running DAIs (including loopback) */
1243 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1244 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1245 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1246
1247 /* DACs */
1248 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
1249 SND_SOC_NOPM, 0, 0),
1250 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
1251 SND_SOC_NOPM, 0, 0),
1252 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
1253 SND_SOC_NOPM, 0, 0),
1254 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
1255 SND_SOC_NOPM, 0, 0),
1256 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
1257 SND_SOC_NOPM, 0, 0),
1258
1259 /* Analog bypasses */
1260 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1261 &twl4030_dapm_abypassr1_control),
1262 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1263 &twl4030_dapm_abypassl1_control),
1264 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1265 &twl4030_dapm_abypassr2_control),
1266 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1267 &twl4030_dapm_abypassl2_control),
1268 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1269 &twl4030_dapm_abypassv_control),
1270
1271 /* Master analog loopback switch */
1272 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1273 NULL, 0),
1274
1275 /* Digital bypasses */
1276 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1277 &twl4030_dapm_dbypassl_control),
1278 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1279 &twl4030_dapm_dbypassr_control),
1280 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1281 &twl4030_dapm_dbypassv_control),
1282
1283 /* Digital mixers, power control for the physical DACs */
1284 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1285 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1286 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1287 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1288 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1289 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1290 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1291 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1292 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1293 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1294
1295 /* Analog mixers, power control for the physical PGAs */
1296 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1297 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1298 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1299 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1300 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1301 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1302 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1303 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1304 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1305 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1306
1307 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1308 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1309
1310 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1311 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1312
1313 /* Output MIXER controls */
1314 /* Earpiece */
1315 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1316 &twl4030_dapm_earpiece_controls[0],
1317 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1318 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1319 0, 0, NULL, 0, earpiecepga_event,
1320 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1321 /* PreDrivL/R */
1322 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1323 &twl4030_dapm_predrivel_controls[0],
1324 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1325 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1326 0, 0, NULL, 0, predrivelpga_event,
1327 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1328 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1329 &twl4030_dapm_predriver_controls[0],
1330 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1331 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1332 0, 0, NULL, 0, predriverpga_event,
1333 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1334 /* HeadsetL/R */
1335 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1336 &twl4030_dapm_hsol_controls[0],
1337 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1338 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1339 0, 0, NULL, 0, headsetlpga_event,
1340 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1341 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1342 &twl4030_dapm_hsor_controls[0],
1343 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1344 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1345 0, 0, NULL, 0, headsetrpga_event,
1346 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1347 /* CarkitL/R */
1348 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1349 &twl4030_dapm_carkitl_controls[0],
1350 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1351 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1352 0, 0, NULL, 0, carkitlpga_event,
1353 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1354 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1355 &twl4030_dapm_carkitr_controls[0],
1356 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1357 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1358 0, 0, NULL, 0, carkitrpga_event,
1359 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1360
1361 /* Output MUX controls */
1362 /* HandsfreeL/R */
1363 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1364 &twl4030_dapm_handsfreel_control),
1365 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1366 &twl4030_dapm_handsfreelmute_control),
1367 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1368 0, 0, NULL, 0, handsfreelpga_event,
1369 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1370 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1371 &twl4030_dapm_handsfreer_control),
1372 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1373 &twl4030_dapm_handsfreermute_control),
1374 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1375 0, 0, NULL, 0, handsfreerpga_event,
1376 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1377 /* Vibra */
1378 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1379 &twl4030_dapm_vibra_control, vibramux_event,
1380 SND_SOC_DAPM_PRE_PMU),
1381 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1382 &twl4030_dapm_vibrapath_control),
1383
1384 /* Introducing four virtual ADC, since TWL4030 have four channel for
1385 capture */
1386 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1387 SND_SOC_NOPM, 0, 0),
1388 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1389 SND_SOC_NOPM, 0, 0),
1390 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1391 SND_SOC_NOPM, 0, 0),
1392 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1393 SND_SOC_NOPM, 0, 0),
1394
1395 /* Analog/Digital mic path selection.
1396 TX1 Left/Right: either analog Left/Right or Digimic0
1397 TX2 Left/Right: either analog Left/Right or Digimic1 */
1398 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1399 &twl4030_dapm_micpathtx1_control, micpath_event,
1400 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1401 SND_SOC_DAPM_POST_REG),
1402 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1403 &twl4030_dapm_micpathtx2_control, micpath_event,
1404 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1405 SND_SOC_DAPM_POST_REG),
1406
1407 /* Analog input mixers for the capture amplifiers */
1408 SND_SOC_DAPM_MIXER("Analog Left",
1409 TWL4030_REG_ANAMICL, 4, 0,
1410 &twl4030_dapm_analoglmic_controls[0],
1411 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1412 SND_SOC_DAPM_MIXER("Analog Right",
1413 TWL4030_REG_ANAMICR, 4, 0,
1414 &twl4030_dapm_analogrmic_controls[0],
1415 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1416
1417 SND_SOC_DAPM_PGA("ADC Physical Left",
1418 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1419 SND_SOC_DAPM_PGA("ADC Physical Right",
1420 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1421
1422 SND_SOC_DAPM_PGA("Digimic0 Enable",
1423 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1424 SND_SOC_DAPM_PGA("Digimic1 Enable",
1425 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1426
1427 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1428 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1429 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1430
1431 };
1432
1433 static const struct snd_soc_dapm_route intercon[] = {
1434 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1435 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1436 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1437 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1438 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1439
1440 /* Supply for the digital part (APLL) */
1441 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1442
1443 {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
1444 {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
1445 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1446 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1447
1448 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1449 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1450 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1451 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1452 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1453
1454 /* Internal playback routings */
1455 /* Earpiece */
1456 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1457 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1458 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1459 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1460 {"Earpiece PGA", NULL, "Earpiece Mixer"},
1461 /* PreDrivL */
1462 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1463 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1464 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1465 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1466 {"PredriveL PGA", NULL, "PredriveL Mixer"},
1467 /* PreDrivR */
1468 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1469 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1470 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1471 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1472 {"PredriveR PGA", NULL, "PredriveR Mixer"},
1473 /* HeadsetL */
1474 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1475 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1476 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1477 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1478 /* HeadsetR */
1479 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1480 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1481 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1482 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1483 /* CarkitL */
1484 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1485 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1486 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1487 {"CarkitL PGA", NULL, "CarkitL Mixer"},
1488 /* CarkitR */
1489 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1490 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1491 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1492 {"CarkitR PGA", NULL, "CarkitR Mixer"},
1493 /* HandsfreeL */
1494 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1495 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1496 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1497 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1498 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1499 {"HandsfreeL PGA", NULL, "HandsfreeL"},
1500 /* HandsfreeR */
1501 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1502 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1503 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1504 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1505 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1506 {"HandsfreeR PGA", NULL, "HandsfreeR"},
1507 /* Vibra */
1508 {"Vibra Mux", "AudioL1", "DAC Left1"},
1509 {"Vibra Mux", "AudioR1", "DAC Right1"},
1510 {"Vibra Mux", "AudioL2", "DAC Left2"},
1511 {"Vibra Mux", "AudioR2", "DAC Right2"},
1512
1513 /* outputs */
1514 /* Must be always connected (for AIF and APLL) */
1515 {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
1516 {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
1517 {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
1518 {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
1519 /* Must be always connected (for APLL) */
1520 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1521 /* Physical outputs */
1522 {"EARPIECE", NULL, "Earpiece PGA"},
1523 {"PREDRIVEL", NULL, "PredriveL PGA"},
1524 {"PREDRIVER", NULL, "PredriveR PGA"},
1525 {"HSOL", NULL, "HeadsetL PGA"},
1526 {"HSOR", NULL, "HeadsetR PGA"},
1527 {"CARKITL", NULL, "CarkitL PGA"},
1528 {"CARKITR", NULL, "CarkitR PGA"},
1529 {"HFL", NULL, "HandsfreeL PGA"},
1530 {"HFR", NULL, "HandsfreeR PGA"},
1531 {"Vibra Route", "Audio", "Vibra Mux"},
1532 {"VIBRA", NULL, "Vibra Route"},
1533
1534 /* Capture path */
1535 /* Must be always connected (for AIF and APLL) */
1536 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1537 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1538 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1539 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1540 /* Physical inputs */
1541 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1542 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1543 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1544 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1545
1546 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1547 {"Analog Right", "AUXR Capture Switch", "AUXR"},
1548
1549 {"ADC Physical Left", NULL, "Analog Left"},
1550 {"ADC Physical Right", NULL, "Analog Right"},
1551
1552 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1553 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1554
1555 /* TX1 Left capture path */
1556 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1557 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1558 /* TX1 Right capture path */
1559 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1560 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1561 /* TX2 Left capture path */
1562 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1563 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1564 /* TX2 Right capture path */
1565 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1566 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1567
1568 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1569 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1570 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1571 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1572
1573 {"ADC Virtual Left1", NULL, "AIF Enable"},
1574 {"ADC Virtual Right1", NULL, "AIF Enable"},
1575 {"ADC Virtual Left2", NULL, "AIF Enable"},
1576 {"ADC Virtual Right2", NULL, "AIF Enable"},
1577
1578 /* Analog bypass routes */
1579 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1580 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1581 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1582 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1583 {"Voice Analog Loopback", "Switch", "Analog Left"},
1584
1585 /* Supply for the Analog loopbacks */
1586 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1587 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1588 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1589 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1590 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1591
1592 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1593 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1594 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1595 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1596 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1597
1598 /* Digital bypass routes */
1599 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1600 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1601 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1602
1603 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1604 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1605 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1606
1607 };
1608
1609 static int twl4030_add_widgets(struct snd_soc_codec *codec)
1610 {
1611 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1612 ARRAY_SIZE(twl4030_dapm_widgets));
1613
1614 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1615
1616 return 0;
1617 }
1618
1619 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1620 enum snd_soc_bias_level level)
1621 {
1622 switch (level) {
1623 case SND_SOC_BIAS_ON:
1624 break;
1625 case SND_SOC_BIAS_PREPARE:
1626 break;
1627 case SND_SOC_BIAS_STANDBY:
1628 if (codec->bias_level == SND_SOC_BIAS_OFF)
1629 twl4030_codec_enable(codec, 1);
1630 break;
1631 case SND_SOC_BIAS_OFF:
1632 twl4030_codec_enable(codec, 0);
1633 break;
1634 }
1635 codec->bias_level = level;
1636
1637 return 0;
1638 }
1639
1640 static void twl4030_constraints(struct twl4030_priv *twl4030,
1641 struct snd_pcm_substream *mst_substream)
1642 {
1643 struct snd_pcm_substream *slv_substream;
1644
1645 /* Pick the stream, which need to be constrained */
1646 if (mst_substream == twl4030->master_substream)
1647 slv_substream = twl4030->slave_substream;
1648 else if (mst_substream == twl4030->slave_substream)
1649 slv_substream = twl4030->master_substream;
1650 else /* This should not happen.. */
1651 return;
1652
1653 /* Set the constraints according to the already configured stream */
1654 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1655 SNDRV_PCM_HW_PARAM_RATE,
1656 twl4030->rate,
1657 twl4030->rate);
1658
1659 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1660 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1661 twl4030->sample_bits,
1662 twl4030->sample_bits);
1663
1664 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1665 SNDRV_PCM_HW_PARAM_CHANNELS,
1666 twl4030->channels,
1667 twl4030->channels);
1668 }
1669
1670 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1671 * capture has to be enabled/disabled. */
1672 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1673 int enable)
1674 {
1675 u8 reg, mask;
1676
1677 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1678
1679 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1680 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1681 else
1682 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1683
1684 if (enable)
1685 reg |= mask;
1686 else
1687 reg &= ~mask;
1688
1689 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1690 }
1691
1692 static int twl4030_startup(struct snd_pcm_substream *substream,
1693 struct snd_soc_dai *dai)
1694 {
1695 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1696 struct snd_soc_device *socdev = rtd->socdev;
1697 struct snd_soc_codec *codec = socdev->card->codec;
1698 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1699
1700 if (twl4030->master_substream) {
1701 twl4030->slave_substream = substream;
1702 /* The DAI has one configuration for playback and capture, so
1703 * if the DAI has been already configured then constrain this
1704 * substream to match it. */
1705 if (twl4030->configured)
1706 twl4030_constraints(twl4030, twl4030->master_substream);
1707 } else {
1708 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1709 TWL4030_OPTION_1)) {
1710 /* In option2 4 channel is not supported, set the
1711 * constraint for the first stream for channels, the
1712 * second stream will 'inherit' this cosntraint */
1713 snd_pcm_hw_constraint_minmax(substream->runtime,
1714 SNDRV_PCM_HW_PARAM_CHANNELS,
1715 2, 2);
1716 }
1717 twl4030->master_substream = substream;
1718 }
1719
1720 return 0;
1721 }
1722
1723 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1724 struct snd_soc_dai *dai)
1725 {
1726 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1727 struct snd_soc_device *socdev = rtd->socdev;
1728 struct snd_soc_codec *codec = socdev->card->codec;
1729 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1730
1731 if (twl4030->master_substream == substream)
1732 twl4030->master_substream = twl4030->slave_substream;
1733
1734 twl4030->slave_substream = NULL;
1735
1736 /* If all streams are closed, or the remaining stream has not yet
1737 * been configured than set the DAI as not configured. */
1738 if (!twl4030->master_substream)
1739 twl4030->configured = 0;
1740 else if (!twl4030->master_substream->runtime->channels)
1741 twl4030->configured = 0;
1742
1743 /* If the closing substream had 4 channel, do the necessary cleanup */
1744 if (substream->runtime->channels == 4)
1745 twl4030_tdm_enable(codec, substream->stream, 0);
1746 }
1747
1748 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1749 struct snd_pcm_hw_params *params,
1750 struct snd_soc_dai *dai)
1751 {
1752 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1753 struct snd_soc_device *socdev = rtd->socdev;
1754 struct snd_soc_codec *codec = socdev->card->codec;
1755 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1756 u8 mode, old_mode, format, old_format;
1757
1758 /* If the substream has 4 channel, do the necessary setup */
1759 if (params_channels(params) == 4) {
1760 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1761 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1762
1763 /* Safety check: are we in the correct operating mode and
1764 * the interface is in TDM mode? */
1765 if ((mode & TWL4030_OPTION_1) &&
1766 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1767 twl4030_tdm_enable(codec, substream->stream, 1);
1768 else
1769 return -EINVAL;
1770 }
1771
1772 if (twl4030->configured)
1773 /* Ignoring hw_params for already configured DAI */
1774 return 0;
1775
1776 /* bit rate */
1777 old_mode = twl4030_read_reg_cache(codec,
1778 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1779 mode = old_mode & ~TWL4030_APLL_RATE;
1780
1781 switch (params_rate(params)) {
1782 case 8000:
1783 mode |= TWL4030_APLL_RATE_8000;
1784 break;
1785 case 11025:
1786 mode |= TWL4030_APLL_RATE_11025;
1787 break;
1788 case 12000:
1789 mode |= TWL4030_APLL_RATE_12000;
1790 break;
1791 case 16000:
1792 mode |= TWL4030_APLL_RATE_16000;
1793 break;
1794 case 22050:
1795 mode |= TWL4030_APLL_RATE_22050;
1796 break;
1797 case 24000:
1798 mode |= TWL4030_APLL_RATE_24000;
1799 break;
1800 case 32000:
1801 mode |= TWL4030_APLL_RATE_32000;
1802 break;
1803 case 44100:
1804 mode |= TWL4030_APLL_RATE_44100;
1805 break;
1806 case 48000:
1807 mode |= TWL4030_APLL_RATE_48000;
1808 break;
1809 case 96000:
1810 mode |= TWL4030_APLL_RATE_96000;
1811 break;
1812 default:
1813 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1814 params_rate(params));
1815 return -EINVAL;
1816 }
1817
1818 if (mode != old_mode) {
1819 /* change rate and set CODECPDZ */
1820 twl4030_codec_enable(codec, 0);
1821 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1822 twl4030_codec_enable(codec, 1);
1823 }
1824
1825 /* sample size */
1826 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1827 format = old_format;
1828 format &= ~TWL4030_DATA_WIDTH;
1829 switch (params_format(params)) {
1830 case SNDRV_PCM_FORMAT_S16_LE:
1831 format |= TWL4030_DATA_WIDTH_16S_16W;
1832 break;
1833 case SNDRV_PCM_FORMAT_S24_LE:
1834 format |= TWL4030_DATA_WIDTH_32S_24W;
1835 break;
1836 default:
1837 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1838 params_format(params));
1839 return -EINVAL;
1840 }
1841
1842 if (format != old_format) {
1843
1844 /* clear CODECPDZ before changing format (codec requirement) */
1845 twl4030_codec_enable(codec, 0);
1846
1847 /* change format */
1848 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1849
1850 /* set CODECPDZ afterwards */
1851 twl4030_codec_enable(codec, 1);
1852 }
1853
1854 /* Store the important parameters for the DAI configuration and set
1855 * the DAI as configured */
1856 twl4030->configured = 1;
1857 twl4030->rate = params_rate(params);
1858 twl4030->sample_bits = hw_param_interval(params,
1859 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1860 twl4030->channels = params_channels(params);
1861
1862 /* If both playback and capture streams are open, and one of them
1863 * is setting the hw parameters right now (since we are here), set
1864 * constraints to the other stream to match the current one. */
1865 if (twl4030->slave_substream)
1866 twl4030_constraints(twl4030, substream);
1867
1868 return 0;
1869 }
1870
1871 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1872 int clk_id, unsigned int freq, int dir)
1873 {
1874 struct snd_soc_codec *codec = codec_dai->codec;
1875 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1876
1877 switch (freq) {
1878 case 19200000:
1879 case 26000000:
1880 case 38400000:
1881 break;
1882 default:
1883 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
1884 return -EINVAL;
1885 }
1886
1887 if ((freq / 1000) != twl4030->sysclk) {
1888 dev_err(codec->dev,
1889 "Mismatch in APLL mclk: %u (configured: %u)\n",
1890 freq, twl4030->sysclk * 1000);
1891 return -EINVAL;
1892 }
1893
1894 return 0;
1895 }
1896
1897 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1898 unsigned int fmt)
1899 {
1900 struct snd_soc_codec *codec = codec_dai->codec;
1901 u8 old_format, format;
1902
1903 /* get format */
1904 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1905 format = old_format;
1906
1907 /* set master/slave audio interface */
1908 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1909 case SND_SOC_DAIFMT_CBM_CFM:
1910 format &= ~(TWL4030_AIF_SLAVE_EN);
1911 format &= ~(TWL4030_CLK256FS_EN);
1912 break;
1913 case SND_SOC_DAIFMT_CBS_CFS:
1914 format |= TWL4030_AIF_SLAVE_EN;
1915 format |= TWL4030_CLK256FS_EN;
1916 break;
1917 default:
1918 return -EINVAL;
1919 }
1920
1921 /* interface format */
1922 format &= ~TWL4030_AIF_FORMAT;
1923 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1924 case SND_SOC_DAIFMT_I2S:
1925 format |= TWL4030_AIF_FORMAT_CODEC;
1926 break;
1927 case SND_SOC_DAIFMT_DSP_A:
1928 format |= TWL4030_AIF_FORMAT_TDM;
1929 break;
1930 default:
1931 return -EINVAL;
1932 }
1933
1934 if (format != old_format) {
1935
1936 /* clear CODECPDZ before changing format (codec requirement) */
1937 twl4030_codec_enable(codec, 0);
1938
1939 /* change format */
1940 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1941
1942 /* set CODECPDZ afterwards */
1943 twl4030_codec_enable(codec, 1);
1944 }
1945
1946 return 0;
1947 }
1948
1949 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1950 {
1951 struct snd_soc_codec *codec = dai->codec;
1952 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1953
1954 if (tristate)
1955 reg |= TWL4030_AIF_TRI_EN;
1956 else
1957 reg &= ~TWL4030_AIF_TRI_EN;
1958
1959 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1960 }
1961
1962 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1963 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1964 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1965 int enable)
1966 {
1967 u8 reg, mask;
1968
1969 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1970
1971 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1972 mask = TWL4030_ARXL1_VRX_EN;
1973 else
1974 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1975
1976 if (enable)
1977 reg |= mask;
1978 else
1979 reg &= ~mask;
1980
1981 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1982 }
1983
1984 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1985 struct snd_soc_dai *dai)
1986 {
1987 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1988 struct snd_soc_device *socdev = rtd->socdev;
1989 struct snd_soc_codec *codec = socdev->card->codec;
1990 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1991 u8 mode;
1992
1993 /* If the system master clock is not 26MHz, the voice PCM interface is
1994 * not avilable.
1995 */
1996 if (twl4030->sysclk != 26000) {
1997 dev_err(codec->dev, "The board is configured for %u Hz, while"
1998 "the Voice interface needs 26MHz APLL mclk\n",
1999 twl4030->sysclk * 1000);
2000 return -EINVAL;
2001 }
2002
2003 /* If the codec mode is not option2, the voice PCM interface is not
2004 * avilable.
2005 */
2006 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2007 & TWL4030_OPT_MODE;
2008
2009 if (mode != TWL4030_OPTION_2) {
2010 printk(KERN_ERR "TWL4030 voice startup: "
2011 "the codec mode is not option2\n");
2012 return -EINVAL;
2013 }
2014
2015 return 0;
2016 }
2017
2018 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2019 struct snd_soc_dai *dai)
2020 {
2021 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2022 struct snd_soc_device *socdev = rtd->socdev;
2023 struct snd_soc_codec *codec = socdev->card->codec;
2024
2025 /* Enable voice digital filters */
2026 twl4030_voice_enable(codec, substream->stream, 0);
2027 }
2028
2029 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2030 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2031 {
2032 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2033 struct snd_soc_device *socdev = rtd->socdev;
2034 struct snd_soc_codec *codec = socdev->card->codec;
2035 u8 old_mode, mode;
2036
2037 /* Enable voice digital filters */
2038 twl4030_voice_enable(codec, substream->stream, 1);
2039
2040 /* bit rate */
2041 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2042 & ~(TWL4030_CODECPDZ);
2043 mode = old_mode;
2044
2045 switch (params_rate(params)) {
2046 case 8000:
2047 mode &= ~(TWL4030_SEL_16K);
2048 break;
2049 case 16000:
2050 mode |= TWL4030_SEL_16K;
2051 break;
2052 default:
2053 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2054 params_rate(params));
2055 return -EINVAL;
2056 }
2057
2058 if (mode != old_mode) {
2059 /* change rate and set CODECPDZ */
2060 twl4030_codec_enable(codec, 0);
2061 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2062 twl4030_codec_enable(codec, 1);
2063 }
2064
2065 return 0;
2066 }
2067
2068 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2069 int clk_id, unsigned int freq, int dir)
2070 {
2071 struct snd_soc_codec *codec = codec_dai->codec;
2072 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2073
2074 if (freq != 26000000) {
2075 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2076 "interface needs 26MHz APLL mclk\n", freq);
2077 return -EINVAL;
2078 }
2079 if ((freq / 1000) != twl4030->sysclk) {
2080 dev_err(codec->dev,
2081 "Mismatch in APLL mclk: %u (configured: %u)\n",
2082 freq, twl4030->sysclk * 1000);
2083 return -EINVAL;
2084 }
2085 return 0;
2086 }
2087
2088 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2089 unsigned int fmt)
2090 {
2091 struct snd_soc_codec *codec = codec_dai->codec;
2092 u8 old_format, format;
2093
2094 /* get format */
2095 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2096 format = old_format;
2097
2098 /* set master/slave audio interface */
2099 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2100 case SND_SOC_DAIFMT_CBM_CFM:
2101 format &= ~(TWL4030_VIF_SLAVE_EN);
2102 break;
2103 case SND_SOC_DAIFMT_CBS_CFS:
2104 format |= TWL4030_VIF_SLAVE_EN;
2105 break;
2106 default:
2107 return -EINVAL;
2108 }
2109
2110 /* clock inversion */
2111 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2112 case SND_SOC_DAIFMT_IB_NF:
2113 format &= ~(TWL4030_VIF_FORMAT);
2114 break;
2115 case SND_SOC_DAIFMT_NB_IF:
2116 format |= TWL4030_VIF_FORMAT;
2117 break;
2118 default:
2119 return -EINVAL;
2120 }
2121
2122 if (format != old_format) {
2123 /* change format and set CODECPDZ */
2124 twl4030_codec_enable(codec, 0);
2125 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2126 twl4030_codec_enable(codec, 1);
2127 }
2128
2129 return 0;
2130 }
2131
2132 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2133 {
2134 struct snd_soc_codec *codec = dai->codec;
2135 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2136
2137 if (tristate)
2138 reg |= TWL4030_VIF_TRI_EN;
2139 else
2140 reg &= ~TWL4030_VIF_TRI_EN;
2141
2142 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2143 }
2144
2145 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
2146 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2147
2148 static struct snd_soc_dai_ops twl4030_dai_ops = {
2149 .startup = twl4030_startup,
2150 .shutdown = twl4030_shutdown,
2151 .hw_params = twl4030_hw_params,
2152 .set_sysclk = twl4030_set_dai_sysclk,
2153 .set_fmt = twl4030_set_dai_fmt,
2154 .set_tristate = twl4030_set_tristate,
2155 };
2156
2157 static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2158 .startup = twl4030_voice_startup,
2159 .shutdown = twl4030_voice_shutdown,
2160 .hw_params = twl4030_voice_hw_params,
2161 .set_sysclk = twl4030_voice_set_dai_sysclk,
2162 .set_fmt = twl4030_voice_set_dai_fmt,
2163 .set_tristate = twl4030_voice_set_tristate,
2164 };
2165
2166 struct snd_soc_dai twl4030_dai[] = {
2167 {
2168 .name = "twl4030",
2169 .playback = {
2170 .stream_name = "HiFi Playback",
2171 .channels_min = 2,
2172 .channels_max = 4,
2173 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2174 .formats = TWL4030_FORMATS,},
2175 .capture = {
2176 .stream_name = "Capture",
2177 .channels_min = 2,
2178 .channels_max = 4,
2179 .rates = TWL4030_RATES,
2180 .formats = TWL4030_FORMATS,},
2181 .ops = &twl4030_dai_ops,
2182 },
2183 {
2184 .name = "twl4030 Voice",
2185 .playback = {
2186 .stream_name = "Voice Playback",
2187 .channels_min = 1,
2188 .channels_max = 1,
2189 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2190 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2191 .capture = {
2192 .stream_name = "Capture",
2193 .channels_min = 1,
2194 .channels_max = 2,
2195 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2196 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2197 .ops = &twl4030_dai_voice_ops,
2198 },
2199 };
2200 EXPORT_SYMBOL_GPL(twl4030_dai);
2201
2202 static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
2203 {
2204 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2205 struct snd_soc_codec *codec = socdev->card->codec;
2206
2207 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2208
2209 return 0;
2210 }
2211
2212 static int twl4030_soc_resume(struct platform_device *pdev)
2213 {
2214 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2215 struct snd_soc_codec *codec = socdev->card->codec;
2216
2217 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2218 return 0;
2219 }
2220
2221 static struct snd_soc_codec *twl4030_codec;
2222
2223 static int twl4030_soc_probe(struct platform_device *pdev)
2224 {
2225 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2226 struct snd_soc_codec *codec;
2227 int ret;
2228
2229 BUG_ON(!twl4030_codec);
2230
2231 codec = twl4030_codec;
2232 socdev->card->codec = codec;
2233
2234 twl4030_init_chip(pdev);
2235 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2236
2237 /* register pcms */
2238 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2239 if (ret < 0) {
2240 dev_err(&pdev->dev, "failed to create pcms\n");
2241 return ret;
2242 }
2243
2244 snd_soc_add_controls(codec, twl4030_snd_controls,
2245 ARRAY_SIZE(twl4030_snd_controls));
2246 twl4030_add_widgets(codec);
2247
2248 return 0;
2249 }
2250
2251 static int twl4030_soc_remove(struct platform_device *pdev)
2252 {
2253 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2254 struct snd_soc_codec *codec = socdev->card->codec;
2255
2256 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2257 snd_soc_free_pcms(socdev);
2258 snd_soc_dapm_free(socdev);
2259
2260 return 0;
2261 }
2262
2263 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2264 {
2265 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
2266 struct snd_soc_codec *codec;
2267 struct twl4030_priv *twl4030;
2268 int ret;
2269
2270 if (!pdata) {
2271 dev_err(&pdev->dev, "platform_data is missing\n");
2272 return -EINVAL;
2273 }
2274
2275 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2276 if (twl4030 == NULL) {
2277 dev_err(&pdev->dev, "Can not allocate memroy\n");
2278 return -ENOMEM;
2279 }
2280
2281 codec = &twl4030->codec;
2282 snd_soc_codec_set_drvdata(codec, twl4030);
2283 codec->dev = &pdev->dev;
2284 twl4030_dai[0].dev = &pdev->dev;
2285 twl4030_dai[1].dev = &pdev->dev;
2286
2287 mutex_init(&codec->mutex);
2288 INIT_LIST_HEAD(&codec->dapm_widgets);
2289 INIT_LIST_HEAD(&codec->dapm_paths);
2290
2291 codec->name = "twl4030";
2292 codec->owner = THIS_MODULE;
2293 codec->read = twl4030_read_reg_cache;
2294 codec->write = twl4030_write;
2295 codec->set_bias_level = twl4030_set_bias_level;
2296 codec->dai = twl4030_dai;
2297 codec->num_dai = ARRAY_SIZE(twl4030_dai);
2298 codec->reg_cache_size = sizeof(twl4030_reg);
2299 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2300 GFP_KERNEL);
2301 if (codec->reg_cache == NULL) {
2302 ret = -ENOMEM;
2303 goto error_cache;
2304 }
2305
2306 platform_set_drvdata(pdev, twl4030);
2307 twl4030_codec = codec;
2308
2309 /* Set the defaults, and power up the codec */
2310 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
2311 codec->bias_level = SND_SOC_BIAS_OFF;
2312
2313 ret = snd_soc_register_codec(codec);
2314 if (ret != 0) {
2315 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2316 goto error_codec;
2317 }
2318
2319 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2320 if (ret != 0) {
2321 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2322 snd_soc_unregister_codec(codec);
2323 goto error_codec;
2324 }
2325
2326 return 0;
2327
2328 error_codec:
2329 twl4030_codec_enable(codec, 0);
2330 kfree(codec->reg_cache);
2331 error_cache:
2332 kfree(twl4030);
2333 return ret;
2334 }
2335
2336 static int __devexit twl4030_codec_remove(struct platform_device *pdev)
2337 {
2338 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
2339
2340 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2341 snd_soc_unregister_codec(&twl4030->codec);
2342 kfree(twl4030->codec.reg_cache);
2343 kfree(twl4030);
2344
2345 twl4030_codec = NULL;
2346 return 0;
2347 }
2348
2349 MODULE_ALIAS("platform:twl4030_codec_audio");
2350
2351 static struct platform_driver twl4030_codec_driver = {
2352 .probe = twl4030_codec_probe,
2353 .remove = __devexit_p(twl4030_codec_remove),
2354 .driver = {
2355 .name = "twl4030_codec_audio",
2356 .owner = THIS_MODULE,
2357 },
2358 };
2359
2360 static int __init twl4030_modinit(void)
2361 {
2362 return platform_driver_register(&twl4030_codec_driver);
2363 }
2364 module_init(twl4030_modinit);
2365
2366 static void __exit twl4030_exit(void)
2367 {
2368 platform_driver_unregister(&twl4030_codec_driver);
2369 }
2370 module_exit(twl4030_exit);
2371
2372 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2373 .probe = twl4030_soc_probe,
2374 .remove = twl4030_soc_remove,
2375 .suspend = twl4030_soc_suspend,
2376 .resume = twl4030_soc_resume,
2377 };
2378 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2379
2380 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2381 MODULE_AUTHOR("Steve Sakoman");
2382 MODULE_LICENSE("GPL");
CJK support for tty framebuffer vt