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ixgbe: Drop RLPML configuration from x540 RXDCTL register configuration
[linux-2.6/cjktty.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
blobe6e12450bf300fc3d897c8fc2b358cb807ec9383
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define MAJ 3
67 #define MIN 9
68 #define BUILD 15
69 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
70 __stringify(BUILD) "-k"
71 const char ixgbe_driver_version[] = DRV_VERSION;
72 static const char ixgbe_copyright[] =
73 "Copyright (c) 1999-2012 Intel Corporation.";
74
75 static const struct ixgbe_info *ixgbe_info_tbl[] = {
76 [board_82598] = &ixgbe_82598_info,
77 [board_82599] = &ixgbe_82599_info,
78 [board_X540] = &ixgbe_X540_info,
79 };
80
81 /* ixgbe_pci_tbl - PCI Device ID Table
82 *
83 * Wildcard entries (PCI_ANY_ID) should come last
84 * Last entry must be all 0s
85 *
86 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
87 * Class, Class Mask, private data (not used) }
88 */
89 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
119 /* required last entry */
120 {0, }
121 };
122 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
123
124 #ifdef CONFIG_IXGBE_DCA
125 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
126 void *p);
127 static struct notifier_block dca_notifier = {
128 .notifier_call = ixgbe_notify_dca,
129 .next = NULL,
130 .priority = 0
131 };
132 #endif
133
134 #ifdef CONFIG_PCI_IOV
135 static unsigned int max_vfs;
136 module_param(max_vfs, uint, 0);
137 MODULE_PARM_DESC(max_vfs,
138 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
139 #endif /* CONFIG_PCI_IOV */
140
141 static unsigned int allow_unsupported_sfp;
142 module_param(allow_unsupported_sfp, uint, 0);
143 MODULE_PARM_DESC(allow_unsupported_sfp,
144 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
145
146 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
147 static int debug = -1;
148 module_param(debug, int, 0);
149 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
150
151 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
152 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
153 MODULE_LICENSE("GPL");
154 MODULE_VERSION(DRV_VERSION);
155
156 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
157 {
158 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
159 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
160 schedule_work(&adapter->service_task);
161 }
162
163 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
164 {
165 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
166
167 /* flush memory to make sure state is correct before next watchdog */
168 smp_mb__before_clear_bit();
169 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
170 }
171
172 struct ixgbe_reg_info {
173 u32 ofs;
174 char *name;
175 };
176
177 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
178
179 /* General Registers */
180 {IXGBE_CTRL, "CTRL"},
181 {IXGBE_STATUS, "STATUS"},
182 {IXGBE_CTRL_EXT, "CTRL_EXT"},
183
184 /* Interrupt Registers */
185 {IXGBE_EICR, "EICR"},
186
187 /* RX Registers */
188 {IXGBE_SRRCTL(0), "SRRCTL"},
189 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
190 {IXGBE_RDLEN(0), "RDLEN"},
191 {IXGBE_RDH(0), "RDH"},
192 {IXGBE_RDT(0), "RDT"},
193 {IXGBE_RXDCTL(0), "RXDCTL"},
194 {IXGBE_RDBAL(0), "RDBAL"},
195 {IXGBE_RDBAH(0), "RDBAH"},
196
197 /* TX Registers */
198 {IXGBE_TDBAL(0), "TDBAL"},
199 {IXGBE_TDBAH(0), "TDBAH"},
200 {IXGBE_TDLEN(0), "TDLEN"},
201 {IXGBE_TDH(0), "TDH"},
202 {IXGBE_TDT(0), "TDT"},
203 {IXGBE_TXDCTL(0), "TXDCTL"},
204
205 /* List Terminator */
206 {}
207 };
208
209
210 /*
211 * ixgbe_regdump - register printout routine
212 */
213 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
214 {
215 int i = 0, j = 0;
216 char rname[16];
217 u32 regs[64];
218
219 switch (reginfo->ofs) {
220 case IXGBE_SRRCTL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
223 break;
224 case IXGBE_DCA_RXCTRL(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
227 break;
228 case IXGBE_RDLEN(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
231 break;
232 case IXGBE_RDH(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
235 break;
236 case IXGBE_RDT(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
239 break;
240 case IXGBE_RXDCTL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
243 break;
244 case IXGBE_RDBAL(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
247 break;
248 case IXGBE_RDBAH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
251 break;
252 case IXGBE_TDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
255 break;
256 case IXGBE_TDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
259 break;
260 case IXGBE_TDLEN(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
263 break;
264 case IXGBE_TDH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
267 break;
268 case IXGBE_TDT(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
271 break;
272 case IXGBE_TXDCTL(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
275 break;
276 default:
277 pr_info("%-15s %08x\n", reginfo->name,
278 IXGBE_READ_REG(hw, reginfo->ofs));
279 return;
280 }
281
282 for (i = 0; i < 8; i++) {
283 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
284 pr_err("%-15s", rname);
285 for (j = 0; j < 8; j++)
286 pr_cont(" %08x", regs[i*8+j]);
287 pr_cont("\n");
288 }
289
290 }
291
292 /*
293 * ixgbe_dump - Print registers, tx-rings and rx-rings
294 */
295 static void ixgbe_dump(struct ixgbe_adapter *adapter)
296 {
297 struct net_device *netdev = adapter->netdev;
298 struct ixgbe_hw *hw = &adapter->hw;
299 struct ixgbe_reg_info *reginfo;
300 int n = 0;
301 struct ixgbe_ring *tx_ring;
302 struct ixgbe_tx_buffer *tx_buffer;
303 union ixgbe_adv_tx_desc *tx_desc;
304 struct my_u0 { u64 a; u64 b; } *u0;
305 struct ixgbe_ring *rx_ring;
306 union ixgbe_adv_rx_desc *rx_desc;
307 struct ixgbe_rx_buffer *rx_buffer_info;
308 u32 staterr;
309 int i = 0;
310
311 if (!netif_msg_hw(adapter))
312 return;
313
314 /* Print netdevice Info */
315 if (netdev) {
316 dev_info(&adapter->pdev->dev, "Net device Info\n");
317 pr_info("Device Name state "
318 "trans_start last_rx\n");
319 pr_info("%-15s %016lX %016lX %016lX\n",
320 netdev->name,
321 netdev->state,
322 netdev->trans_start,
323 netdev->last_rx);
324 }
325
326 /* Print Registers */
327 dev_info(&adapter->pdev->dev, "Register Dump\n");
328 pr_info(" Register Name Value\n");
329 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
330 reginfo->name; reginfo++) {
331 ixgbe_regdump(hw, reginfo);
332 }
333
334 /* Print TX Ring Summary */
335 if (!netdev || !netif_running(netdev))
336 goto exit;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
339 pr_info(" %s %s %s %s\n",
340 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
341 "leng", "ntw", "timestamp");
342 for (n = 0; n < adapter->num_tx_queues; n++) {
343 tx_ring = adapter->tx_ring[n];
344 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
345 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
346 n, tx_ring->next_to_use, tx_ring->next_to_clean,
347 (u64)dma_unmap_addr(tx_buffer, dma),
348 dma_unmap_len(tx_buffer, len),
349 tx_buffer->next_to_watch,
350 (u64)tx_buffer->time_stamp);
351 }
352
353 /* Print TX Rings */
354 if (!netif_msg_tx_done(adapter))
355 goto rx_ring_summary;
356
357 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
358
359 /* Transmit Descriptor Formats
360 *
361 * 82598 Advanced Transmit Descriptor
362 * +--------------------------------------------------------------+
363 * 0 | Buffer Address [63:0] |
364 * +--------------------------------------------------------------+
365 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
366 * +--------------------------------------------------------------+
367 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
368 *
369 * 82598 Advanced Transmit Descriptor (Write-Back Format)
370 * +--------------------------------------------------------------+
371 * 0 | RSV [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | RSV | STA | NXTSEQ |
374 * +--------------------------------------------------------------+
375 * 63 36 35 32 31 0
376 *
377 * 82599+ Advanced Transmit Descriptor
378 * +--------------------------------------------------------------+
379 * 0 | Buffer Address [63:0] |
380 * +--------------------------------------------------------------+
381 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
382 * +--------------------------------------------------------------+
383 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
384 *
385 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
386 * +--------------------------------------------------------------+
387 * 0 | RSV [63:0] |
388 * +--------------------------------------------------------------+
389 * 8 | RSV | STA | RSV |
390 * +--------------------------------------------------------------+
391 * 63 36 35 32 31 0
392 */
393
394 for (n = 0; n < adapter->num_tx_queues; n++) {
395 tx_ring = adapter->tx_ring[n];
396 pr_info("------------------------------------\n");
397 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
398 pr_info("------------------------------------\n");
399 pr_info("%s%s %s %s %s %s\n",
400 "T [desc] [address 63:0 ] ",
401 "[PlPOIdStDDt Ln] [bi->dma ] ",
402 "leng", "ntw", "timestamp", "bi->skb");
403
404 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
405 tx_desc = IXGBE_TX_DESC(tx_ring, i);
406 tx_buffer = &tx_ring->tx_buffer_info[i];
407 u0 = (struct my_u0 *)tx_desc;
408 if (dma_unmap_len(tx_buffer, len) > 0) {
409 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
410 i,
411 le64_to_cpu(u0->a),
412 le64_to_cpu(u0->b),
413 (u64)dma_unmap_addr(tx_buffer, dma),
414 dma_unmap_len(tx_buffer, len),
415 tx_buffer->next_to_watch,
416 (u64)tx_buffer->time_stamp,
417 tx_buffer->skb);
418 if (i == tx_ring->next_to_use &&
419 i == tx_ring->next_to_clean)
420 pr_cont(" NTC/U\n");
421 else if (i == tx_ring->next_to_use)
422 pr_cont(" NTU\n");
423 else if (i == tx_ring->next_to_clean)
424 pr_cont(" NTC\n");
425 else
426 pr_cont("\n");
427
428 if (netif_msg_pktdata(adapter) &&
429 tx_buffer->skb)
430 print_hex_dump(KERN_INFO, "",
431 DUMP_PREFIX_ADDRESS, 16, 1,
432 tx_buffer->skb->data,
433 dma_unmap_len(tx_buffer, len),
434 true);
435 }
436 }
437 }
438
439 /* Print RX Rings Summary */
440 rx_ring_summary:
441 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
442 pr_info("Queue [NTU] [NTC]\n");
443 for (n = 0; n < adapter->num_rx_queues; n++) {
444 rx_ring = adapter->rx_ring[n];
445 pr_info("%5d %5X %5X\n",
446 n, rx_ring->next_to_use, rx_ring->next_to_clean);
447 }
448
449 /* Print RX Rings */
450 if (!netif_msg_rx_status(adapter))
451 goto exit;
452
453 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
454
455 /* Receive Descriptor Formats
456 *
457 * 82598 Advanced Receive Descriptor (Read) Format
458 * 63 1 0
459 * +-----------------------------------------------------+
460 * 0 | Packet Buffer Address [63:1] |A0/NSE|
461 * +----------------------------------------------+------+
462 * 8 | Header Buffer Address [63:1] | DD |
463 * +-----------------------------------------------------+
464 *
465 *
466 * 82598 Advanced Receive Descriptor (Write-Back) Format
467 *
468 * 63 48 47 32 31 30 21 20 16 15 4 3 0
469 * +------------------------------------------------------+
470 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
471 * | Packet | IP | | | | Type | Type |
472 * | Checksum | Ident | | | | | |
473 * +------------------------------------------------------+
474 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
475 * +------------------------------------------------------+
476 * 63 48 47 32 31 20 19 0
477 *
478 * 82599+ Advanced Receive Descriptor (Read) Format
479 * 63 1 0
480 * +-----------------------------------------------------+
481 * 0 | Packet Buffer Address [63:1] |A0/NSE|
482 * +----------------------------------------------+------+
483 * 8 | Header Buffer Address [63:1] | DD |
484 * +-----------------------------------------------------+
485 *
486 *
487 * 82599+ Advanced Receive Descriptor (Write-Back) Format
488 *
489 * 63 48 47 32 31 30 21 20 17 16 4 3 0
490 * +------------------------------------------------------+
491 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
492 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
493 * |/ Flow Dir Flt ID | | | | | |
494 * +------------------------------------------------------+
495 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
496 * +------------------------------------------------------+
497 * 63 48 47 32 31 20 19 0
498 */
499
500 for (n = 0; n < adapter->num_rx_queues; n++) {
501 rx_ring = adapter->rx_ring[n];
502 pr_info("------------------------------------\n");
503 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
504 pr_info("------------------------------------\n");
505 pr_info("%s%s%s",
506 "R [desc] [ PktBuf A0] ",
507 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
508 "<-- Adv Rx Read format\n");
509 pr_info("%s%s%s",
510 "RWB[desc] [PcsmIpSHl PtRs] ",
511 "[vl er S cks ln] ---------------- [bi->skb ] ",
512 "<-- Adv Rx Write-Back format\n");
513
514 for (i = 0; i < rx_ring->count; i++) {
515 rx_buffer_info = &rx_ring->rx_buffer_info[i];
516 rx_desc = IXGBE_RX_DESC(rx_ring, i);
517 u0 = (struct my_u0 *)rx_desc;
518 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
519 if (staterr & IXGBE_RXD_STAT_DD) {
520 /* Descriptor Done */
521 pr_info("RWB[0x%03X] %016llX "
522 "%016llX ---------------- %p", i,
523 le64_to_cpu(u0->a),
524 le64_to_cpu(u0->b),
525 rx_buffer_info->skb);
526 } else {
527 pr_info("R [0x%03X] %016llX "
528 "%016llX %016llX %p", i,
529 le64_to_cpu(u0->a),
530 le64_to_cpu(u0->b),
531 (u64)rx_buffer_info->dma,
532 rx_buffer_info->skb);
533
534 if (netif_msg_pktdata(adapter) &&
535 rx_buffer_info->dma) {
536 print_hex_dump(KERN_INFO, "",
537 DUMP_PREFIX_ADDRESS, 16, 1,
538 page_address(rx_buffer_info->page) +
539 rx_buffer_info->page_offset,
540 ixgbe_rx_bufsz(rx_ring), true);
541 }
542 }
543
544 if (i == rx_ring->next_to_use)
545 pr_cont(" NTU\n");
546 else if (i == rx_ring->next_to_clean)
547 pr_cont(" NTC\n");
548 else
549 pr_cont("\n");
550
551 }
552 }
553
554 exit:
555 return;
556 }
557
558 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
559 {
560 u32 ctrl_ext;
561
562 /* Let firmware take over control of h/w */
563 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
565 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
566 }
567
568 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
569 {
570 u32 ctrl_ext;
571
572 /* Let firmware know the driver has taken over */
573 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
575 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
576 }
577
578 /**
579 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
580 * @adapter: pointer to adapter struct
581 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
582 * @queue: queue to map the corresponding interrupt to
583 * @msix_vector: the vector to map to the corresponding queue
584 *
585 */
586 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
587 u8 queue, u8 msix_vector)
588 {
589 u32 ivar, index;
590 struct ixgbe_hw *hw = &adapter->hw;
591 switch (hw->mac.type) {
592 case ixgbe_mac_82598EB:
593 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
594 if (direction == -1)
595 direction = 0;
596 index = (((direction * 64) + queue) >> 2) & 0x1F;
597 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
598 ivar &= ~(0xFF << (8 * (queue & 0x3)));
599 ivar |= (msix_vector << (8 * (queue & 0x3)));
600 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
601 break;
602 case ixgbe_mac_82599EB:
603 case ixgbe_mac_X540:
604 if (direction == -1) {
605 /* other causes */
606 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
607 index = ((queue & 1) * 8);
608 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
609 ivar &= ~(0xFF << index);
610 ivar |= (msix_vector << index);
611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
612 break;
613 } else {
614 /* tx or rx causes */
615 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
616 index = ((16 * (queue & 1)) + (8 * direction));
617 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
618 ivar &= ~(0xFF << index);
619 ivar |= (msix_vector << index);
620 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
621 break;
622 }
623 default:
624 break;
625 }
626 }
627
628 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
629 u64 qmask)
630 {
631 u32 mask;
632
633 switch (adapter->hw.mac.type) {
634 case ixgbe_mac_82598EB:
635 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
637 break;
638 case ixgbe_mac_82599EB:
639 case ixgbe_mac_X540:
640 mask = (qmask & 0xFFFFFFFF);
641 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
642 mask = (qmask >> 32);
643 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
644 break;
645 default:
646 break;
647 }
648 }
649
650 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
651 struct ixgbe_tx_buffer *tx_buffer)
652 {
653 if (tx_buffer->skb) {
654 dev_kfree_skb_any(tx_buffer->skb);
655 if (dma_unmap_len(tx_buffer, len))
656 dma_unmap_single(ring->dev,
657 dma_unmap_addr(tx_buffer, dma),
658 dma_unmap_len(tx_buffer, len),
659 DMA_TO_DEVICE);
660 } else if (dma_unmap_len(tx_buffer, len)) {
661 dma_unmap_page(ring->dev,
662 dma_unmap_addr(tx_buffer, dma),
663 dma_unmap_len(tx_buffer, len),
664 DMA_TO_DEVICE);
665 }
666 tx_buffer->next_to_watch = NULL;
667 tx_buffer->skb = NULL;
668 dma_unmap_len_set(tx_buffer, len, 0);
669 /* tx_buffer must be completely set up in the transmit path */
670 }
671
672 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
673 {
674 struct ixgbe_hw *hw = &adapter->hw;
675 struct ixgbe_hw_stats *hwstats = &adapter->stats;
676 int i;
677 u32 data;
678
679 if ((hw->fc.current_mode != ixgbe_fc_full) &&
680 (hw->fc.current_mode != ixgbe_fc_rx_pause))
681 return;
682
683 switch (hw->mac.type) {
684 case ixgbe_mac_82598EB:
685 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
686 break;
687 default:
688 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
689 }
690 hwstats->lxoffrxc += data;
691
692 /* refill credits (no tx hang) if we received xoff */
693 if (!data)
694 return;
695
696 for (i = 0; i < adapter->num_tx_queues; i++)
697 clear_bit(__IXGBE_HANG_CHECK_ARMED,
698 &adapter->tx_ring[i]->state);
699 }
700
701 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
702 {
703 struct ixgbe_hw *hw = &adapter->hw;
704 struct ixgbe_hw_stats *hwstats = &adapter->stats;
705 u32 xoff[8] = {0};
706 int i;
707 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
708
709 if (adapter->ixgbe_ieee_pfc)
710 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
711
712 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
713 ixgbe_update_xoff_rx_lfc(adapter);
714 return;
715 }
716
717 /* update stats for each tc, only valid with PFC enabled */
718 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
719 switch (hw->mac.type) {
720 case ixgbe_mac_82598EB:
721 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
722 break;
723 default:
724 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
725 }
726 hwstats->pxoffrxc[i] += xoff[i];
727 }
728
729 /* disarm tx queues that have received xoff frames */
730 for (i = 0; i < adapter->num_tx_queues; i++) {
731 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
732 u8 tc = tx_ring->dcb_tc;
733
734 if (xoff[tc])
735 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
736 }
737 }
738
739 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
740 {
741 return ring->stats.packets;
742 }
743
744 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
745 {
746 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
747 struct ixgbe_hw *hw = &adapter->hw;
748
749 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
750 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
751
752 if (head != tail)
753 return (head < tail) ?
754 tail - head : (tail + ring->count - head);
755
756 return 0;
757 }
758
759 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
760 {
761 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
762 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
763 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
764 bool ret = false;
765
766 clear_check_for_tx_hang(tx_ring);
767
768 /*
769 * Check for a hung queue, but be thorough. This verifies
770 * that a transmit has been completed since the previous
771 * check AND there is at least one packet pending. The
772 * ARMED bit is set to indicate a potential hang. The
773 * bit is cleared if a pause frame is received to remove
774 * false hang detection due to PFC or 802.3x frames. By
775 * requiring this to fail twice we avoid races with
776 * pfc clearing the ARMED bit and conditions where we
777 * run the check_tx_hang logic with a transmit completion
778 * pending but without time to complete it yet.
779 */
780 if ((tx_done_old == tx_done) && tx_pending) {
781 /* make sure it is true for two checks in a row */
782 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
783 &tx_ring->state);
784 } else {
785 /* update completed stats and continue */
786 tx_ring->tx_stats.tx_done_old = tx_done;
787 /* reset the countdown */
788 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
789 }
790
791 return ret;
792 }
793
794 /**
795 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
796 * @adapter: driver private struct
797 **/
798 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
799 {
800
801 /* Do the reset outside of interrupt context */
802 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
803 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
804 ixgbe_service_event_schedule(adapter);
805 }
806 }
807
808 /**
809 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
810 * @q_vector: structure containing interrupt and ring information
811 * @tx_ring: tx ring to clean
812 **/
813 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
814 struct ixgbe_ring *tx_ring)
815 {
816 struct ixgbe_adapter *adapter = q_vector->adapter;
817 struct ixgbe_tx_buffer *tx_buffer;
818 union ixgbe_adv_tx_desc *tx_desc;
819 unsigned int total_bytes = 0, total_packets = 0;
820 unsigned int budget = q_vector->tx.work_limit;
821 unsigned int i = tx_ring->next_to_clean;
822
823 if (test_bit(__IXGBE_DOWN, &adapter->state))
824 return true;
825
826 tx_buffer = &tx_ring->tx_buffer_info[i];
827 tx_desc = IXGBE_TX_DESC(tx_ring, i);
828 i -= tx_ring->count;
829
830 do {
831 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
832
833 /* if next_to_watch is not set then there is no work pending */
834 if (!eop_desc)
835 break;
836
837 /* prevent any other reads prior to eop_desc */
838 rmb();
839
840 /* if DD is not set pending work has not been completed */
841 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
842 break;
843
844 /* clear next_to_watch to prevent false hangs */
845 tx_buffer->next_to_watch = NULL;
846
847 /* update the statistics for this packet */
848 total_bytes += tx_buffer->bytecount;
849 total_packets += tx_buffer->gso_segs;
850
851 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
852 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
853
854 /* free the skb */
855 dev_kfree_skb_any(tx_buffer->skb);
856
857 /* unmap skb header data */
858 dma_unmap_single(tx_ring->dev,
859 dma_unmap_addr(tx_buffer, dma),
860 dma_unmap_len(tx_buffer, len),
861 DMA_TO_DEVICE);
862
863 /* clear tx_buffer data */
864 tx_buffer->skb = NULL;
865 dma_unmap_len_set(tx_buffer, len, 0);
866
867 /* unmap remaining buffers */
868 while (tx_desc != eop_desc) {
869 tx_buffer++;
870 tx_desc++;
871 i++;
872 if (unlikely(!i)) {
873 i -= tx_ring->count;
874 tx_buffer = tx_ring->tx_buffer_info;
875 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
876 }
877
878 /* unmap any remaining paged data */
879 if (dma_unmap_len(tx_buffer, len)) {
880 dma_unmap_page(tx_ring->dev,
881 dma_unmap_addr(tx_buffer, dma),
882 dma_unmap_len(tx_buffer, len),
883 DMA_TO_DEVICE);
884 dma_unmap_len_set(tx_buffer, len, 0);
885 }
886 }
887
888 /* move us one more past the eop_desc for start of next pkt */
889 tx_buffer++;
890 tx_desc++;
891 i++;
892 if (unlikely(!i)) {
893 i -= tx_ring->count;
894 tx_buffer = tx_ring->tx_buffer_info;
895 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
896 }
897
898 /* issue prefetch for next Tx descriptor */
899 prefetch(tx_desc);
900
901 /* update budget accounting */
902 budget--;
903 } while (likely(budget));
904
905 i += tx_ring->count;
906 tx_ring->next_to_clean = i;
907 u64_stats_update_begin(&tx_ring->syncp);
908 tx_ring->stats.bytes += total_bytes;
909 tx_ring->stats.packets += total_packets;
910 u64_stats_update_end(&tx_ring->syncp);
911 q_vector->tx.total_bytes += total_bytes;
912 q_vector->tx.total_packets += total_packets;
913
914 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
915 /* schedule immediate reset if we believe we hung */
916 struct ixgbe_hw *hw = &adapter->hw;
917 e_err(drv, "Detected Tx Unit Hang\n"
918 " Tx Queue <%d>\n"
919 " TDH, TDT <%x>, <%x>\n"
920 " next_to_use <%x>\n"
921 " next_to_clean <%x>\n"
922 "tx_buffer_info[next_to_clean]\n"
923 " time_stamp <%lx>\n"
924 " jiffies <%lx>\n",
925 tx_ring->queue_index,
926 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
927 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
928 tx_ring->next_to_use, i,
929 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
930
931 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
932
933 e_info(probe,
934 "tx hang %d detected on queue %d, resetting adapter\n",
935 adapter->tx_timeout_count + 1, tx_ring->queue_index);
936
937 /* schedule immediate reset if we believe we hung */
938 ixgbe_tx_timeout_reset(adapter);
939
940 /* the adapter is about to reset, no point in enabling stuff */
941 return true;
942 }
943
944 netdev_tx_completed_queue(txring_txq(tx_ring),
945 total_packets, total_bytes);
946
947 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
948 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
949 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
950 /* Make sure that anybody stopping the queue after this
951 * sees the new next_to_clean.
952 */
953 smp_mb();
954 if (__netif_subqueue_stopped(tx_ring->netdev,
955 tx_ring->queue_index)
956 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
957 netif_wake_subqueue(tx_ring->netdev,
958 tx_ring->queue_index);
959 ++tx_ring->tx_stats.restart_queue;
960 }
961 }
962
963 return !!budget;
964 }
965
966 #ifdef CONFIG_IXGBE_DCA
967 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
968 struct ixgbe_ring *tx_ring,
969 int cpu)
970 {
971 struct ixgbe_hw *hw = &adapter->hw;
972 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
973 u16 reg_offset;
974
975 switch (hw->mac.type) {
976 case ixgbe_mac_82598EB:
977 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
978 break;
979 case ixgbe_mac_82599EB:
980 case ixgbe_mac_X540:
981 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
982 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
983 break;
984 default:
985 /* for unknown hardware do not write register */
986 return;
987 }
988
989 /*
990 * We can enable relaxed ordering for reads, but not writes when
991 * DCA is enabled. This is due to a known issue in some chipsets
992 * which will cause the DCA tag to be cleared.
993 */
994 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
995 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
996 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
997
998 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
999 }
1000
1001 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1002 struct ixgbe_ring *rx_ring,
1003 int cpu)
1004 {
1005 struct ixgbe_hw *hw = &adapter->hw;
1006 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1007 u8 reg_idx = rx_ring->reg_idx;
1008
1009
1010 switch (hw->mac.type) {
1011 case ixgbe_mac_82599EB:
1012 case ixgbe_mac_X540:
1013 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1014 break;
1015 default:
1016 break;
1017 }
1018
1019 /*
1020 * We can enable relaxed ordering for reads, but not writes when
1021 * DCA is enabled. This is due to a known issue in some chipsets
1022 * which will cause the DCA tag to be cleared.
1023 */
1024 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1025 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1026
1027 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1028 }
1029
1030 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1031 {
1032 struct ixgbe_adapter *adapter = q_vector->adapter;
1033 struct ixgbe_ring *ring;
1034 int cpu = get_cpu();
1035
1036 if (q_vector->cpu == cpu)
1037 goto out_no_update;
1038
1039 ixgbe_for_each_ring(ring, q_vector->tx)
1040 ixgbe_update_tx_dca(adapter, ring, cpu);
1041
1042 ixgbe_for_each_ring(ring, q_vector->rx)
1043 ixgbe_update_rx_dca(adapter, ring, cpu);
1044
1045 q_vector->cpu = cpu;
1046 out_no_update:
1047 put_cpu();
1048 }
1049
1050 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1051 {
1052 int i;
1053
1054 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1055 return;
1056
1057 /* always use CB2 mode, difference is masked in the CB driver */
1058 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1059
1060 for (i = 0; i < adapter->num_q_vectors; i++) {
1061 adapter->q_vector[i]->cpu = -1;
1062 ixgbe_update_dca(adapter->q_vector[i]);
1063 }
1064 }
1065
1066 static int __ixgbe_notify_dca(struct device *dev, void *data)
1067 {
1068 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1069 unsigned long event = *(unsigned long *)data;
1070
1071 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1072 return 0;
1073
1074 switch (event) {
1075 case DCA_PROVIDER_ADD:
1076 /* if we're already enabled, don't do it again */
1077 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1078 break;
1079 if (dca_add_requester(dev) == 0) {
1080 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1081 ixgbe_setup_dca(adapter);
1082 break;
1083 }
1084 /* Fall Through since DCA is disabled. */
1085 case DCA_PROVIDER_REMOVE:
1086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1087 dca_remove_requester(dev);
1088 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1090 }
1091 break;
1092 }
1093
1094 return 0;
1095 }
1096
1097 #endif /* CONFIG_IXGBE_DCA */
1098 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1101 {
1102 if (ring->netdev->features & NETIF_F_RXHASH)
1103 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1104 }
1105
1106 #ifdef IXGBE_FCOE
1107 /**
1108 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1109 * @ring: structure containing ring specific data
1110 * @rx_desc: advanced rx descriptor
1111 *
1112 * Returns : true if it is FCoE pkt
1113 */
1114 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1115 union ixgbe_adv_rx_desc *rx_desc)
1116 {
1117 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1118
1119 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1120 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1121 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1122 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1123 }
1124
1125 #endif /* IXGBE_FCOE */
1126 /**
1127 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1128 * @ring: structure containing ring specific data
1129 * @rx_desc: current Rx descriptor being processed
1130 * @skb: skb currently being received and modified
1131 **/
1132 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1133 union ixgbe_adv_rx_desc *rx_desc,
1134 struct sk_buff *skb)
1135 {
1136 skb_checksum_none_assert(skb);
1137
1138 /* Rx csum disabled */
1139 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1140 return;
1141
1142 /* if IP and error */
1143 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1144 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1145 ring->rx_stats.csum_err++;
1146 return;
1147 }
1148
1149 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1150 return;
1151
1152 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1153 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1154
1155 /*
1156 * 82599 errata, UDP frames with a 0 checksum can be marked as
1157 * checksum errors.
1158 */
1159 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1160 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1161 return;
1162
1163 ring->rx_stats.csum_err++;
1164 return;
1165 }
1166
1167 /* It must be a TCP or UDP packet with a valid checksum */
1168 skb->ip_summed = CHECKSUM_UNNECESSARY;
1169 }
1170
1171 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1172 {
1173 rx_ring->next_to_use = val;
1174
1175 /* update next to alloc since we have filled the ring */
1176 rx_ring->next_to_alloc = val;
1177 /*
1178 * Force memory writes to complete before letting h/w
1179 * know there are new descriptors to fetch. (Only
1180 * applicable for weak-ordered memory model archs,
1181 * such as IA-64).
1182 */
1183 wmb();
1184 writel(val, rx_ring->tail);
1185 }
1186
1187 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1188 struct ixgbe_rx_buffer *bi)
1189 {
1190 struct page *page = bi->page;
1191 dma_addr_t dma = bi->dma;
1192
1193 /* since we are recycling buffers we should seldom need to alloc */
1194 if (likely(dma))
1195 return true;
1196
1197 /* alloc new page for storage */
1198 if (likely(!page)) {
1199 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1200 bi->skb, ixgbe_rx_pg_order(rx_ring));
1201 if (unlikely(!page)) {
1202 rx_ring->rx_stats.alloc_rx_page_failed++;
1203 return false;
1204 }
1205 bi->page = page;
1206 }
1207
1208 /* map page for use */
1209 dma = dma_map_page(rx_ring->dev, page, 0,
1210 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1211
1212 /*
1213 * if mapping failed free memory back to system since
1214 * there isn't much point in holding memory we can't use
1215 */
1216 if (dma_mapping_error(rx_ring->dev, dma)) {
1217 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1218 bi->page = NULL;
1219
1220 rx_ring->rx_stats.alloc_rx_page_failed++;
1221 return false;
1222 }
1223
1224 bi->dma = dma;
1225 bi->page_offset = 0;
1226
1227 return true;
1228 }
1229
1230 /**
1231 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1232 * @rx_ring: ring to place buffers on
1233 * @cleaned_count: number of buffers to replace
1234 **/
1235 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1236 {
1237 union ixgbe_adv_rx_desc *rx_desc;
1238 struct ixgbe_rx_buffer *bi;
1239 u16 i = rx_ring->next_to_use;
1240
1241 /* nothing to do */
1242 if (!cleaned_count)
1243 return;
1244
1245 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1246 bi = &rx_ring->rx_buffer_info[i];
1247 i -= rx_ring->count;
1248
1249 do {
1250 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1251 break;
1252
1253 /*
1254 * Refresh the desc even if buffer_addrs didn't change
1255 * because each write-back erases this info.
1256 */
1257 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1258
1259 rx_desc++;
1260 bi++;
1261 i++;
1262 if (unlikely(!i)) {
1263 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1264 bi = rx_ring->rx_buffer_info;
1265 i -= rx_ring->count;
1266 }
1267
1268 /* clear the hdr_addr for the next_to_use descriptor */
1269 rx_desc->read.hdr_addr = 0;
1270
1271 cleaned_count--;
1272 } while (cleaned_count);
1273
1274 i += rx_ring->count;
1275
1276 if (rx_ring->next_to_use != i)
1277 ixgbe_release_rx_desc(rx_ring, i);
1278 }
1279
1280 /**
1281 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1282 * @data: pointer to the start of the headers
1283 * @max_len: total length of section to find headers in
1284 *
1285 * This function is meant to determine the length of headers that will
1286 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1287 * motivation of doing this is to only perform one pull for IPv4 TCP
1288 * packets so that we can do basic things like calculating the gso_size
1289 * based on the average data per packet.
1290 **/
1291 static unsigned int ixgbe_get_headlen(unsigned char *data,
1292 unsigned int max_len)
1293 {
1294 union {
1295 unsigned char *network;
1296 /* l2 headers */
1297 struct ethhdr *eth;
1298 struct vlan_hdr *vlan;
1299 /* l3 headers */
1300 struct iphdr *ipv4;
1301 struct ipv6hdr *ipv6;
1302 } hdr;
1303 __be16 protocol;
1304 u8 nexthdr = 0; /* default to not TCP */
1305 u8 hlen;
1306
1307 /* this should never happen, but better safe than sorry */
1308 if (max_len < ETH_HLEN)
1309 return max_len;
1310
1311 /* initialize network frame pointer */
1312 hdr.network = data;
1313
1314 /* set first protocol and move network header forward */
1315 protocol = hdr.eth->h_proto;
1316 hdr.network += ETH_HLEN;
1317
1318 /* handle any vlan tag if present */
1319 if (protocol == __constant_htons(ETH_P_8021Q)) {
1320 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1321 return max_len;
1322
1323 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1324 hdr.network += VLAN_HLEN;
1325 }
1326
1327 /* handle L3 protocols */
1328 if (protocol == __constant_htons(ETH_P_IP)) {
1329 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1330 return max_len;
1331
1332 /* access ihl as a u8 to avoid unaligned access on ia64 */
1333 hlen = (hdr.network[0] & 0x0F) << 2;
1334
1335 /* verify hlen meets minimum size requirements */
1336 if (hlen < sizeof(struct iphdr))
1337 return hdr.network - data;
1338
1339 /* record next protocol */
1340 nexthdr = hdr.ipv4->protocol;
1341 hdr.network += hlen;
1342 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1343 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1344 return max_len;
1345
1346 /* record next protocol */
1347 nexthdr = hdr.ipv6->nexthdr;
1348 hdr.network += sizeof(struct ipv6hdr);
1349 #ifdef IXGBE_FCOE
1350 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1351 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1352 return max_len;
1353 hdr.network += FCOE_HEADER_LEN;
1354 #endif
1355 } else {
1356 return hdr.network - data;
1357 }
1358
1359 /* finally sort out TCP/UDP */
1360 if (nexthdr == IPPROTO_TCP) {
1361 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1362 return max_len;
1363
1364 /* access doff as a u8 to avoid unaligned access on ia64 */
1365 hlen = (hdr.network[12] & 0xF0) >> 2;
1366
1367 /* verify hlen meets minimum size requirements */
1368 if (hlen < sizeof(struct tcphdr))
1369 return hdr.network - data;
1370
1371 hdr.network += hlen;
1372 } else if (nexthdr == IPPROTO_UDP) {
1373 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1374 return max_len;
1375
1376 hdr.network += sizeof(struct udphdr);
1377 }
1378
1379 /*
1380 * If everything has gone correctly hdr.network should be the
1381 * data section of the packet and will be the end of the header.
1382 * If not then it probably represents the end of the last recognized
1383 * header.
1384 */
1385 if ((hdr.network - data) < max_len)
1386 return hdr.network - data;
1387 else
1388 return max_len;
1389 }
1390
1391 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1392 struct sk_buff *skb)
1393 {
1394 u16 hdr_len = skb_headlen(skb);
1395
1396 /* set gso_size to avoid messing up TCP MSS */
1397 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1398 IXGBE_CB(skb)->append_cnt);
1399 }
1400
1401 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1402 struct sk_buff *skb)
1403 {
1404 /* if append_cnt is 0 then frame is not RSC */
1405 if (!IXGBE_CB(skb)->append_cnt)
1406 return;
1407
1408 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1409 rx_ring->rx_stats.rsc_flush++;
1410
1411 ixgbe_set_rsc_gso_size(rx_ring, skb);
1412
1413 /* gso_size is computed using append_cnt so always clear it last */
1414 IXGBE_CB(skb)->append_cnt = 0;
1415 }
1416
1417 /**
1418 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1419 * @rx_ring: rx descriptor ring packet is being transacted on
1420 * @rx_desc: pointer to the EOP Rx descriptor
1421 * @skb: pointer to current skb being populated
1422 *
1423 * This function checks the ring, descriptor, and packet information in
1424 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1425 * other fields within the skb.
1426 **/
1427 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1428 union ixgbe_adv_rx_desc *rx_desc,
1429 struct sk_buff *skb)
1430 {
1431 struct net_device *dev = rx_ring->netdev;
1432
1433 ixgbe_update_rsc_stats(rx_ring, skb);
1434
1435 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1436
1437 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1438
1439 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
1440
1441 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1442 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1443 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1444 __vlan_hwaccel_put_tag(skb, vid);
1445 }
1446
1447 skb_record_rx_queue(skb, rx_ring->queue_index);
1448
1449 skb->protocol = eth_type_trans(skb, dev);
1450 }
1451
1452 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1453 struct sk_buff *skb)
1454 {
1455 struct ixgbe_adapter *adapter = q_vector->adapter;
1456
1457 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1458 napi_gro_receive(&q_vector->napi, skb);
1459 else
1460 netif_rx(skb);
1461 }
1462
1463 /**
1464 * ixgbe_is_non_eop - process handling of non-EOP buffers
1465 * @rx_ring: Rx ring being processed
1466 * @rx_desc: Rx descriptor for current buffer
1467 * @skb: Current socket buffer containing buffer in progress
1468 *
1469 * This function updates next to clean. If the buffer is an EOP buffer
1470 * this function exits returning false, otherwise it will place the
1471 * sk_buff in the next buffer to be chained and return true indicating
1472 * that this is in fact a non-EOP buffer.
1473 **/
1474 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1475 union ixgbe_adv_rx_desc *rx_desc,
1476 struct sk_buff *skb)
1477 {
1478 u32 ntc = rx_ring->next_to_clean + 1;
1479
1480 /* fetch, update, and store next to clean */
1481 ntc = (ntc < rx_ring->count) ? ntc : 0;
1482 rx_ring->next_to_clean = ntc;
1483
1484 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1485
1486 /* update RSC append count if present */
1487 if (ring_is_rsc_enabled(rx_ring)) {
1488 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1489 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1490
1491 if (unlikely(rsc_enabled)) {
1492 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1493
1494 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1495 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1496
1497 /* update ntc based on RSC value */
1498 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1499 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1500 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1501 }
1502 }
1503
1504 /* if we are the last buffer then there is nothing else to do */
1505 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1506 return false;
1507
1508 /* place skb in next buffer to be received */
1509 rx_ring->rx_buffer_info[ntc].skb = skb;
1510 rx_ring->rx_stats.non_eop_descs++;
1511
1512 return true;
1513 }
1514
1515 /**
1516 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1517 * @rx_ring: rx descriptor ring packet is being transacted on
1518 * @skb: pointer to current skb being adjusted
1519 *
1520 * This function is an ixgbe specific version of __pskb_pull_tail. The
1521 * main difference between this version and the original function is that
1522 * this function can make several assumptions about the state of things
1523 * that allow for significant optimizations versus the standard function.
1524 * As a result we can do things like drop a frag and maintain an accurate
1525 * truesize for the skb.
1526 */
1527 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1528 struct sk_buff *skb)
1529 {
1530 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1531 unsigned char *va;
1532 unsigned int pull_len;
1533
1534 /*
1535 * it is valid to use page_address instead of kmap since we are
1536 * working with pages allocated out of the lomem pool per
1537 * alloc_page(GFP_ATOMIC)
1538 */
1539 va = skb_frag_address(frag);
1540
1541 /*
1542 * we need the header to contain the greater of either ETH_HLEN or
1543 * 60 bytes if the skb->len is less than 60 for skb_pad.
1544 */
1545 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1546
1547 /* align pull length to size of long to optimize memcpy performance */
1548 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1549
1550 /* update all of the pointers */
1551 skb_frag_size_sub(frag, pull_len);
1552 frag->page_offset += pull_len;
1553 skb->data_len -= pull_len;
1554 skb->tail += pull_len;
1555 }
1556
1557 /**
1558 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1559 * @rx_ring: rx descriptor ring packet is being transacted on
1560 * @skb: pointer to current skb being updated
1561 *
1562 * This function provides a basic DMA sync up for the first fragment of an
1563 * skb. The reason for doing this is that the first fragment cannot be
1564 * unmapped until we have reached the end of packet descriptor for a buffer
1565 * chain.
1566 */
1567 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1568 struct sk_buff *skb)
1569 {
1570 /* if the page was released unmap it, else just sync our portion */
1571 if (unlikely(IXGBE_CB(skb)->page_released)) {
1572 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1573 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1574 IXGBE_CB(skb)->page_released = false;
1575 } else {
1576 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1577
1578 dma_sync_single_range_for_cpu(rx_ring->dev,
1579 IXGBE_CB(skb)->dma,
1580 frag->page_offset,
1581 ixgbe_rx_bufsz(rx_ring),
1582 DMA_FROM_DEVICE);
1583 }
1584 IXGBE_CB(skb)->dma = 0;
1585 }
1586
1587 /**
1588 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1589 * @rx_ring: rx descriptor ring packet is being transacted on
1590 * @rx_desc: pointer to the EOP Rx descriptor
1591 * @skb: pointer to current skb being fixed
1592 *
1593 * Check for corrupted packet headers caused by senders on the local L2
1594 * embedded NIC switch not setting up their Tx Descriptors right. These
1595 * should be very rare.
1596 *
1597 * Also address the case where we are pulling data in on pages only
1598 * and as such no data is present in the skb header.
1599 *
1600 * In addition if skb is not at least 60 bytes we need to pad it so that
1601 * it is large enough to qualify as a valid Ethernet frame.
1602 *
1603 * Returns true if an error was encountered and skb was freed.
1604 **/
1605 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1606 union ixgbe_adv_rx_desc *rx_desc,
1607 struct sk_buff *skb)
1608 {
1609 struct net_device *netdev = rx_ring->netdev;
1610
1611 /* verify that the packet does not have any known errors */
1612 if (unlikely(ixgbe_test_staterr(rx_desc,
1613 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1614 !(netdev->features & NETIF_F_RXALL))) {
1615 dev_kfree_skb_any(skb);
1616 return true;
1617 }
1618
1619 /* place header in linear portion of buffer */
1620 if (skb_is_nonlinear(skb))
1621 ixgbe_pull_tail(rx_ring, skb);
1622
1623 #ifdef IXGBE_FCOE
1624 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1625 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1626 return false;
1627
1628 #endif
1629 /* if skb_pad returns an error the skb was freed */
1630 if (unlikely(skb->len < 60)) {
1631 int pad_len = 60 - skb->len;
1632
1633 if (skb_pad(skb, pad_len))
1634 return true;
1635 __skb_put(skb, pad_len);
1636 }
1637
1638 return false;
1639 }
1640
1641 /**
1642 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1643 * @rx_ring: rx descriptor ring to store buffers on
1644 * @old_buff: donor buffer to have page reused
1645 *
1646 * Synchronizes page for reuse by the adapter
1647 **/
1648 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1649 struct ixgbe_rx_buffer *old_buff)
1650 {
1651 struct ixgbe_rx_buffer *new_buff;
1652 u16 nta = rx_ring->next_to_alloc;
1653
1654 new_buff = &rx_ring->rx_buffer_info[nta];
1655
1656 /* update, and store next to alloc */
1657 nta++;
1658 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1659
1660 /* transfer page from old buffer to new buffer */
1661 new_buff->page = old_buff->page;
1662 new_buff->dma = old_buff->dma;
1663 new_buff->page_offset = old_buff->page_offset;
1664
1665 /* sync the buffer for use by the device */
1666 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1667 new_buff->page_offset,
1668 ixgbe_rx_bufsz(rx_ring),
1669 DMA_FROM_DEVICE);
1670 }
1671
1672 /**
1673 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1674 * @rx_ring: rx descriptor ring to transact packets on
1675 * @rx_buffer: buffer containing page to add
1676 * @rx_desc: descriptor containing length of buffer written by hardware
1677 * @skb: sk_buff to place the data into
1678 *
1679 * This function will add the data contained in rx_buffer->page to the skb.
1680 * This is done either through a direct copy if the data in the buffer is
1681 * less than the skb header size, otherwise it will just attach the page as
1682 * a frag to the skb.
1683 *
1684 * The function will then update the page offset if necessary and return
1685 * true if the buffer can be reused by the adapter.
1686 **/
1687 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1688 struct ixgbe_rx_buffer *rx_buffer,
1689 union ixgbe_adv_rx_desc *rx_desc,
1690 struct sk_buff *skb)
1691 {
1692 struct page *page = rx_buffer->page;
1693 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1694 #if (PAGE_SIZE < 8192)
1695 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1696 #else
1697 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1698 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1699 ixgbe_rx_bufsz(rx_ring);
1700 #endif
1701
1702 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1703 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1704
1705 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1706
1707 /* we can reuse buffer as-is, just make sure it is local */
1708 if (likely(page_to_nid(page) == numa_node_id()))
1709 return true;
1710
1711 /* this page cannot be reused so discard it */
1712 put_page(page);
1713 return false;
1714 }
1715
1716 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1717 rx_buffer->page_offset, size, truesize);
1718
1719 /* avoid re-using remote pages */
1720 if (unlikely(page_to_nid(page) != numa_node_id()))
1721 return false;
1722
1723 #if (PAGE_SIZE < 8192)
1724 /* if we are only owner of page we can reuse it */
1725 if (unlikely(page_count(page) != 1))
1726 return false;
1727
1728 /* flip page offset to other buffer */
1729 rx_buffer->page_offset ^= truesize;
1730
1731 /*
1732 * since we are the only owner of the page and we need to
1733 * increment it, just set the value to 2 in order to avoid
1734 * an unecessary locked operation
1735 */
1736 atomic_set(&page->_count, 2);
1737 #else
1738 /* move offset up to the next cache line */
1739 rx_buffer->page_offset += truesize;
1740
1741 if (rx_buffer->page_offset > last_offset)
1742 return false;
1743
1744 /* bump ref count on page before it is given to the stack */
1745 get_page(page);
1746 #endif
1747
1748 return true;
1749 }
1750
1751 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1752 union ixgbe_adv_rx_desc *rx_desc)
1753 {
1754 struct ixgbe_rx_buffer *rx_buffer;
1755 struct sk_buff *skb;
1756 struct page *page;
1757
1758 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1759 page = rx_buffer->page;
1760 prefetchw(page);
1761
1762 skb = rx_buffer->skb;
1763
1764 if (likely(!skb)) {
1765 void *page_addr = page_address(page) +
1766 rx_buffer->page_offset;
1767
1768 /* prefetch first cache line of first page */
1769 prefetch(page_addr);
1770 #if L1_CACHE_BYTES < 128
1771 prefetch(page_addr + L1_CACHE_BYTES);
1772 #endif
1773
1774 /* allocate a skb to store the frags */
1775 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1776 IXGBE_RX_HDR_SIZE);
1777 if (unlikely(!skb)) {
1778 rx_ring->rx_stats.alloc_rx_buff_failed++;
1779 return NULL;
1780 }
1781
1782 /*
1783 * we will be copying header into skb->data in
1784 * pskb_may_pull so it is in our interest to prefetch
1785 * it now to avoid a possible cache miss
1786 */
1787 prefetchw(skb->data);
1788
1789 /*
1790 * Delay unmapping of the first packet. It carries the
1791 * header information, HW may still access the header
1792 * after the writeback. Only unmap it when EOP is
1793 * reached
1794 */
1795 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1796 goto dma_sync;
1797
1798 IXGBE_CB(skb)->dma = rx_buffer->dma;
1799 } else {
1800 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1801 ixgbe_dma_sync_frag(rx_ring, skb);
1802
1803 dma_sync:
1804 /* we are reusing so sync this buffer for CPU use */
1805 dma_sync_single_range_for_cpu(rx_ring->dev,
1806 rx_buffer->dma,
1807 rx_buffer->page_offset,
1808 ixgbe_rx_bufsz(rx_ring),
1809 DMA_FROM_DEVICE);
1810 }
1811
1812 /* pull page into skb */
1813 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1814 /* hand second half of page back to the ring */
1815 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1816 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1817 /* the page has been released from the ring */
1818 IXGBE_CB(skb)->page_released = true;
1819 } else {
1820 /* we are not reusing the buffer so unmap it */
1821 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1822 ixgbe_rx_pg_size(rx_ring),
1823 DMA_FROM_DEVICE);
1824 }
1825
1826 /* clear contents of buffer_info */
1827 rx_buffer->skb = NULL;
1828 rx_buffer->dma = 0;
1829 rx_buffer->page = NULL;
1830
1831 return skb;
1832 }
1833
1834 /**
1835 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1836 * @q_vector: structure containing interrupt and ring information
1837 * @rx_ring: rx descriptor ring to transact packets on
1838 * @budget: Total limit on number of packets to process
1839 *
1840 * This function provides a "bounce buffer" approach to Rx interrupt
1841 * processing. The advantage to this is that on systems that have
1842 * expensive overhead for IOMMU access this provides a means of avoiding
1843 * it by maintaining the mapping of the page to the syste.
1844 *
1845 * Returns true if all work is completed without reaching budget
1846 **/
1847 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1848 struct ixgbe_ring *rx_ring,
1849 const int budget)
1850 {
1851 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1852 #ifdef IXGBE_FCOE
1853 struct ixgbe_adapter *adapter = q_vector->adapter;
1854 int ddp_bytes;
1855 unsigned int mss = 0;
1856 #endif /* IXGBE_FCOE */
1857 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1858
1859 do {
1860 union ixgbe_adv_rx_desc *rx_desc;
1861 struct sk_buff *skb;
1862
1863 /* return some buffers to hardware, one at a time is too slow */
1864 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1865 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1866 cleaned_count = 0;
1867 }
1868
1869 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1870
1871 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1872 break;
1873
1874 /*
1875 * This memory barrier is needed to keep us from reading
1876 * any other fields out of the rx_desc until we know the
1877 * RXD_STAT_DD bit is set
1878 */
1879 rmb();
1880
1881 /* retrieve a buffer from the ring */
1882 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1883
1884 /* exit if we failed to retrieve a buffer */
1885 if (!skb)
1886 break;
1887
1888 cleaned_count++;
1889
1890 /* place incomplete frames back on ring for completion */
1891 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1892 continue;
1893
1894 /* verify the packet layout is correct */
1895 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1896 continue;
1897
1898 /* probably a little skewed due to removing CRC */
1899 total_rx_bytes += skb->len;
1900
1901 /* populate checksum, timestamp, VLAN, and protocol */
1902 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1903
1904 #ifdef IXGBE_FCOE
1905 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1906 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1907 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1908 /* include DDPed FCoE data */
1909 if (ddp_bytes > 0) {
1910 if (!mss) {
1911 mss = rx_ring->netdev->mtu -
1912 sizeof(struct fcoe_hdr) -
1913 sizeof(struct fc_frame_header) -
1914 sizeof(struct fcoe_crc_eof);
1915 if (mss > 512)
1916 mss &= ~511;
1917 }
1918 total_rx_bytes += ddp_bytes;
1919 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1920 mss);
1921 }
1922 if (!ddp_bytes) {
1923 dev_kfree_skb_any(skb);
1924 continue;
1925 }
1926 }
1927
1928 #endif /* IXGBE_FCOE */
1929 ixgbe_rx_skb(q_vector, skb);
1930
1931 /* update budget accounting */
1932 total_rx_packets++;
1933 } while (likely(total_rx_packets < budget));
1934
1935 u64_stats_update_begin(&rx_ring->syncp);
1936 rx_ring->stats.packets += total_rx_packets;
1937 rx_ring->stats.bytes += total_rx_bytes;
1938 u64_stats_update_end(&rx_ring->syncp);
1939 q_vector->rx.total_packets += total_rx_packets;
1940 q_vector->rx.total_bytes += total_rx_bytes;
1941
1942 if (cleaned_count)
1943 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1944
1945 return (total_rx_packets < budget);
1946 }
1947
1948 /**
1949 * ixgbe_configure_msix - Configure MSI-X hardware
1950 * @adapter: board private structure
1951 *
1952 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1953 * interrupts.
1954 **/
1955 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1956 {
1957 struct ixgbe_q_vector *q_vector;
1958 int v_idx;
1959 u32 mask;
1960
1961 /* Populate MSIX to EITR Select */
1962 if (adapter->num_vfs > 32) {
1963 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1964 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1965 }
1966
1967 /*
1968 * Populate the IVAR table and set the ITR values to the
1969 * corresponding register.
1970 */
1971 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1972 struct ixgbe_ring *ring;
1973 q_vector = adapter->q_vector[v_idx];
1974
1975 ixgbe_for_each_ring(ring, q_vector->rx)
1976 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1977
1978 ixgbe_for_each_ring(ring, q_vector->tx)
1979 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1980
1981 ixgbe_write_eitr(q_vector);
1982 }
1983
1984 switch (adapter->hw.mac.type) {
1985 case ixgbe_mac_82598EB:
1986 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1987 v_idx);
1988 break;
1989 case ixgbe_mac_82599EB:
1990 case ixgbe_mac_X540:
1991 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1992 break;
1993 default:
1994 break;
1995 }
1996 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1997
1998 /* set up to autoclear timer, and the vectors */
1999 mask = IXGBE_EIMS_ENABLE_MASK;
2000 mask &= ~(IXGBE_EIMS_OTHER |
2001 IXGBE_EIMS_MAILBOX |
2002 IXGBE_EIMS_LSC);
2003
2004 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2005 }
2006
2007 enum latency_range {
2008 lowest_latency = 0,
2009 low_latency = 1,
2010 bulk_latency = 2,
2011 latency_invalid = 255
2012 };
2013
2014 /**
2015 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2016 * @q_vector: structure containing interrupt and ring information
2017 * @ring_container: structure containing ring performance data
2018 *
2019 * Stores a new ITR value based on packets and byte
2020 * counts during the last interrupt. The advantage of per interrupt
2021 * computation is faster updates and more accurate ITR for the current
2022 * traffic pattern. Constants in this function were computed
2023 * based on theoretical maximum wire speed and thresholds were set based
2024 * on testing data as well as attempting to minimize response time
2025 * while increasing bulk throughput.
2026 * this functionality is controlled by the InterruptThrottleRate module
2027 * parameter (see ixgbe_param.c)
2028 **/
2029 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2030 struct ixgbe_ring_container *ring_container)
2031 {
2032 int bytes = ring_container->total_bytes;
2033 int packets = ring_container->total_packets;
2034 u32 timepassed_us;
2035 u64 bytes_perint;
2036 u8 itr_setting = ring_container->itr;
2037
2038 if (packets == 0)
2039 return;
2040
2041 /* simple throttlerate management
2042 * 0-10MB/s lowest (100000 ints/s)
2043 * 10-20MB/s low (20000 ints/s)
2044 * 20-1249MB/s bulk (8000 ints/s)
2045 */
2046 /* what was last interrupt timeslice? */
2047 timepassed_us = q_vector->itr >> 2;
2048 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2049
2050 switch (itr_setting) {
2051 case lowest_latency:
2052 if (bytes_perint > 10)
2053 itr_setting = low_latency;
2054 break;
2055 case low_latency:
2056 if (bytes_perint > 20)
2057 itr_setting = bulk_latency;
2058 else if (bytes_perint <= 10)
2059 itr_setting = lowest_latency;
2060 break;
2061 case bulk_latency:
2062 if (bytes_perint <= 20)
2063 itr_setting = low_latency;
2064 break;
2065 }
2066
2067 /* clear work counters since we have the values we need */
2068 ring_container->total_bytes = 0;
2069 ring_container->total_packets = 0;
2070
2071 /* write updated itr to ring container */
2072 ring_container->itr = itr_setting;
2073 }
2074
2075 /**
2076 * ixgbe_write_eitr - write EITR register in hardware specific way
2077 * @q_vector: structure containing interrupt and ring information
2078 *
2079 * This function is made to be called by ethtool and by the driver
2080 * when it needs to update EITR registers at runtime. Hardware
2081 * specific quirks/differences are taken care of here.
2082 */
2083 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2084 {
2085 struct ixgbe_adapter *adapter = q_vector->adapter;
2086 struct ixgbe_hw *hw = &adapter->hw;
2087 int v_idx = q_vector->v_idx;
2088 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2089
2090 switch (adapter->hw.mac.type) {
2091 case ixgbe_mac_82598EB:
2092 /* must write high and low 16 bits to reset counter */
2093 itr_reg |= (itr_reg << 16);
2094 break;
2095 case ixgbe_mac_82599EB:
2096 case ixgbe_mac_X540:
2097 /*
2098 * set the WDIS bit to not clear the timer bits and cause an
2099 * immediate assertion of the interrupt
2100 */
2101 itr_reg |= IXGBE_EITR_CNT_WDIS;
2102 break;
2103 default:
2104 break;
2105 }
2106 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2107 }
2108
2109 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2110 {
2111 u32 new_itr = q_vector->itr;
2112 u8 current_itr;
2113
2114 ixgbe_update_itr(q_vector, &q_vector->tx);
2115 ixgbe_update_itr(q_vector, &q_vector->rx);
2116
2117 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2118
2119 switch (current_itr) {
2120 /* counts and packets in update_itr are dependent on these numbers */
2121 case lowest_latency:
2122 new_itr = IXGBE_100K_ITR;
2123 break;
2124 case low_latency:
2125 new_itr = IXGBE_20K_ITR;
2126 break;
2127 case bulk_latency:
2128 new_itr = IXGBE_8K_ITR;
2129 break;
2130 default:
2131 break;
2132 }
2133
2134 if (new_itr != q_vector->itr) {
2135 /* do an exponential smoothing */
2136 new_itr = (10 * new_itr * q_vector->itr) /
2137 ((9 * new_itr) + q_vector->itr);
2138
2139 /* save the algorithm value here */
2140 q_vector->itr = new_itr;
2141
2142 ixgbe_write_eitr(q_vector);
2143 }
2144 }
2145
2146 /**
2147 * ixgbe_check_overtemp_subtask - check for over temperature
2148 * @adapter: pointer to adapter
2149 **/
2150 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2151 {
2152 struct ixgbe_hw *hw = &adapter->hw;
2153 u32 eicr = adapter->interrupt_event;
2154
2155 if (test_bit(__IXGBE_DOWN, &adapter->state))
2156 return;
2157
2158 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2159 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2160 return;
2161
2162 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2163
2164 switch (hw->device_id) {
2165 case IXGBE_DEV_ID_82599_T3_LOM:
2166 /*
2167 * Since the warning interrupt is for both ports
2168 * we don't have to check if:
2169 * - This interrupt wasn't for our port.
2170 * - We may have missed the interrupt so always have to
2171 * check if we got a LSC
2172 */
2173 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2174 !(eicr & IXGBE_EICR_LSC))
2175 return;
2176
2177 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2178 u32 autoneg;
2179 bool link_up = false;
2180
2181 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2182
2183 if (link_up)
2184 return;
2185 }
2186
2187 /* Check if this is not due to overtemp */
2188 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2189 return;
2190
2191 break;
2192 default:
2193 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2194 return;
2195 break;
2196 }
2197 e_crit(drv,
2198 "Network adapter has been stopped because it has over heated. "
2199 "Restart the computer. If the problem persists, "
2200 "power off the system and replace the adapter\n");
2201
2202 adapter->interrupt_event = 0;
2203 }
2204
2205 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2206 {
2207 struct ixgbe_hw *hw = &adapter->hw;
2208
2209 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2210 (eicr & IXGBE_EICR_GPI_SDP1)) {
2211 e_crit(probe, "Fan has stopped, replace the adapter\n");
2212 /* write to clear the interrupt */
2213 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2214 }
2215 }
2216
2217 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2218 {
2219 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2220 return;
2221
2222 switch (adapter->hw.mac.type) {
2223 case ixgbe_mac_82599EB:
2224 /*
2225 * Need to check link state so complete overtemp check
2226 * on service task
2227 */
2228 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2229 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2230 adapter->interrupt_event = eicr;
2231 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2232 ixgbe_service_event_schedule(adapter);
2233 return;
2234 }
2235 return;
2236 case ixgbe_mac_X540:
2237 if (!(eicr & IXGBE_EICR_TS))
2238 return;
2239 break;
2240 default:
2241 return;
2242 }
2243
2244 e_crit(drv,
2245 "Network adapter has been stopped because it has over heated. "
2246 "Restart the computer. If the problem persists, "
2247 "power off the system and replace the adapter\n");
2248 }
2249
2250 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2251 {
2252 struct ixgbe_hw *hw = &adapter->hw;
2253
2254 if (eicr & IXGBE_EICR_GPI_SDP2) {
2255 /* Clear the interrupt */
2256 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2257 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2258 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2259 ixgbe_service_event_schedule(adapter);
2260 }
2261 }
2262
2263 if (eicr & IXGBE_EICR_GPI_SDP1) {
2264 /* Clear the interrupt */
2265 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2266 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2267 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2268 ixgbe_service_event_schedule(adapter);
2269 }
2270 }
2271 }
2272
2273 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2274 {
2275 struct ixgbe_hw *hw = &adapter->hw;
2276
2277 adapter->lsc_int++;
2278 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2279 adapter->link_check_timeout = jiffies;
2280 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2282 IXGBE_WRITE_FLUSH(hw);
2283 ixgbe_service_event_schedule(adapter);
2284 }
2285 }
2286
2287 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2288 u64 qmask)
2289 {
2290 u32 mask;
2291 struct ixgbe_hw *hw = &adapter->hw;
2292
2293 switch (hw->mac.type) {
2294 case ixgbe_mac_82598EB:
2295 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2296 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2297 break;
2298 case ixgbe_mac_82599EB:
2299 case ixgbe_mac_X540:
2300 mask = (qmask & 0xFFFFFFFF);
2301 if (mask)
2302 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2303 mask = (qmask >> 32);
2304 if (mask)
2305 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2306 break;
2307 default:
2308 break;
2309 }
2310 /* skip the flush */
2311 }
2312
2313 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2314 u64 qmask)
2315 {
2316 u32 mask;
2317 struct ixgbe_hw *hw = &adapter->hw;
2318
2319 switch (hw->mac.type) {
2320 case ixgbe_mac_82598EB:
2321 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2322 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2323 break;
2324 case ixgbe_mac_82599EB:
2325 case ixgbe_mac_X540:
2326 mask = (qmask & 0xFFFFFFFF);
2327 if (mask)
2328 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2329 mask = (qmask >> 32);
2330 if (mask)
2331 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2332 break;
2333 default:
2334 break;
2335 }
2336 /* skip the flush */
2337 }
2338
2339 /**
2340 * ixgbe_irq_enable - Enable default interrupt generation settings
2341 * @adapter: board private structure
2342 **/
2343 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2344 bool flush)
2345 {
2346 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2347
2348 /* don't reenable LSC while waiting for link */
2349 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2350 mask &= ~IXGBE_EIMS_LSC;
2351
2352 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2353 switch (adapter->hw.mac.type) {
2354 case ixgbe_mac_82599EB:
2355 mask |= IXGBE_EIMS_GPI_SDP0;
2356 break;
2357 case ixgbe_mac_X540:
2358 mask |= IXGBE_EIMS_TS;
2359 break;
2360 default:
2361 break;
2362 }
2363 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2364 mask |= IXGBE_EIMS_GPI_SDP1;
2365 switch (adapter->hw.mac.type) {
2366 case ixgbe_mac_82599EB:
2367 mask |= IXGBE_EIMS_GPI_SDP1;
2368 mask |= IXGBE_EIMS_GPI_SDP2;
2369 case ixgbe_mac_X540:
2370 mask |= IXGBE_EIMS_ECC;
2371 mask |= IXGBE_EIMS_MAILBOX;
2372 break;
2373 default:
2374 break;
2375 }
2376
2377 if (adapter->hw.mac.type == ixgbe_mac_X540)
2378 mask |= IXGBE_EIMS_TIMESYNC;
2379
2380 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2381 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2382 mask |= IXGBE_EIMS_FLOW_DIR;
2383
2384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2385 if (queues)
2386 ixgbe_irq_enable_queues(adapter, ~0);
2387 if (flush)
2388 IXGBE_WRITE_FLUSH(&adapter->hw);
2389 }
2390
2391 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2392 {
2393 struct ixgbe_adapter *adapter = data;
2394 struct ixgbe_hw *hw = &adapter->hw;
2395 u32 eicr;
2396
2397 /*
2398 * Workaround for Silicon errata. Use clear-by-write instead
2399 * of clear-by-read. Reading with EICS will return the
2400 * interrupt causes without clearing, which later be done
2401 * with the write to EICR.
2402 */
2403 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2404 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2405
2406 if (eicr & IXGBE_EICR_LSC)
2407 ixgbe_check_lsc(adapter);
2408
2409 if (eicr & IXGBE_EICR_MAILBOX)
2410 ixgbe_msg_task(adapter);
2411
2412 switch (hw->mac.type) {
2413 case ixgbe_mac_82599EB:
2414 case ixgbe_mac_X540:
2415 if (eicr & IXGBE_EICR_ECC)
2416 e_info(link, "Received unrecoverable ECC Err, please "
2417 "reboot\n");
2418 /* Handle Flow Director Full threshold interrupt */
2419 if (eicr & IXGBE_EICR_FLOW_DIR) {
2420 int reinit_count = 0;
2421 int i;
2422 for (i = 0; i < adapter->num_tx_queues; i++) {
2423 struct ixgbe_ring *ring = adapter->tx_ring[i];
2424 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2425 &ring->state))
2426 reinit_count++;
2427 }
2428 if (reinit_count) {
2429 /* no more flow director interrupts until after init */
2430 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2431 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2432 ixgbe_service_event_schedule(adapter);
2433 }
2434 }
2435 ixgbe_check_sfp_event(adapter, eicr);
2436 ixgbe_check_overtemp_event(adapter, eicr);
2437 break;
2438 default:
2439 break;
2440 }
2441
2442 ixgbe_check_fan_failure(adapter, eicr);
2443
2444 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2445 ixgbe_ptp_check_pps_event(adapter, eicr);
2446
2447 /* re-enable the original interrupt state, no lsc, no queues */
2448 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2449 ixgbe_irq_enable(adapter, false, false);
2450
2451 return IRQ_HANDLED;
2452 }
2453
2454 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2455 {
2456 struct ixgbe_q_vector *q_vector = data;
2457
2458 /* EIAM disabled interrupts (on this vector) for us */
2459
2460 if (q_vector->rx.ring || q_vector->tx.ring)
2461 napi_schedule(&q_vector->napi);
2462
2463 return IRQ_HANDLED;
2464 }
2465
2466 /**
2467 * ixgbe_poll - NAPI Rx polling callback
2468 * @napi: structure for representing this polling device
2469 * @budget: how many packets driver is allowed to clean
2470 *
2471 * This function is used for legacy and MSI, NAPI mode
2472 **/
2473 int ixgbe_poll(struct napi_struct *napi, int budget)
2474 {
2475 struct ixgbe_q_vector *q_vector =
2476 container_of(napi, struct ixgbe_q_vector, napi);
2477 struct ixgbe_adapter *adapter = q_vector->adapter;
2478 struct ixgbe_ring *ring;
2479 int per_ring_budget;
2480 bool clean_complete = true;
2481
2482 #ifdef CONFIG_IXGBE_DCA
2483 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2484 ixgbe_update_dca(q_vector);
2485 #endif
2486
2487 ixgbe_for_each_ring(ring, q_vector->tx)
2488 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2489
2490 /* attempt to distribute budget to each queue fairly, but don't allow
2491 * the budget to go below 1 because we'll exit polling */
2492 if (q_vector->rx.count > 1)
2493 per_ring_budget = max(budget/q_vector->rx.count, 1);
2494 else
2495 per_ring_budget = budget;
2496
2497 ixgbe_for_each_ring(ring, q_vector->rx)
2498 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2499 per_ring_budget);
2500
2501 /* If all work not completed, return budget and keep polling */
2502 if (!clean_complete)
2503 return budget;
2504
2505 /* all work done, exit the polling mode */
2506 napi_complete(napi);
2507 if (adapter->rx_itr_setting & 1)
2508 ixgbe_set_itr(q_vector);
2509 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2510 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2511
2512 return 0;
2513 }
2514
2515 /**
2516 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2517 * @adapter: board private structure
2518 *
2519 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2520 * interrupts from the kernel.
2521 **/
2522 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2523 {
2524 struct net_device *netdev = adapter->netdev;
2525 int vector, err;
2526 int ri = 0, ti = 0;
2527
2528 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2529 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2530 struct msix_entry *entry = &adapter->msix_entries[vector];
2531
2532 if (q_vector->tx.ring && q_vector->rx.ring) {
2533 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2534 "%s-%s-%d", netdev->name, "TxRx", ri++);
2535 ti++;
2536 } else if (q_vector->rx.ring) {
2537 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2538 "%s-%s-%d", netdev->name, "rx", ri++);
2539 } else if (q_vector->tx.ring) {
2540 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2541 "%s-%s-%d", netdev->name, "tx", ti++);
2542 } else {
2543 /* skip this unused q_vector */
2544 continue;
2545 }
2546 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2547 q_vector->name, q_vector);
2548 if (err) {
2549 e_err(probe, "request_irq failed for MSIX interrupt "
2550 "Error: %d\n", err);
2551 goto free_queue_irqs;
2552 }
2553 /* If Flow Director is enabled, set interrupt affinity */
2554 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2555 /* assign the mask for this irq */
2556 irq_set_affinity_hint(entry->vector,
2557 &q_vector->affinity_mask);
2558 }
2559 }
2560
2561 err = request_irq(adapter->msix_entries[vector].vector,
2562 ixgbe_msix_other, 0, netdev->name, adapter);
2563 if (err) {
2564 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2565 goto free_queue_irqs;
2566 }
2567
2568 return 0;
2569
2570 free_queue_irqs:
2571 while (vector) {
2572 vector--;
2573 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2574 NULL);
2575 free_irq(adapter->msix_entries[vector].vector,
2576 adapter->q_vector[vector]);
2577 }
2578 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2579 pci_disable_msix(adapter->pdev);
2580 kfree(adapter->msix_entries);
2581 adapter->msix_entries = NULL;
2582 return err;
2583 }
2584
2585 /**
2586 * ixgbe_intr - legacy mode Interrupt Handler
2587 * @irq: interrupt number
2588 * @data: pointer to a network interface device structure
2589 **/
2590 static irqreturn_t ixgbe_intr(int irq, void *data)
2591 {
2592 struct ixgbe_adapter *adapter = data;
2593 struct ixgbe_hw *hw = &adapter->hw;
2594 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2595 u32 eicr;
2596
2597 /*
2598 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2599 * before the read of EICR.
2600 */
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2602
2603 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2604 * therefore no explicit interrupt disable is necessary */
2605 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2606 if (!eicr) {
2607 /*
2608 * shared interrupt alert!
2609 * make sure interrupts are enabled because the read will
2610 * have disabled interrupts due to EIAM
2611 * finish the workaround of silicon errata on 82598. Unmask
2612 * the interrupt that we masked before the EICR read.
2613 */
2614 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2615 ixgbe_irq_enable(adapter, true, true);
2616 return IRQ_NONE; /* Not our interrupt */
2617 }
2618
2619 if (eicr & IXGBE_EICR_LSC)
2620 ixgbe_check_lsc(adapter);
2621
2622 switch (hw->mac.type) {
2623 case ixgbe_mac_82599EB:
2624 ixgbe_check_sfp_event(adapter, eicr);
2625 /* Fall through */
2626 case ixgbe_mac_X540:
2627 if (eicr & IXGBE_EICR_ECC)
2628 e_info(link, "Received unrecoverable ECC err, please "
2629 "reboot\n");
2630 ixgbe_check_overtemp_event(adapter, eicr);
2631 break;
2632 default:
2633 break;
2634 }
2635
2636 ixgbe_check_fan_failure(adapter, eicr);
2637 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2638 ixgbe_ptp_check_pps_event(adapter, eicr);
2639
2640 /* would disable interrupts here but EIAM disabled it */
2641 napi_schedule(&q_vector->napi);
2642
2643 /*
2644 * re-enable link(maybe) and non-queue interrupts, no flush.
2645 * ixgbe_poll will re-enable the queue interrupts
2646 */
2647 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2648 ixgbe_irq_enable(adapter, false, false);
2649
2650 return IRQ_HANDLED;
2651 }
2652
2653 /**
2654 * ixgbe_request_irq - initialize interrupts
2655 * @adapter: board private structure
2656 *
2657 * Attempts to configure interrupts using the best available
2658 * capabilities of the hardware and kernel.
2659 **/
2660 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2661 {
2662 struct net_device *netdev = adapter->netdev;
2663 int err;
2664
2665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2666 err = ixgbe_request_msix_irqs(adapter);
2667 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2668 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2669 netdev->name, adapter);
2670 else
2671 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2672 netdev->name, adapter);
2673
2674 if (err)
2675 e_err(probe, "request_irq failed, Error %d\n", err);
2676
2677 return err;
2678 }
2679
2680 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2681 {
2682 int vector;
2683
2684 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2685 free_irq(adapter->pdev->irq, adapter);
2686 return;
2687 }
2688
2689 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2690 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2691 struct msix_entry *entry = &adapter->msix_entries[vector];
2692
2693 /* free only the irqs that were actually requested */
2694 if (!q_vector->rx.ring && !q_vector->tx.ring)
2695 continue;
2696
2697 /* clear the affinity_mask in the IRQ descriptor */
2698 irq_set_affinity_hint(entry->vector, NULL);
2699
2700 free_irq(entry->vector, q_vector);
2701 }
2702
2703 free_irq(adapter->msix_entries[vector++].vector, adapter);
2704 }
2705
2706 /**
2707 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2708 * @adapter: board private structure
2709 **/
2710 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2711 {
2712 switch (adapter->hw.mac.type) {
2713 case ixgbe_mac_82598EB:
2714 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2715 break;
2716 case ixgbe_mac_82599EB:
2717 case ixgbe_mac_X540:
2718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2719 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2720 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2721 break;
2722 default:
2723 break;
2724 }
2725 IXGBE_WRITE_FLUSH(&adapter->hw);
2726 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2727 int vector;
2728
2729 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2730 synchronize_irq(adapter->msix_entries[vector].vector);
2731
2732 synchronize_irq(adapter->msix_entries[vector++].vector);
2733 } else {
2734 synchronize_irq(adapter->pdev->irq);
2735 }
2736 }
2737
2738 /**
2739 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2740 *
2741 **/
2742 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2743 {
2744 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2745
2746 ixgbe_write_eitr(q_vector);
2747
2748 ixgbe_set_ivar(adapter, 0, 0, 0);
2749 ixgbe_set_ivar(adapter, 1, 0, 0);
2750
2751 e_info(hw, "Legacy interrupt IVAR setup done\n");
2752 }
2753
2754 /**
2755 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2756 * @adapter: board private structure
2757 * @ring: structure containing ring specific data
2758 *
2759 * Configure the Tx descriptor ring after a reset.
2760 **/
2761 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2762 struct ixgbe_ring *ring)
2763 {
2764 struct ixgbe_hw *hw = &adapter->hw;
2765 u64 tdba = ring->dma;
2766 int wait_loop = 10;
2767 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2768 u8 reg_idx = ring->reg_idx;
2769
2770 /* disable queue to avoid issues while updating state */
2771 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2772 IXGBE_WRITE_FLUSH(hw);
2773
2774 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2775 (tdba & DMA_BIT_MASK(32)));
2776 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2777 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2778 ring->count * sizeof(union ixgbe_adv_tx_desc));
2779 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2780 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2781 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2782
2783 /*
2784 * set WTHRESH to encourage burst writeback, it should not be set
2785 * higher than 1 when ITR is 0 as it could cause false TX hangs
2786 *
2787 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2788 * to or less than the number of on chip descriptors, which is
2789 * currently 40.
2790 */
2791 if (!ring->q_vector || (ring->q_vector->itr < 8))
2792 txdctl |= (1 << 16); /* WTHRESH = 1 */
2793 else
2794 txdctl |= (8 << 16); /* WTHRESH = 8 */
2795
2796 /*
2797 * Setting PTHRESH to 32 both improves performance
2798 * and avoids a TX hang with DFP enabled
2799 */
2800 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2801 32; /* PTHRESH = 32 */
2802
2803 /* reinitialize flowdirector state */
2804 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2805 ring->atr_sample_rate = adapter->atr_sample_rate;
2806 ring->atr_count = 0;
2807 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2808 } else {
2809 ring->atr_sample_rate = 0;
2810 }
2811
2812 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2813
2814 /* enable queue */
2815 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2816
2817 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2818 if (hw->mac.type == ixgbe_mac_82598EB &&
2819 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2820 return;
2821
2822 /* poll to verify queue is enabled */
2823 do {
2824 usleep_range(1000, 2000);
2825 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2826 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2827 if (!wait_loop)
2828 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2829 }
2830
2831 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2832 {
2833 struct ixgbe_hw *hw = &adapter->hw;
2834 u32 rttdcs, mtqc;
2835 u8 tcs = netdev_get_num_tc(adapter->netdev);
2836
2837 if (hw->mac.type == ixgbe_mac_82598EB)
2838 return;
2839
2840 /* disable the arbiter while setting MTQC */
2841 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2842 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2843 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2844
2845 /* set transmit pool layout */
2846 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2847 mtqc = IXGBE_MTQC_VT_ENA;
2848 if (tcs > 4)
2849 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2850 else if (tcs > 1)
2851 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2852 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2853 mtqc |= IXGBE_MTQC_32VF;
2854 else
2855 mtqc |= IXGBE_MTQC_64VF;
2856 } else {
2857 if (tcs > 4)
2858 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2859 else if (tcs > 1)
2860 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2861 else
2862 mtqc = IXGBE_MTQC_64Q_1PB;
2863 }
2864
2865 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2866
2867 /* Enable Security TX Buffer IFG for multiple pb */
2868 if (tcs) {
2869 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2870 sectx |= IXGBE_SECTX_DCB;
2871 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2872 }
2873
2874 /* re-enable the arbiter */
2875 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2876 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2877 }
2878
2879 /**
2880 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2881 * @adapter: board private structure
2882 *
2883 * Configure the Tx unit of the MAC after a reset.
2884 **/
2885 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2886 {
2887 struct ixgbe_hw *hw = &adapter->hw;
2888 u32 dmatxctl;
2889 u32 i;
2890
2891 ixgbe_setup_mtqc(adapter);
2892
2893 if (hw->mac.type != ixgbe_mac_82598EB) {
2894 /* DMATXCTL.EN must be before Tx queues are enabled */
2895 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2896 dmatxctl |= IXGBE_DMATXCTL_TE;
2897 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2898 }
2899
2900 /* Setup the HW Tx Head and Tail descriptor pointers */
2901 for (i = 0; i < adapter->num_tx_queues; i++)
2902 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2903 }
2904
2905 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2906 struct ixgbe_ring *ring)
2907 {
2908 struct ixgbe_hw *hw = &adapter->hw;
2909 u8 reg_idx = ring->reg_idx;
2910 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2911
2912 srrctl |= IXGBE_SRRCTL_DROP_EN;
2913
2914 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2915 }
2916
2917 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2918 struct ixgbe_ring *ring)
2919 {
2920 struct ixgbe_hw *hw = &adapter->hw;
2921 u8 reg_idx = ring->reg_idx;
2922 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2923
2924 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2925
2926 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2927 }
2928
2929 #ifdef CONFIG_IXGBE_DCB
2930 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2931 #else
2932 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2933 #endif
2934 {
2935 int i;
2936 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2937
2938 if (adapter->ixgbe_ieee_pfc)
2939 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2940
2941 /*
2942 * We should set the drop enable bit if:
2943 * SR-IOV is enabled
2944 * or
2945 * Number of Rx queues > 1 and flow control is disabled
2946 *
2947 * This allows us to avoid head of line blocking for security
2948 * and performance reasons.
2949 */
2950 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2951 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2952 for (i = 0; i < adapter->num_rx_queues; i++)
2953 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2954 } else {
2955 for (i = 0; i < adapter->num_rx_queues; i++)
2956 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2957 }
2958 }
2959
2960 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2961
2962 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2963 struct ixgbe_ring *rx_ring)
2964 {
2965 struct ixgbe_hw *hw = &adapter->hw;
2966 u32 srrctl;
2967 u8 reg_idx = rx_ring->reg_idx;
2968
2969 if (hw->mac.type == ixgbe_mac_82598EB) {
2970 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
2971
2972 /*
2973 * if VMDq is not active we must program one srrctl register
2974 * per RSS queue since we have enabled RDRXCTL.MVMEN
2975 */
2976 reg_idx &= mask;
2977 }
2978
2979 /* configure header buffer length, needed for RSC */
2980 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
2981
2982 /* configure the packet buffer length */
2983 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2984
2985 /* configure descriptor type */
2986 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2987
2988 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2989 }
2990
2991 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2992 {
2993 struct ixgbe_hw *hw = &adapter->hw;
2994 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2995 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2996 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2997 u32 mrqc = 0, reta = 0;
2998 u32 rxcsum;
2999 int i, j;
3000 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3001
3002 /*
3003 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3004 * make full use of any rings they may have. We will use the
3005 * PSRTYPE register to control how many rings we use within the PF.
3006 */
3007 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3008 rss_i = 2;
3009
3010 /* Fill out hash function seeds */
3011 for (i = 0; i < 10; i++)
3012 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3013
3014 /* Fill out redirection table */
3015 for (i = 0, j = 0; i < 128; i++, j++) {
3016 if (j == rss_i)
3017 j = 0;
3018 /* reta = 4-byte sliding window of
3019 * 0x00..(indices-1)(indices-1)00..etc. */
3020 reta = (reta << 8) | (j * 0x11);
3021 if ((i & 3) == 3)
3022 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3023 }
3024
3025 /* Disable indicating checksum in descriptor, enables RSS hash */
3026 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3027 rxcsum |= IXGBE_RXCSUM_PCSD;
3028 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3029
3030 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3031 if (adapter->ring_feature[RING_F_RSS].mask)
3032 mrqc = IXGBE_MRQC_RSSEN;
3033 } else {
3034 u8 tcs = netdev_get_num_tc(adapter->netdev);
3035
3036 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3037 if (tcs > 4)
3038 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3039 else if (tcs > 1)
3040 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3041 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3042 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3043 else
3044 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3045 } else {
3046 if (tcs > 4)
3047 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3048 else if (tcs > 1)
3049 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3050 else
3051 mrqc = IXGBE_MRQC_RSSEN;
3052 }
3053 }
3054
3055 /* Perform hash on these packet types */
3056 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3057 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3058 IXGBE_MRQC_RSS_FIELD_IPV6 |
3059 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3060
3061 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3062 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3063 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3064 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3065
3066 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3067 }
3068
3069 /**
3070 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3071 * @adapter: address of board private structure
3072 * @index: index of ring to set
3073 **/
3074 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3075 struct ixgbe_ring *ring)
3076 {
3077 struct ixgbe_hw *hw = &adapter->hw;
3078 u32 rscctrl;
3079 u8 reg_idx = ring->reg_idx;
3080
3081 if (!ring_is_rsc_enabled(ring))
3082 return;
3083
3084 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3085 rscctrl |= IXGBE_RSCCTL_RSCEN;
3086 /*
3087 * we must limit the number of descriptors so that the
3088 * total size of max desc * buf_len is not greater
3089 * than 65536
3090 */
3091 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3092 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3093 }
3094
3095 #define IXGBE_MAX_RX_DESC_POLL 10
3096 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3097 struct ixgbe_ring *ring)
3098 {
3099 struct ixgbe_hw *hw = &adapter->hw;
3100 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3101 u32 rxdctl;
3102 u8 reg_idx = ring->reg_idx;
3103
3104 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3105 if (hw->mac.type == ixgbe_mac_82598EB &&
3106 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3107 return;
3108
3109 do {
3110 usleep_range(1000, 2000);
3111 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3112 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3113
3114 if (!wait_loop) {
3115 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3116 "the polling period\n", reg_idx);
3117 }
3118 }
3119
3120 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3121 struct ixgbe_ring *ring)
3122 {
3123 struct ixgbe_hw *hw = &adapter->hw;
3124 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3125 u32 rxdctl;
3126 u8 reg_idx = ring->reg_idx;
3127
3128 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3129 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3130
3131 /* write value back with RXDCTL.ENABLE bit cleared */
3132 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3133
3134 if (hw->mac.type == ixgbe_mac_82598EB &&
3135 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3136 return;
3137
3138 /* the hardware may take up to 100us to really disable the rx queue */
3139 do {
3140 udelay(10);
3141 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3142 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3143
3144 if (!wait_loop) {
3145 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3146 "the polling period\n", reg_idx);
3147 }
3148 }
3149
3150 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3151 struct ixgbe_ring *ring)
3152 {
3153 struct ixgbe_hw *hw = &adapter->hw;
3154 u64 rdba = ring->dma;
3155 u32 rxdctl;
3156 u8 reg_idx = ring->reg_idx;
3157
3158 /* disable queue to avoid issues while updating state */
3159 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3160 ixgbe_disable_rx_queue(adapter, ring);
3161
3162 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3163 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3164 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3165 ring->count * sizeof(union ixgbe_adv_rx_desc));
3166 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3167 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3168 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3169
3170 ixgbe_configure_srrctl(adapter, ring);
3171 ixgbe_configure_rscctl(adapter, ring);
3172
3173 if (hw->mac.type == ixgbe_mac_82598EB) {
3174 /*
3175 * enable cache line friendly hardware writes:
3176 * PTHRESH=32 descriptors (half the internal cache),
3177 * this also removes ugly rx_no_buffer_count increment
3178 * HTHRESH=4 descriptors (to minimize latency on fetch)
3179 * WTHRESH=8 burst writeback up to two cache lines
3180 */
3181 rxdctl &= ~0x3FFFFF;
3182 rxdctl |= 0x080420;
3183 }
3184
3185 /* enable receive descriptor ring */
3186 rxdctl |= IXGBE_RXDCTL_ENABLE;
3187 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3188
3189 ixgbe_rx_desc_queue_enable(adapter, ring);
3190 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3191 }
3192
3193 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3194 {
3195 struct ixgbe_hw *hw = &adapter->hw;
3196 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3197 int p;
3198
3199 /* PSRTYPE must be initialized in non 82598 adapters */
3200 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3201 IXGBE_PSRTYPE_UDPHDR |
3202 IXGBE_PSRTYPE_IPV4HDR |
3203 IXGBE_PSRTYPE_L2HDR |
3204 IXGBE_PSRTYPE_IPV6HDR;
3205
3206 if (hw->mac.type == ixgbe_mac_82598EB)
3207 return;
3208
3209 if (rss_i > 3)
3210 psrtype |= 2 << 29;
3211 else if (rss_i > 1)
3212 psrtype |= 1 << 29;
3213
3214 for (p = 0; p < adapter->num_rx_pools; p++)
3215 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3216 psrtype);
3217 }
3218
3219 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3220 {
3221 struct ixgbe_hw *hw = &adapter->hw;
3222 u32 reg_offset, vf_shift;
3223 u32 gcr_ext, vmdctl;
3224 int i;
3225
3226 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3227 return;
3228
3229 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3230 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3231 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3232 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3233 vmdctl |= IXGBE_VT_CTL_REPLEN;
3234 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3235
3236 vf_shift = VMDQ_P(0) % 32;
3237 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3238
3239 /* Enable only the PF's pool for Tx/Rx */
3240 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3241 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3242 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3243 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3244
3245 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3246 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3247
3248 /*
3249 * Set up VF register offsets for selected VT Mode,
3250 * i.e. 32 or 64 VFs for SR-IOV
3251 */
3252 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3253 case IXGBE_82599_VMDQ_8Q_MASK:
3254 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3255 break;
3256 case IXGBE_82599_VMDQ_4Q_MASK:
3257 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3258 break;
3259 default:
3260 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3261 break;
3262 }
3263
3264 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3265
3266
3267 /* Enable MAC Anti-Spoofing */
3268 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3269 adapter->num_vfs);
3270 /* For VFs that have spoof checking turned off */
3271 for (i = 0; i < adapter->num_vfs; i++) {
3272 if (!adapter->vfinfo[i].spoofchk_enabled)
3273 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3274 }
3275 }
3276
3277 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3278 {
3279 struct ixgbe_hw *hw = &adapter->hw;
3280 struct net_device *netdev = adapter->netdev;
3281 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3282 struct ixgbe_ring *rx_ring;
3283 int i;
3284 u32 mhadd, hlreg0;
3285
3286 #ifdef IXGBE_FCOE
3287 /* adjust max frame to be able to do baby jumbo for FCoE */
3288 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3289 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3290 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3291
3292 #endif /* IXGBE_FCOE */
3293
3294 /* adjust max frame to be at least the size of a standard frame */
3295 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3296 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3297
3298 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3299 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3300 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3301 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3302
3303 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3304 }
3305
3306 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3307 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3308 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3309 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3310
3311 /*
3312 * Setup the HW Rx Head and Tail Descriptor Pointers and
3313 * the Base and Length of the Rx Descriptor Ring
3314 */
3315 for (i = 0; i < adapter->num_rx_queues; i++) {
3316 rx_ring = adapter->rx_ring[i];
3317 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3318 set_ring_rsc_enabled(rx_ring);
3319 else
3320 clear_ring_rsc_enabled(rx_ring);
3321 }
3322 }
3323
3324 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3325 {
3326 struct ixgbe_hw *hw = &adapter->hw;
3327 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3328
3329 switch (hw->mac.type) {
3330 case ixgbe_mac_82598EB:
3331 /*
3332 * For VMDq support of different descriptor types or
3333 * buffer sizes through the use of multiple SRRCTL
3334 * registers, RDRXCTL.MVMEN must be set to 1
3335 *
3336 * also, the manual doesn't mention it clearly but DCA hints
3337 * will only use queue 0's tags unless this bit is set. Side
3338 * effects of setting this bit are only that SRRCTL must be
3339 * fully programmed [0..15]
3340 */
3341 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3342 break;
3343 case ixgbe_mac_82599EB:
3344 case ixgbe_mac_X540:
3345 /* Disable RSC for ACK packets */
3346 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3347 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3348 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3349 /* hardware requires some bits to be set by default */
3350 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3351 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3352 break;
3353 default:
3354 /* We should do nothing since we don't know this hardware */
3355 return;
3356 }
3357
3358 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3359 }
3360
3361 /**
3362 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3363 * @adapter: board private structure
3364 *
3365 * Configure the Rx unit of the MAC after a reset.
3366 **/
3367 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3368 {
3369 struct ixgbe_hw *hw = &adapter->hw;
3370 int i;
3371 u32 rxctrl;
3372
3373 /* disable receives while setting up the descriptors */
3374 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3375 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3376
3377 ixgbe_setup_psrtype(adapter);
3378 ixgbe_setup_rdrxctl(adapter);
3379
3380 /* Program registers for the distribution of queues */
3381 ixgbe_setup_mrqc(adapter);
3382
3383 /* set_rx_buffer_len must be called before ring initialization */
3384 ixgbe_set_rx_buffer_len(adapter);
3385
3386 /*
3387 * Setup the HW Rx Head and Tail Descriptor Pointers and
3388 * the Base and Length of the Rx Descriptor Ring
3389 */
3390 for (i = 0; i < adapter->num_rx_queues; i++)
3391 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3392
3393 /* disable drop enable for 82598 parts */
3394 if (hw->mac.type == ixgbe_mac_82598EB)
3395 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3396
3397 /* enable all receives */
3398 rxctrl |= IXGBE_RXCTRL_RXEN;
3399 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3400 }
3401
3402 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3403 {
3404 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3405 struct ixgbe_hw *hw = &adapter->hw;
3406
3407 /* add VID to filter table */
3408 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3409 set_bit(vid, adapter->active_vlans);
3410
3411 return 0;
3412 }
3413
3414 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3415 {
3416 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3417 struct ixgbe_hw *hw = &adapter->hw;
3418
3419 /* remove VID from filter table */
3420 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3421 clear_bit(vid, adapter->active_vlans);
3422
3423 return 0;
3424 }
3425
3426 /**
3427 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3428 * @adapter: driver data
3429 */
3430 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3431 {
3432 struct ixgbe_hw *hw = &adapter->hw;
3433 u32 vlnctrl;
3434
3435 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3436 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3437 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3438 }
3439
3440 /**
3441 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3442 * @adapter: driver data
3443 */
3444 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3445 {
3446 struct ixgbe_hw *hw = &adapter->hw;
3447 u32 vlnctrl;
3448
3449 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3450 vlnctrl |= IXGBE_VLNCTRL_VFE;
3451 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3452 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3453 }
3454
3455 /**
3456 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3457 * @adapter: driver data
3458 */
3459 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3460 {
3461 struct ixgbe_hw *hw = &adapter->hw;
3462 u32 vlnctrl;
3463 int i, j;
3464
3465 switch (hw->mac.type) {
3466 case ixgbe_mac_82598EB:
3467 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3468 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3469 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3470 break;
3471 case ixgbe_mac_82599EB:
3472 case ixgbe_mac_X540:
3473 for (i = 0; i < adapter->num_rx_queues; i++) {
3474 j = adapter->rx_ring[i]->reg_idx;
3475 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3476 vlnctrl &= ~IXGBE_RXDCTL_VME;
3477 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3478 }
3479 break;
3480 default:
3481 break;
3482 }
3483 }
3484
3485 /**
3486 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3487 * @adapter: driver data
3488 */
3489 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3490 {
3491 struct ixgbe_hw *hw = &adapter->hw;
3492 u32 vlnctrl;
3493 int i, j;
3494
3495 switch (hw->mac.type) {
3496 case ixgbe_mac_82598EB:
3497 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3498 vlnctrl |= IXGBE_VLNCTRL_VME;
3499 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3500 break;
3501 case ixgbe_mac_82599EB:
3502 case ixgbe_mac_X540:
3503 for (i = 0; i < adapter->num_rx_queues; i++) {
3504 j = adapter->rx_ring[i]->reg_idx;
3505 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3506 vlnctrl |= IXGBE_RXDCTL_VME;
3507 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3508 }
3509 break;
3510 default:
3511 break;
3512 }
3513 }
3514
3515 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3516 {
3517 u16 vid;
3518
3519 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3520
3521 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3522 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3523 }
3524
3525 /**
3526 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3527 * @netdev: network interface device structure
3528 *
3529 * Writes unicast address list to the RAR table.
3530 * Returns: -ENOMEM on failure/insufficient address space
3531 * 0 on no addresses written
3532 * X on writing X addresses to the RAR table
3533 **/
3534 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3535 {
3536 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3537 struct ixgbe_hw *hw = &adapter->hw;
3538 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3539 int count = 0;
3540
3541 /* In SR-IOV mode significantly less RAR entries are available */
3542 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3543 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3544
3545 /* return ENOMEM indicating insufficient memory for addresses */
3546 if (netdev_uc_count(netdev) > rar_entries)
3547 return -ENOMEM;
3548
3549 if (!netdev_uc_empty(netdev)) {
3550 struct netdev_hw_addr *ha;
3551 /* return error if we do not support writing to RAR table */
3552 if (!hw->mac.ops.set_rar)
3553 return -ENOMEM;
3554
3555 netdev_for_each_uc_addr(ha, netdev) {
3556 if (!rar_entries)
3557 break;
3558 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3559 VMDQ_P(0), IXGBE_RAH_AV);
3560 count++;
3561 }
3562 }
3563 /* write the addresses in reverse order to avoid write combining */
3564 for (; rar_entries > 0 ; rar_entries--)
3565 hw->mac.ops.clear_rar(hw, rar_entries);
3566
3567 return count;
3568 }
3569
3570 /**
3571 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3572 * @netdev: network interface device structure
3573 *
3574 * The set_rx_method entry point is called whenever the unicast/multicast
3575 * address list or the network interface flags are updated. This routine is
3576 * responsible for configuring the hardware for proper unicast, multicast and
3577 * promiscuous mode.
3578 **/
3579 void ixgbe_set_rx_mode(struct net_device *netdev)
3580 {
3581 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3582 struct ixgbe_hw *hw = &adapter->hw;
3583 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3584 int count;
3585
3586 /* Check for Promiscuous and All Multicast modes */
3587
3588 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3589
3590 /* set all bits that we expect to always be set */
3591 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3592 fctrl |= IXGBE_FCTRL_BAM;
3593 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3594 fctrl |= IXGBE_FCTRL_PMCF;
3595
3596 /* clear the bits we are changing the status of */
3597 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3598
3599 if (netdev->flags & IFF_PROMISC) {
3600 hw->addr_ctrl.user_set_promisc = true;
3601 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3602 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3603 /* don't hardware filter vlans in promisc mode */
3604 ixgbe_vlan_filter_disable(adapter);
3605 } else {
3606 if (netdev->flags & IFF_ALLMULTI) {
3607 fctrl |= IXGBE_FCTRL_MPE;
3608 vmolr |= IXGBE_VMOLR_MPE;
3609 } else {
3610 /*
3611 * Write addresses to the MTA, if the attempt fails
3612 * then we should just turn on promiscuous mode so
3613 * that we can at least receive multicast traffic
3614 */
3615 hw->mac.ops.update_mc_addr_list(hw, netdev);
3616 vmolr |= IXGBE_VMOLR_ROMPE;
3617 }
3618 ixgbe_vlan_filter_enable(adapter);
3619 hw->addr_ctrl.user_set_promisc = false;
3620 }
3621
3622 /*
3623 * Write addresses to available RAR registers, if there is not
3624 * sufficient space to store all the addresses then enable
3625 * unicast promiscuous mode
3626 */
3627 count = ixgbe_write_uc_addr_list(netdev);
3628 if (count < 0) {
3629 fctrl |= IXGBE_FCTRL_UPE;
3630 vmolr |= IXGBE_VMOLR_ROPE;
3631 }
3632
3633 if (adapter->num_vfs)
3634 ixgbe_restore_vf_multicasts(adapter);
3635
3636 if (hw->mac.type != ixgbe_mac_82598EB) {
3637 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3638 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3639 IXGBE_VMOLR_ROPE);
3640 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3641 }
3642
3643 /* This is useful for sniffing bad packets. */
3644 if (adapter->netdev->features & NETIF_F_RXALL) {
3645 /* UPE and MPE will be handled by normal PROMISC logic
3646 * in e1000e_set_rx_mode */
3647 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3648 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3649 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3650
3651 fctrl &= ~(IXGBE_FCTRL_DPF);
3652 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3653 }
3654
3655 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3656
3657 if (netdev->features & NETIF_F_HW_VLAN_RX)
3658 ixgbe_vlan_strip_enable(adapter);
3659 else
3660 ixgbe_vlan_strip_disable(adapter);
3661 }
3662
3663 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3664 {
3665 int q_idx;
3666
3667 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3668 napi_enable(&adapter->q_vector[q_idx]->napi);
3669 }
3670
3671 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3672 {
3673 int q_idx;
3674
3675 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3676 napi_disable(&adapter->q_vector[q_idx]->napi);
3677 }
3678
3679 #ifdef CONFIG_IXGBE_DCB
3680 /**
3681 * ixgbe_configure_dcb - Configure DCB hardware
3682 * @adapter: ixgbe adapter struct
3683 *
3684 * This is called by the driver on open to configure the DCB hardware.
3685 * This is also called by the gennetlink interface when reconfiguring
3686 * the DCB state.
3687 */
3688 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3689 {
3690 struct ixgbe_hw *hw = &adapter->hw;
3691 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3692
3693 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3694 if (hw->mac.type == ixgbe_mac_82598EB)
3695 netif_set_gso_max_size(adapter->netdev, 65536);
3696 return;
3697 }
3698
3699 if (hw->mac.type == ixgbe_mac_82598EB)
3700 netif_set_gso_max_size(adapter->netdev, 32768);
3701
3702 #ifdef IXGBE_FCOE
3703 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3704 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3705 #endif
3706
3707 /* reconfigure the hardware */
3708 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3709 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3710 DCB_TX_CONFIG);
3711 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3712 DCB_RX_CONFIG);
3713 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3714 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3715 ixgbe_dcb_hw_ets(&adapter->hw,
3716 adapter->ixgbe_ieee_ets,
3717 max_frame);
3718 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3719 adapter->ixgbe_ieee_pfc->pfc_en,
3720 adapter->ixgbe_ieee_ets->prio_tc);
3721 }
3722
3723 /* Enable RSS Hash per TC */
3724 if (hw->mac.type != ixgbe_mac_82598EB) {
3725 u32 msb = 0;
3726 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3727
3728 while (rss_i) {
3729 msb++;
3730 rss_i >>= 1;
3731 }
3732
3733 /* write msb to all 8 TCs in one write */
3734 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3735 }
3736 }
3737 #endif
3738
3739 /* Additional bittime to account for IXGBE framing */
3740 #define IXGBE_ETH_FRAMING 20
3741
3742 /**
3743 * ixgbe_hpbthresh - calculate high water mark for flow control
3744 *
3745 * @adapter: board private structure to calculate for
3746 * @pb: packet buffer to calculate
3747 */
3748 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3749 {
3750 struct ixgbe_hw *hw = &adapter->hw;
3751 struct net_device *dev = adapter->netdev;
3752 int link, tc, kb, marker;
3753 u32 dv_id, rx_pba;
3754
3755 /* Calculate max LAN frame size */
3756 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3757
3758 #ifdef IXGBE_FCOE
3759 /* FCoE traffic class uses FCOE jumbo frames */
3760 if ((dev->features & NETIF_F_FCOE_MTU) &&
3761 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3762 (pb == ixgbe_fcoe_get_tc(adapter)))
3763 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3764
3765 #endif
3766 /* Calculate delay value for device */
3767 switch (hw->mac.type) {
3768 case ixgbe_mac_X540:
3769 dv_id = IXGBE_DV_X540(link, tc);
3770 break;
3771 default:
3772 dv_id = IXGBE_DV(link, tc);
3773 break;
3774 }
3775
3776 /* Loopback switch introduces additional latency */
3777 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3778 dv_id += IXGBE_B2BT(tc);
3779
3780 /* Delay value is calculated in bit times convert to KB */
3781 kb = IXGBE_BT2KB(dv_id);
3782 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3783
3784 marker = rx_pba - kb;
3785
3786 /* It is possible that the packet buffer is not large enough
3787 * to provide required headroom. In this case throw an error
3788 * to user and a do the best we can.
3789 */
3790 if (marker < 0) {
3791 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3792 "headroom to support flow control."
3793 "Decrease MTU or number of traffic classes\n", pb);
3794 marker = tc + 1;
3795 }
3796
3797 return marker;
3798 }
3799
3800 /**
3801 * ixgbe_lpbthresh - calculate low water mark for for flow control
3802 *
3803 * @adapter: board private structure to calculate for
3804 * @pb: packet buffer to calculate
3805 */
3806 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3807 {
3808 struct ixgbe_hw *hw = &adapter->hw;
3809 struct net_device *dev = adapter->netdev;
3810 int tc;
3811 u32 dv_id;
3812
3813 /* Calculate max LAN frame size */
3814 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3815
3816 /* Calculate delay value for device */
3817 switch (hw->mac.type) {
3818 case ixgbe_mac_X540:
3819 dv_id = IXGBE_LOW_DV_X540(tc);
3820 break;
3821 default:
3822 dv_id = IXGBE_LOW_DV(tc);
3823 break;
3824 }
3825
3826 /* Delay value is calculated in bit times convert to KB */
3827 return IXGBE_BT2KB(dv_id);
3828 }
3829
3830 /*
3831 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3832 */
3833 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3834 {
3835 struct ixgbe_hw *hw = &adapter->hw;
3836 int num_tc = netdev_get_num_tc(adapter->netdev);
3837 int i;
3838
3839 if (!num_tc)
3840 num_tc = 1;
3841
3842 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3843
3844 for (i = 0; i < num_tc; i++) {
3845 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3846
3847 /* Low water marks must not be larger than high water marks */
3848 if (hw->fc.low_water > hw->fc.high_water[i])
3849 hw->fc.low_water = 0;
3850 }
3851 }
3852
3853 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3854 {
3855 struct ixgbe_hw *hw = &adapter->hw;
3856 int hdrm;
3857 u8 tc = netdev_get_num_tc(adapter->netdev);
3858
3859 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3860 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3861 hdrm = 32 << adapter->fdir_pballoc;
3862 else
3863 hdrm = 0;
3864
3865 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3866 ixgbe_pbthresh_setup(adapter);
3867 }
3868
3869 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3870 {
3871 struct ixgbe_hw *hw = &adapter->hw;
3872 struct hlist_node *node, *node2;
3873 struct ixgbe_fdir_filter *filter;
3874
3875 spin_lock(&adapter->fdir_perfect_lock);
3876
3877 if (!hlist_empty(&adapter->fdir_filter_list))
3878 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3879
3880 hlist_for_each_entry_safe(filter, node, node2,
3881 &adapter->fdir_filter_list, fdir_node) {
3882 ixgbe_fdir_write_perfect_filter_82599(hw,
3883 &filter->filter,
3884 filter->sw_idx,
3885 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3886 IXGBE_FDIR_DROP_QUEUE :
3887 adapter->rx_ring[filter->action]->reg_idx);
3888 }
3889
3890 spin_unlock(&adapter->fdir_perfect_lock);
3891 }
3892
3893 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3894 {
3895 struct ixgbe_hw *hw = &adapter->hw;
3896
3897 ixgbe_configure_pb(adapter);
3898 #ifdef CONFIG_IXGBE_DCB
3899 ixgbe_configure_dcb(adapter);
3900 #endif
3901 /*
3902 * We must restore virtualization before VLANs or else
3903 * the VLVF registers will not be populated
3904 */
3905 ixgbe_configure_virtualization(adapter);
3906
3907 ixgbe_set_rx_mode(adapter->netdev);
3908 ixgbe_restore_vlan(adapter);
3909
3910 switch (hw->mac.type) {
3911 case ixgbe_mac_82599EB:
3912 case ixgbe_mac_X540:
3913 hw->mac.ops.disable_rx_buff(hw);
3914 break;
3915 default:
3916 break;
3917 }
3918
3919 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3920 ixgbe_init_fdir_signature_82599(&adapter->hw,
3921 adapter->fdir_pballoc);
3922 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3923 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3924 adapter->fdir_pballoc);
3925 ixgbe_fdir_filter_restore(adapter);
3926 }
3927
3928 switch (hw->mac.type) {
3929 case ixgbe_mac_82599EB:
3930 case ixgbe_mac_X540:
3931 hw->mac.ops.enable_rx_buff(hw);
3932 break;
3933 default:
3934 break;
3935 }
3936
3937 #ifdef IXGBE_FCOE
3938 /* configure FCoE L2 filters, redirection table, and Rx control */
3939 ixgbe_configure_fcoe(adapter);
3940
3941 #endif /* IXGBE_FCOE */
3942 ixgbe_configure_tx(adapter);
3943 ixgbe_configure_rx(adapter);
3944 }
3945
3946 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3947 {
3948 switch (hw->phy.type) {
3949 case ixgbe_phy_sfp_avago:
3950 case ixgbe_phy_sfp_ftl:
3951 case ixgbe_phy_sfp_intel:
3952 case ixgbe_phy_sfp_unknown:
3953 case ixgbe_phy_sfp_passive_tyco:
3954 case ixgbe_phy_sfp_passive_unknown:
3955 case ixgbe_phy_sfp_active_unknown:
3956 case ixgbe_phy_sfp_ftl_active:
3957 return true;
3958 case ixgbe_phy_nl:
3959 if (hw->mac.type == ixgbe_mac_82598EB)
3960 return true;
3961 default:
3962 return false;
3963 }
3964 }
3965
3966 /**
3967 * ixgbe_sfp_link_config - set up SFP+ link
3968 * @adapter: pointer to private adapter struct
3969 **/
3970 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3971 {
3972 /*
3973 * We are assuming the worst case scenario here, and that
3974 * is that an SFP was inserted/removed after the reset
3975 * but before SFP detection was enabled. As such the best
3976 * solution is to just start searching as soon as we start
3977 */
3978 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3979 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3980
3981 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3982 }
3983
3984 /**
3985 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3986 * @hw: pointer to private hardware struct
3987 *
3988 * Returns 0 on success, negative on failure
3989 **/
3990 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3991 {
3992 u32 autoneg;
3993 bool negotiation, link_up = false;
3994 u32 ret = IXGBE_ERR_LINK_SETUP;
3995
3996 if (hw->mac.ops.check_link)
3997 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3998
3999 if (ret)
4000 goto link_cfg_out;
4001
4002 autoneg = hw->phy.autoneg_advertised;
4003 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4004 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
4005 &negotiation);
4006 if (ret)
4007 goto link_cfg_out;
4008
4009 if (hw->mac.ops.setup_link)
4010 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
4011 link_cfg_out:
4012 return ret;
4013 }
4014
4015 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4016 {
4017 struct ixgbe_hw *hw = &adapter->hw;
4018 u32 gpie = 0;
4019
4020 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4021 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4022 IXGBE_GPIE_OCD;
4023 gpie |= IXGBE_GPIE_EIAME;
4024 /*
4025 * use EIAM to auto-mask when MSI-X interrupt is asserted
4026 * this saves a register write for every interrupt
4027 */
4028 switch (hw->mac.type) {
4029 case ixgbe_mac_82598EB:
4030 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4031 break;
4032 case ixgbe_mac_82599EB:
4033 case ixgbe_mac_X540:
4034 default:
4035 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4036 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4037 break;
4038 }
4039 } else {
4040 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4041 * specifically only auto mask tx and rx interrupts */
4042 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4043 }
4044
4045 /* XXX: to interrupt immediately for EICS writes, enable this */
4046 /* gpie |= IXGBE_GPIE_EIMEN; */
4047
4048 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4049 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4050
4051 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4052 case IXGBE_82599_VMDQ_8Q_MASK:
4053 gpie |= IXGBE_GPIE_VTMODE_16;
4054 break;
4055 case IXGBE_82599_VMDQ_4Q_MASK:
4056 gpie |= IXGBE_GPIE_VTMODE_32;
4057 break;
4058 default:
4059 gpie |= IXGBE_GPIE_VTMODE_64;
4060 break;
4061 }
4062 }
4063
4064 /* Enable Thermal over heat sensor interrupt */
4065 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4066 switch (adapter->hw.mac.type) {
4067 case ixgbe_mac_82599EB:
4068 gpie |= IXGBE_SDP0_GPIEN;
4069 break;
4070 case ixgbe_mac_X540:
4071 gpie |= IXGBE_EIMS_TS;
4072 break;
4073 default:
4074 break;
4075 }
4076 }
4077
4078 /* Enable fan failure interrupt */
4079 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4080 gpie |= IXGBE_SDP1_GPIEN;
4081
4082 if (hw->mac.type == ixgbe_mac_82599EB) {
4083 gpie |= IXGBE_SDP1_GPIEN;
4084 gpie |= IXGBE_SDP2_GPIEN;
4085 }
4086
4087 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4088 }
4089
4090 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4091 {
4092 struct ixgbe_hw *hw = &adapter->hw;
4093 int err;
4094 u32 ctrl_ext;
4095
4096 ixgbe_get_hw_control(adapter);
4097 ixgbe_setup_gpie(adapter);
4098
4099 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4100 ixgbe_configure_msix(adapter);
4101 else
4102 ixgbe_configure_msi_and_legacy(adapter);
4103
4104 /* enable the optics for 82599 SFP+ fiber */
4105 if (hw->mac.ops.enable_tx_laser)
4106 hw->mac.ops.enable_tx_laser(hw);
4107
4108 clear_bit(__IXGBE_DOWN, &adapter->state);
4109 ixgbe_napi_enable_all(adapter);
4110
4111 if (ixgbe_is_sfp(hw)) {
4112 ixgbe_sfp_link_config(adapter);
4113 } else {
4114 err = ixgbe_non_sfp_link_config(hw);
4115 if (err)
4116 e_err(probe, "link_config FAILED %d\n", err);
4117 }
4118
4119 /* clear any pending interrupts, may auto mask */
4120 IXGBE_READ_REG(hw, IXGBE_EICR);
4121 ixgbe_irq_enable(adapter, true, true);
4122
4123 /*
4124 * If this adapter has a fan, check to see if we had a failure
4125 * before we enabled the interrupt.
4126 */
4127 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4128 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4129 if (esdp & IXGBE_ESDP_SDP1)
4130 e_crit(drv, "Fan has stopped, replace the adapter\n");
4131 }
4132
4133 /* enable transmits */
4134 netif_tx_start_all_queues(adapter->netdev);
4135
4136 /* bring the link up in the watchdog, this could race with our first
4137 * link up interrupt but shouldn't be a problem */
4138 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4139 adapter->link_check_timeout = jiffies;
4140 mod_timer(&adapter->service_timer, jiffies);
4141
4142 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4143 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4144 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4145 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4146 }
4147
4148 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4149 {
4150 WARN_ON(in_interrupt());
4151 /* put off any impending NetWatchDogTimeout */
4152 adapter->netdev->trans_start = jiffies;
4153
4154 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4155 usleep_range(1000, 2000);
4156 ixgbe_down(adapter);
4157 /*
4158 * If SR-IOV enabled then wait a bit before bringing the adapter
4159 * back up to give the VFs time to respond to the reset. The
4160 * two second wait is based upon the watchdog timer cycle in
4161 * the VF driver.
4162 */
4163 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4164 msleep(2000);
4165 ixgbe_up(adapter);
4166 clear_bit(__IXGBE_RESETTING, &adapter->state);
4167 }
4168
4169 void ixgbe_up(struct ixgbe_adapter *adapter)
4170 {
4171 /* hardware has been reset, we need to reload some things */
4172 ixgbe_configure(adapter);
4173
4174 ixgbe_up_complete(adapter);
4175 }
4176
4177 void ixgbe_reset(struct ixgbe_adapter *adapter)
4178 {
4179 struct ixgbe_hw *hw = &adapter->hw;
4180 int err;
4181
4182 /* lock SFP init bit to prevent race conditions with the watchdog */
4183 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4184 usleep_range(1000, 2000);
4185
4186 /* clear all SFP and link config related flags while holding SFP_INIT */
4187 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4188 IXGBE_FLAG2_SFP_NEEDS_RESET);
4189 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4190
4191 err = hw->mac.ops.init_hw(hw);
4192 switch (err) {
4193 case 0:
4194 case IXGBE_ERR_SFP_NOT_PRESENT:
4195 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4196 break;
4197 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4198 e_dev_err("master disable timed out\n");
4199 break;
4200 case IXGBE_ERR_EEPROM_VERSION:
4201 /* We are running on a pre-production device, log a warning */
4202 e_dev_warn("This device is a pre-production adapter/LOM. "
4203 "Please be aware there may be issues associated with "
4204 "your hardware. If you are experiencing problems "
4205 "please contact your Intel or hardware "
4206 "representative who provided you with this "
4207 "hardware.\n");
4208 break;
4209 default:
4210 e_dev_err("Hardware Error: %d\n", err);
4211 }
4212
4213 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4214
4215 /* reprogram the RAR[0] in case user changed it. */
4216 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4217
4218 /* update SAN MAC vmdq pool selection */
4219 if (hw->mac.san_mac_rar_index)
4220 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4221
4222 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4223 ixgbe_ptp_reset(adapter);
4224 }
4225
4226 /**
4227 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4228 * @rx_ring: ring to free buffers from
4229 **/
4230 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4231 {
4232 struct device *dev = rx_ring->dev;
4233 unsigned long size;
4234 u16 i;
4235
4236 /* ring already cleared, nothing to do */
4237 if (!rx_ring->rx_buffer_info)
4238 return;
4239
4240 /* Free all the Rx ring sk_buffs */
4241 for (i = 0; i < rx_ring->count; i++) {
4242 struct ixgbe_rx_buffer *rx_buffer;
4243
4244 rx_buffer = &rx_ring->rx_buffer_info[i];
4245 if (rx_buffer->skb) {
4246 struct sk_buff *skb = rx_buffer->skb;
4247 if (IXGBE_CB(skb)->page_released) {
4248 dma_unmap_page(dev,
4249 IXGBE_CB(skb)->dma,
4250 ixgbe_rx_bufsz(rx_ring),
4251 DMA_FROM_DEVICE);
4252 IXGBE_CB(skb)->page_released = false;
4253 }
4254 dev_kfree_skb(skb);
4255 }
4256 rx_buffer->skb = NULL;
4257 if (rx_buffer->dma)
4258 dma_unmap_page(dev, rx_buffer->dma,
4259 ixgbe_rx_pg_size(rx_ring),
4260 DMA_FROM_DEVICE);
4261 rx_buffer->dma = 0;
4262 if (rx_buffer->page)
4263 __free_pages(rx_buffer->page,
4264 ixgbe_rx_pg_order(rx_ring));
4265 rx_buffer->page = NULL;
4266 }
4267
4268 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4269 memset(rx_ring->rx_buffer_info, 0, size);
4270
4271 /* Zero out the descriptor ring */
4272 memset(rx_ring->desc, 0, rx_ring->size);
4273
4274 rx_ring->next_to_alloc = 0;
4275 rx_ring->next_to_clean = 0;
4276 rx_ring->next_to_use = 0;
4277 }
4278
4279 /**
4280 * ixgbe_clean_tx_ring - Free Tx Buffers
4281 * @tx_ring: ring to be cleaned
4282 **/
4283 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4284 {
4285 struct ixgbe_tx_buffer *tx_buffer_info;
4286 unsigned long size;
4287 u16 i;
4288
4289 /* ring already cleared, nothing to do */
4290 if (!tx_ring->tx_buffer_info)
4291 return;
4292
4293 /* Free all the Tx ring sk_buffs */
4294 for (i = 0; i < tx_ring->count; i++) {
4295 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4296 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4297 }
4298
4299 netdev_tx_reset_queue(txring_txq(tx_ring));
4300
4301 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4302 memset(tx_ring->tx_buffer_info, 0, size);
4303
4304 /* Zero out the descriptor ring */
4305 memset(tx_ring->desc, 0, tx_ring->size);
4306
4307 tx_ring->next_to_use = 0;
4308 tx_ring->next_to_clean = 0;
4309 }
4310
4311 /**
4312 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4313 * @adapter: board private structure
4314 **/
4315 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4316 {
4317 int i;
4318
4319 for (i = 0; i < adapter->num_rx_queues; i++)
4320 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4321 }
4322
4323 /**
4324 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4325 * @adapter: board private structure
4326 **/
4327 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4328 {
4329 int i;
4330
4331 for (i = 0; i < adapter->num_tx_queues; i++)
4332 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4333 }
4334
4335 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4336 {
4337 struct hlist_node *node, *node2;
4338 struct ixgbe_fdir_filter *filter;
4339
4340 spin_lock(&adapter->fdir_perfect_lock);
4341
4342 hlist_for_each_entry_safe(filter, node, node2,
4343 &adapter->fdir_filter_list, fdir_node) {
4344 hlist_del(&filter->fdir_node);
4345 kfree(filter);
4346 }
4347 adapter->fdir_filter_count = 0;
4348
4349 spin_unlock(&adapter->fdir_perfect_lock);
4350 }
4351
4352 void ixgbe_down(struct ixgbe_adapter *adapter)
4353 {
4354 struct net_device *netdev = adapter->netdev;
4355 struct ixgbe_hw *hw = &adapter->hw;
4356 u32 rxctrl;
4357 int i;
4358
4359 /* signal that we are down to the interrupt handler */
4360 set_bit(__IXGBE_DOWN, &adapter->state);
4361
4362 /* disable receives */
4363 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4364 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4365
4366 /* disable all enabled rx queues */
4367 for (i = 0; i < adapter->num_rx_queues; i++)
4368 /* this call also flushes the previous write */
4369 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4370
4371 usleep_range(10000, 20000);
4372
4373 netif_tx_stop_all_queues(netdev);
4374
4375 /* call carrier off first to avoid false dev_watchdog timeouts */
4376 netif_carrier_off(netdev);
4377 netif_tx_disable(netdev);
4378
4379 ixgbe_irq_disable(adapter);
4380
4381 ixgbe_napi_disable_all(adapter);
4382
4383 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4384 IXGBE_FLAG2_RESET_REQUESTED);
4385 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4386
4387 del_timer_sync(&adapter->service_timer);
4388
4389 if (adapter->num_vfs) {
4390 /* Clear EITR Select mapping */
4391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4392
4393 /* Mark all the VFs as inactive */
4394 for (i = 0 ; i < adapter->num_vfs; i++)
4395 adapter->vfinfo[i].clear_to_send = false;
4396
4397 /* ping all the active vfs to let them know we are going down */
4398 ixgbe_ping_all_vfs(adapter);
4399
4400 /* Disable all VFTE/VFRE TX/RX */
4401 ixgbe_disable_tx_rx(adapter);
4402 }
4403
4404 /* disable transmits in the hardware now that interrupts are off */
4405 for (i = 0; i < adapter->num_tx_queues; i++) {
4406 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4407 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4408 }
4409
4410 /* Disable the Tx DMA engine on 82599 and X540 */
4411 switch (hw->mac.type) {
4412 case ixgbe_mac_82599EB:
4413 case ixgbe_mac_X540:
4414 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4415 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4416 ~IXGBE_DMATXCTL_TE));
4417 break;
4418 default:
4419 break;
4420 }
4421
4422 if (!pci_channel_offline(adapter->pdev))
4423 ixgbe_reset(adapter);
4424
4425 /* power down the optics for 82599 SFP+ fiber */
4426 if (hw->mac.ops.disable_tx_laser)
4427 hw->mac.ops.disable_tx_laser(hw);
4428
4429 ixgbe_clean_all_tx_rings(adapter);
4430 ixgbe_clean_all_rx_rings(adapter);
4431
4432 #ifdef CONFIG_IXGBE_DCA
4433 /* since we reset the hardware DCA settings were cleared */
4434 ixgbe_setup_dca(adapter);
4435 #endif
4436 }
4437
4438 /**
4439 * ixgbe_tx_timeout - Respond to a Tx Hang
4440 * @netdev: network interface device structure
4441 **/
4442 static void ixgbe_tx_timeout(struct net_device *netdev)
4443 {
4444 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4445
4446 /* Do the reset outside of interrupt context */
4447 ixgbe_tx_timeout_reset(adapter);
4448 }
4449
4450 /**
4451 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4452 * @adapter: board private structure to initialize
4453 *
4454 * ixgbe_sw_init initializes the Adapter private data structure.
4455 * Fields are initialized based on PCI device information and
4456 * OS network device settings (MTU size).
4457 **/
4458 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4459 {
4460 struct ixgbe_hw *hw = &adapter->hw;
4461 struct pci_dev *pdev = adapter->pdev;
4462 unsigned int rss;
4463 #ifdef CONFIG_IXGBE_DCB
4464 int j;
4465 struct tc_configuration *tc;
4466 #endif
4467
4468 /* PCI config space info */
4469
4470 hw->vendor_id = pdev->vendor;
4471 hw->device_id = pdev->device;
4472 hw->revision_id = pdev->revision;
4473 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4474 hw->subsystem_device_id = pdev->subsystem_device;
4475
4476 /* Set capability flags */
4477 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4478 adapter->ring_feature[RING_F_RSS].limit = rss;
4479 switch (hw->mac.type) {
4480 case ixgbe_mac_82598EB:
4481 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4482 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4483 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4484 break;
4485 case ixgbe_mac_X540:
4486 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4487 case ixgbe_mac_82599EB:
4488 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4489 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4490 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4491 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4492 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4493 /* Flow Director hash filters enabled */
4494 adapter->atr_sample_rate = 20;
4495 adapter->ring_feature[RING_F_FDIR].limit =
4496 IXGBE_MAX_FDIR_INDICES;
4497 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4498 #ifdef IXGBE_FCOE
4499 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4500 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4501 #ifdef CONFIG_IXGBE_DCB
4502 /* Default traffic class to use for FCoE */
4503 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4504 #endif
4505 #endif /* IXGBE_FCOE */
4506 break;
4507 default:
4508 break;
4509 }
4510
4511 #ifdef IXGBE_FCOE
4512 /* FCoE support exists, always init the FCoE lock */
4513 spin_lock_init(&adapter->fcoe.lock);
4514
4515 #endif
4516 /* n-tuple support exists, always init our spinlock */
4517 spin_lock_init(&adapter->fdir_perfect_lock);
4518
4519 #ifdef CONFIG_IXGBE_DCB
4520 switch (hw->mac.type) {
4521 case ixgbe_mac_X540:
4522 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4523 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4524 break;
4525 default:
4526 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4527 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4528 break;
4529 }
4530
4531 /* Configure DCB traffic classes */
4532 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4533 tc = &adapter->dcb_cfg.tc_config[j];
4534 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4535 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4536 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4537 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4538 tc->dcb_pfc = pfc_disabled;
4539 }
4540
4541 /* Initialize default user to priority mapping, UPx->TC0 */
4542 tc = &adapter->dcb_cfg.tc_config[0];
4543 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4544 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4545
4546 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4547 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4548 adapter->dcb_cfg.pfc_mode_enable = false;
4549 adapter->dcb_set_bitmap = 0x00;
4550 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4551 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4552 sizeof(adapter->temp_dcb_cfg));
4553
4554 #endif
4555
4556 /* default flow control settings */
4557 hw->fc.requested_mode = ixgbe_fc_full;
4558 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4559 ixgbe_pbthresh_setup(adapter);
4560 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4561 hw->fc.send_xon = true;
4562 hw->fc.disable_fc_autoneg =
4563 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4564
4565 #ifdef CONFIG_PCI_IOV
4566 /* assign number of SR-IOV VFs */
4567 if (hw->mac.type != ixgbe_mac_82598EB)
4568 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4569
4570 #endif
4571 /* enable itr by default in dynamic mode */
4572 adapter->rx_itr_setting = 1;
4573 adapter->tx_itr_setting = 1;
4574
4575 /* set default ring sizes */
4576 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4577 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4578
4579 /* set default work limits */
4580 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4581
4582 /* initialize eeprom parameters */
4583 if (ixgbe_init_eeprom_params_generic(hw)) {
4584 e_dev_err("EEPROM initialization failed\n");
4585 return -EIO;
4586 }
4587
4588 set_bit(__IXGBE_DOWN, &adapter->state);
4589
4590 return 0;
4591 }
4592
4593 /**
4594 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4595 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4596 *
4597 * Return 0 on success, negative on failure
4598 **/
4599 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4600 {
4601 struct device *dev = tx_ring->dev;
4602 int orig_node = dev_to_node(dev);
4603 int numa_node = -1;
4604 int size;
4605
4606 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4607
4608 if (tx_ring->q_vector)
4609 numa_node = tx_ring->q_vector->numa_node;
4610
4611 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4612 if (!tx_ring->tx_buffer_info)
4613 tx_ring->tx_buffer_info = vzalloc(size);
4614 if (!tx_ring->tx_buffer_info)
4615 goto err;
4616
4617 /* round up to nearest 4K */
4618 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4619 tx_ring->size = ALIGN(tx_ring->size, 4096);
4620
4621 set_dev_node(dev, numa_node);
4622 tx_ring->desc = dma_alloc_coherent(dev,
4623 tx_ring->size,
4624 &tx_ring->dma,
4625 GFP_KERNEL);
4626 set_dev_node(dev, orig_node);
4627 if (!tx_ring->desc)
4628 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4629 &tx_ring->dma, GFP_KERNEL);
4630 if (!tx_ring->desc)
4631 goto err;
4632
4633 tx_ring->next_to_use = 0;
4634 tx_ring->next_to_clean = 0;
4635 return 0;
4636
4637 err:
4638 vfree(tx_ring->tx_buffer_info);
4639 tx_ring->tx_buffer_info = NULL;
4640 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4641 return -ENOMEM;
4642 }
4643
4644 /**
4645 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4646 * @adapter: board private structure
4647 *
4648 * If this function returns with an error, then it's possible one or
4649 * more of the rings is populated (while the rest are not). It is the
4650 * callers duty to clean those orphaned rings.
4651 *
4652 * Return 0 on success, negative on failure
4653 **/
4654 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4655 {
4656 int i, err = 0;
4657
4658 for (i = 0; i < adapter->num_tx_queues; i++) {
4659 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4660 if (!err)
4661 continue;
4662
4663 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4664 goto err_setup_tx;
4665 }
4666
4667 return 0;
4668 err_setup_tx:
4669 /* rewind the index freeing the rings as we go */
4670 while (i--)
4671 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4672 return err;
4673 }
4674
4675 /**
4676 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4677 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4678 *
4679 * Returns 0 on success, negative on failure
4680 **/
4681 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4682 {
4683 struct device *dev = rx_ring->dev;
4684 int orig_node = dev_to_node(dev);
4685 int numa_node = -1;
4686 int size;
4687
4688 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4689
4690 if (rx_ring->q_vector)
4691 numa_node = rx_ring->q_vector->numa_node;
4692
4693 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4694 if (!rx_ring->rx_buffer_info)
4695 rx_ring->rx_buffer_info = vzalloc(size);
4696 if (!rx_ring->rx_buffer_info)
4697 goto err;
4698
4699 /* Round up to nearest 4K */
4700 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4701 rx_ring->size = ALIGN(rx_ring->size, 4096);
4702
4703 set_dev_node(dev, numa_node);
4704 rx_ring->desc = dma_alloc_coherent(dev,
4705 rx_ring->size,
4706 &rx_ring->dma,
4707 GFP_KERNEL);
4708 set_dev_node(dev, orig_node);
4709 if (!rx_ring->desc)
4710 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4711 &rx_ring->dma, GFP_KERNEL);
4712 if (!rx_ring->desc)
4713 goto err;
4714
4715 rx_ring->next_to_clean = 0;
4716 rx_ring->next_to_use = 0;
4717
4718 return 0;
4719 err:
4720 vfree(rx_ring->rx_buffer_info);
4721 rx_ring->rx_buffer_info = NULL;
4722 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4723 return -ENOMEM;
4724 }
4725
4726 /**
4727 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4728 * @adapter: board private structure
4729 *
4730 * If this function returns with an error, then it's possible one or
4731 * more of the rings is populated (while the rest are not). It is the
4732 * callers duty to clean those orphaned rings.
4733 *
4734 * Return 0 on success, negative on failure
4735 **/
4736 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4737 {
4738 int i, err = 0;
4739
4740 for (i = 0; i < adapter->num_rx_queues; i++) {
4741 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4742 if (!err)
4743 continue;
4744
4745 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4746 goto err_setup_rx;
4747 }
4748
4749 #ifdef IXGBE_FCOE
4750 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4751 if (!err)
4752 #endif
4753 return 0;
4754 err_setup_rx:
4755 /* rewind the index freeing the rings as we go */
4756 while (i--)
4757 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4758 return err;
4759 }
4760
4761 /**
4762 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4763 * @tx_ring: Tx descriptor ring for a specific queue
4764 *
4765 * Free all transmit software resources
4766 **/
4767 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4768 {
4769 ixgbe_clean_tx_ring(tx_ring);
4770
4771 vfree(tx_ring->tx_buffer_info);
4772 tx_ring->tx_buffer_info = NULL;
4773
4774 /* if not set, then don't free */
4775 if (!tx_ring->desc)
4776 return;
4777
4778 dma_free_coherent(tx_ring->dev, tx_ring->size,
4779 tx_ring->desc, tx_ring->dma);
4780
4781 tx_ring->desc = NULL;
4782 }
4783
4784 /**
4785 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4786 * @adapter: board private structure
4787 *
4788 * Free all transmit software resources
4789 **/
4790 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4791 {
4792 int i;
4793
4794 for (i = 0; i < adapter->num_tx_queues; i++)
4795 if (adapter->tx_ring[i]->desc)
4796 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4797 }
4798
4799 /**
4800 * ixgbe_free_rx_resources - Free Rx Resources
4801 * @rx_ring: ring to clean the resources from
4802 *
4803 * Free all receive software resources
4804 **/
4805 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4806 {
4807 ixgbe_clean_rx_ring(rx_ring);
4808
4809 vfree(rx_ring->rx_buffer_info);
4810 rx_ring->rx_buffer_info = NULL;
4811
4812 /* if not set, then don't free */
4813 if (!rx_ring->desc)
4814 return;
4815
4816 dma_free_coherent(rx_ring->dev, rx_ring->size,
4817 rx_ring->desc, rx_ring->dma);
4818
4819 rx_ring->desc = NULL;
4820 }
4821
4822 /**
4823 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4824 * @adapter: board private structure
4825 *
4826 * Free all receive software resources
4827 **/
4828 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4829 {
4830 int i;
4831
4832 #ifdef IXGBE_FCOE
4833 ixgbe_free_fcoe_ddp_resources(adapter);
4834
4835 #endif
4836 for (i = 0; i < adapter->num_rx_queues; i++)
4837 if (adapter->rx_ring[i]->desc)
4838 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4839 }
4840
4841 /**
4842 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4843 * @netdev: network interface device structure
4844 * @new_mtu: new value for maximum frame size
4845 *
4846 * Returns 0 on success, negative on failure
4847 **/
4848 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4849 {
4850 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4851 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4852
4853 /* MTU < 68 is an error and causes problems on some kernels */
4854 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4855 return -EINVAL;
4856
4857 /*
4858 * For 82599EB we cannot allow legacy VFs to enable their receive
4859 * paths when MTU greater than 1500 is configured. So display a
4860 * warning that legacy VFs will be disabled.
4861 */
4862 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4863 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4864 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4865 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4866
4867 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4868
4869 /* must set new MTU before calling down or up */
4870 netdev->mtu = new_mtu;
4871
4872 if (netif_running(netdev))
4873 ixgbe_reinit_locked(adapter);
4874
4875 return 0;
4876 }
4877
4878 /**
4879 * ixgbe_open - Called when a network interface is made active
4880 * @netdev: network interface device structure
4881 *
4882 * Returns 0 on success, negative value on failure
4883 *
4884 * The open entry point is called when a network interface is made
4885 * active by the system (IFF_UP). At this point all resources needed
4886 * for transmit and receive operations are allocated, the interrupt
4887 * handler is registered with the OS, the watchdog timer is started,
4888 * and the stack is notified that the interface is ready.
4889 **/
4890 static int ixgbe_open(struct net_device *netdev)
4891 {
4892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4893 int err;
4894
4895 /* disallow open during test */
4896 if (test_bit(__IXGBE_TESTING, &adapter->state))
4897 return -EBUSY;
4898
4899 netif_carrier_off(netdev);
4900
4901 /* allocate transmit descriptors */
4902 err = ixgbe_setup_all_tx_resources(adapter);
4903 if (err)
4904 goto err_setup_tx;
4905
4906 /* allocate receive descriptors */
4907 err = ixgbe_setup_all_rx_resources(adapter);
4908 if (err)
4909 goto err_setup_rx;
4910
4911 ixgbe_configure(adapter);
4912
4913 err = ixgbe_request_irq(adapter);
4914 if (err)
4915 goto err_req_irq;
4916
4917 /* Notify the stack of the actual queue counts. */
4918 err = netif_set_real_num_tx_queues(netdev,
4919 adapter->num_rx_pools > 1 ? 1 :
4920 adapter->num_tx_queues);
4921 if (err)
4922 goto err_set_queues;
4923
4924
4925 err = netif_set_real_num_rx_queues(netdev,
4926 adapter->num_rx_pools > 1 ? 1 :
4927 adapter->num_rx_queues);
4928 if (err)
4929 goto err_set_queues;
4930
4931 ixgbe_ptp_init(adapter);
4932
4933 ixgbe_up_complete(adapter);
4934
4935 return 0;
4936
4937 err_set_queues:
4938 ixgbe_free_irq(adapter);
4939 err_req_irq:
4940 ixgbe_free_all_rx_resources(adapter);
4941 err_setup_rx:
4942 ixgbe_free_all_tx_resources(adapter);
4943 err_setup_tx:
4944 ixgbe_reset(adapter);
4945
4946 return err;
4947 }
4948
4949 /**
4950 * ixgbe_close - Disables a network interface
4951 * @netdev: network interface device structure
4952 *
4953 * Returns 0, this is not allowed to fail
4954 *
4955 * The close entry point is called when an interface is de-activated
4956 * by the OS. The hardware is still under the drivers control, but
4957 * needs to be disabled. A global MAC reset is issued to stop the
4958 * hardware, and all transmit and receive resources are freed.
4959 **/
4960 static int ixgbe_close(struct net_device *netdev)
4961 {
4962 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4963
4964 ixgbe_ptp_stop(adapter);
4965
4966 ixgbe_down(adapter);
4967 ixgbe_free_irq(adapter);
4968
4969 ixgbe_fdir_filter_exit(adapter);
4970
4971 ixgbe_free_all_tx_resources(adapter);
4972 ixgbe_free_all_rx_resources(adapter);
4973
4974 ixgbe_release_hw_control(adapter);
4975
4976 return 0;
4977 }
4978
4979 #ifdef CONFIG_PM
4980 static int ixgbe_resume(struct pci_dev *pdev)
4981 {
4982 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4983 struct net_device *netdev = adapter->netdev;
4984 u32 err;
4985
4986 pci_set_power_state(pdev, PCI_D0);
4987 pci_restore_state(pdev);
4988 /*
4989 * pci_restore_state clears dev->state_saved so call
4990 * pci_save_state to restore it.
4991 */
4992 pci_save_state(pdev);
4993
4994 err = pci_enable_device_mem(pdev);
4995 if (err) {
4996 e_dev_err("Cannot enable PCI device from suspend\n");
4997 return err;
4998 }
4999 pci_set_master(pdev);
5000
5001 pci_wake_from_d3(pdev, false);
5002
5003 ixgbe_reset(adapter);
5004
5005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5006
5007 rtnl_lock();
5008 err = ixgbe_init_interrupt_scheme(adapter);
5009 if (!err && netif_running(netdev))
5010 err = ixgbe_open(netdev);
5011
5012 rtnl_unlock();
5013
5014 if (err)
5015 return err;
5016
5017 netif_device_attach(netdev);
5018
5019 return 0;
5020 }
5021 #endif /* CONFIG_PM */
5022
5023 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5024 {
5025 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5026 struct net_device *netdev = adapter->netdev;
5027 struct ixgbe_hw *hw = &adapter->hw;
5028 u32 ctrl, fctrl;
5029 u32 wufc = adapter->wol;
5030 #ifdef CONFIG_PM
5031 int retval = 0;
5032 #endif
5033
5034 netif_device_detach(netdev);
5035
5036 if (netif_running(netdev)) {
5037 rtnl_lock();
5038 ixgbe_down(adapter);
5039 ixgbe_free_irq(adapter);
5040 ixgbe_free_all_tx_resources(adapter);
5041 ixgbe_free_all_rx_resources(adapter);
5042 rtnl_unlock();
5043 }
5044
5045 ixgbe_clear_interrupt_scheme(adapter);
5046
5047 #ifdef CONFIG_PM
5048 retval = pci_save_state(pdev);
5049 if (retval)
5050 return retval;
5051
5052 #endif
5053 if (wufc) {
5054 ixgbe_set_rx_mode(netdev);
5055
5056 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5057 if (hw->mac.ops.enable_tx_laser)
5058 hw->mac.ops.enable_tx_laser(hw);
5059
5060 /* turn on all-multi mode if wake on multicast is enabled */
5061 if (wufc & IXGBE_WUFC_MC) {
5062 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5063 fctrl |= IXGBE_FCTRL_MPE;
5064 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5065 }
5066
5067 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5068 ctrl |= IXGBE_CTRL_GIO_DIS;
5069 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5070
5071 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5072 } else {
5073 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5074 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5075 }
5076
5077 switch (hw->mac.type) {
5078 case ixgbe_mac_82598EB:
5079 pci_wake_from_d3(pdev, false);
5080 break;
5081 case ixgbe_mac_82599EB:
5082 case ixgbe_mac_X540:
5083 pci_wake_from_d3(pdev, !!wufc);
5084 break;
5085 default:
5086 break;
5087 }
5088
5089 *enable_wake = !!wufc;
5090
5091 ixgbe_release_hw_control(adapter);
5092
5093 pci_disable_device(pdev);
5094
5095 return 0;
5096 }
5097
5098 #ifdef CONFIG_PM
5099 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5100 {
5101 int retval;
5102 bool wake;
5103
5104 retval = __ixgbe_shutdown(pdev, &wake);
5105 if (retval)
5106 return retval;
5107
5108 if (wake) {
5109 pci_prepare_to_sleep(pdev);
5110 } else {
5111 pci_wake_from_d3(pdev, false);
5112 pci_set_power_state(pdev, PCI_D3hot);
5113 }
5114
5115 return 0;
5116 }
5117 #endif /* CONFIG_PM */
5118
5119 static void ixgbe_shutdown(struct pci_dev *pdev)
5120 {
5121 bool wake;
5122
5123 __ixgbe_shutdown(pdev, &wake);
5124
5125 if (system_state == SYSTEM_POWER_OFF) {
5126 pci_wake_from_d3(pdev, wake);
5127 pci_set_power_state(pdev, PCI_D3hot);
5128 }
5129 }
5130
5131 /**
5132 * ixgbe_update_stats - Update the board statistics counters.
5133 * @adapter: board private structure
5134 **/
5135 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5136 {
5137 struct net_device *netdev = adapter->netdev;
5138 struct ixgbe_hw *hw = &adapter->hw;
5139 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5140 u64 total_mpc = 0;
5141 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5142 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5143 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5144 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5145
5146 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5147 test_bit(__IXGBE_RESETTING, &adapter->state))
5148 return;
5149
5150 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5151 u64 rsc_count = 0;
5152 u64 rsc_flush = 0;
5153 for (i = 0; i < adapter->num_rx_queues; i++) {
5154 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5155 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5156 }
5157 adapter->rsc_total_count = rsc_count;
5158 adapter->rsc_total_flush = rsc_flush;
5159 }
5160
5161 for (i = 0; i < adapter->num_rx_queues; i++) {
5162 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5163 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5164 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5165 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5166 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5167 bytes += rx_ring->stats.bytes;
5168 packets += rx_ring->stats.packets;
5169 }
5170 adapter->non_eop_descs = non_eop_descs;
5171 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5172 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5173 adapter->hw_csum_rx_error = hw_csum_rx_error;
5174 netdev->stats.rx_bytes = bytes;
5175 netdev->stats.rx_packets = packets;
5176
5177 bytes = 0;
5178 packets = 0;
5179 /* gather some stats to the adapter struct that are per queue */
5180 for (i = 0; i < adapter->num_tx_queues; i++) {
5181 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5182 restart_queue += tx_ring->tx_stats.restart_queue;
5183 tx_busy += tx_ring->tx_stats.tx_busy;
5184 bytes += tx_ring->stats.bytes;
5185 packets += tx_ring->stats.packets;
5186 }
5187 adapter->restart_queue = restart_queue;
5188 adapter->tx_busy = tx_busy;
5189 netdev->stats.tx_bytes = bytes;
5190 netdev->stats.tx_packets = packets;
5191
5192 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5193
5194 /* 8 register reads */
5195 for (i = 0; i < 8; i++) {
5196 /* for packet buffers not used, the register should read 0 */
5197 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5198 missed_rx += mpc;
5199 hwstats->mpc[i] += mpc;
5200 total_mpc += hwstats->mpc[i];
5201 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5202 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5203 switch (hw->mac.type) {
5204 case ixgbe_mac_82598EB:
5205 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5206 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5207 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5208 hwstats->pxonrxc[i] +=
5209 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5210 break;
5211 case ixgbe_mac_82599EB:
5212 case ixgbe_mac_X540:
5213 hwstats->pxonrxc[i] +=
5214 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5215 break;
5216 default:
5217 break;
5218 }
5219 }
5220
5221 /*16 register reads */
5222 for (i = 0; i < 16; i++) {
5223 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5224 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5225 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5226 (hw->mac.type == ixgbe_mac_X540)) {
5227 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5228 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5229 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5230 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5231 }
5232 }
5233
5234 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5235 /* work around hardware counting issue */
5236 hwstats->gprc -= missed_rx;
5237
5238 ixgbe_update_xoff_received(adapter);
5239
5240 /* 82598 hardware only has a 32 bit counter in the high register */
5241 switch (hw->mac.type) {
5242 case ixgbe_mac_82598EB:
5243 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5244 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5245 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5246 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5247 break;
5248 case ixgbe_mac_X540:
5249 /* OS2BMC stats are X540 only*/
5250 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5251 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5252 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5253 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5254 case ixgbe_mac_82599EB:
5255 for (i = 0; i < 16; i++)
5256 adapter->hw_rx_no_dma_resources +=
5257 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5258 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5259 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5260 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5261 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5262 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5263 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5264 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5265 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5266 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5267 #ifdef IXGBE_FCOE
5268 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5269 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5270 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5271 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5272 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5273 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5274 /* Add up per cpu counters for total ddp aloc fail */
5275 if (adapter->fcoe.ddp_pool) {
5276 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5277 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5278 unsigned int cpu;
5279 u64 noddp = 0, noddp_ext_buff = 0;
5280 for_each_possible_cpu(cpu) {
5281 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5282 noddp += ddp_pool->noddp;
5283 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5284 }
5285 hwstats->fcoe_noddp = noddp;
5286 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5287 }
5288 #endif /* IXGBE_FCOE */
5289 break;
5290 default:
5291 break;
5292 }
5293 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5294 hwstats->bprc += bprc;
5295 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5296 if (hw->mac.type == ixgbe_mac_82598EB)
5297 hwstats->mprc -= bprc;
5298 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5299 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5300 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5301 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5302 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5303 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5304 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5305 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5306 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5307 hwstats->lxontxc += lxon;
5308 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5309 hwstats->lxofftxc += lxoff;
5310 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5311 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5312 /*
5313 * 82598 errata - tx of flow control packets is included in tx counters
5314 */
5315 xon_off_tot = lxon + lxoff;
5316 hwstats->gptc -= xon_off_tot;
5317 hwstats->mptc -= xon_off_tot;
5318 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5319 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5320 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5321 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5322 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5323 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5324 hwstats->ptc64 -= xon_off_tot;
5325 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5326 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5327 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5328 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5329 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5330 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5331
5332 /* Fill out the OS statistics structure */
5333 netdev->stats.multicast = hwstats->mprc;
5334
5335 /* Rx Errors */
5336 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5337 netdev->stats.rx_dropped = 0;
5338 netdev->stats.rx_length_errors = hwstats->rlec;
5339 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5340 netdev->stats.rx_missed_errors = total_mpc;
5341 }
5342
5343 /**
5344 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5345 * @adapter: pointer to the device adapter structure
5346 **/
5347 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5348 {
5349 struct ixgbe_hw *hw = &adapter->hw;
5350 int i;
5351
5352 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5353 return;
5354
5355 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5356
5357 /* if interface is down do nothing */
5358 if (test_bit(__IXGBE_DOWN, &adapter->state))
5359 return;
5360
5361 /* do nothing if we are not using signature filters */
5362 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5363 return;
5364
5365 adapter->fdir_overflow++;
5366
5367 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5368 for (i = 0; i < adapter->num_tx_queues; i++)
5369 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5370 &(adapter->tx_ring[i]->state));
5371 /* re-enable flow director interrupts */
5372 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5373 } else {
5374 e_err(probe, "failed to finish FDIR re-initialization, "
5375 "ignored adding FDIR ATR filters\n");
5376 }
5377 }
5378
5379 /**
5380 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5381 * @adapter: pointer to the device adapter structure
5382 *
5383 * This function serves two purposes. First it strobes the interrupt lines
5384 * in order to make certain interrupts are occurring. Secondly it sets the
5385 * bits needed to check for TX hangs. As a result we should immediately
5386 * determine if a hang has occurred.
5387 */
5388 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5389 {
5390 struct ixgbe_hw *hw = &adapter->hw;
5391 u64 eics = 0;
5392 int i;
5393
5394 /* If we're down or resetting, just bail */
5395 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5396 test_bit(__IXGBE_RESETTING, &adapter->state))
5397 return;
5398
5399 /* Force detection of hung controller */
5400 if (netif_carrier_ok(adapter->netdev)) {
5401 for (i = 0; i < adapter->num_tx_queues; i++)
5402 set_check_for_tx_hang(adapter->tx_ring[i]);
5403 }
5404
5405 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5406 /*
5407 * for legacy and MSI interrupts don't set any bits
5408 * that are enabled for EIAM, because this operation
5409 * would set *both* EIMS and EICS for any bit in EIAM
5410 */
5411 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5412 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5413 } else {
5414 /* get one bit for every active tx/rx interrupt vector */
5415 for (i = 0; i < adapter->num_q_vectors; i++) {
5416 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5417 if (qv->rx.ring || qv->tx.ring)
5418 eics |= ((u64)1 << i);
5419 }
5420 }
5421
5422 /* Cause software interrupt to ensure rings are cleaned */
5423 ixgbe_irq_rearm_queues(adapter, eics);
5424
5425 }
5426
5427 /**
5428 * ixgbe_watchdog_update_link - update the link status
5429 * @adapter: pointer to the device adapter structure
5430 * @link_speed: pointer to a u32 to store the link_speed
5431 **/
5432 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5433 {
5434 struct ixgbe_hw *hw = &adapter->hw;
5435 u32 link_speed = adapter->link_speed;
5436 bool link_up = adapter->link_up;
5437 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5438
5439 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5440 return;
5441
5442 if (hw->mac.ops.check_link) {
5443 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5444 } else {
5445 /* always assume link is up, if no check link function */
5446 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5447 link_up = true;
5448 }
5449
5450 if (adapter->ixgbe_ieee_pfc)
5451 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5452
5453 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5454 hw->mac.ops.fc_enable(hw);
5455 ixgbe_set_rx_drop_en(adapter);
5456 }
5457
5458 if (link_up ||
5459 time_after(jiffies, (adapter->link_check_timeout +
5460 IXGBE_TRY_LINK_TIMEOUT))) {
5461 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5462 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5463 IXGBE_WRITE_FLUSH(hw);
5464 }
5465
5466 adapter->link_up = link_up;
5467 adapter->link_speed = link_speed;
5468 }
5469
5470 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5471 {
5472 #ifdef CONFIG_IXGBE_DCB
5473 struct net_device *netdev = adapter->netdev;
5474 struct dcb_app app = {
5475 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5476 .protocol = 0,
5477 };
5478 u8 up = 0;
5479
5480 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5481 up = dcb_ieee_getapp_mask(netdev, &app);
5482
5483 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5484 #endif
5485 }
5486
5487 /**
5488 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5489 * print link up message
5490 * @adapter: pointer to the device adapter structure
5491 **/
5492 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5493 {
5494 struct net_device *netdev = adapter->netdev;
5495 struct ixgbe_hw *hw = &adapter->hw;
5496 u32 link_speed = adapter->link_speed;
5497 bool flow_rx, flow_tx;
5498
5499 /* only continue if link was previously down */
5500 if (netif_carrier_ok(netdev))
5501 return;
5502
5503 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5504
5505 switch (hw->mac.type) {
5506 case ixgbe_mac_82598EB: {
5507 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5508 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5509 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5510 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5511 }
5512 break;
5513 case ixgbe_mac_X540:
5514 case ixgbe_mac_82599EB: {
5515 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5516 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5517 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5518 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5519 }
5520 break;
5521 default:
5522 flow_tx = false;
5523 flow_rx = false;
5524 break;
5525 }
5526
5527 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5528 ixgbe_ptp_start_cyclecounter(adapter);
5529
5530 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5531 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5532 "10 Gbps" :
5533 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5534 "1 Gbps" :
5535 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5536 "100 Mbps" :
5537 "unknown speed"))),
5538 ((flow_rx && flow_tx) ? "RX/TX" :
5539 (flow_rx ? "RX" :
5540 (flow_tx ? "TX" : "None"))));
5541
5542 netif_carrier_on(netdev);
5543 ixgbe_check_vf_rate_limit(adapter);
5544
5545 /* update the default user priority for VFs */
5546 ixgbe_update_default_up(adapter);
5547
5548 /* ping all the active vfs to let them know link has changed */
5549 ixgbe_ping_all_vfs(adapter);
5550 }
5551
5552 /**
5553 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5554 * print link down message
5555 * @adapter: pointer to the adapter structure
5556 **/
5557 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5558 {
5559 struct net_device *netdev = adapter->netdev;
5560 struct ixgbe_hw *hw = &adapter->hw;
5561
5562 adapter->link_up = false;
5563 adapter->link_speed = 0;
5564
5565 /* only continue if link was up previously */
5566 if (!netif_carrier_ok(netdev))
5567 return;
5568
5569 /* poll for SFP+ cable when link is down */
5570 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5571 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5572
5573 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5574 ixgbe_ptp_start_cyclecounter(adapter);
5575
5576 e_info(drv, "NIC Link is Down\n");
5577 netif_carrier_off(netdev);
5578
5579 /* ping all the active vfs to let them know link has changed */
5580 ixgbe_ping_all_vfs(adapter);
5581 }
5582
5583 /**
5584 * ixgbe_watchdog_flush_tx - flush queues on link down
5585 * @adapter: pointer to the device adapter structure
5586 **/
5587 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5588 {
5589 int i;
5590 int some_tx_pending = 0;
5591
5592 if (!netif_carrier_ok(adapter->netdev)) {
5593 for (i = 0; i < adapter->num_tx_queues; i++) {
5594 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5595 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5596 some_tx_pending = 1;
5597 break;
5598 }
5599 }
5600
5601 if (some_tx_pending) {
5602 /* We've lost link, so the controller stops DMA,
5603 * but we've got queued Tx work that's never going
5604 * to get done, so reset controller to flush Tx.
5605 * (Do the reset outside of interrupt context).
5606 */
5607 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5608 }
5609 }
5610 }
5611
5612 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5613 {
5614 u32 ssvpc;
5615
5616 /* Do not perform spoof check for 82598 or if not in IOV mode */
5617 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5618 adapter->num_vfs == 0)
5619 return;
5620
5621 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5622
5623 /*
5624 * ssvpc register is cleared on read, if zero then no
5625 * spoofed packets in the last interval.
5626 */
5627 if (!ssvpc)
5628 return;
5629
5630 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5631 }
5632
5633 /**
5634 * ixgbe_watchdog_subtask - check and bring link up
5635 * @adapter: pointer to the device adapter structure
5636 **/
5637 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5638 {
5639 /* if interface is down do nothing */
5640 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5641 test_bit(__IXGBE_RESETTING, &adapter->state))
5642 return;
5643
5644 ixgbe_watchdog_update_link(adapter);
5645
5646 if (adapter->link_up)
5647 ixgbe_watchdog_link_is_up(adapter);
5648 else
5649 ixgbe_watchdog_link_is_down(adapter);
5650
5651 ixgbe_spoof_check(adapter);
5652 ixgbe_update_stats(adapter);
5653
5654 ixgbe_watchdog_flush_tx(adapter);
5655 }
5656
5657 /**
5658 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5659 * @adapter: the ixgbe adapter structure
5660 **/
5661 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5662 {
5663 struct ixgbe_hw *hw = &adapter->hw;
5664 s32 err;
5665
5666 /* not searching for SFP so there is nothing to do here */
5667 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5668 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5669 return;
5670
5671 /* someone else is in init, wait until next service event */
5672 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5673 return;
5674
5675 err = hw->phy.ops.identify_sfp(hw);
5676 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5677 goto sfp_out;
5678
5679 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5680 /* If no cable is present, then we need to reset
5681 * the next time we find a good cable. */
5682 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5683 }
5684
5685 /* exit on error */
5686 if (err)
5687 goto sfp_out;
5688
5689 /* exit if reset not needed */
5690 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5691 goto sfp_out;
5692
5693 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5694
5695 /*
5696 * A module may be identified correctly, but the EEPROM may not have
5697 * support for that module. setup_sfp() will fail in that case, so
5698 * we should not allow that module to load.
5699 */
5700 if (hw->mac.type == ixgbe_mac_82598EB)
5701 err = hw->phy.ops.reset(hw);
5702 else
5703 err = hw->mac.ops.setup_sfp(hw);
5704
5705 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5706 goto sfp_out;
5707
5708 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5709 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5710
5711 sfp_out:
5712 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5713
5714 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5715 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5716 e_dev_err("failed to initialize because an unsupported "
5717 "SFP+ module type was detected.\n");
5718 e_dev_err("Reload the driver after installing a "
5719 "supported module.\n");
5720 unregister_netdev(adapter->netdev);
5721 }
5722 }
5723
5724 /**
5725 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5726 * @adapter: the ixgbe adapter structure
5727 **/
5728 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5729 {
5730 struct ixgbe_hw *hw = &adapter->hw;
5731 u32 autoneg;
5732 bool negotiation;
5733
5734 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5735 return;
5736
5737 /* someone else is in init, wait until next service event */
5738 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5739 return;
5740
5741 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5742
5743 autoneg = hw->phy.autoneg_advertised;
5744 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5745 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5746 if (hw->mac.ops.setup_link)
5747 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5748
5749 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5750 adapter->link_check_timeout = jiffies;
5751 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5752 }
5753
5754 #ifdef CONFIG_PCI_IOV
5755 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5756 {
5757 int vf;
5758 struct ixgbe_hw *hw = &adapter->hw;
5759 struct net_device *netdev = adapter->netdev;
5760 u32 gpc;
5761 u32 ciaa, ciad;
5762
5763 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5764 if (gpc) /* If incrementing then no need for the check below */
5765 return;
5766 /*
5767 * Check to see if a bad DMA write target from an errant or
5768 * malicious VF has caused a PCIe error. If so then we can
5769 * issue a VFLR to the offending VF(s) and then resume without
5770 * requesting a full slot reset.
5771 */
5772
5773 for (vf = 0; vf < adapter->num_vfs; vf++) {
5774 ciaa = (vf << 16) | 0x80000000;
5775 /* 32 bit read so align, we really want status at offset 6 */
5776 ciaa |= PCI_COMMAND;
5777 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5778 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5779 ciaa &= 0x7FFFFFFF;
5780 /* disable debug mode asap after reading data */
5781 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5782 /* Get the upper 16 bits which will be the PCI status reg */
5783 ciad >>= 16;
5784 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5785 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5786 /* Issue VFLR */
5787 ciaa = (vf << 16) | 0x80000000;
5788 ciaa |= 0xA8;
5789 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5790 ciad = 0x00008000; /* VFLR */
5791 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5792 ciaa &= 0x7FFFFFFF;
5793 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5794 }
5795 }
5796 }
5797
5798 #endif
5799 /**
5800 * ixgbe_service_timer - Timer Call-back
5801 * @data: pointer to adapter cast into an unsigned long
5802 **/
5803 static void ixgbe_service_timer(unsigned long data)
5804 {
5805 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5806 unsigned long next_event_offset;
5807 bool ready = true;
5808
5809 /* poll faster when waiting for link */
5810 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5811 next_event_offset = HZ / 10;
5812 else
5813 next_event_offset = HZ * 2;
5814
5815 #ifdef CONFIG_PCI_IOV
5816 /*
5817 * don't bother with SR-IOV VF DMA hang check if there are
5818 * no VFs or the link is down
5819 */
5820 if (!adapter->num_vfs ||
5821 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5822 goto normal_timer_service;
5823
5824 /* If we have VFs allocated then we must check for DMA hangs */
5825 ixgbe_check_for_bad_vf(adapter);
5826 next_event_offset = HZ / 50;
5827 adapter->timer_event_accumulator++;
5828
5829 if (adapter->timer_event_accumulator >= 100)
5830 adapter->timer_event_accumulator = 0;
5831 else
5832 ready = false;
5833
5834 normal_timer_service:
5835 #endif
5836 /* Reset the timer */
5837 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5838
5839 if (ready)
5840 ixgbe_service_event_schedule(adapter);
5841 }
5842
5843 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5844 {
5845 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5846 return;
5847
5848 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5849
5850 /* If we're already down or resetting, just bail */
5851 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5852 test_bit(__IXGBE_RESETTING, &adapter->state))
5853 return;
5854
5855 ixgbe_dump(adapter);
5856 netdev_err(adapter->netdev, "Reset adapter\n");
5857 adapter->tx_timeout_count++;
5858
5859 ixgbe_reinit_locked(adapter);
5860 }
5861
5862 /**
5863 * ixgbe_service_task - manages and runs subtasks
5864 * @work: pointer to work_struct containing our data
5865 **/
5866 static void ixgbe_service_task(struct work_struct *work)
5867 {
5868 struct ixgbe_adapter *adapter = container_of(work,
5869 struct ixgbe_adapter,
5870 service_task);
5871
5872 ixgbe_reset_subtask(adapter);
5873 ixgbe_sfp_detection_subtask(adapter);
5874 ixgbe_sfp_link_config_subtask(adapter);
5875 ixgbe_check_overtemp_subtask(adapter);
5876 ixgbe_watchdog_subtask(adapter);
5877 ixgbe_fdir_reinit_subtask(adapter);
5878 ixgbe_check_hang_subtask(adapter);
5879 ixgbe_ptp_overflow_check(adapter);
5880
5881 ixgbe_service_event_complete(adapter);
5882 }
5883
5884 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5885 struct ixgbe_tx_buffer *first,
5886 u8 *hdr_len)
5887 {
5888 struct sk_buff *skb = first->skb;
5889 u32 vlan_macip_lens, type_tucmd;
5890 u32 mss_l4len_idx, l4len;
5891
5892 if (!skb_is_gso(skb))
5893 return 0;
5894
5895 if (skb_header_cloned(skb)) {
5896 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5897 if (err)
5898 return err;
5899 }
5900
5901 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5902 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5903
5904 if (first->protocol == __constant_htons(ETH_P_IP)) {
5905 struct iphdr *iph = ip_hdr(skb);
5906 iph->tot_len = 0;
5907 iph->check = 0;
5908 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5909 iph->daddr, 0,
5910 IPPROTO_TCP,
5911 0);
5912 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5913 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5914 IXGBE_TX_FLAGS_CSUM |
5915 IXGBE_TX_FLAGS_IPV4;
5916 } else if (skb_is_gso_v6(skb)) {
5917 ipv6_hdr(skb)->payload_len = 0;
5918 tcp_hdr(skb)->check =
5919 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5920 &ipv6_hdr(skb)->daddr,
5921 0, IPPROTO_TCP, 0);
5922 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5923 IXGBE_TX_FLAGS_CSUM;
5924 }
5925
5926 /* compute header lengths */
5927 l4len = tcp_hdrlen(skb);
5928 *hdr_len = skb_transport_offset(skb) + l4len;
5929
5930 /* update gso size and bytecount with header size */
5931 first->gso_segs = skb_shinfo(skb)->gso_segs;
5932 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5933
5934 /* mss_l4len_id: use 1 as index for TSO */
5935 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5936 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5937 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5938
5939 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5940 vlan_macip_lens = skb_network_header_len(skb);
5941 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5942 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5943
5944 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5945 mss_l4len_idx);
5946
5947 return 1;
5948 }
5949
5950 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5951 struct ixgbe_tx_buffer *first)
5952 {
5953 struct sk_buff *skb = first->skb;
5954 u32 vlan_macip_lens = 0;
5955 u32 mss_l4len_idx = 0;
5956 u32 type_tucmd = 0;
5957
5958 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5959 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5960 if (unlikely(skb->no_fcs))
5961 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5962 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5963 return;
5964 }
5965 } else {
5966 u8 l4_hdr = 0;
5967 switch (first->protocol) {
5968 case __constant_htons(ETH_P_IP):
5969 vlan_macip_lens |= skb_network_header_len(skb);
5970 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5971 l4_hdr = ip_hdr(skb)->protocol;
5972 break;
5973 case __constant_htons(ETH_P_IPV6):
5974 vlan_macip_lens |= skb_network_header_len(skb);
5975 l4_hdr = ipv6_hdr(skb)->nexthdr;
5976 break;
5977 default:
5978 if (unlikely(net_ratelimit())) {
5979 dev_warn(tx_ring->dev,
5980 "partial checksum but proto=%x!\n",
5981 first->protocol);
5982 }
5983 break;
5984 }
5985
5986 switch (l4_hdr) {
5987 case IPPROTO_TCP:
5988 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5989 mss_l4len_idx = tcp_hdrlen(skb) <<
5990 IXGBE_ADVTXD_L4LEN_SHIFT;
5991 break;
5992 case IPPROTO_SCTP:
5993 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5994 mss_l4len_idx = sizeof(struct sctphdr) <<
5995 IXGBE_ADVTXD_L4LEN_SHIFT;
5996 break;
5997 case IPPROTO_UDP:
5998 mss_l4len_idx = sizeof(struct udphdr) <<
5999 IXGBE_ADVTXD_L4LEN_SHIFT;
6000 break;
6001 default:
6002 if (unlikely(net_ratelimit())) {
6003 dev_warn(tx_ring->dev,
6004 "partial checksum but l4 proto=%x!\n",
6005 l4_hdr);
6006 }
6007 break;
6008 }
6009
6010 /* update TX checksum flag */
6011 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6012 }
6013
6014 /* vlan_macip_lens: MACLEN, VLAN tag */
6015 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6016 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6017
6018 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6019 type_tucmd, mss_l4len_idx);
6020 }
6021
6022 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6023 {
6024 /* set type for advanced descriptor with frame checksum insertion */
6025 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6026 IXGBE_ADVTXD_DCMD_DEXT);
6027
6028 /* set HW vlan bit if vlan is present */
6029 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6030 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6031
6032 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6033 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
6034
6035 /* set segmentation enable bits for TSO/FSO */
6036 #ifdef IXGBE_FCOE
6037 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
6038 #else
6039 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6040 #endif
6041 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6042
6043 /* insert frame checksum */
6044 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6045 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6046
6047 return cmd_type;
6048 }
6049
6050 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6051 u32 tx_flags, unsigned int paylen)
6052 {
6053 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6054
6055 /* enable L4 checksum for TSO and TX checksum offload */
6056 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6057 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6058
6059 /* enble IPv4 checksum for TSO */
6060 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6061 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6062
6063 /* use index 1 context for TSO/FSO/FCOE */
6064 #ifdef IXGBE_FCOE
6065 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6066 #else
6067 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6068 #endif
6069 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6070
6071 /*
6072 * Check Context must be set if Tx switch is enabled, which it
6073 * always is for case where virtual functions are running
6074 */
6075 #ifdef IXGBE_FCOE
6076 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6077 #else
6078 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6079 #endif
6080 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6081
6082 tx_desc->read.olinfo_status = olinfo_status;
6083 }
6084
6085 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6086 IXGBE_TXD_CMD_RS)
6087
6088 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6089 struct ixgbe_tx_buffer *first,
6090 const u8 hdr_len)
6091 {
6092 dma_addr_t dma;
6093 struct sk_buff *skb = first->skb;
6094 struct ixgbe_tx_buffer *tx_buffer;
6095 union ixgbe_adv_tx_desc *tx_desc;
6096 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6097 unsigned int data_len = skb->data_len;
6098 unsigned int size = skb_headlen(skb);
6099 unsigned int paylen = skb->len - hdr_len;
6100 u32 tx_flags = first->tx_flags;
6101 __le32 cmd_type;
6102 u16 i = tx_ring->next_to_use;
6103
6104 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6105
6106 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6107 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6108
6109 #ifdef IXGBE_FCOE
6110 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6111 if (data_len < sizeof(struct fcoe_crc_eof)) {
6112 size -= sizeof(struct fcoe_crc_eof) - data_len;
6113 data_len = 0;
6114 } else {
6115 data_len -= sizeof(struct fcoe_crc_eof);
6116 }
6117 }
6118
6119 #endif
6120 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6121 if (dma_mapping_error(tx_ring->dev, dma))
6122 goto dma_error;
6123
6124 /* record length, and DMA address */
6125 dma_unmap_len_set(first, len, size);
6126 dma_unmap_addr_set(first, dma, dma);
6127
6128 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6129
6130 for (;;) {
6131 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6132 tx_desc->read.cmd_type_len =
6133 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6134
6135 i++;
6136 tx_desc++;
6137 if (i == tx_ring->count) {
6138 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6139 i = 0;
6140 }
6141
6142 dma += IXGBE_MAX_DATA_PER_TXD;
6143 size -= IXGBE_MAX_DATA_PER_TXD;
6144
6145 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6146 tx_desc->read.olinfo_status = 0;
6147 }
6148
6149 if (likely(!data_len))
6150 break;
6151
6152 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6153
6154 i++;
6155 tx_desc++;
6156 if (i == tx_ring->count) {
6157 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6158 i = 0;
6159 }
6160
6161 #ifdef IXGBE_FCOE
6162 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6163 #else
6164 size = skb_frag_size(frag);
6165 #endif
6166 data_len -= size;
6167
6168 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6169 DMA_TO_DEVICE);
6170 if (dma_mapping_error(tx_ring->dev, dma))
6171 goto dma_error;
6172
6173 tx_buffer = &tx_ring->tx_buffer_info[i];
6174 dma_unmap_len_set(tx_buffer, len, size);
6175 dma_unmap_addr_set(tx_buffer, dma, dma);
6176
6177 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6178 tx_desc->read.olinfo_status = 0;
6179
6180 frag++;
6181 }
6182
6183 /* write last descriptor with RS and EOP bits */
6184 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6185 tx_desc->read.cmd_type_len = cmd_type;
6186
6187 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6188
6189 /* set the timestamp */
6190 first->time_stamp = jiffies;
6191
6192 /*
6193 * Force memory writes to complete before letting h/w know there
6194 * are new descriptors to fetch. (Only applicable for weak-ordered
6195 * memory model archs, such as IA-64).
6196 *
6197 * We also need this memory barrier to make certain all of the
6198 * status bits have been updated before next_to_watch is written.
6199 */
6200 wmb();
6201
6202 /* set next_to_watch value indicating a packet is present */
6203 first->next_to_watch = tx_desc;
6204
6205 i++;
6206 if (i == tx_ring->count)
6207 i = 0;
6208
6209 tx_ring->next_to_use = i;
6210
6211 /* notify HW of packet */
6212 writel(i, tx_ring->tail);
6213
6214 return;
6215 dma_error:
6216 dev_err(tx_ring->dev, "TX DMA map failed\n");
6217
6218 /* clear dma mappings for failed tx_buffer_info map */
6219 for (;;) {
6220 tx_buffer = &tx_ring->tx_buffer_info[i];
6221 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6222 if (tx_buffer == first)
6223 break;
6224 if (i == 0)
6225 i = tx_ring->count;
6226 i--;
6227 }
6228
6229 tx_ring->next_to_use = i;
6230 }
6231
6232 static void ixgbe_atr(struct ixgbe_ring *ring,
6233 struct ixgbe_tx_buffer *first)
6234 {
6235 struct ixgbe_q_vector *q_vector = ring->q_vector;
6236 union ixgbe_atr_hash_dword input = { .dword = 0 };
6237 union ixgbe_atr_hash_dword common = { .dword = 0 };
6238 union {
6239 unsigned char *network;
6240 struct iphdr *ipv4;
6241 struct ipv6hdr *ipv6;
6242 } hdr;
6243 struct tcphdr *th;
6244 __be16 vlan_id;
6245
6246 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6247 if (!q_vector)
6248 return;
6249
6250 /* do nothing if sampling is disabled */
6251 if (!ring->atr_sample_rate)
6252 return;
6253
6254 ring->atr_count++;
6255
6256 /* snag network header to get L4 type and address */
6257 hdr.network = skb_network_header(first->skb);
6258
6259 /* Currently only IPv4/IPv6 with TCP is supported */
6260 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6261 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6262 (first->protocol != __constant_htons(ETH_P_IP) ||
6263 hdr.ipv4->protocol != IPPROTO_TCP))
6264 return;
6265
6266 th = tcp_hdr(first->skb);
6267
6268 /* skip this packet since it is invalid or the socket is closing */
6269 if (!th || th->fin)
6270 return;
6271
6272 /* sample on all syn packets or once every atr sample count */
6273 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6274 return;
6275
6276 /* reset sample count */
6277 ring->atr_count = 0;
6278
6279 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6280
6281 /*
6282 * src and dst are inverted, think how the receiver sees them
6283 *
6284 * The input is broken into two sections, a non-compressed section
6285 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6286 * is XORed together and stored in the compressed dword.
6287 */
6288 input.formatted.vlan_id = vlan_id;
6289
6290 /*
6291 * since src port and flex bytes occupy the same word XOR them together
6292 * and write the value to source port portion of compressed dword
6293 */
6294 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6295 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6296 else
6297 common.port.src ^= th->dest ^ first->protocol;
6298 common.port.dst ^= th->source;
6299
6300 if (first->protocol == __constant_htons(ETH_P_IP)) {
6301 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6302 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6303 } else {
6304 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6305 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6306 hdr.ipv6->saddr.s6_addr32[1] ^
6307 hdr.ipv6->saddr.s6_addr32[2] ^
6308 hdr.ipv6->saddr.s6_addr32[3] ^
6309 hdr.ipv6->daddr.s6_addr32[0] ^
6310 hdr.ipv6->daddr.s6_addr32[1] ^
6311 hdr.ipv6->daddr.s6_addr32[2] ^
6312 hdr.ipv6->daddr.s6_addr32[3];
6313 }
6314
6315 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6316 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6317 input, common, ring->queue_index);
6318 }
6319
6320 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6321 {
6322 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6323 /* Herbert's original patch had:
6324 * smp_mb__after_netif_stop_queue();
6325 * but since that doesn't exist yet, just open code it. */
6326 smp_mb();
6327
6328 /* We need to check again in a case another CPU has just
6329 * made room available. */
6330 if (likely(ixgbe_desc_unused(tx_ring) < size))
6331 return -EBUSY;
6332
6333 /* A reprieve! - use start_queue because it doesn't call schedule */
6334 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6335 ++tx_ring->tx_stats.restart_queue;
6336 return 0;
6337 }
6338
6339 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6340 {
6341 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6342 return 0;
6343 return __ixgbe_maybe_stop_tx(tx_ring, size);
6344 }
6345
6346 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6347 {
6348 struct ixgbe_adapter *adapter = netdev_priv(dev);
6349 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6350 smp_processor_id();
6351 #ifdef IXGBE_FCOE
6352 __be16 protocol = vlan_get_protocol(skb);
6353
6354 if (((protocol == htons(ETH_P_FCOE)) ||
6355 (protocol == htons(ETH_P_FIP))) &&
6356 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6357 struct ixgbe_ring_feature *f;
6358
6359 f = &adapter->ring_feature[RING_F_FCOE];
6360
6361 while (txq >= f->indices)
6362 txq -= f->indices;
6363 txq += adapter->ring_feature[RING_F_FCOE].offset;
6364
6365 return txq;
6366 }
6367 #endif
6368
6369 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6370 while (unlikely(txq >= dev->real_num_tx_queues))
6371 txq -= dev->real_num_tx_queues;
6372 return txq;
6373 }
6374
6375 return skb_tx_hash(dev, skb);
6376 }
6377
6378 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6379 struct ixgbe_adapter *adapter,
6380 struct ixgbe_ring *tx_ring)
6381 {
6382 struct ixgbe_tx_buffer *first;
6383 int tso;
6384 u32 tx_flags = 0;
6385 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6386 unsigned short f;
6387 #endif
6388 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6389 __be16 protocol = skb->protocol;
6390 u8 hdr_len = 0;
6391
6392 /*
6393 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6394 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6395 * + 2 desc gap to keep tail from touching head,
6396 * + 1 desc for context descriptor,
6397 * otherwise try next time
6398 */
6399 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6400 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6401 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6402 #else
6403 count += skb_shinfo(skb)->nr_frags;
6404 #endif
6405 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6406 tx_ring->tx_stats.tx_busy++;
6407 return NETDEV_TX_BUSY;
6408 }
6409
6410 /* record the location of the first descriptor for this packet */
6411 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6412 first->skb = skb;
6413 first->bytecount = skb->len;
6414 first->gso_segs = 1;
6415
6416 /* if we have a HW VLAN tag being added default to the HW one */
6417 if (vlan_tx_tag_present(skb)) {
6418 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6419 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6420 /* else if it is a SW VLAN check the next protocol and store the tag */
6421 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6422 struct vlan_hdr *vhdr, _vhdr;
6423 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6424 if (!vhdr)
6425 goto out_drop;
6426
6427 protocol = vhdr->h_vlan_encapsulated_proto;
6428 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6429 IXGBE_TX_FLAGS_VLAN_SHIFT;
6430 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6431 }
6432
6433 skb_tx_timestamp(skb);
6434
6435 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6436 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6437 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6438 }
6439
6440 #ifdef CONFIG_PCI_IOV
6441 /*
6442 * Use the l2switch_enable flag - would be false if the DMA
6443 * Tx switch had been disabled.
6444 */
6445 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6446 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6447
6448 #endif
6449 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6450 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6451 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6452 (skb->priority != TC_PRIO_CONTROL))) {
6453 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6454 tx_flags |= (skb->priority & 0x7) <<
6455 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6456 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6457 struct vlan_ethhdr *vhdr;
6458 if (skb_header_cloned(skb) &&
6459 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6460 goto out_drop;
6461 vhdr = (struct vlan_ethhdr *)skb->data;
6462 vhdr->h_vlan_TCI = htons(tx_flags >>
6463 IXGBE_TX_FLAGS_VLAN_SHIFT);
6464 } else {
6465 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6466 }
6467 }
6468
6469 /* record initial flags and protocol */
6470 first->tx_flags = tx_flags;
6471 first->protocol = protocol;
6472
6473 #ifdef IXGBE_FCOE
6474 /* setup tx offload for FCoE */
6475 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6476 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6477 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6478 if (tso < 0)
6479 goto out_drop;
6480
6481 goto xmit_fcoe;
6482 }
6483
6484 #endif /* IXGBE_FCOE */
6485 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6486 if (tso < 0)
6487 goto out_drop;
6488 else if (!tso)
6489 ixgbe_tx_csum(tx_ring, first);
6490
6491 /* add the ATR filter if ATR is on */
6492 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6493 ixgbe_atr(tx_ring, first);
6494
6495 #ifdef IXGBE_FCOE
6496 xmit_fcoe:
6497 #endif /* IXGBE_FCOE */
6498 ixgbe_tx_map(tx_ring, first, hdr_len);
6499
6500 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6501
6502 return NETDEV_TX_OK;
6503
6504 out_drop:
6505 dev_kfree_skb_any(first->skb);
6506 first->skb = NULL;
6507
6508 return NETDEV_TX_OK;
6509 }
6510
6511 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6512 struct net_device *netdev)
6513 {
6514 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6515 struct ixgbe_ring *tx_ring;
6516
6517 /*
6518 * The minimum packet size for olinfo paylen is 17 so pad the skb
6519 * in order to meet this minimum size requirement.
6520 */
6521 if (unlikely(skb->len < 17)) {
6522 if (skb_pad(skb, 17 - skb->len))
6523 return NETDEV_TX_OK;
6524 skb->len = 17;
6525 skb_set_tail_pointer(skb, 17);
6526 }
6527
6528 tx_ring = adapter->tx_ring[skb->queue_mapping];
6529 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6530 }
6531
6532 /**
6533 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6534 * @netdev: network interface device structure
6535 * @p: pointer to an address structure
6536 *
6537 * Returns 0 on success, negative on failure
6538 **/
6539 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6540 {
6541 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6542 struct ixgbe_hw *hw = &adapter->hw;
6543 struct sockaddr *addr = p;
6544
6545 if (!is_valid_ether_addr(addr->sa_data))
6546 return -EADDRNOTAVAIL;
6547
6548 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6549 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6550
6551 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6552
6553 return 0;
6554 }
6555
6556 static int
6557 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6558 {
6559 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6560 struct ixgbe_hw *hw = &adapter->hw;
6561 u16 value;
6562 int rc;
6563
6564 if (prtad != hw->phy.mdio.prtad)
6565 return -EINVAL;
6566 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6567 if (!rc)
6568 rc = value;
6569 return rc;
6570 }
6571
6572 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6573 u16 addr, u16 value)
6574 {
6575 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6576 struct ixgbe_hw *hw = &adapter->hw;
6577
6578 if (prtad != hw->phy.mdio.prtad)
6579 return -EINVAL;
6580 return hw->phy.ops.write_reg(hw, addr, devad, value);
6581 }
6582
6583 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6584 {
6585 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6586
6587 switch (cmd) {
6588 case SIOCSHWTSTAMP:
6589 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6590 default:
6591 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6592 }
6593 }
6594
6595 /**
6596 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6597 * netdev->dev_addrs
6598 * @netdev: network interface device structure
6599 *
6600 * Returns non-zero on failure
6601 **/
6602 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6603 {
6604 int err = 0;
6605 struct ixgbe_adapter *adapter = netdev_priv(dev);
6606 struct ixgbe_hw *hw = &adapter->hw;
6607
6608 if (is_valid_ether_addr(hw->mac.san_addr)) {
6609 rtnl_lock();
6610 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6611 rtnl_unlock();
6612
6613 /* update SAN MAC vmdq pool selection */
6614 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6615 }
6616 return err;
6617 }
6618
6619 /**
6620 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6621 * netdev->dev_addrs
6622 * @netdev: network interface device structure
6623 *
6624 * Returns non-zero on failure
6625 **/
6626 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6627 {
6628 int err = 0;
6629 struct ixgbe_adapter *adapter = netdev_priv(dev);
6630 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6631
6632 if (is_valid_ether_addr(mac->san_addr)) {
6633 rtnl_lock();
6634 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6635 rtnl_unlock();
6636 }
6637 return err;
6638 }
6639
6640 #ifdef CONFIG_NET_POLL_CONTROLLER
6641 /*
6642 * Polling 'interrupt' - used by things like netconsole to send skbs
6643 * without having to re-enable interrupts. It's not called while
6644 * the interrupt routine is executing.
6645 */
6646 static void ixgbe_netpoll(struct net_device *netdev)
6647 {
6648 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6649 int i;
6650
6651 /* if interface is down do nothing */
6652 if (test_bit(__IXGBE_DOWN, &adapter->state))
6653 return;
6654
6655 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6656 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6657 for (i = 0; i < adapter->num_q_vectors; i++)
6658 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6659 } else {
6660 ixgbe_intr(adapter->pdev->irq, netdev);
6661 }
6662 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6663 }
6664
6665 #endif
6666 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6667 struct rtnl_link_stats64 *stats)
6668 {
6669 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6670 int i;
6671
6672 rcu_read_lock();
6673 for (i = 0; i < adapter->num_rx_queues; i++) {
6674 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6675 u64 bytes, packets;
6676 unsigned int start;
6677
6678 if (ring) {
6679 do {
6680 start = u64_stats_fetch_begin_bh(&ring->syncp);
6681 packets = ring->stats.packets;
6682 bytes = ring->stats.bytes;
6683 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6684 stats->rx_packets += packets;
6685 stats->rx_bytes += bytes;
6686 }
6687 }
6688
6689 for (i = 0; i < adapter->num_tx_queues; i++) {
6690 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6691 u64 bytes, packets;
6692 unsigned int start;
6693
6694 if (ring) {
6695 do {
6696 start = u64_stats_fetch_begin_bh(&ring->syncp);
6697 packets = ring->stats.packets;
6698 bytes = ring->stats.bytes;
6699 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6700 stats->tx_packets += packets;
6701 stats->tx_bytes += bytes;
6702 }
6703 }
6704 rcu_read_unlock();
6705 /* following stats updated by ixgbe_watchdog_task() */
6706 stats->multicast = netdev->stats.multicast;
6707 stats->rx_errors = netdev->stats.rx_errors;
6708 stats->rx_length_errors = netdev->stats.rx_length_errors;
6709 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6710 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6711 return stats;
6712 }
6713
6714 #ifdef CONFIG_IXGBE_DCB
6715 /**
6716 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6717 * @adapter: pointer to ixgbe_adapter
6718 * @tc: number of traffic classes currently enabled
6719 *
6720 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6721 * 802.1Q priority maps to a packet buffer that exists.
6722 */
6723 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6724 {
6725 struct ixgbe_hw *hw = &adapter->hw;
6726 u32 reg, rsave;
6727 int i;
6728
6729 /* 82598 have a static priority to TC mapping that can not
6730 * be changed so no validation is needed.
6731 */
6732 if (hw->mac.type == ixgbe_mac_82598EB)
6733 return;
6734
6735 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6736 rsave = reg;
6737
6738 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6739 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6740
6741 /* If up2tc is out of bounds default to zero */
6742 if (up2tc > tc)
6743 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6744 }
6745
6746 if (reg != rsave)
6747 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6748
6749 return;
6750 }
6751
6752 /**
6753 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6754 * @adapter: Pointer to adapter struct
6755 *
6756 * Populate the netdev user priority to tc map
6757 */
6758 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6759 {
6760 struct net_device *dev = adapter->netdev;
6761 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6762 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6763 u8 prio;
6764
6765 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6766 u8 tc = 0;
6767
6768 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6769 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6770 else if (ets)
6771 tc = ets->prio_tc[prio];
6772
6773 netdev_set_prio_tc_map(dev, prio, tc);
6774 }
6775 }
6776
6777 /**
6778 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6779 *
6780 * @netdev: net device to configure
6781 * @tc: number of traffic classes to enable
6782 */
6783 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6784 {
6785 struct ixgbe_adapter *adapter = netdev_priv(dev);
6786 struct ixgbe_hw *hw = &adapter->hw;
6787
6788 /* Hardware supports up to 8 traffic classes */
6789 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6790 (hw->mac.type == ixgbe_mac_82598EB &&
6791 tc < MAX_TRAFFIC_CLASS))
6792 return -EINVAL;
6793
6794 /* Hardware has to reinitialize queues and interrupts to
6795 * match packet buffer alignment. Unfortunately, the
6796 * hardware is not flexible enough to do this dynamically.
6797 */
6798 if (netif_running(dev))
6799 ixgbe_close(dev);
6800 ixgbe_clear_interrupt_scheme(adapter);
6801
6802 if (tc) {
6803 netdev_set_num_tc(dev, tc);
6804 ixgbe_set_prio_tc_map(adapter);
6805
6806 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6807
6808 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6809 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6810 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6811 }
6812 } else {
6813 netdev_reset_tc(dev);
6814
6815 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6816 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6817
6818 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6819
6820 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6821 adapter->dcb_cfg.pfc_mode_enable = false;
6822 }
6823
6824 ixgbe_init_interrupt_scheme(adapter);
6825 ixgbe_validate_rtr(adapter, tc);
6826 if (netif_running(dev))
6827 ixgbe_open(dev);
6828
6829 return 0;
6830 }
6831
6832 #endif /* CONFIG_IXGBE_DCB */
6833 void ixgbe_do_reset(struct net_device *netdev)
6834 {
6835 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6836
6837 if (netif_running(netdev))
6838 ixgbe_reinit_locked(adapter);
6839 else
6840 ixgbe_reset(adapter);
6841 }
6842
6843 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6844 netdev_features_t features)
6845 {
6846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6847
6848 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6849 if (!(features & NETIF_F_RXCSUM))
6850 features &= ~NETIF_F_LRO;
6851
6852 /* Turn off LRO if not RSC capable */
6853 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6854 features &= ~NETIF_F_LRO;
6855
6856 return features;
6857 }
6858
6859 static int ixgbe_set_features(struct net_device *netdev,
6860 netdev_features_t features)
6861 {
6862 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6863 netdev_features_t changed = netdev->features ^ features;
6864 bool need_reset = false;
6865
6866 /* Make sure RSC matches LRO, reset if change */
6867 if (!(features & NETIF_F_LRO)) {
6868 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6869 need_reset = true;
6870 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6871 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6872 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6873 if (adapter->rx_itr_setting == 1 ||
6874 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6875 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6876 need_reset = true;
6877 } else if ((changed ^ features) & NETIF_F_LRO) {
6878 e_info(probe, "rx-usecs set too low, "
6879 "disabling RSC\n");
6880 }
6881 }
6882
6883 /*
6884 * Check if Flow Director n-tuple support was enabled or disabled. If
6885 * the state changed, we need to reset.
6886 */
6887 switch (features & NETIF_F_NTUPLE) {
6888 case NETIF_F_NTUPLE:
6889 /* turn off ATR, enable perfect filters and reset */
6890 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6891 need_reset = true;
6892
6893 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6894 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6895 break;
6896 default:
6897 /* turn off perfect filters, enable ATR and reset */
6898 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6899 need_reset = true;
6900
6901 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6902
6903 /* We cannot enable ATR if SR-IOV is enabled */
6904 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6905 break;
6906
6907 /* We cannot enable ATR if we have 2 or more traffic classes */
6908 if (netdev_get_num_tc(netdev) > 1)
6909 break;
6910
6911 /* We cannot enable ATR if RSS is disabled */
6912 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6913 break;
6914
6915 /* A sample rate of 0 indicates ATR disabled */
6916 if (!adapter->atr_sample_rate)
6917 break;
6918
6919 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6920 break;
6921 }
6922
6923 if (features & NETIF_F_HW_VLAN_RX)
6924 ixgbe_vlan_strip_enable(adapter);
6925 else
6926 ixgbe_vlan_strip_disable(adapter);
6927
6928 if (changed & NETIF_F_RXALL)
6929 need_reset = true;
6930
6931 netdev->features = features;
6932 if (need_reset)
6933 ixgbe_do_reset(netdev);
6934
6935 return 0;
6936 }
6937
6938 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6939 struct net_device *dev,
6940 const unsigned char *addr,
6941 u16 flags)
6942 {
6943 struct ixgbe_adapter *adapter = netdev_priv(dev);
6944 int err;
6945
6946 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6947 return -EOPNOTSUPP;
6948
6949 /* Hardware does not support aging addresses so if a
6950 * ndm_state is given only allow permanent addresses
6951 */
6952 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6953 pr_info("%s: FDB only supports static addresses\n",
6954 ixgbe_driver_name);
6955 return -EINVAL;
6956 }
6957
6958 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
6959 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6960
6961 if (netdev_uc_count(dev) < rar_uc_entries)
6962 err = dev_uc_add_excl(dev, addr);
6963 else
6964 err = -ENOMEM;
6965 } else if (is_multicast_ether_addr(addr)) {
6966 err = dev_mc_add_excl(dev, addr);
6967 } else {
6968 err = -EINVAL;
6969 }
6970
6971 /* Only return duplicate errors if NLM_F_EXCL is set */
6972 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6973 err = 0;
6974
6975 return err;
6976 }
6977
6978 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6979 struct net_device *dev,
6980 const unsigned char *addr)
6981 {
6982 struct ixgbe_adapter *adapter = netdev_priv(dev);
6983 int err = -EOPNOTSUPP;
6984
6985 if (ndm->ndm_state & NUD_PERMANENT) {
6986 pr_info("%s: FDB only supports static addresses\n",
6987 ixgbe_driver_name);
6988 return -EINVAL;
6989 }
6990
6991 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6992 if (is_unicast_ether_addr(addr))
6993 err = dev_uc_del(dev, addr);
6994 else if (is_multicast_ether_addr(addr))
6995 err = dev_mc_del(dev, addr);
6996 else
6997 err = -EINVAL;
6998 }
6999
7000 return err;
7001 }
7002
7003 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7004 struct netlink_callback *cb,
7005 struct net_device *dev,
7006 int idx)
7007 {
7008 struct ixgbe_adapter *adapter = netdev_priv(dev);
7009
7010 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7011 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7012
7013 return idx;
7014 }
7015
7016 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7017 struct nlmsghdr *nlh)
7018 {
7019 struct ixgbe_adapter *adapter = netdev_priv(dev);
7020 struct nlattr *attr, *br_spec;
7021 int rem;
7022
7023 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7024 return -EOPNOTSUPP;
7025
7026 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7027
7028 nla_for_each_nested(attr, br_spec, rem) {
7029 __u16 mode;
7030 u32 reg = 0;
7031
7032 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7033 continue;
7034
7035 mode = nla_get_u16(attr);
7036 if (mode == BRIDGE_MODE_VEPA)
7037 reg = 0;
7038 else if (mode == BRIDGE_MODE_VEB)
7039 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7040 else
7041 return -EINVAL;
7042
7043 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7044
7045 e_info(drv, "enabling bridge mode: %s\n",
7046 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7047 }
7048
7049 return 0;
7050 }
7051
7052 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7053 struct net_device *dev)
7054 {
7055 struct ixgbe_adapter *adapter = netdev_priv(dev);
7056 u16 mode;
7057
7058 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7059 return 0;
7060
7061 if (IXGBE_READ_REG(&adapter->hw, IXGBE_PFDTXGSWC) & 1)
7062 mode = BRIDGE_MODE_VEB;
7063 else
7064 mode = BRIDGE_MODE_VEPA;
7065
7066 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7067 }
7068
7069 static const struct net_device_ops ixgbe_netdev_ops = {
7070 .ndo_open = ixgbe_open,
7071 .ndo_stop = ixgbe_close,
7072 .ndo_start_xmit = ixgbe_xmit_frame,
7073 .ndo_select_queue = ixgbe_select_queue,
7074 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7075 .ndo_validate_addr = eth_validate_addr,
7076 .ndo_set_mac_address = ixgbe_set_mac,
7077 .ndo_change_mtu = ixgbe_change_mtu,
7078 .ndo_tx_timeout = ixgbe_tx_timeout,
7079 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7080 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7081 .ndo_do_ioctl = ixgbe_ioctl,
7082 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7083 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7084 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7085 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7086 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7087 .ndo_get_stats64 = ixgbe_get_stats64,
7088 #ifdef CONFIG_IXGBE_DCB
7089 .ndo_setup_tc = ixgbe_setup_tc,
7090 #endif
7091 #ifdef CONFIG_NET_POLL_CONTROLLER
7092 .ndo_poll_controller = ixgbe_netpoll,
7093 #endif
7094 #ifdef IXGBE_FCOE
7095 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7096 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7097 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7098 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7099 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7100 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7101 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7102 #endif /* IXGBE_FCOE */
7103 .ndo_set_features = ixgbe_set_features,
7104 .ndo_fix_features = ixgbe_fix_features,
7105 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7106 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7107 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
7108 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7109 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7110 };
7111
7112 /**
7113 * ixgbe_wol_supported - Check whether device supports WoL
7114 * @hw: hw specific details
7115 * @device_id: the device ID
7116 * @subdev_id: the subsystem device ID
7117 *
7118 * This function is used by probe and ethtool to determine
7119 * which devices have WoL support
7120 *
7121 **/
7122 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7123 u16 subdevice_id)
7124 {
7125 struct ixgbe_hw *hw = &adapter->hw;
7126 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7127 int is_wol_supported = 0;
7128
7129 switch (device_id) {
7130 case IXGBE_DEV_ID_82599_SFP:
7131 /* Only these subdevices could supports WOL */
7132 switch (subdevice_id) {
7133 case IXGBE_SUBDEV_ID_82599_560FLR:
7134 /* only support first port */
7135 if (hw->bus.func != 0)
7136 break;
7137 case IXGBE_SUBDEV_ID_82599_SFP:
7138 case IXGBE_SUBDEV_ID_82599_RNDC:
7139 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7140 is_wol_supported = 1;
7141 break;
7142 }
7143 break;
7144 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7145 /* All except this subdevice support WOL */
7146 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7147 is_wol_supported = 1;
7148 break;
7149 case IXGBE_DEV_ID_82599_KX4:
7150 is_wol_supported = 1;
7151 break;
7152 case IXGBE_DEV_ID_X540T:
7153 case IXGBE_DEV_ID_X540T1:
7154 /* check eeprom to see if enabled wol */
7155 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7156 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7157 (hw->bus.func == 0))) {
7158 is_wol_supported = 1;
7159 }
7160 break;
7161 }
7162
7163 return is_wol_supported;
7164 }
7165
7166 /**
7167 * ixgbe_probe - Device Initialization Routine
7168 * @pdev: PCI device information struct
7169 * @ent: entry in ixgbe_pci_tbl
7170 *
7171 * Returns 0 on success, negative on failure
7172 *
7173 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7174 * The OS initialization, configuring of the adapter private structure,
7175 * and a hardware reset occur.
7176 **/
7177 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7178 const struct pci_device_id *ent)
7179 {
7180 struct net_device *netdev;
7181 struct ixgbe_adapter *adapter = NULL;
7182 struct ixgbe_hw *hw;
7183 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7184 static int cards_found;
7185 int i, err, pci_using_dac;
7186 u8 part_str[IXGBE_PBANUM_LENGTH];
7187 unsigned int indices = num_possible_cpus();
7188 unsigned int dcb_max = 0;
7189 #ifdef IXGBE_FCOE
7190 u16 device_caps;
7191 #endif
7192 u32 eec;
7193
7194 /* Catch broken hardware that put the wrong VF device ID in
7195 * the PCIe SR-IOV capability.
7196 */
7197 if (pdev->is_virtfn) {
7198 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7199 pci_name(pdev), pdev->vendor, pdev->device);
7200 return -EINVAL;
7201 }
7202
7203 err = pci_enable_device_mem(pdev);
7204 if (err)
7205 return err;
7206
7207 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7208 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7209 pci_using_dac = 1;
7210 } else {
7211 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7212 if (err) {
7213 err = dma_set_coherent_mask(&pdev->dev,
7214 DMA_BIT_MASK(32));
7215 if (err) {
7216 dev_err(&pdev->dev,
7217 "No usable DMA configuration, aborting\n");
7218 goto err_dma;
7219 }
7220 }
7221 pci_using_dac = 0;
7222 }
7223
7224 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7225 IORESOURCE_MEM), ixgbe_driver_name);
7226 if (err) {
7227 dev_err(&pdev->dev,
7228 "pci_request_selected_regions failed 0x%x\n", err);
7229 goto err_pci_reg;
7230 }
7231
7232 pci_enable_pcie_error_reporting(pdev);
7233
7234 pci_set_master(pdev);
7235 pci_save_state(pdev);
7236
7237 #ifdef CONFIG_IXGBE_DCB
7238 if (ii->mac == ixgbe_mac_82598EB)
7239 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7240 IXGBE_MAX_RSS_INDICES);
7241 else
7242 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7243 IXGBE_MAX_FDIR_INDICES);
7244 #endif
7245
7246 if (ii->mac == ixgbe_mac_82598EB)
7247 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7248 else
7249 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7250
7251 #ifdef IXGBE_FCOE
7252 indices += min_t(unsigned int, num_possible_cpus(),
7253 IXGBE_MAX_FCOE_INDICES);
7254 #endif
7255 indices = max_t(unsigned int, dcb_max, indices);
7256 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7257 if (!netdev) {
7258 err = -ENOMEM;
7259 goto err_alloc_etherdev;
7260 }
7261
7262 SET_NETDEV_DEV(netdev, &pdev->dev);
7263
7264 adapter = netdev_priv(netdev);
7265 pci_set_drvdata(pdev, adapter);
7266
7267 adapter->netdev = netdev;
7268 adapter->pdev = pdev;
7269 hw = &adapter->hw;
7270 hw->back = adapter;
7271 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7272
7273 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7274 pci_resource_len(pdev, 0));
7275 if (!hw->hw_addr) {
7276 err = -EIO;
7277 goto err_ioremap;
7278 }
7279
7280 netdev->netdev_ops = &ixgbe_netdev_ops;
7281 ixgbe_set_ethtool_ops(netdev);
7282 netdev->watchdog_timeo = 5 * HZ;
7283 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7284
7285 adapter->bd_number = cards_found;
7286
7287 /* Setup hw api */
7288 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7289 hw->mac.type = ii->mac;
7290
7291 /* EEPROM */
7292 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7293 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7294 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7295 if (!(eec & (1 << 8)))
7296 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7297
7298 /* PHY */
7299 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7300 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7301 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7302 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7303 hw->phy.mdio.mmds = 0;
7304 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7305 hw->phy.mdio.dev = netdev;
7306 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7307 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7308
7309 ii->get_invariants(hw);
7310
7311 /* setup the private structure */
7312 err = ixgbe_sw_init(adapter);
7313 if (err)
7314 goto err_sw_init;
7315
7316 /* Make it possible the adapter to be woken up via WOL */
7317 switch (adapter->hw.mac.type) {
7318 case ixgbe_mac_82599EB:
7319 case ixgbe_mac_X540:
7320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7321 break;
7322 default:
7323 break;
7324 }
7325
7326 /*
7327 * If there is a fan on this device and it has failed log the
7328 * failure.
7329 */
7330 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7331 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7332 if (esdp & IXGBE_ESDP_SDP1)
7333 e_crit(probe, "Fan has stopped, replace the adapter\n");
7334 }
7335
7336 if (allow_unsupported_sfp)
7337 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7338
7339 /* reset_hw fills in the perm_addr as well */
7340 hw->phy.reset_if_overtemp = true;
7341 err = hw->mac.ops.reset_hw(hw);
7342 hw->phy.reset_if_overtemp = false;
7343 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7344 hw->mac.type == ixgbe_mac_82598EB) {
7345 err = 0;
7346 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7347 e_dev_err("failed to load because an unsupported SFP+ "
7348 "module type was detected.\n");
7349 e_dev_err("Reload the driver after installing a supported "
7350 "module.\n");
7351 goto err_sw_init;
7352 } else if (err) {
7353 e_dev_err("HW Init failed: %d\n", err);
7354 goto err_sw_init;
7355 }
7356
7357 #ifdef CONFIG_PCI_IOV
7358 ixgbe_enable_sriov(adapter, ii);
7359
7360 #endif
7361 netdev->features = NETIF_F_SG |
7362 NETIF_F_IP_CSUM |
7363 NETIF_F_IPV6_CSUM |
7364 NETIF_F_HW_VLAN_TX |
7365 NETIF_F_HW_VLAN_RX |
7366 NETIF_F_HW_VLAN_FILTER |
7367 NETIF_F_TSO |
7368 NETIF_F_TSO6 |
7369 NETIF_F_RXHASH |
7370 NETIF_F_RXCSUM;
7371
7372 netdev->hw_features = netdev->features;
7373
7374 switch (adapter->hw.mac.type) {
7375 case ixgbe_mac_82599EB:
7376 case ixgbe_mac_X540:
7377 netdev->features |= NETIF_F_SCTP_CSUM;
7378 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7379 NETIF_F_NTUPLE;
7380 break;
7381 default:
7382 break;
7383 }
7384
7385 netdev->hw_features |= NETIF_F_RXALL;
7386
7387 netdev->vlan_features |= NETIF_F_TSO;
7388 netdev->vlan_features |= NETIF_F_TSO6;
7389 netdev->vlan_features |= NETIF_F_IP_CSUM;
7390 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7391 netdev->vlan_features |= NETIF_F_SG;
7392
7393 netdev->priv_flags |= IFF_UNICAST_FLT;
7394 netdev->priv_flags |= IFF_SUPP_NOFCS;
7395
7396 #ifdef CONFIG_IXGBE_DCB
7397 netdev->dcbnl_ops = &dcbnl_ops;
7398 #endif
7399
7400 #ifdef IXGBE_FCOE
7401 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7402 if (hw->mac.ops.get_device_caps) {
7403 hw->mac.ops.get_device_caps(hw, &device_caps);
7404 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7405 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7406 }
7407
7408 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7409
7410 netdev->features |= NETIF_F_FSO |
7411 NETIF_F_FCOE_CRC;
7412
7413 netdev->vlan_features |= NETIF_F_FSO |
7414 NETIF_F_FCOE_CRC |
7415 NETIF_F_FCOE_MTU;
7416 }
7417 #endif /* IXGBE_FCOE */
7418 if (pci_using_dac) {
7419 netdev->features |= NETIF_F_HIGHDMA;
7420 netdev->vlan_features |= NETIF_F_HIGHDMA;
7421 }
7422
7423 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7424 netdev->hw_features |= NETIF_F_LRO;
7425 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7426 netdev->features |= NETIF_F_LRO;
7427
7428 /* make sure the EEPROM is good */
7429 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7430 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7431 err = -EIO;
7432 goto err_sw_init;
7433 }
7434
7435 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7436 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7437
7438 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7439 e_dev_err("invalid MAC address\n");
7440 err = -EIO;
7441 goto err_sw_init;
7442 }
7443
7444 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7445 (unsigned long) adapter);
7446
7447 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7448 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7449
7450 err = ixgbe_init_interrupt_scheme(adapter);
7451 if (err)
7452 goto err_sw_init;
7453
7454 /* WOL not supported for all devices */
7455 adapter->wol = 0;
7456 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7457 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7458 adapter->wol = IXGBE_WUFC_MAG;
7459
7460 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7461
7462 /* save off EEPROM version number */
7463 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7464 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7465
7466 /* pick up the PCI bus settings for reporting later */
7467 hw->mac.ops.get_bus_info(hw);
7468
7469 /* print bus type/speed/width info */
7470 e_dev_info("(PCI Express:%s:%s) %pM\n",
7471 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7472 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7473 "Unknown"),
7474 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7475 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7476 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7477 "Unknown"),
7478 netdev->dev_addr);
7479
7480 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7481 if (err)
7482 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7483 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7484 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7485 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7486 part_str);
7487 else
7488 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7489 hw->mac.type, hw->phy.type, part_str);
7490
7491 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7492 e_dev_warn("PCI-Express bandwidth available for this card is "
7493 "not sufficient for optimal performance.\n");
7494 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7495 "is required.\n");
7496 }
7497
7498 /* reset the hardware with the new settings */
7499 err = hw->mac.ops.start_hw(hw);
7500 if (err == IXGBE_ERR_EEPROM_VERSION) {
7501 /* We are running on a pre-production device, log a warning */
7502 e_dev_warn("This device is a pre-production adapter/LOM. "
7503 "Please be aware there may be issues associated "
7504 "with your hardware. If you are experiencing "
7505 "problems please contact your Intel or hardware "
7506 "representative who provided you with this "
7507 "hardware.\n");
7508 }
7509 strcpy(netdev->name, "eth%d");
7510 err = register_netdev(netdev);
7511 if (err)
7512 goto err_register;
7513
7514 /* power down the optics for 82599 SFP+ fiber */
7515 if (hw->mac.ops.disable_tx_laser)
7516 hw->mac.ops.disable_tx_laser(hw);
7517
7518 /* carrier off reporting is important to ethtool even BEFORE open */
7519 netif_carrier_off(netdev);
7520
7521 #ifdef CONFIG_IXGBE_DCA
7522 if (dca_add_requester(&pdev->dev) == 0) {
7523 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7524 ixgbe_setup_dca(adapter);
7525 }
7526 #endif
7527 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7528 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7529 for (i = 0; i < adapter->num_vfs; i++)
7530 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7531 }
7532
7533 /* firmware requires driver version to be 0xFFFFFFFF
7534 * since os does not support feature
7535 */
7536 if (hw->mac.ops.set_fw_drv_ver)
7537 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7538 0xFF);
7539
7540 /* add san mac addr to netdev */
7541 ixgbe_add_sanmac_netdev(netdev);
7542
7543 e_dev_info("%s\n", ixgbe_default_device_descr);
7544 cards_found++;
7545
7546 #ifdef CONFIG_IXGBE_HWMON
7547 if (ixgbe_sysfs_init(adapter))
7548 e_err(probe, "failed to allocate sysfs resources\n");
7549 #endif /* CONFIG_IXGBE_HWMON */
7550
7551 #ifdef CONFIG_DEBUG_FS
7552 ixgbe_dbg_adapter_init(adapter);
7553 #endif /* CONFIG_DEBUG_FS */
7554
7555 return 0;
7556
7557 err_register:
7558 ixgbe_release_hw_control(adapter);
7559 ixgbe_clear_interrupt_scheme(adapter);
7560 err_sw_init:
7561 ixgbe_disable_sriov(adapter);
7562 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7563 iounmap(hw->hw_addr);
7564 err_ioremap:
7565 free_netdev(netdev);
7566 err_alloc_etherdev:
7567 pci_release_selected_regions(pdev,
7568 pci_select_bars(pdev, IORESOURCE_MEM));
7569 err_pci_reg:
7570 err_dma:
7571 pci_disable_device(pdev);
7572 return err;
7573 }
7574
7575 /**
7576 * ixgbe_remove - Device Removal Routine
7577 * @pdev: PCI device information struct
7578 *
7579 * ixgbe_remove is called by the PCI subsystem to alert the driver
7580 * that it should release a PCI device. The could be caused by a
7581 * Hot-Plug event, or because the driver is going to be removed from
7582 * memory.
7583 **/
7584 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7585 {
7586 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7587 struct net_device *netdev = adapter->netdev;
7588
7589 #ifdef CONFIG_DEBUG_FS
7590 ixgbe_dbg_adapter_exit(adapter);
7591 #endif /*CONFIG_DEBUG_FS */
7592
7593 set_bit(__IXGBE_DOWN, &adapter->state);
7594 cancel_work_sync(&adapter->service_task);
7595
7596
7597 #ifdef CONFIG_IXGBE_DCA
7598 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7599 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7600 dca_remove_requester(&pdev->dev);
7601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7602 }
7603
7604 #endif
7605 #ifdef CONFIG_IXGBE_HWMON
7606 ixgbe_sysfs_exit(adapter);
7607 #endif /* CONFIG_IXGBE_HWMON */
7608
7609 /* remove the added san mac */
7610 ixgbe_del_sanmac_netdev(netdev);
7611
7612 if (netdev->reg_state == NETREG_REGISTERED)
7613 unregister_netdev(netdev);
7614
7615 ixgbe_disable_sriov(adapter);
7616
7617 ixgbe_clear_interrupt_scheme(adapter);
7618
7619 ixgbe_release_hw_control(adapter);
7620
7621 #ifdef CONFIG_DCB
7622 kfree(adapter->ixgbe_ieee_pfc);
7623 kfree(adapter->ixgbe_ieee_ets);
7624
7625 #endif
7626 iounmap(adapter->hw.hw_addr);
7627 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7628 IORESOURCE_MEM));
7629
7630 e_dev_info("complete\n");
7631
7632 free_netdev(netdev);
7633
7634 pci_disable_pcie_error_reporting(pdev);
7635
7636 pci_disable_device(pdev);
7637 }
7638
7639 /**
7640 * ixgbe_io_error_detected - called when PCI error is detected
7641 * @pdev: Pointer to PCI device
7642 * @state: The current pci connection state
7643 *
7644 * This function is called after a PCI bus error affecting
7645 * this device has been detected.
7646 */
7647 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7648 pci_channel_state_t state)
7649 {
7650 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7651 struct net_device *netdev = adapter->netdev;
7652
7653 #ifdef CONFIG_PCI_IOV
7654 struct pci_dev *bdev, *vfdev;
7655 u32 dw0, dw1, dw2, dw3;
7656 int vf, pos;
7657 u16 req_id, pf_func;
7658
7659 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7660 adapter->num_vfs == 0)
7661 goto skip_bad_vf_detection;
7662
7663 bdev = pdev->bus->self;
7664 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7665 bdev = bdev->bus->self;
7666
7667 if (!bdev)
7668 goto skip_bad_vf_detection;
7669
7670 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7671 if (!pos)
7672 goto skip_bad_vf_detection;
7673
7674 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7675 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7676 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7677 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7678
7679 req_id = dw1 >> 16;
7680 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7681 if (!(req_id & 0x0080))
7682 goto skip_bad_vf_detection;
7683
7684 pf_func = req_id & 0x01;
7685 if ((pf_func & 1) == (pdev->devfn & 1)) {
7686 unsigned int device_id;
7687
7688 vf = (req_id & 0x7F) >> 1;
7689 e_dev_err("VF %d has caused a PCIe error\n", vf);
7690 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7691 "%8.8x\tdw3: %8.8x\n",
7692 dw0, dw1, dw2, dw3);
7693 switch (adapter->hw.mac.type) {
7694 case ixgbe_mac_82599EB:
7695 device_id = IXGBE_82599_VF_DEVICE_ID;
7696 break;
7697 case ixgbe_mac_X540:
7698 device_id = IXGBE_X540_VF_DEVICE_ID;
7699 break;
7700 default:
7701 device_id = 0;
7702 break;
7703 }
7704
7705 /* Find the pci device of the offending VF */
7706 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7707 while (vfdev) {
7708 if (vfdev->devfn == (req_id & 0xFF))
7709 break;
7710 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7711 device_id, vfdev);
7712 }
7713 /*
7714 * There's a slim chance the VF could have been hot plugged,
7715 * so if it is no longer present we don't need to issue the
7716 * VFLR. Just clean up the AER in that case.
7717 */
7718 if (vfdev) {
7719 e_dev_err("Issuing VFLR to VF %d\n", vf);
7720 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7721 }
7722
7723 pci_cleanup_aer_uncorrect_error_status(pdev);
7724 }
7725
7726 /*
7727 * Even though the error may have occurred on the other port
7728 * we still need to increment the vf error reference count for
7729 * both ports because the I/O resume function will be called
7730 * for both of them.
7731 */
7732 adapter->vferr_refcount++;
7733
7734 return PCI_ERS_RESULT_RECOVERED;
7735
7736 skip_bad_vf_detection:
7737 #endif /* CONFIG_PCI_IOV */
7738 netif_device_detach(netdev);
7739
7740 if (state == pci_channel_io_perm_failure)
7741 return PCI_ERS_RESULT_DISCONNECT;
7742
7743 if (netif_running(netdev))
7744 ixgbe_down(adapter);
7745 pci_disable_device(pdev);
7746
7747 /* Request a slot reset. */
7748 return PCI_ERS_RESULT_NEED_RESET;
7749 }
7750
7751 /**
7752 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7753 * @pdev: Pointer to PCI device
7754 *
7755 * Restart the card from scratch, as if from a cold-boot.
7756 */
7757 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7758 {
7759 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7760 pci_ers_result_t result;
7761 int err;
7762
7763 if (pci_enable_device_mem(pdev)) {
7764 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7765 result = PCI_ERS_RESULT_DISCONNECT;
7766 } else {
7767 pci_set_master(pdev);
7768 pci_restore_state(pdev);
7769 pci_save_state(pdev);
7770
7771 pci_wake_from_d3(pdev, false);
7772
7773 ixgbe_reset(adapter);
7774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7775 result = PCI_ERS_RESULT_RECOVERED;
7776 }
7777
7778 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7779 if (err) {
7780 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7781 "failed 0x%0x\n", err);
7782 /* non-fatal, continue */
7783 }
7784
7785 return result;
7786 }
7787
7788 /**
7789 * ixgbe_io_resume - called when traffic can start flowing again.
7790 * @pdev: Pointer to PCI device
7791 *
7792 * This callback is called when the error recovery driver tells us that
7793 * its OK to resume normal operation.
7794 */
7795 static void ixgbe_io_resume(struct pci_dev *pdev)
7796 {
7797 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7798 struct net_device *netdev = adapter->netdev;
7799
7800 #ifdef CONFIG_PCI_IOV
7801 if (adapter->vferr_refcount) {
7802 e_info(drv, "Resuming after VF err\n");
7803 adapter->vferr_refcount--;
7804 return;
7805 }
7806
7807 #endif
7808 if (netif_running(netdev))
7809 ixgbe_up(adapter);
7810
7811 netif_device_attach(netdev);
7812 }
7813
7814 static const struct pci_error_handlers ixgbe_err_handler = {
7815 .error_detected = ixgbe_io_error_detected,
7816 .slot_reset = ixgbe_io_slot_reset,
7817 .resume = ixgbe_io_resume,
7818 };
7819
7820 static struct pci_driver ixgbe_driver = {
7821 .name = ixgbe_driver_name,
7822 .id_table = ixgbe_pci_tbl,
7823 .probe = ixgbe_probe,
7824 .remove = __devexit_p(ixgbe_remove),
7825 #ifdef CONFIG_PM
7826 .suspend = ixgbe_suspend,
7827 .resume = ixgbe_resume,
7828 #endif
7829 .shutdown = ixgbe_shutdown,
7830 .err_handler = &ixgbe_err_handler
7831 };
7832
7833 /**
7834 * ixgbe_init_module - Driver Registration Routine
7835 *
7836 * ixgbe_init_module is the first routine called when the driver is
7837 * loaded. All it does is register with the PCI subsystem.
7838 **/
7839 static int __init ixgbe_init_module(void)
7840 {
7841 int ret;
7842 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7843 pr_info("%s\n", ixgbe_copyright);
7844
7845 #ifdef CONFIG_DEBUG_FS
7846 ixgbe_dbg_init();
7847 #endif /* CONFIG_DEBUG_FS */
7848
7849 #ifdef CONFIG_IXGBE_DCA
7850 dca_register_notify(&dca_notifier);
7851 #endif
7852
7853 ret = pci_register_driver(&ixgbe_driver);
7854 return ret;
7855 }
7856
7857 module_init(ixgbe_init_module);
7858
7859 /**
7860 * ixgbe_exit_module - Driver Exit Cleanup Routine
7861 *
7862 * ixgbe_exit_module is called just before the driver is removed
7863 * from memory.
7864 **/
7865 static void __exit ixgbe_exit_module(void)
7866 {
7867 #ifdef CONFIG_IXGBE_DCA
7868 dca_unregister_notify(&dca_notifier);
7869 #endif
7870 pci_unregister_driver(&ixgbe_driver);
7871
7872 #ifdef CONFIG_DEBUG_FS
7873 ixgbe_dbg_exit();
7874 #endif /* CONFIG_DEBUG_FS */
7875
7876 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7877 }
7878
7879 #ifdef CONFIG_IXGBE_DCA
7880 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7881 void *p)
7882 {
7883 int ret_val;
7884
7885 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7886 __ixgbe_notify_dca);
7887
7888 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7889 }
7890
7891 #endif /* CONFIG_IXGBE_DCA */
7892
7893 module_exit(ixgbe_exit_module);
7894
7895 /* ixgbe_main.c */
CJK support for tty framebuffer vt