2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
18 #include <asm/machdep.h>
19 #include <asm/firmware.h>
20 #include <asm/ptrace.h>
22 struct cpu_hw_events
{
29 struct perf_event
*event
[MAX_HWEVENTS
];
30 u64 events
[MAX_HWEVENTS
];
31 unsigned int flags
[MAX_HWEVENTS
];
32 unsigned long mmcr
[3];
33 struct perf_event
*limited_counter
[MAX_LIMITED_HWCOUNTERS
];
34 u8 limited_hwidx
[MAX_LIMITED_HWCOUNTERS
];
35 u64 alternatives
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
36 unsigned long amasks
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
37 unsigned long avalues
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
39 unsigned int group_flag
;
42 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
44 struct power_pmu
*ppmu
;
47 * Normally, to ignore kernel events we set the FCS (freeze counters
48 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
49 * hypervisor bit set in the MSR, or if we are running on a processor
50 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
51 * then we need to use the FCHV bit to ignore kernel events.
53 static unsigned int freeze_events_kernel
= MMCR0_FCS
;
56 * 32-bit doesn't have MMCRA but does have an MMCR2,
57 * and a few other names are different.
62 #define MMCR0_PMCjCE MMCR0_PMCnCE
64 #define SPRN_MMCRA SPRN_MMCR2
65 #define MMCRA_SAMPLE_ENABLE 0
67 static inline unsigned long perf_ip_adjust(struct pt_regs
*regs
)
71 static inline void perf_get_data_addr(struct pt_regs
*regs
, u64
*addrp
) { }
72 static inline u32
perf_get_misc_flags(struct pt_regs
*regs
)
76 static inline void perf_read_regs(struct pt_regs
*regs
) { }
77 static inline int perf_intr_is_nmi(struct pt_regs
*regs
)
82 #endif /* CONFIG_PPC32 */
85 * Things that are specific to 64-bit implementations.
89 static inline unsigned long perf_ip_adjust(struct pt_regs
*regs
)
91 unsigned long mmcra
= regs
->dsisr
;
93 if ((mmcra
& MMCRA_SAMPLE_ENABLE
) && !(ppmu
->flags
& PPMU_ALT_SIPR
)) {
94 unsigned long slot
= (mmcra
& MMCRA_SLOT
) >> MMCRA_SLOT_SHIFT
;
96 return 4 * (slot
- 1);
102 * The user wants a data address recorded.
103 * If we're not doing instruction sampling, give them the SDAR
104 * (sampled data address). If we are doing instruction sampling, then
105 * only give them the SDAR if it corresponds to the instruction
106 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC
109 static inline void perf_get_data_addr(struct pt_regs
*regs
, u64
*addrp
)
111 unsigned long mmcra
= regs
->dsisr
;
112 unsigned long sdsync
= (ppmu
->flags
& PPMU_ALT_SIPR
) ?
113 POWER6_MMCRA_SDSYNC
: MMCRA_SDSYNC
;
115 if (!(mmcra
& MMCRA_SAMPLE_ENABLE
) || (mmcra
& sdsync
))
116 *addrp
= mfspr(SPRN_SDAR
);
119 static inline u32
perf_get_misc_flags(struct pt_regs
*regs
)
121 unsigned long mmcra
= regs
->dsisr
;
122 unsigned long sihv
= MMCRA_SIHV
;
123 unsigned long sipr
= MMCRA_SIPR
;
125 if (TRAP(regs
) != 0xf00)
126 return 0; /* not a PMU interrupt */
128 if (ppmu
->flags
& PPMU_ALT_SIPR
) {
129 sihv
= POWER6_MMCRA_SIHV
;
130 sipr
= POWER6_MMCRA_SIPR
;
133 /* PR has priority over HV, so order below is important */
135 return PERF_RECORD_MISC_USER
;
136 if ((mmcra
& sihv
) && (freeze_events_kernel
!= MMCR0_FCHV
))
137 return PERF_RECORD_MISC_HYPERVISOR
;
138 return PERF_RECORD_MISC_KERNEL
;
142 * Overload regs->dsisr to store MMCRA so we only need to read it once
145 static inline void perf_read_regs(struct pt_regs
*regs
)
147 regs
->dsisr
= mfspr(SPRN_MMCRA
);
151 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
154 static inline int perf_intr_is_nmi(struct pt_regs
*regs
)
159 #endif /* CONFIG_PPC64 */
161 static void perf_event_interrupt(struct pt_regs
*regs
);
163 void perf_event_print_debug(void)
168 * Read one performance monitor counter (PMC).
170 static unsigned long read_pmc(int idx
)
176 val
= mfspr(SPRN_PMC1
);
179 val
= mfspr(SPRN_PMC2
);
182 val
= mfspr(SPRN_PMC3
);
185 val
= mfspr(SPRN_PMC4
);
188 val
= mfspr(SPRN_PMC5
);
191 val
= mfspr(SPRN_PMC6
);
195 val
= mfspr(SPRN_PMC7
);
198 val
= mfspr(SPRN_PMC8
);
200 #endif /* CONFIG_PPC64 */
202 printk(KERN_ERR
"oops trying to read PMC%d\n", idx
);
211 static void write_pmc(int idx
, unsigned long val
)
215 mtspr(SPRN_PMC1
, val
);
218 mtspr(SPRN_PMC2
, val
);
221 mtspr(SPRN_PMC3
, val
);
224 mtspr(SPRN_PMC4
, val
);
227 mtspr(SPRN_PMC5
, val
);
230 mtspr(SPRN_PMC6
, val
);
234 mtspr(SPRN_PMC7
, val
);
237 mtspr(SPRN_PMC8
, val
);
239 #endif /* CONFIG_PPC64 */
241 printk(KERN_ERR
"oops trying to write PMC%d\n", idx
);
246 * Check if a set of events can all go on the PMU at once.
247 * If they can't, this will look at alternative codes for the events
248 * and see if any combination of alternative codes is feasible.
249 * The feasible set is returned in event_id[].
251 static int power_check_constraints(struct cpu_hw_events
*cpuhw
,
252 u64 event_id
[], unsigned int cflags
[],
255 unsigned long mask
, value
, nv
;
256 unsigned long smasks
[MAX_HWEVENTS
], svalues
[MAX_HWEVENTS
];
257 int n_alt
[MAX_HWEVENTS
], choice
[MAX_HWEVENTS
];
259 unsigned long addf
= ppmu
->add_fields
;
260 unsigned long tadd
= ppmu
->test_adder
;
262 if (n_ev
> ppmu
->n_counter
)
265 /* First see if the events will go on as-is */
266 for (i
= 0; i
< n_ev
; ++i
) {
267 if ((cflags
[i
] & PPMU_LIMITED_PMC_REQD
)
268 && !ppmu
->limited_pmc_event(event_id
[i
])) {
269 ppmu
->get_alternatives(event_id
[i
], cflags
[i
],
270 cpuhw
->alternatives
[i
]);
271 event_id
[i
] = cpuhw
->alternatives
[i
][0];
273 if (ppmu
->get_constraint(event_id
[i
], &cpuhw
->amasks
[i
][0],
274 &cpuhw
->avalues
[i
][0]))
278 for (i
= 0; i
< n_ev
; ++i
) {
279 nv
= (value
| cpuhw
->avalues
[i
][0]) +
280 (value
& cpuhw
->avalues
[i
][0] & addf
);
281 if ((((nv
+ tadd
) ^ value
) & mask
) != 0 ||
282 (((nv
+ tadd
) ^ cpuhw
->avalues
[i
][0]) &
283 cpuhw
->amasks
[i
][0]) != 0)
286 mask
|= cpuhw
->amasks
[i
][0];
289 return 0; /* all OK */
291 /* doesn't work, gather alternatives... */
292 if (!ppmu
->get_alternatives
)
294 for (i
= 0; i
< n_ev
; ++i
) {
296 n_alt
[i
] = ppmu
->get_alternatives(event_id
[i
], cflags
[i
],
297 cpuhw
->alternatives
[i
]);
298 for (j
= 1; j
< n_alt
[i
]; ++j
)
299 ppmu
->get_constraint(cpuhw
->alternatives
[i
][j
],
300 &cpuhw
->amasks
[i
][j
],
301 &cpuhw
->avalues
[i
][j
]);
304 /* enumerate all possibilities and see if any will work */
307 value
= mask
= nv
= 0;
310 /* we're backtracking, restore context */
316 * See if any alternative k for event_id i,
317 * where k > j, will satisfy the constraints.
319 while (++j
< n_alt
[i
]) {
320 nv
= (value
| cpuhw
->avalues
[i
][j
]) +
321 (value
& cpuhw
->avalues
[i
][j
] & addf
);
322 if ((((nv
+ tadd
) ^ value
) & mask
) == 0 &&
323 (((nv
+ tadd
) ^ cpuhw
->avalues
[i
][j
])
324 & cpuhw
->amasks
[i
][j
]) == 0)
329 * No feasible alternative, backtrack
330 * to event_id i-1 and continue enumerating its
331 * alternatives from where we got up to.
337 * Found a feasible alternative for event_id i,
338 * remember where we got up to with this event_id,
339 * go on to the next event_id, and start with
340 * the first alternative for it.
346 mask
|= cpuhw
->amasks
[i
][j
];
352 /* OK, we have a feasible combination, tell the caller the solution */
353 for (i
= 0; i
< n_ev
; ++i
)
354 event_id
[i
] = cpuhw
->alternatives
[i
][choice
[i
]];
359 * Check if newly-added events have consistent settings for
360 * exclude_{user,kernel,hv} with each other and any previously
363 static int check_excludes(struct perf_event
**ctrs
, unsigned int cflags
[],
364 int n_prev
, int n_new
)
366 int eu
= 0, ek
= 0, eh
= 0;
368 struct perf_event
*event
;
375 for (i
= 0; i
< n
; ++i
) {
376 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
) {
377 cflags
[i
] &= ~PPMU_LIMITED_PMC_REQD
;
382 eu
= event
->attr
.exclude_user
;
383 ek
= event
->attr
.exclude_kernel
;
384 eh
= event
->attr
.exclude_hv
;
386 } else if (event
->attr
.exclude_user
!= eu
||
387 event
->attr
.exclude_kernel
!= ek
||
388 event
->attr
.exclude_hv
!= eh
) {
394 for (i
= 0; i
< n
; ++i
)
395 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
)
396 cflags
[i
] |= PPMU_LIMITED_PMC_REQD
;
401 static void power_pmu_read(struct perf_event
*event
)
403 s64 val
, delta
, prev
;
408 * Performance monitor interrupts come even when interrupts
409 * are soft-disabled, as long as interrupts are hard-enabled.
410 * Therefore we treat them like NMIs.
413 prev
= local64_read(&event
->hw
.prev_count
);
415 val
= read_pmc(event
->hw
.idx
);
416 } while (local64_cmpxchg(&event
->hw
.prev_count
, prev
, val
) != prev
);
418 /* The counters are only 32 bits wide */
419 delta
= (val
- prev
) & 0xfffffffful
;
420 local64_add(delta
, &event
->count
);
421 local64_sub(delta
, &event
->hw
.period_left
);
425 * On some machines, PMC5 and PMC6 can't be written, don't respect
426 * the freeze conditions, and don't generate interrupts. This tells
427 * us if `event' is using such a PMC.
429 static int is_limited_pmc(int pmcnum
)
431 return (ppmu
->flags
& PPMU_LIMITED_PMC5_6
)
432 && (pmcnum
== 5 || pmcnum
== 6);
435 static void freeze_limited_counters(struct cpu_hw_events
*cpuhw
,
436 unsigned long pmc5
, unsigned long pmc6
)
438 struct perf_event
*event
;
439 u64 val
, prev
, delta
;
442 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
443 event
= cpuhw
->limited_counter
[i
];
446 val
= (event
->hw
.idx
== 5) ? pmc5
: pmc6
;
447 prev
= local64_read(&event
->hw
.prev_count
);
449 delta
= (val
- prev
) & 0xfffffffful
;
450 local64_add(delta
, &event
->count
);
454 static void thaw_limited_counters(struct cpu_hw_events
*cpuhw
,
455 unsigned long pmc5
, unsigned long pmc6
)
457 struct perf_event
*event
;
461 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
462 event
= cpuhw
->limited_counter
[i
];
463 event
->hw
.idx
= cpuhw
->limited_hwidx
[i
];
464 val
= (event
->hw
.idx
== 5) ? pmc5
: pmc6
;
465 local64_set(&event
->hw
.prev_count
, val
);
466 perf_event_update_userpage(event
);
471 * Since limited events don't respect the freeze conditions, we
472 * have to read them immediately after freezing or unfreezing the
473 * other events. We try to keep the values from the limited
474 * events as consistent as possible by keeping the delay (in
475 * cycles and instructions) between freezing/unfreezing and reading
476 * the limited events as small and consistent as possible.
477 * Therefore, if any limited events are in use, we read them
478 * both, and always in the same order, to minimize variability,
479 * and do it inside the same asm that writes MMCR0.
481 static void write_mmcr0(struct cpu_hw_events
*cpuhw
, unsigned long mmcr0
)
483 unsigned long pmc5
, pmc6
;
485 if (!cpuhw
->n_limited
) {
486 mtspr(SPRN_MMCR0
, mmcr0
);
491 * Write MMCR0, then read PMC5 and PMC6 immediately.
492 * To ensure we don't get a performance monitor interrupt
493 * between writing MMCR0 and freezing/thawing the limited
494 * events, we first write MMCR0 with the event overflow
495 * interrupt enable bits turned off.
497 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
498 : "=&r" (pmc5
), "=&r" (pmc6
)
499 : "r" (mmcr0
& ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
)),
501 "i" (SPRN_PMC5
), "i" (SPRN_PMC6
));
503 if (mmcr0
& MMCR0_FC
)
504 freeze_limited_counters(cpuhw
, pmc5
, pmc6
);
506 thaw_limited_counters(cpuhw
, pmc5
, pmc6
);
509 * Write the full MMCR0 including the event overflow interrupt
510 * enable bits, if necessary.
512 if (mmcr0
& (MMCR0_PMC1CE
| MMCR0_PMCjCE
))
513 mtspr(SPRN_MMCR0
, mmcr0
);
517 * Disable all events to prevent PMU interrupts and to allow
518 * events to be added or removed.
520 void hw_perf_disable(void)
522 struct cpu_hw_events
*cpuhw
;
527 local_irq_save(flags
);
528 cpuhw
= &__get_cpu_var(cpu_hw_events
);
530 if (!cpuhw
->disabled
) {
535 * Check if we ever enabled the PMU on this cpu.
537 if (!cpuhw
->pmcs_enabled
) {
539 cpuhw
->pmcs_enabled
= 1;
543 * Disable instruction sampling if it was enabled
545 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
547 cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
552 * Set the 'freeze counters' bit.
553 * The barrier is to make sure the mtspr has been
554 * executed and the PMU has frozen the events
557 write_mmcr0(cpuhw
, mfspr(SPRN_MMCR0
) | MMCR0_FC
);
560 local_irq_restore(flags
);
564 * Re-enable all events if disable == 0.
565 * If we were previously disabled and events were added, then
566 * put the new config on the PMU.
568 void hw_perf_enable(void)
570 struct perf_event
*event
;
571 struct cpu_hw_events
*cpuhw
;
576 unsigned int hwc_index
[MAX_HWEVENTS
];
582 local_irq_save(flags
);
583 cpuhw
= &__get_cpu_var(cpu_hw_events
);
584 if (!cpuhw
->disabled
) {
585 local_irq_restore(flags
);
591 * If we didn't change anything, or only removed events,
592 * no need to recalculate MMCR* settings and reset the PMCs.
593 * Just reenable the PMU with the current MMCR* settings
594 * (possibly updated for removal of events).
596 if (!cpuhw
->n_added
) {
597 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
598 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
599 if (cpuhw
->n_events
== 0)
600 ppc_set_pmu_inuse(0);
605 * Compute MMCR* values for the new set of events
607 if (ppmu
->compute_mmcr(cpuhw
->events
, cpuhw
->n_events
, hwc_index
,
609 /* shouldn't ever get here */
610 printk(KERN_ERR
"oops compute_mmcr failed\n");
615 * Add in MMCR0 freeze bits corresponding to the
616 * attr.exclude_* bits for the first event.
617 * We have already checked that all events have the
618 * same values for these bits as the first event.
620 event
= cpuhw
->event
[0];
621 if (event
->attr
.exclude_user
)
622 cpuhw
->mmcr
[0] |= MMCR0_FCP
;
623 if (event
->attr
.exclude_kernel
)
624 cpuhw
->mmcr
[0] |= freeze_events_kernel
;
625 if (event
->attr
.exclude_hv
)
626 cpuhw
->mmcr
[0] |= MMCR0_FCHV
;
629 * Write the new configuration to MMCR* with the freeze
630 * bit set and set the hardware events to their initial values.
631 * Then unfreeze the events.
633 ppc_set_pmu_inuse(1);
634 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
635 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
636 mtspr(SPRN_MMCR0
, (cpuhw
->mmcr
[0] & ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
))
640 * Read off any pre-existing events that need to move
643 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
644 event
= cpuhw
->event
[i
];
645 if (event
->hw
.idx
&& event
->hw
.idx
!= hwc_index
[i
] + 1) {
646 power_pmu_read(event
);
647 write_pmc(event
->hw
.idx
, 0);
653 * Initialize the PMCs for all the new and moved events.
655 cpuhw
->n_limited
= n_lim
= 0;
656 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
657 event
= cpuhw
->event
[i
];
660 idx
= hwc_index
[i
] + 1;
661 if (is_limited_pmc(idx
)) {
662 cpuhw
->limited_counter
[n_lim
] = event
;
663 cpuhw
->limited_hwidx
[n_lim
] = idx
;
668 if (event
->hw
.sample_period
) {
669 left
= local64_read(&event
->hw
.period_left
);
670 if (left
< 0x80000000L
)
671 val
= 0x80000000L
- left
;
673 local64_set(&event
->hw
.prev_count
, val
);
676 perf_event_update_userpage(event
);
678 cpuhw
->n_limited
= n_lim
;
679 cpuhw
->mmcr
[0] |= MMCR0_PMXE
| MMCR0_FCECE
;
683 write_mmcr0(cpuhw
, cpuhw
->mmcr
[0]);
686 * Enable instruction sampling if necessary
688 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
690 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2]);
694 local_irq_restore(flags
);
697 static int collect_events(struct perf_event
*group
, int max_count
,
698 struct perf_event
*ctrs
[], u64
*events
,
702 struct perf_event
*event
;
704 if (!is_software_event(group
)) {
708 flags
[n
] = group
->hw
.event_base
;
709 events
[n
++] = group
->hw
.config
;
711 list_for_each_entry(event
, &group
->sibling_list
, group_entry
) {
712 if (!is_software_event(event
) &&
713 event
->state
!= PERF_EVENT_STATE_OFF
) {
717 flags
[n
] = event
->hw
.event_base
;
718 events
[n
++] = event
->hw
.config
;
725 * Add a event to the PMU.
726 * If all events are not already frozen, then we disable and
727 * re-enable the PMU in order to get hw_perf_enable to do the
728 * actual work of reconfiguring the PMU.
730 static int power_pmu_enable(struct perf_event
*event
)
732 struct cpu_hw_events
*cpuhw
;
737 local_irq_save(flags
);
741 * Add the event to the list (if there is room)
742 * and check whether the total set is still feasible.
744 cpuhw
= &__get_cpu_var(cpu_hw_events
);
745 n0
= cpuhw
->n_events
;
746 if (n0
>= ppmu
->n_counter
)
748 cpuhw
->event
[n0
] = event
;
749 cpuhw
->events
[n0
] = event
->hw
.config
;
750 cpuhw
->flags
[n0
] = event
->hw
.event_base
;
753 * If group events scheduling transaction was started,
754 * skip the schedulability test here, it will be peformed
755 * at commit time(->commit_txn) as a whole
757 if (cpuhw
->group_flag
& PERF_EVENT_TXN
)
760 if (check_excludes(cpuhw
->event
, cpuhw
->flags
, n0
, 1))
762 if (power_check_constraints(cpuhw
, cpuhw
->events
, cpuhw
->flags
, n0
+ 1))
764 event
->hw
.config
= cpuhw
->events
[n0
];
773 local_irq_restore(flags
);
778 * Remove a event from the PMU.
780 static void power_pmu_disable(struct perf_event
*event
)
782 struct cpu_hw_events
*cpuhw
;
786 local_irq_save(flags
);
789 power_pmu_read(event
);
791 cpuhw
= &__get_cpu_var(cpu_hw_events
);
792 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
793 if (event
== cpuhw
->event
[i
]) {
794 while (++i
< cpuhw
->n_events
) {
795 cpuhw
->event
[i
-1] = cpuhw
->event
[i
];
796 cpuhw
->events
[i
-1] = cpuhw
->events
[i
];
797 cpuhw
->flags
[i
-1] = cpuhw
->flags
[i
];
800 ppmu
->disable_pmc(event
->hw
.idx
- 1, cpuhw
->mmcr
);
802 write_pmc(event
->hw
.idx
, 0);
805 perf_event_update_userpage(event
);
809 for (i
= 0; i
< cpuhw
->n_limited
; ++i
)
810 if (event
== cpuhw
->limited_counter
[i
])
812 if (i
< cpuhw
->n_limited
) {
813 while (++i
< cpuhw
->n_limited
) {
814 cpuhw
->limited_counter
[i
-1] = cpuhw
->limited_counter
[i
];
815 cpuhw
->limited_hwidx
[i
-1] = cpuhw
->limited_hwidx
[i
];
819 if (cpuhw
->n_events
== 0) {
820 /* disable exceptions if no events are running */
821 cpuhw
->mmcr
[0] &= ~(MMCR0_PMXE
| MMCR0_FCECE
);
825 local_irq_restore(flags
);
829 * Re-enable interrupts on a event after they were throttled
830 * because they were coming too fast.
832 static void power_pmu_unthrottle(struct perf_event
*event
)
837 if (!event
->hw
.idx
|| !event
->hw
.sample_period
)
839 local_irq_save(flags
);
841 power_pmu_read(event
);
842 left
= event
->hw
.sample_period
;
843 event
->hw
.last_period
= left
;
845 if (left
< 0x80000000L
)
846 val
= 0x80000000L
- left
;
847 write_pmc(event
->hw
.idx
, val
);
848 local64_set(&event
->hw
.prev_count
, val
);
849 local64_set(&event
->hw
.period_left
, left
);
850 perf_event_update_userpage(event
);
852 local_irq_restore(flags
);
856 * Start group events scheduling transaction
857 * Set the flag to make pmu::enable() not perform the
858 * schedulability test, it will be performed at commit time
860 void power_pmu_start_txn(const struct pmu
*pmu
)
862 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
864 cpuhw
->group_flag
|= PERF_EVENT_TXN
;
865 cpuhw
->n_txn_start
= cpuhw
->n_events
;
869 * Stop group events scheduling transaction
870 * Clear the flag and pmu::enable() will perform the
871 * schedulability test.
873 void power_pmu_cancel_txn(const struct pmu
*pmu
)
875 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
877 cpuhw
->group_flag
&= ~PERF_EVENT_TXN
;
881 * Commit group events scheduling transaction
882 * Perform the group schedulability test as a whole
883 * Return 0 if success
885 int power_pmu_commit_txn(const struct pmu
*pmu
)
887 struct cpu_hw_events
*cpuhw
;
892 cpuhw
= &__get_cpu_var(cpu_hw_events
);
894 if (check_excludes(cpuhw
->event
, cpuhw
->flags
, 0, n
))
896 i
= power_check_constraints(cpuhw
, cpuhw
->events
, cpuhw
->flags
, n
);
900 for (i
= cpuhw
->n_txn_start
; i
< n
; ++i
)
901 cpuhw
->event
[i
]->hw
.config
= cpuhw
->events
[i
];
903 cpuhw
->group_flag
&= ~PERF_EVENT_TXN
;
907 struct pmu power_pmu
= {
908 .enable
= power_pmu_enable
,
909 .disable
= power_pmu_disable
,
910 .read
= power_pmu_read
,
911 .unthrottle
= power_pmu_unthrottle
,
912 .start_txn
= power_pmu_start_txn
,
913 .cancel_txn
= power_pmu_cancel_txn
,
914 .commit_txn
= power_pmu_commit_txn
,
918 * Return 1 if we might be able to put event on a limited PMC,
920 * A event can only go on a limited PMC if it counts something
921 * that a limited PMC can count, doesn't require interrupts, and
922 * doesn't exclude any processor mode.
924 static int can_go_on_limited_pmc(struct perf_event
*event
, u64 ev
,
928 u64 alt
[MAX_EVENT_ALTERNATIVES
];
930 if (event
->attr
.exclude_user
931 || event
->attr
.exclude_kernel
932 || event
->attr
.exclude_hv
933 || event
->attr
.sample_period
)
936 if (ppmu
->limited_pmc_event(ev
))
940 * The requested event_id isn't on a limited PMC already;
941 * see if any alternative code goes on a limited PMC.
943 if (!ppmu
->get_alternatives
)
946 flags
|= PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
;
947 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
953 * Find an alternative event_id that goes on a normal PMC, if possible,
954 * and return the event_id code, or 0 if there is no such alternative.
955 * (Note: event_id code 0 is "don't count" on all machines.)
957 static u64
normal_pmc_alternative(u64 ev
, unsigned long flags
)
959 u64 alt
[MAX_EVENT_ALTERNATIVES
];
962 flags
&= ~(PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
);
963 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
969 /* Number of perf_events counting hardware events */
970 static atomic_t num_events
;
971 /* Used to avoid races in calling reserve/release_pmc_hardware */
972 static DEFINE_MUTEX(pmc_reserve_mutex
);
975 * Release the PMU if this is the last perf_event.
977 static void hw_perf_event_destroy(struct perf_event
*event
)
979 if (!atomic_add_unless(&num_events
, -1, 1)) {
980 mutex_lock(&pmc_reserve_mutex
);
981 if (atomic_dec_return(&num_events
) == 0)
982 release_pmc_hardware();
983 mutex_unlock(&pmc_reserve_mutex
);
988 * Translate a generic cache event_id config to a raw event_id code.
990 static int hw_perf_cache_event(u64 config
, u64
*eventp
)
992 unsigned long type
, op
, result
;
995 if (!ppmu
->cache_events
)
999 type
= config
& 0xff;
1000 op
= (config
>> 8) & 0xff;
1001 result
= (config
>> 16) & 0xff;
1003 if (type
>= PERF_COUNT_HW_CACHE_MAX
||
1004 op
>= PERF_COUNT_HW_CACHE_OP_MAX
||
1005 result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
1008 ev
= (*ppmu
->cache_events
)[type
][op
][result
];
1017 const struct pmu
*hw_perf_event_init(struct perf_event
*event
)
1020 unsigned long flags
;
1021 struct perf_event
*ctrs
[MAX_HWEVENTS
];
1022 u64 events
[MAX_HWEVENTS
];
1023 unsigned int cflags
[MAX_HWEVENTS
];
1026 struct cpu_hw_events
*cpuhw
;
1029 return ERR_PTR(-ENXIO
);
1030 switch (event
->attr
.type
) {
1031 case PERF_TYPE_HARDWARE
:
1032 ev
= event
->attr
.config
;
1033 if (ev
>= ppmu
->n_generic
|| ppmu
->generic_events
[ev
] == 0)
1034 return ERR_PTR(-EOPNOTSUPP
);
1035 ev
= ppmu
->generic_events
[ev
];
1037 case PERF_TYPE_HW_CACHE
:
1038 err
= hw_perf_cache_event(event
->attr
.config
, &ev
);
1040 return ERR_PTR(err
);
1043 ev
= event
->attr
.config
;
1046 return ERR_PTR(-EINVAL
);
1048 event
->hw
.config_base
= ev
;
1052 * If we are not running on a hypervisor, force the
1053 * exclude_hv bit to 0 so that we don't care what
1054 * the user set it to.
1056 if (!firmware_has_feature(FW_FEATURE_LPAR
))
1057 event
->attr
.exclude_hv
= 0;
1060 * If this is a per-task event, then we can use
1061 * PM_RUN_* events interchangeably with their non RUN_*
1062 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1063 * XXX we should check if the task is an idle task.
1066 if (event
->ctx
->task
)
1067 flags
|= PPMU_ONLY_COUNT_RUN
;
1070 * If this machine has limited events, check whether this
1071 * event_id could go on a limited event.
1073 if (ppmu
->flags
& PPMU_LIMITED_PMC5_6
) {
1074 if (can_go_on_limited_pmc(event
, ev
, flags
)) {
1075 flags
|= PPMU_LIMITED_PMC_OK
;
1076 } else if (ppmu
->limited_pmc_event(ev
)) {
1078 * The requested event_id is on a limited PMC,
1079 * but we can't use a limited PMC; see if any
1080 * alternative goes on a normal PMC.
1082 ev
= normal_pmc_alternative(ev
, flags
);
1084 return ERR_PTR(-EINVAL
);
1089 * If this is in a group, check if it can go on with all the
1090 * other hardware events in the group. We assume the event
1091 * hasn't been linked into its leader's sibling list at this point.
1094 if (event
->group_leader
!= event
) {
1095 n
= collect_events(event
->group_leader
, ppmu
->n_counter
- 1,
1096 ctrs
, events
, cflags
);
1098 return ERR_PTR(-EINVAL
);
1103 if (check_excludes(ctrs
, cflags
, n
, 1))
1104 return ERR_PTR(-EINVAL
);
1106 cpuhw
= &get_cpu_var(cpu_hw_events
);
1107 err
= power_check_constraints(cpuhw
, events
, cflags
, n
+ 1);
1108 put_cpu_var(cpu_hw_events
);
1110 return ERR_PTR(-EINVAL
);
1112 event
->hw
.config
= events
[n
];
1113 event
->hw
.event_base
= cflags
[n
];
1114 event
->hw
.last_period
= event
->hw
.sample_period
;
1115 local64_set(&event
->hw
.period_left
, event
->hw
.last_period
);
1118 * See if we need to reserve the PMU.
1119 * If no events are currently in use, then we have to take a
1120 * mutex to ensure that we don't race with another task doing
1121 * reserve_pmc_hardware or release_pmc_hardware.
1124 if (!atomic_inc_not_zero(&num_events
)) {
1125 mutex_lock(&pmc_reserve_mutex
);
1126 if (atomic_read(&num_events
) == 0 &&
1127 reserve_pmc_hardware(perf_event_interrupt
))
1130 atomic_inc(&num_events
);
1131 mutex_unlock(&pmc_reserve_mutex
);
1133 event
->destroy
= hw_perf_event_destroy
;
1136 return ERR_PTR(err
);
1141 * A counter has overflowed; update its count and record
1142 * things if requested. Note that interrupts are hard-disabled
1143 * here so there is no possibility of being interrupted.
1145 static void record_and_restart(struct perf_event
*event
, unsigned long val
,
1146 struct pt_regs
*regs
, int nmi
)
1148 u64 period
= event
->hw
.sample_period
;
1149 s64 prev
, delta
, left
;
1152 /* we don't have to worry about interrupts here */
1153 prev
= local64_read(&event
->hw
.prev_count
);
1154 delta
= (val
- prev
) & 0xfffffffful
;
1155 local64_add(delta
, &event
->count
);
1158 * See if the total period for this event has expired,
1159 * and update for the next period.
1162 left
= local64_read(&event
->hw
.period_left
) - delta
;
1170 if (left
< 0x80000000LL
)
1171 val
= 0x80000000LL
- left
;
1175 * Finally record data if requested.
1178 struct perf_sample_data data
;
1180 perf_sample_data_init(&data
, ~0ULL);
1181 data
.period
= event
->hw
.last_period
;
1183 if (event
->attr
.sample_type
& PERF_SAMPLE_ADDR
)
1184 perf_get_data_addr(regs
, &data
.addr
);
1186 if (perf_event_overflow(event
, nmi
, &data
, regs
)) {
1188 * Interrupts are coming too fast - throttle them
1189 * by setting the event to 0, so it will be
1190 * at least 2^30 cycles until the next interrupt
1191 * (assuming each event counts at most 2 counts
1199 write_pmc(event
->hw
.idx
, val
);
1200 local64_set(&event
->hw
.prev_count
, val
);
1201 local64_set(&event
->hw
.period_left
, left
);
1202 perf_event_update_userpage(event
);
1206 * Called from generic code to get the misc flags (i.e. processor mode)
1209 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1211 u32 flags
= perf_get_misc_flags(regs
);
1215 return user_mode(regs
) ? PERF_RECORD_MISC_USER
:
1216 PERF_RECORD_MISC_KERNEL
;
1220 * Called from generic code to get the instruction pointer
1223 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1227 if (TRAP(regs
) != 0xf00)
1228 return regs
->nip
; /* not a PMU interrupt */
1230 ip
= mfspr(SPRN_SIAR
) + perf_ip_adjust(regs
);
1235 * Performance monitor interrupt stuff
1237 static void perf_event_interrupt(struct pt_regs
*regs
)
1240 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
1241 struct perf_event
*event
;
1246 if (cpuhw
->n_limited
)
1247 freeze_limited_counters(cpuhw
, mfspr(SPRN_PMC5
),
1250 perf_read_regs(regs
);
1252 nmi
= perf_intr_is_nmi(regs
);
1258 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1259 event
= cpuhw
->event
[i
];
1260 if (!event
->hw
.idx
|| is_limited_pmc(event
->hw
.idx
))
1262 val
= read_pmc(event
->hw
.idx
);
1264 /* event has overflowed */
1266 record_and_restart(event
, val
, regs
, nmi
);
1271 * In case we didn't find and reset the event that caused
1272 * the interrupt, scan all events and reset any that are
1273 * negative, to avoid getting continual interrupts.
1274 * Any that we processed in the previous loop will not be negative.
1277 for (i
= 0; i
< ppmu
->n_counter
; ++i
) {
1278 if (is_limited_pmc(i
+ 1))
1280 val
= read_pmc(i
+ 1);
1282 write_pmc(i
+ 1, 0);
1287 * Reset MMCR0 to its normal value. This will set PMXE and
1288 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1289 * and thus allow interrupts to occur again.
1290 * XXX might want to use MSR.PM to keep the events frozen until
1291 * we get back out of this interrupt.
1293 write_mmcr0(cpuhw
, cpuhw
->mmcr
[0]);
1301 static void power_pmu_setup(int cpu
)
1303 struct cpu_hw_events
*cpuhw
= &per_cpu(cpu_hw_events
, cpu
);
1307 memset(cpuhw
, 0, sizeof(*cpuhw
));
1308 cpuhw
->mmcr
[0] = MMCR0_FC
;
1311 static int __cpuinit
1312 power_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1314 unsigned int cpu
= (long)hcpu
;
1316 switch (action
& ~CPU_TASKS_FROZEN
) {
1317 case CPU_UP_PREPARE
:
1318 power_pmu_setup(cpu
);
1328 int register_power_pmu(struct power_pmu
*pmu
)
1331 return -EBUSY
; /* something's already registered */
1334 pr_info("%s performance monitor hardware support registered\n",
1339 * Use FCHV to ignore kernel events if MSR.HV is set.
1341 if (mfmsr() & MSR_HV
)
1342 freeze_events_kernel
= MMCR0_FCHV
;
1343 #endif /* CONFIG_PPC64 */
1345 perf_cpu_notifier(power_pmu_notifier
);