1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
51 #define I915_NUM_PIPE 2
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
67 #define WATCH_COHERENCY 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
80 struct drm_i915_gem_phys_object
{
82 struct page
**page_list
;
83 drm_dma_handle_t
*handle
;
84 struct drm_gem_object
*cur_obj
;
87 typedef struct _drm_i915_ring_buffer
{
95 struct drm_gem_object
*ring_obj
;
96 } drm_i915_ring_buffer_t
;
99 struct mem_block
*next
;
100 struct mem_block
*prev
;
103 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header
;
107 struct opregion_acpi
;
108 struct opregion_swsci
;
109 struct opregion_asle
;
111 struct intel_opregion
{
112 struct opregion_header
*header
;
113 struct opregion_acpi
*acpi
;
114 struct opregion_swsci
*swsci
;
115 struct opregion_asle
*asle
;
119 struct drm_i915_master_private
{
120 drm_local_map_t
*sarea
;
121 struct _drm_i915_sarea
*sarea_priv
;
123 #define I915_FENCE_REG_NONE -1
125 struct drm_i915_fence_reg
{
126 struct drm_gem_object
*obj
;
129 struct sdvo_device_mapping
{
136 typedef struct drm_i915_private
{
137 struct drm_device
*dev
;
143 drm_i915_ring_buffer_t ring
;
145 drm_dma_handle_t
*status_page_dmah
;
146 void *hw_status_page
;
147 dma_addr_t dma_status_page
;
149 unsigned int status_gfx_addr
;
150 drm_local_map_t hws_map
;
151 struct drm_gem_object
*hws_obj
;
159 wait_queue_head_t irq_queue
;
160 atomic_t irq_received
;
161 /** Protects user_irq_refcount and irq_mask_reg */
162 spinlock_t user_irq_lock
;
163 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
164 int user_irq_refcount
;
165 /** Cached value of IMR to avoid reads in updating the bitfield */
169 u32 hotplug_supported_mask
;
170 struct work_struct hotplug_work
;
172 int tex_lru_log_granularity
;
173 int allow_batchbuffer
;
174 struct mem_block
*agp_heap
;
175 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
178 bool cursor_needs_physical
;
184 struct intel_opregion opregion
;
187 int backlight_duty_cycle
; /* restore backlight to this value */
188 bool panel_wants_dither
;
189 struct drm_display_mode
*panel_fixed_mode
;
190 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
191 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
193 /* Feature bits from the VBIOS */
194 unsigned int int_tv_support
:1;
195 unsigned int lvds_dither
:1;
196 unsigned int lvds_vbt
:1;
197 unsigned int int_crt_support
:1;
198 unsigned int lvds_use_ssc
:1;
201 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
202 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
203 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
210 u32 saveRENDERSTANDBY
;
234 u32 savePFIT_PGM_RATIOS
;
236 u32 saveBLC_PWM_CTL2
;
261 u32 savePP_ON_DELAYS
;
262 u32 savePP_OFF_DELAYS
;
270 u32 savePFIT_CONTROL
;
271 u32 save_palette_a
[256];
272 u32 save_palette_b
[256];
273 u32 saveFBC_CFB_BASE
;
276 u32 saveFBC_CONTROL2
;
280 u32 saveCACHE_MODE_0
;
283 u32 saveMI_ARB_STATE
;
294 uint64_t saveFENCE
[16];
304 struct drm_mm gtt_space
;
306 struct io_mapping
*gtt_mapping
;
310 * List of objects currently involved in rendering from the
313 * Includes buffers having the contents of their GPU caches
314 * flushed, not necessarily primitives. last_rendering_seqno
315 * represents when the rendering involved will be completed.
317 * A reference is held on the buffer while on this list.
319 spinlock_t active_list_lock
;
320 struct list_head active_list
;
323 * List of objects which are not in the ringbuffer but which
324 * still have a write_domain which needs to be flushed before
327 * last_rendering_seqno is 0 while an object is in this list.
329 * A reference is held on the buffer while on this list.
331 struct list_head flushing_list
;
334 * LRU list of objects which are not in the ringbuffer and
335 * are ready to unbind, but are still in the GTT.
337 * last_rendering_seqno is 0 while an object is in this list.
339 * A reference is not held on the buffer while on this list,
340 * as merely being GTT-bound shouldn't prevent its being
341 * freed, and we'll pull it off the list in the free path.
343 struct list_head inactive_list
;
346 * List of breadcrumbs associated with GPU requests currently
349 struct list_head request_list
;
352 * We leave the user IRQ off as much as possible,
353 * but this means that requests will finish and never
354 * be retired once the system goes idle. Set a timer to
355 * fire periodically while the ring is running. When it
356 * fires, go retire requests.
358 struct delayed_work retire_work
;
360 uint32_t next_gem_seqno
;
363 * Waiting sequence number, if any
365 uint32_t waiting_gem_seqno
;
368 * Last seq seen at irq time
370 uint32_t irq_gem_seqno
;
373 * Flag if the X Server, and thus DRM, is not currently in
374 * control of the device.
376 * This is set between LeaveVT and EnterVT. It needs to be
377 * replaced with a semaphore. It also needs to be
378 * transitioned away from for kernel modesetting.
383 * Flag if the hardware appears to be wedged.
385 * This is set when attempts to idle the device timeout.
386 * It prevents command submission from occuring and makes
387 * every pending request fail
391 /** Bit 6 swizzling required for X tiling */
392 uint32_t bit_6_swizzle_x
;
393 /** Bit 6 swizzling required for Y tiling */
394 uint32_t bit_6_swizzle_y
;
396 /* storage for physical objects */
397 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
399 struct sdvo_device_mapping sdvo_mappings
[2];
400 } drm_i915_private_t
;
402 /** driver private structure attached to each drm_gem_object */
403 struct drm_i915_gem_object
{
404 struct drm_gem_object
*obj
;
406 /** Current space allocated to this object in the GTT, if any. */
407 struct drm_mm_node
*gtt_space
;
409 /** This object's place on the active/flushing/inactive lists */
410 struct list_head list
;
413 * This is set if the object is on the active or flushing lists
414 * (has pending rendering), and is not set if it's on inactive (ready
420 * This is set if the object has been written to since last bound
425 /** AGP memory structure for our GTT binding. */
426 DRM_AGP_MEM
*agp_mem
;
432 * Current offset of the object in GTT space.
434 * This is the same as gtt_space->start
438 * Required alignment for the object
440 uint32_t gtt_alignment
;
442 * Fake offset for use by mmap(2)
444 uint64_t mmap_offset
;
447 * Fence register bits (if any) for this object. Will be set
448 * as needed when mapped into the GTT.
449 * Protected by dev->struct_mutex.
453 /** Boolean whether this object has a valid gtt offset. */
456 /** How many users have pinned this object in GTT space */
459 /** Breadcrumb of last rendering to the buffer. */
460 uint32_t last_rendering_seqno
;
462 /** Current tiling mode for the object. */
463 uint32_t tiling_mode
;
466 /** Record of address bit 17 of each page at last unbind. */
469 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
473 * If present, while GEM_DOMAIN_CPU is in the read domain this array
474 * flags which individual pages are valid.
476 uint8_t *page_cpu_valid
;
478 /** User space pin count and filp owning the pin */
479 uint32_t user_pin_count
;
480 struct drm_file
*pin_filp
;
482 /** for phy allocated objects */
483 struct drm_i915_gem_phys_object
*phys_obj
;
486 * Used for checking the object doesn't appear more than once
487 * in an execbuffer object list.
493 * Request queue structure.
495 * The request queue allows us to note sequence numbers that have been emitted
496 * and may be associated with active buffers to be retired.
498 * By keeping this list, we can avoid having to do questionable
499 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
500 * an emission time with seqnos for tracking how far ahead of the GPU we are.
502 struct drm_i915_gem_request
{
503 /** GEM sequence number associated with this request. */
506 /** Time at which this request was emitted, in jiffies. */
507 unsigned long emitted_jiffies
;
509 /** global list entry for this request */
510 struct list_head list
;
512 /** file_priv list entry for this request */
513 struct list_head client_list
;
516 struct drm_i915_file_private
{
518 struct list_head request_list
;
522 enum intel_chip_family
{
529 extern struct drm_ioctl_desc i915_ioctls
[];
530 extern int i915_max_ioctl
;
531 extern unsigned int i915_fbpercrtc
;
533 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
534 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
537 extern void i915_kernel_lost_context(struct drm_device
* dev
);
538 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
539 extern int i915_driver_unload(struct drm_device
*);
540 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
541 extern void i915_driver_lastclose(struct drm_device
* dev
);
542 extern void i915_driver_preclose(struct drm_device
*dev
,
543 struct drm_file
*file_priv
);
544 extern void i915_driver_postclose(struct drm_device
*dev
,
545 struct drm_file
*file_priv
);
546 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
547 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
549 extern int i915_emit_box(struct drm_device
*dev
,
550 struct drm_clip_rect
*boxes
,
551 int i
, int DR1
, int DR4
);
554 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
555 struct drm_file
*file_priv
);
556 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
557 struct drm_file
*file_priv
);
558 void i915_user_irq_get(struct drm_device
*dev
);
559 void i915_user_irq_put(struct drm_device
*dev
);
560 extern void i915_enable_interrupt (struct drm_device
*dev
);
562 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
563 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
564 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
565 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
566 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
567 struct drm_file
*file_priv
);
568 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
569 struct drm_file
*file_priv
);
570 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
571 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
572 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
573 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
574 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
575 struct drm_file
*file_priv
);
576 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
579 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
582 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
586 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
587 struct drm_file
*file_priv
);
588 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
589 struct drm_file
*file_priv
);
590 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
591 struct drm_file
*file_priv
);
592 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
593 struct drm_file
*file_priv
);
594 extern void i915_mem_takedown(struct mem_block
**heap
);
595 extern void i915_mem_release(struct drm_device
* dev
,
596 struct drm_file
*file_priv
, struct mem_block
*heap
);
598 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
599 struct drm_file
*file_priv
);
600 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
601 struct drm_file
*file_priv
);
602 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
603 struct drm_file
*file_priv
);
604 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
605 struct drm_file
*file_priv
);
606 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
607 struct drm_file
*file_priv
);
608 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
609 struct drm_file
*file_priv
);
610 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
611 struct drm_file
*file_priv
);
612 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
613 struct drm_file
*file_priv
);
614 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
615 struct drm_file
*file_priv
);
616 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
617 struct drm_file
*file_priv
);
618 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
619 struct drm_file
*file_priv
);
620 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
621 struct drm_file
*file_priv
);
622 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
623 struct drm_file
*file_priv
);
624 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
625 struct drm_file
*file_priv
);
626 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
627 struct drm_file
*file_priv
);
628 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
629 struct drm_file
*file_priv
);
630 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
631 struct drm_file
*file_priv
);
632 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
633 struct drm_file
*file_priv
);
634 void i915_gem_load(struct drm_device
*dev
);
635 int i915_gem_init_object(struct drm_gem_object
*obj
);
636 void i915_gem_free_object(struct drm_gem_object
*obj
);
637 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
);
638 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
639 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
640 void i915_gem_lastclose(struct drm_device
*dev
);
641 uint32_t i915_get_gem_seqno(struct drm_device
*dev
);
642 void i915_gem_retire_requests(struct drm_device
*dev
);
643 void i915_gem_retire_work_handler(struct work_struct
*work
);
644 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
645 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
646 uint32_t read_domains
,
647 uint32_t write_domain
);
648 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
649 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
650 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
652 int i915_gem_idle(struct drm_device
*dev
);
653 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
654 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
656 int i915_gem_attach_phys_object(struct drm_device
*dev
,
657 struct drm_gem_object
*obj
, int id
);
658 void i915_gem_detach_phys_object(struct drm_device
*dev
,
659 struct drm_gem_object
*obj
);
660 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
661 int i915_gem_object_get_pages(struct drm_gem_object
*obj
);
662 void i915_gem_object_put_pages(struct drm_gem_object
*obj
);
663 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
665 /* i915_gem_tiling.c */
666 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
667 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
668 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
670 /* i915_gem_debug.c */
671 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
672 const char *where
, uint32_t mark
);
674 void i915_verify_inactive(struct drm_device
*dev
, char *file
, int line
);
676 #define i915_verify_inactive(dev, file, line)
678 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
679 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
680 const char *where
, uint32_t mark
);
681 void i915_dump_lru(struct drm_device
*dev
, const char *where
);
684 int i915_gem_debugfs_init(struct drm_minor
*minor
);
685 void i915_gem_debugfs_cleanup(struct drm_minor
*minor
);
688 extern int i915_save_state(struct drm_device
*dev
);
689 extern int i915_restore_state(struct drm_device
*dev
);
692 extern int i915_save_state(struct drm_device
*dev
);
693 extern int i915_restore_state(struct drm_device
*dev
);
696 /* i915_opregion.c */
697 extern int intel_opregion_init(struct drm_device
*dev
, int resume
);
698 extern void intel_opregion_free(struct drm_device
*dev
, int suspend
);
699 extern void opregion_asle_intr(struct drm_device
*dev
);
700 extern void opregion_enable_asle(struct drm_device
*dev
);
702 static inline int intel_opregion_init(struct drm_device
*dev
, int resume
) { return 0; }
703 static inline void intel_opregion_free(struct drm_device
*dev
, int suspend
) { return; }
704 static inline void opregion_asle_intr(struct drm_device
*dev
) { return; }
705 static inline void opregion_enable_asle(struct drm_device
*dev
) { return; }
709 extern void intel_modeset_init(struct drm_device
*dev
);
710 extern void intel_modeset_cleanup(struct drm_device
*dev
);
713 * Lock test for when it's just for synchronization of ring access.
715 * In that case, we don't need to do it when GEM is initialized as nobody else
716 * has access to the ring.
718 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
719 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
720 LOCK_TEST_WITH_RETURN(dev, file_priv); \
723 #define I915_READ(reg) readl(dev_priv->regs + (reg))
724 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
725 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
726 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
727 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
728 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
729 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
730 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
731 #define POSTING_READ(reg) (void)I915_READ(reg)
733 #define I915_VERBOSE 0
735 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
738 #define BEGIN_LP_RING(n) do { \
740 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
741 if (dev_priv->ring.space < (n)*4) \
742 i915_wait_ring(dev, (n)*4, __func__); \
744 outring = dev_priv->ring.tail; \
745 ringmask = dev_priv->ring.tail_mask; \
746 virt = dev_priv->ring.virtual_start; \
749 #define OUT_RING(n) do { \
750 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
751 *(volatile unsigned int *)(virt + outring) = (n); \
754 outring &= ringmask; \
757 #define ADVANCE_LP_RING() do { \
758 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
759 dev_priv->ring.tail = outring; \
760 dev_priv->ring.space -= outcount * 4; \
761 I915_WRITE(PRB0_TAIL, outring); \
765 * Reads a dword out of the status page, which is written to from the command
766 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
769 * The following dwords have a reserved meaning:
770 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
771 * 0x04: ring 0 head pointer
772 * 0x05: ring 1 head pointer (915-class)
773 * 0x06: ring 2 head pointer (915-class)
774 * 0x10-0x1b: Context status DWords (GM45)
775 * 0x1f: Last written status offset. (GM45)
777 * The area from dword 0x20 to 0x3ff is available for driver usage.
779 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
780 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
781 #define I915_GEM_HWS_INDEX 0x20
782 #define I915_BREADCRUMB_INDEX 0x21
784 extern int i915_wait_ring(struct drm_device
* dev
, int n
, const char *caller
);
786 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
787 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
788 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
789 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
790 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
792 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
793 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
794 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
795 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
796 (dev)->pci_device == 0x27AE)
797 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
798 (dev)->pci_device == 0x2982 || \
799 (dev)->pci_device == 0x2992 || \
800 (dev)->pci_device == 0x29A2 || \
801 (dev)->pci_device == 0x2A02 || \
802 (dev)->pci_device == 0x2A12 || \
803 (dev)->pci_device == 0x2A42 || \
804 (dev)->pci_device == 0x2E02 || \
805 (dev)->pci_device == 0x2E12 || \
806 (dev)->pci_device == 0x2E22 || \
807 (dev)->pci_device == 0x2E32 || \
808 (dev)->pci_device == 0x0042 || \
809 (dev)->pci_device == 0x0046)
811 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
812 (dev)->pci_device == 0x2A12)
814 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
816 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
817 (dev)->pci_device == 0x2E12 || \
818 (dev)->pci_device == 0x2E22 || \
819 (dev)->pci_device == 0x2E32 || \
822 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
823 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
824 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
826 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
827 (dev)->pci_device == 0x29B2 || \
828 (dev)->pci_device == 0x29D2 || \
831 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
832 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
833 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
835 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
836 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
839 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
840 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
841 IS_IGD(dev) || IS_IGDNG_M(dev))
843 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
845 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
846 * rows, which changed the alignment requirements and fence programming.
848 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
850 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
851 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
853 #define PRIMARY_RINGBUFFER_SIZE (128*1024)