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OMAP: McBSP: Add link DMA mode selection
[linux-2.6/cjktty.git] / arch / arm / plat-omap / mcbsp.c
blob9e699947a693d3476326252d7cd45284b1115480
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26
27 #include <mach/dma.h>
28 #include <mach/mcbsp.h>
29
30 struct omap_mcbsp **mcbsp_ptr;
31 int omap_mcbsp_count;
32
33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
34 {
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16)val, io_base + reg);
37 else
38 __raw_writel(val, io_base + reg);
39 }
40
41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
42 {
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base + reg);
45 else
46 return __raw_readl(io_base + reg);
47 }
48
49 #define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51 #define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
53
54 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
56
57 static void omap_mcbsp_dump_reg(u8 id)
58 {
59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
60
61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
89 }
90
91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
92 {
93 struct omap_mcbsp *mcbsp_tx = dev_id;
94 u16 irqst_spcr2;
95
96 irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
97 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
98
99 if (irqst_spcr2 & XSYNC_ERR) {
100 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
101 irqst_spcr2);
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
104 irqst_spcr2 & ~(XSYNC_ERR));
105 } else {
106 complete(&mcbsp_tx->tx_irq_completion);
107 }
108
109 return IRQ_HANDLED;
110 }
111
112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
113 {
114 struct omap_mcbsp *mcbsp_rx = dev_id;
115 u16 irqst_spcr1;
116
117 irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
118 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
119
120 if (irqst_spcr1 & RSYNC_ERR) {
121 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
122 irqst_spcr1);
123 /* Writing zero to RSYNC_ERR clears the IRQ */
124 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
125 irqst_spcr1 & ~(RSYNC_ERR));
126 } else {
127 complete(&mcbsp_rx->tx_irq_completion);
128 }
129
130 return IRQ_HANDLED;
131 }
132
133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
134 {
135 struct omap_mcbsp *mcbsp_dma_tx = data;
136
137 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
138 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
139
140 /* We can free the channels */
141 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
142 mcbsp_dma_tx->dma_tx_lch = -1;
143
144 complete(&mcbsp_dma_tx->tx_dma_completion);
145 }
146
147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
148 {
149 struct omap_mcbsp *mcbsp_dma_rx = data;
150
151 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
152 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
153
154 /* We can free the channels */
155 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
156 mcbsp_dma_rx->dma_rx_lch = -1;
157
158 complete(&mcbsp_dma_rx->rx_dma_completion);
159 }
160
161 /*
162 * omap_mcbsp_config simply write a config to the
163 * appropriate McBSP.
164 * You either call this function or set the McBSP registers
165 * by yourself before calling omap_mcbsp_start().
166 */
167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
168 {
169 struct omap_mcbsp *mcbsp;
170 void __iomem *io_base;
171
172 if (!omap_mcbsp_check_valid_id(id)) {
173 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
174 return;
175 }
176 mcbsp = id_to_mcbsp_ptr(id);
177
178 io_base = mcbsp->io_base;
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
181
182 /* We write the given config */
183 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
184 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
185 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
186 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
187 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
188 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
189 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
190 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
194 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
197 }
198 }
199 EXPORT_SYMBOL(omap_mcbsp_config);
200
201 #ifdef CONFIG_ARCH_OMAP34XX
202 /*
203 * omap_mcbsp_set_tx_threshold configures how to deal
204 * with transmit threshold. the threshold value and handler can be
205 * configure in here.
206 */
207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
208 {
209 struct omap_mcbsp *mcbsp;
210 void __iomem *io_base;
211
212 if (!cpu_is_omap34xx())
213 return;
214
215 if (!omap_mcbsp_check_valid_id(id)) {
216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
217 return;
218 }
219 mcbsp = id_to_mcbsp_ptr(id);
220 io_base = mcbsp->io_base;
221
222 OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
223 }
224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
225
226 /*
227 * omap_mcbsp_set_rx_threshold configures how to deal
228 * with receive threshold. the threshold value and handler can be
229 * configure in here.
230 */
231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
232 {
233 struct omap_mcbsp *mcbsp;
234 void __iomem *io_base;
235
236 if (!cpu_is_omap34xx())
237 return;
238
239 if (!omap_mcbsp_check_valid_id(id)) {
240 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
241 return;
242 }
243 mcbsp = id_to_mcbsp_ptr(id);
244 io_base = mcbsp->io_base;
245
246 OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
247 }
248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
249
250 /*
251 * omap_mcbsp_get_max_tx_thres just return the current configured
252 * maximum threshold for transmission
253 */
254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
255 {
256 struct omap_mcbsp *mcbsp;
257
258 if (!omap_mcbsp_check_valid_id(id)) {
259 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
260 return -ENODEV;
261 }
262 mcbsp = id_to_mcbsp_ptr(id);
263
264 return mcbsp->max_tx_thres;
265 }
266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
267
268 /*
269 * omap_mcbsp_get_max_rx_thres just return the current configured
270 * maximum threshold for reception
271 */
272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
273 {
274 struct omap_mcbsp *mcbsp;
275
276 if (!omap_mcbsp_check_valid_id(id)) {
277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
278 return -ENODEV;
279 }
280 mcbsp = id_to_mcbsp_ptr(id);
281
282 return mcbsp->max_rx_thres;
283 }
284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
285
286 /*
287 * omap_mcbsp_get_dma_op_mode just return the current configured
288 * operating mode for the mcbsp channel
289 */
290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
291 {
292 struct omap_mcbsp *mcbsp;
293 int dma_op_mode;
294
295 if (!omap_mcbsp_check_valid_id(id)) {
296 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
297 return -ENODEV;
298 }
299 mcbsp = id_to_mcbsp_ptr(id);
300
301 spin_lock_irq(&mcbsp->lock);
302 dma_op_mode = mcbsp->dma_op_mode;
303 spin_unlock_irq(&mcbsp->lock);
304
305 return dma_op_mode;
306 }
307 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
308 #endif
309
310 /*
311 * We can choose between IRQ based or polled IO.
312 * This needs to be called before omap_mcbsp_request().
313 */
314 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
315 {
316 struct omap_mcbsp *mcbsp;
317
318 if (!omap_mcbsp_check_valid_id(id)) {
319 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
320 return -ENODEV;
321 }
322 mcbsp = id_to_mcbsp_ptr(id);
323
324 spin_lock(&mcbsp->lock);
325
326 if (!mcbsp->free) {
327 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
328 mcbsp->id);
329 spin_unlock(&mcbsp->lock);
330 return -EINVAL;
331 }
332
333 mcbsp->io_type = io_type;
334
335 spin_unlock(&mcbsp->lock);
336
337 return 0;
338 }
339 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
340
341 int omap_mcbsp_request(unsigned int id)
342 {
343 struct omap_mcbsp *mcbsp;
344 int err;
345
346 if (!omap_mcbsp_check_valid_id(id)) {
347 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
348 return -ENODEV;
349 }
350 mcbsp = id_to_mcbsp_ptr(id);
351
352 spin_lock(&mcbsp->lock);
353 if (!mcbsp->free) {
354 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
355 mcbsp->id);
356 spin_unlock(&mcbsp->lock);
357 return -EBUSY;
358 }
359
360 mcbsp->free = 0;
361 spin_unlock(&mcbsp->lock);
362
363 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
364 mcbsp->pdata->ops->request(id);
365
366 clk_enable(mcbsp->iclk);
367 clk_enable(mcbsp->fclk);
368
369 /*
370 * Make sure that transmitter, receiver and sample-rate generator are
371 * not running before activating IRQs.
372 */
373 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
374 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
375
376 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
377 /* We need to get IRQs here */
378 init_completion(&mcbsp->tx_irq_completion);
379 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
380 0, "McBSP", (void *)mcbsp);
381 if (err != 0) {
382 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
383 "for McBSP%d\n", mcbsp->tx_irq,
384 mcbsp->id);
385 return err;
386 }
387
388 init_completion(&mcbsp->rx_irq_completion);
389 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
390 0, "McBSP", (void *)mcbsp);
391 if (err != 0) {
392 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
393 "for McBSP%d\n", mcbsp->rx_irq,
394 mcbsp->id);
395 free_irq(mcbsp->tx_irq, (void *)mcbsp);
396 return err;
397 }
398 }
399
400 return 0;
401 }
402 EXPORT_SYMBOL(omap_mcbsp_request);
403
404 void omap_mcbsp_free(unsigned int id)
405 {
406 struct omap_mcbsp *mcbsp;
407
408 if (!omap_mcbsp_check_valid_id(id)) {
409 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
410 return;
411 }
412 mcbsp = id_to_mcbsp_ptr(id);
413
414 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
415 mcbsp->pdata->ops->free(id);
416
417 clk_disable(mcbsp->fclk);
418 clk_disable(mcbsp->iclk);
419
420 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
421 /* Free IRQs */
422 free_irq(mcbsp->rx_irq, (void *)mcbsp);
423 free_irq(mcbsp->tx_irq, (void *)mcbsp);
424 }
425
426 spin_lock(&mcbsp->lock);
427 if (mcbsp->free) {
428 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
429 mcbsp->id);
430 spin_unlock(&mcbsp->lock);
431 return;
432 }
433
434 mcbsp->free = 1;
435 spin_unlock(&mcbsp->lock);
436 }
437 EXPORT_SYMBOL(omap_mcbsp_free);
438
439 /*
440 * Here we start the McBSP, by enabling transmitter, receiver or both.
441 * If no transmitter or receiver is active prior calling, then sample-rate
442 * generator and frame sync are started.
443 */
444 void omap_mcbsp_start(unsigned int id, int tx, int rx)
445 {
446 struct omap_mcbsp *mcbsp;
447 void __iomem *io_base;
448 int idle;
449 u16 w;
450
451 if (!omap_mcbsp_check_valid_id(id)) {
452 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
453 return;
454 }
455 mcbsp = id_to_mcbsp_ptr(id);
456 io_base = mcbsp->io_base;
457
458 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
459 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
460
461 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
462 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
463
464 if (idle) {
465 /* Start the sample generator */
466 w = OMAP_MCBSP_READ(io_base, SPCR2);
467 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
468 }
469
470 /* Enable transmitter and receiver */
471 w = OMAP_MCBSP_READ(io_base, SPCR2);
472 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
473
474 w = OMAP_MCBSP_READ(io_base, SPCR1);
475 OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
476
477 /*
478 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
479 * REVISIT: 100us may give enough time for two CLKSRG, however
480 * due to some unknown PM related, clock gating etc. reason it
481 * is now at 500us.
482 */
483 udelay(500);
484
485 if (idle) {
486 /* Start frame sync */
487 w = OMAP_MCBSP_READ(io_base, SPCR2);
488 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
489 }
490
491 /* Dump McBSP Regs */
492 omap_mcbsp_dump_reg(id);
493 }
494 EXPORT_SYMBOL(omap_mcbsp_start);
495
496 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
497 {
498 struct omap_mcbsp *mcbsp;
499 void __iomem *io_base;
500 int idle;
501 u16 w;
502
503 if (!omap_mcbsp_check_valid_id(id)) {
504 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
505 return;
506 }
507
508 mcbsp = id_to_mcbsp_ptr(id);
509 io_base = mcbsp->io_base;
510
511 /* Reset transmitter */
512 w = OMAP_MCBSP_READ(io_base, SPCR2);
513 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
514
515 /* Reset receiver */
516 w = OMAP_MCBSP_READ(io_base, SPCR1);
517 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
518
519 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
520 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
521
522 if (idle) {
523 /* Reset the sample rate generator */
524 w = OMAP_MCBSP_READ(io_base, SPCR2);
525 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
526 }
527 }
528 EXPORT_SYMBOL(omap_mcbsp_stop);
529
530 void omap_mcbsp_xmit_enable(unsigned int id, u8 enable)
531 {
532 struct omap_mcbsp *mcbsp;
533 void __iomem *io_base;
534 u16 w;
535
536 if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
537 return;
538
539 if (!omap_mcbsp_check_valid_id(id)) {
540 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
541 return;
542 }
543
544 mcbsp = id_to_mcbsp_ptr(id);
545 io_base = mcbsp->io_base;
546
547 w = OMAP_MCBSP_READ(io_base, XCCR);
548
549 if (enable)
550 OMAP_MCBSP_WRITE(io_base, XCCR, w & ~(XDISABLE));
551 else
552 OMAP_MCBSP_WRITE(io_base, XCCR, w | XDISABLE);
553 }
554 EXPORT_SYMBOL(omap_mcbsp_xmit_enable);
555
556 void omap_mcbsp_recv_enable(unsigned int id, u8 enable)
557 {
558 struct omap_mcbsp *mcbsp;
559 void __iomem *io_base;
560 u16 w;
561
562 if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
563 return;
564
565 if (!omap_mcbsp_check_valid_id(id)) {
566 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
567 return;
568 }
569
570 mcbsp = id_to_mcbsp_ptr(id);
571 io_base = mcbsp->io_base;
572
573 w = OMAP_MCBSP_READ(io_base, RCCR);
574
575 if (enable)
576 OMAP_MCBSP_WRITE(io_base, RCCR, w & ~(RDISABLE));
577 else
578 OMAP_MCBSP_WRITE(io_base, RCCR, w | RDISABLE);
579 }
580 EXPORT_SYMBOL(omap_mcbsp_recv_enable);
581
582 /* polled mcbsp i/o operations */
583 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
584 {
585 struct omap_mcbsp *mcbsp;
586 void __iomem *base;
587
588 if (!omap_mcbsp_check_valid_id(id)) {
589 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
590 return -ENODEV;
591 }
592
593 mcbsp = id_to_mcbsp_ptr(id);
594 base = mcbsp->io_base;
595
596 writew(buf, base + OMAP_MCBSP_REG_DXR1);
597 /* if frame sync error - clear the error */
598 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
599 /* clear error */
600 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
601 base + OMAP_MCBSP_REG_SPCR2);
602 /* resend */
603 return -1;
604 } else {
605 /* wait for transmit confirmation */
606 int attemps = 0;
607 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
608 if (attemps++ > 1000) {
609 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
610 (~XRST),
611 base + OMAP_MCBSP_REG_SPCR2);
612 udelay(10);
613 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
614 (XRST),
615 base + OMAP_MCBSP_REG_SPCR2);
616 udelay(10);
617 dev_err(mcbsp->dev, "Could not write to"
618 " McBSP%d Register\n", mcbsp->id);
619 return -2;
620 }
621 }
622 }
623
624 return 0;
625 }
626 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
627
628 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
629 {
630 struct omap_mcbsp *mcbsp;
631 void __iomem *base;
632
633 if (!omap_mcbsp_check_valid_id(id)) {
634 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
635 return -ENODEV;
636 }
637 mcbsp = id_to_mcbsp_ptr(id);
638
639 base = mcbsp->io_base;
640 /* if frame sync error - clear the error */
641 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
642 /* clear error */
643 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
644 base + OMAP_MCBSP_REG_SPCR1);
645 /* resend */
646 return -1;
647 } else {
648 /* wait for recieve confirmation */
649 int attemps = 0;
650 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
651 if (attemps++ > 1000) {
652 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
653 (~RRST),
654 base + OMAP_MCBSP_REG_SPCR1);
655 udelay(10);
656 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
657 (RRST),
658 base + OMAP_MCBSP_REG_SPCR1);
659 udelay(10);
660 dev_err(mcbsp->dev, "Could not read from"
661 " McBSP%d Register\n", mcbsp->id);
662 return -2;
663 }
664 }
665 }
666 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
667
668 return 0;
669 }
670 EXPORT_SYMBOL(omap_mcbsp_pollread);
671
672 /*
673 * IRQ based word transmission.
674 */
675 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
676 {
677 struct omap_mcbsp *mcbsp;
678 void __iomem *io_base;
679 omap_mcbsp_word_length word_length;
680
681 if (!omap_mcbsp_check_valid_id(id)) {
682 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
683 return;
684 }
685
686 mcbsp = id_to_mcbsp_ptr(id);
687 io_base = mcbsp->io_base;
688 word_length = mcbsp->tx_word_length;
689
690 wait_for_completion(&mcbsp->tx_irq_completion);
691
692 if (word_length > OMAP_MCBSP_WORD_16)
693 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
694 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
695 }
696 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
697
698 u32 omap_mcbsp_recv_word(unsigned int id)
699 {
700 struct omap_mcbsp *mcbsp;
701 void __iomem *io_base;
702 u16 word_lsb, word_msb = 0;
703 omap_mcbsp_word_length word_length;
704
705 if (!omap_mcbsp_check_valid_id(id)) {
706 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
707 return -ENODEV;
708 }
709 mcbsp = id_to_mcbsp_ptr(id);
710
711 word_length = mcbsp->rx_word_length;
712 io_base = mcbsp->io_base;
713
714 wait_for_completion(&mcbsp->rx_irq_completion);
715
716 if (word_length > OMAP_MCBSP_WORD_16)
717 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
718 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
719
720 return (word_lsb | (word_msb << 16));
721 }
722 EXPORT_SYMBOL(omap_mcbsp_recv_word);
723
724 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
725 {
726 struct omap_mcbsp *mcbsp;
727 void __iomem *io_base;
728 omap_mcbsp_word_length tx_word_length;
729 omap_mcbsp_word_length rx_word_length;
730 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
731
732 if (!omap_mcbsp_check_valid_id(id)) {
733 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
734 return -ENODEV;
735 }
736 mcbsp = id_to_mcbsp_ptr(id);
737 io_base = mcbsp->io_base;
738 tx_word_length = mcbsp->tx_word_length;
739 rx_word_length = mcbsp->rx_word_length;
740
741 if (tx_word_length != rx_word_length)
742 return -EINVAL;
743
744 /* First we wait for the transmitter to be ready */
745 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
746 while (!(spcr2 & XRDY)) {
747 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
748 if (attempts++ > 1000) {
749 /* We must reset the transmitter */
750 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
751 udelay(10);
752 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
753 udelay(10);
754 dev_err(mcbsp->dev, "McBSP%d transmitter not "
755 "ready\n", mcbsp->id);
756 return -EAGAIN;
757 }
758 }
759
760 /* Now we can push the data */
761 if (tx_word_length > OMAP_MCBSP_WORD_16)
762 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
763 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
764
765 /* We wait for the receiver to be ready */
766 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
767 while (!(spcr1 & RRDY)) {
768 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
769 if (attempts++ > 1000) {
770 /* We must reset the receiver */
771 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
772 udelay(10);
773 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
774 udelay(10);
775 dev_err(mcbsp->dev, "McBSP%d receiver not "
776 "ready\n", mcbsp->id);
777 return -EAGAIN;
778 }
779 }
780
781 /* Receiver is ready, let's read the dummy data */
782 if (rx_word_length > OMAP_MCBSP_WORD_16)
783 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
784 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
785
786 return 0;
787 }
788 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
789
790 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
791 {
792 struct omap_mcbsp *mcbsp;
793 u32 clock_word = 0;
794 void __iomem *io_base;
795 omap_mcbsp_word_length tx_word_length;
796 omap_mcbsp_word_length rx_word_length;
797 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
798
799 if (!omap_mcbsp_check_valid_id(id)) {
800 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
801 return -ENODEV;
802 }
803
804 mcbsp = id_to_mcbsp_ptr(id);
805 io_base = mcbsp->io_base;
806
807 tx_word_length = mcbsp->tx_word_length;
808 rx_word_length = mcbsp->rx_word_length;
809
810 if (tx_word_length != rx_word_length)
811 return -EINVAL;
812
813 /* First we wait for the transmitter to be ready */
814 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
815 while (!(spcr2 & XRDY)) {
816 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
817 if (attempts++ > 1000) {
818 /* We must reset the transmitter */
819 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
820 udelay(10);
821 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
822 udelay(10);
823 dev_err(mcbsp->dev, "McBSP%d transmitter not "
824 "ready\n", mcbsp->id);
825 return -EAGAIN;
826 }
827 }
828
829 /* We first need to enable the bus clock */
830 if (tx_word_length > OMAP_MCBSP_WORD_16)
831 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
832 OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
833
834 /* We wait for the receiver to be ready */
835 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
836 while (!(spcr1 & RRDY)) {
837 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
838 if (attempts++ > 1000) {
839 /* We must reset the receiver */
840 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
841 udelay(10);
842 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
843 udelay(10);
844 dev_err(mcbsp->dev, "McBSP%d receiver not "
845 "ready\n", mcbsp->id);
846 return -EAGAIN;
847 }
848 }
849
850 /* Receiver is ready, there is something for us */
851 if (rx_word_length > OMAP_MCBSP_WORD_16)
852 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
853 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
854
855 word[0] = (word_lsb | (word_msb << 16));
856
857 return 0;
858 }
859 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
860
861 /*
862 * Simple DMA based buffer rx/tx routines.
863 * Nothing fancy, just a single buffer tx/rx through DMA.
864 * The DMA resources are released once the transfer is done.
865 * For anything fancier, you should use your own customized DMA
866 * routines and callbacks.
867 */
868 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
869 unsigned int length)
870 {
871 struct omap_mcbsp *mcbsp;
872 int dma_tx_ch;
873 int src_port = 0;
874 int dest_port = 0;
875 int sync_dev = 0;
876
877 if (!omap_mcbsp_check_valid_id(id)) {
878 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
879 return -ENODEV;
880 }
881 mcbsp = id_to_mcbsp_ptr(id);
882
883 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
884 omap_mcbsp_tx_dma_callback,
885 mcbsp,
886 &dma_tx_ch)) {
887 dev_err(mcbsp->dev, " Unable to request DMA channel for "
888 "McBSP%d TX. Trying IRQ based TX\n",
889 mcbsp->id);
890 return -EAGAIN;
891 }
892 mcbsp->dma_tx_lch = dma_tx_ch;
893
894 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
895 dma_tx_ch);
896
897 init_completion(&mcbsp->tx_dma_completion);
898
899 if (cpu_class_is_omap1()) {
900 src_port = OMAP_DMA_PORT_TIPB;
901 dest_port = OMAP_DMA_PORT_EMIFF;
902 }
903 if (cpu_class_is_omap2())
904 sync_dev = mcbsp->dma_tx_sync;
905
906 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
907 OMAP_DMA_DATA_TYPE_S16,
908 length >> 1, 1,
909 OMAP_DMA_SYNC_ELEMENT,
910 sync_dev, 0);
911
912 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
913 src_port,
914 OMAP_DMA_AMODE_CONSTANT,
915 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
916 0, 0);
917
918 omap_set_dma_src_params(mcbsp->dma_tx_lch,
919 dest_port,
920 OMAP_DMA_AMODE_POST_INC,
921 buffer,
922 0, 0);
923
924 omap_start_dma(mcbsp->dma_tx_lch);
925 wait_for_completion(&mcbsp->tx_dma_completion);
926
927 return 0;
928 }
929 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
930
931 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
932 unsigned int length)
933 {
934 struct omap_mcbsp *mcbsp;
935 int dma_rx_ch;
936 int src_port = 0;
937 int dest_port = 0;
938 int sync_dev = 0;
939
940 if (!omap_mcbsp_check_valid_id(id)) {
941 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
942 return -ENODEV;
943 }
944 mcbsp = id_to_mcbsp_ptr(id);
945
946 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
947 omap_mcbsp_rx_dma_callback,
948 mcbsp,
949 &dma_rx_ch)) {
950 dev_err(mcbsp->dev, "Unable to request DMA channel for "
951 "McBSP%d RX. Trying IRQ based RX\n",
952 mcbsp->id);
953 return -EAGAIN;
954 }
955 mcbsp->dma_rx_lch = dma_rx_ch;
956
957 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
958 dma_rx_ch);
959
960 init_completion(&mcbsp->rx_dma_completion);
961
962 if (cpu_class_is_omap1()) {
963 src_port = OMAP_DMA_PORT_TIPB;
964 dest_port = OMAP_DMA_PORT_EMIFF;
965 }
966 if (cpu_class_is_omap2())
967 sync_dev = mcbsp->dma_rx_sync;
968
969 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
970 OMAP_DMA_DATA_TYPE_S16,
971 length >> 1, 1,
972 OMAP_DMA_SYNC_ELEMENT,
973 sync_dev, 0);
974
975 omap_set_dma_src_params(mcbsp->dma_rx_lch,
976 src_port,
977 OMAP_DMA_AMODE_CONSTANT,
978 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
979 0, 0);
980
981 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
982 dest_port,
983 OMAP_DMA_AMODE_POST_INC,
984 buffer,
985 0, 0);
986
987 omap_start_dma(mcbsp->dma_rx_lch);
988 wait_for_completion(&mcbsp->rx_dma_completion);
989
990 return 0;
991 }
992 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
993
994 /*
995 * SPI wrapper.
996 * Since SPI setup is much simpler than the generic McBSP one,
997 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
998 * Once this is done, you can call omap_mcbsp_start().
999 */
1000 void omap_mcbsp_set_spi_mode(unsigned int id,
1001 const struct omap_mcbsp_spi_cfg *spi_cfg)
1002 {
1003 struct omap_mcbsp *mcbsp;
1004 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1005
1006 if (!omap_mcbsp_check_valid_id(id)) {
1007 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1008 return;
1009 }
1010 mcbsp = id_to_mcbsp_ptr(id);
1011
1012 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1013
1014 /* SPI has only one frame */
1015 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1016 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1017
1018 /* Clock stop mode */
1019 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1020 mcbsp_cfg.spcr1 |= (1 << 12);
1021 else
1022 mcbsp_cfg.spcr1 |= (3 << 11);
1023
1024 /* Set clock parities */
1025 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1026 mcbsp_cfg.pcr0 |= CLKRP;
1027 else
1028 mcbsp_cfg.pcr0 &= ~CLKRP;
1029
1030 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1031 mcbsp_cfg.pcr0 &= ~CLKXP;
1032 else
1033 mcbsp_cfg.pcr0 |= CLKXP;
1034
1035 /* Set SCLKME to 0 and CLKSM to 1 */
1036 mcbsp_cfg.pcr0 &= ~SCLKME;
1037 mcbsp_cfg.srgr2 |= CLKSM;
1038
1039 /* Set FSXP */
1040 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1041 mcbsp_cfg.pcr0 &= ~FSXP;
1042 else
1043 mcbsp_cfg.pcr0 |= FSXP;
1044
1045 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1046 mcbsp_cfg.pcr0 |= CLKXM;
1047 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1048 mcbsp_cfg.pcr0 |= FSXM;
1049 mcbsp_cfg.srgr2 &= ~FSGM;
1050 mcbsp_cfg.xcr2 |= XDATDLY(1);
1051 mcbsp_cfg.rcr2 |= RDATDLY(1);
1052 } else {
1053 mcbsp_cfg.pcr0 &= ~CLKXM;
1054 mcbsp_cfg.srgr1 |= CLKGDV(1);
1055 mcbsp_cfg.pcr0 &= ~FSXM;
1056 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1057 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1058 }
1059
1060 mcbsp_cfg.xcr2 &= ~XPHASE;
1061 mcbsp_cfg.rcr2 &= ~RPHASE;
1062
1063 omap_mcbsp_config(id, &mcbsp_cfg);
1064 }
1065 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1066
1067 #ifdef CONFIG_ARCH_OMAP34XX
1068 #define max_thres(m) (mcbsp->pdata->buffer_size)
1069 #define valid_threshold(m, val) ((val) <= max_thres(m))
1070 #define THRESHOLD_PROP_BUILDER(prop) \
1071 static ssize_t prop##_show(struct device *dev, \
1072 struct device_attribute *attr, char *buf) \
1073 { \
1074 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1075 \
1076 return sprintf(buf, "%u\n", mcbsp->prop); \
1077 } \
1078 \
1079 static ssize_t prop##_store(struct device *dev, \
1080 struct device_attribute *attr, \
1081 const char *buf, size_t size) \
1082 { \
1083 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1084 unsigned long val; \
1085 int status; \
1086 \
1087 status = strict_strtoul(buf, 0, &val); \
1088 if (status) \
1089 return status; \
1090 \
1091 if (!valid_threshold(mcbsp, val)) \
1092 return -EDOM; \
1093 \
1094 mcbsp->prop = val; \
1095 return size; \
1096 } \
1097 \
1098 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1099
1100 THRESHOLD_PROP_BUILDER(max_tx_thres);
1101 THRESHOLD_PROP_BUILDER(max_rx_thres);
1102
1103 static ssize_t dma_op_mode_show(struct device *dev,
1104 struct device_attribute *attr, char *buf)
1105 {
1106 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1107 int dma_op_mode;
1108
1109 spin_lock_irq(&mcbsp->lock);
1110 dma_op_mode = mcbsp->dma_op_mode;
1111 spin_unlock_irq(&mcbsp->lock);
1112
1113 return sprintf(buf, "current mode: %d\n"
1114 "possible mode values are:\n"
1115 "%d - %s\n"
1116 "%d - %s\n"
1117 "%d - %s\n",
1118 dma_op_mode,
1119 MCBSP_DMA_MODE_ELEMENT, "element mode",
1120 MCBSP_DMA_MODE_THRESHOLD, "threshold mode",
1121 MCBSP_DMA_MODE_FRAME, "frame mode");
1122 }
1123
1124 static ssize_t dma_op_mode_store(struct device *dev,
1125 struct device_attribute *attr,
1126 const char *buf, size_t size)
1127 {
1128 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1129 unsigned long val;
1130 int status;
1131
1132 status = strict_strtoul(buf, 0, &val);
1133 if (status)
1134 return status;
1135
1136 spin_lock_irq(&mcbsp->lock);
1137
1138 if (!mcbsp->free) {
1139 size = -EBUSY;
1140 goto unlock;
1141 }
1142
1143 if (val > MCBSP_DMA_MODE_FRAME || val < MCBSP_DMA_MODE_ELEMENT) {
1144 size = -EINVAL;
1145 goto unlock;
1146 }
1147
1148 mcbsp->dma_op_mode = val;
1149
1150 unlock:
1151 spin_unlock_irq(&mcbsp->lock);
1152
1153 return size;
1154 }
1155
1156 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1157
1158 static const struct attribute *additional_attrs[] = {
1159 &dev_attr_max_tx_thres.attr,
1160 &dev_attr_max_rx_thres.attr,
1161 &dev_attr_dma_op_mode.attr,
1162 NULL,
1163 };
1164
1165 static const struct attribute_group additional_attr_group = {
1166 .attrs = (struct attribute **)additional_attrs,
1167 };
1168
1169 static inline int __devinit omap_additional_add(struct device *dev)
1170 {
1171 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1172 }
1173
1174 static inline void __devexit omap_additional_remove(struct device *dev)
1175 {
1176 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1177 }
1178
1179 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1180 {
1181 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1182 if (cpu_is_omap34xx()) {
1183 mcbsp->max_tx_thres = max_thres(mcbsp);
1184 mcbsp->max_rx_thres = max_thres(mcbsp);
1185 /*
1186 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1187 * for mcbsp2 instances.
1188 */
1189 if (omap_additional_add(mcbsp->dev))
1190 dev_warn(mcbsp->dev,
1191 "Unable to create additional controls\n");
1192 } else {
1193 mcbsp->max_tx_thres = -EINVAL;
1194 mcbsp->max_rx_thres = -EINVAL;
1195 }
1196 }
1197
1198 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1199 {
1200 if (cpu_is_omap34xx())
1201 omap_additional_remove(mcbsp->dev);
1202 }
1203 #else
1204 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1205 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1206 #endif /* CONFIG_ARCH_OMAP34XX */
1207
1208 /*
1209 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1210 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1211 */
1212 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1213 {
1214 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1215 struct omap_mcbsp *mcbsp;
1216 int id = pdev->id - 1;
1217 int ret = 0;
1218
1219 if (!pdata) {
1220 dev_err(&pdev->dev, "McBSP device initialized without"
1221 "platform data\n");
1222 ret = -EINVAL;
1223 goto exit;
1224 }
1225
1226 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1227
1228 if (id >= omap_mcbsp_count) {
1229 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1230 ret = -EINVAL;
1231 goto exit;
1232 }
1233
1234 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1235 if (!mcbsp) {
1236 ret = -ENOMEM;
1237 goto exit;
1238 }
1239
1240 spin_lock_init(&mcbsp->lock);
1241 mcbsp->id = id + 1;
1242 mcbsp->free = 1;
1243 mcbsp->dma_tx_lch = -1;
1244 mcbsp->dma_rx_lch = -1;
1245
1246 mcbsp->phys_base = pdata->phys_base;
1247 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1248 if (!mcbsp->io_base) {
1249 ret = -ENOMEM;
1250 goto err_ioremap;
1251 }
1252
1253 /* Default I/O is IRQ based */
1254 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1255 mcbsp->tx_irq = pdata->tx_irq;
1256 mcbsp->rx_irq = pdata->rx_irq;
1257 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1258 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1259
1260 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1261 if (IS_ERR(mcbsp->iclk)) {
1262 ret = PTR_ERR(mcbsp->iclk);
1263 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1264 goto err_iclk;
1265 }
1266
1267 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1268 if (IS_ERR(mcbsp->fclk)) {
1269 ret = PTR_ERR(mcbsp->fclk);
1270 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1271 goto err_fclk;
1272 }
1273
1274 mcbsp->pdata = pdata;
1275 mcbsp->dev = &pdev->dev;
1276 mcbsp_ptr[id] = mcbsp;
1277 platform_set_drvdata(pdev, mcbsp);
1278
1279 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1280 omap34xx_device_init(mcbsp);
1281
1282 return 0;
1283
1284 err_fclk:
1285 clk_put(mcbsp->iclk);
1286 err_iclk:
1287 iounmap(mcbsp->io_base);
1288 err_ioremap:
1289 kfree(mcbsp);
1290 exit:
1291 return ret;
1292 }
1293
1294 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1295 {
1296 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1297
1298 platform_set_drvdata(pdev, NULL);
1299 if (mcbsp) {
1300
1301 if (mcbsp->pdata && mcbsp->pdata->ops &&
1302 mcbsp->pdata->ops->free)
1303 mcbsp->pdata->ops->free(mcbsp->id);
1304
1305 omap34xx_device_exit(mcbsp);
1306
1307 clk_disable(mcbsp->fclk);
1308 clk_disable(mcbsp->iclk);
1309 clk_put(mcbsp->fclk);
1310 clk_put(mcbsp->iclk);
1311
1312 iounmap(mcbsp->io_base);
1313
1314 mcbsp->fclk = NULL;
1315 mcbsp->iclk = NULL;
1316 mcbsp->free = 0;
1317 mcbsp->dev = NULL;
1318 }
1319
1320 return 0;
1321 }
1322
1323 static struct platform_driver omap_mcbsp_driver = {
1324 .probe = omap_mcbsp_probe,
1325 .remove = __devexit_p(omap_mcbsp_remove),
1326 .driver = {
1327 .name = "omap-mcbsp",
1328 },
1329 };
1330
1331 int __init omap_mcbsp_init(void)
1332 {
1333 /* Register the McBSP driver */
1334 return platform_driver_register(&omap_mcbsp_driver);
1335 }
CJK support for tty framebuffer vt