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[PATCH] rtl8187: Fix more frag bit checking, rts duration calc
[linux-2.6/cjktty.git] / drivers / net / tulip / media.c
blobb56256636543f0685f38ab0cd30023335194367b
1 /*
2 drivers/net/tulip/media.c
3
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include "tulip.h"
23
24
25 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
26 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
27 "overclocking" issues or future 66Mhz PCI. */
28 #define mdio_delay() ioread32(mdio_addr)
29
30 /* Read and write the MII registers using software-generated serial
31 MDIO protocol. It is just different enough from the EEPROM protocol
32 to not share code. The maxium data clock rate is 2.5 Mhz. */
33 #define MDIO_SHIFT_CLK 0x10000
34 #define MDIO_DATA_WRITE0 0x00000
35 #define MDIO_DATA_WRITE1 0x20000
36 #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
37 #define MDIO_ENB_IN 0x40000
38 #define MDIO_DATA_READ 0x80000
39
40 static const unsigned char comet_miireg2offset[32] = {
41 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
42 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
43
44
45 /* MII transceiver control section.
46 Read and write the MII registers using software-generated serial
47 MDIO protocol.
48 See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
49 or DP83840A data sheet for more details.
50 */
51
52 int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
53 {
54 struct tulip_private *tp = netdev_priv(dev);
55 int i;
56 int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
57 int retval = 0;
58 void __iomem *ioaddr = tp->base_addr;
59 void __iomem *mdio_addr = ioaddr + CSR9;
60 unsigned long flags;
61
62 if (location & ~0x1f)
63 return 0xffff;
64
65 if (tp->chip_id == COMET && phy_id == 30) {
66 if (comet_miireg2offset[location])
67 return ioread32(ioaddr + comet_miireg2offset[location]);
68 return 0xffff;
69 }
70
71 spin_lock_irqsave(&tp->mii_lock, flags);
72 if (tp->chip_id == LC82C168) {
73 int i = 1000;
74 iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
75 ioread32(ioaddr + 0xA0);
76 ioread32(ioaddr + 0xA0);
77 while (--i > 0) {
78 barrier();
79 if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
80 break;
81 }
82 spin_unlock_irqrestore(&tp->mii_lock, flags);
83 return retval & 0xffff;
84 }
85
86 /* Establish sync by sending at least 32 logic ones. */
87 for (i = 32; i >= 0; i--) {
88 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
89 mdio_delay();
90 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
91 mdio_delay();
92 }
93 /* Shift the read command bits out. */
94 for (i = 15; i >= 0; i--) {
95 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
96
97 iowrite32(MDIO_ENB | dataval, mdio_addr);
98 mdio_delay();
99 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
100 mdio_delay();
101 }
102 /* Read the two transition, 16 data, and wire-idle bits. */
103 for (i = 19; i > 0; i--) {
104 iowrite32(MDIO_ENB_IN, mdio_addr);
105 mdio_delay();
106 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
107 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
108 mdio_delay();
109 }
110
111 spin_unlock_irqrestore(&tp->mii_lock, flags);
112 return (retval>>1) & 0xffff;
113 }
114
115 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
116 {
117 struct tulip_private *tp = netdev_priv(dev);
118 int i;
119 int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
120 void __iomem *ioaddr = tp->base_addr;
121 void __iomem *mdio_addr = ioaddr + CSR9;
122 unsigned long flags;
123
124 if (location & ~0x1f)
125 return;
126
127 if (tp->chip_id == COMET && phy_id == 30) {
128 if (comet_miireg2offset[location])
129 iowrite32(val, ioaddr + comet_miireg2offset[location]);
130 return;
131 }
132
133 spin_lock_irqsave(&tp->mii_lock, flags);
134 if (tp->chip_id == LC82C168) {
135 int i = 1000;
136 iowrite32(cmd, ioaddr + 0xA0);
137 do {
138 barrier();
139 if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
140 break;
141 } while (--i > 0);
142 spin_unlock_irqrestore(&tp->mii_lock, flags);
143 return;
144 }
145
146 /* Establish sync by sending 32 logic ones. */
147 for (i = 32; i >= 0; i--) {
148 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
149 mdio_delay();
150 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
151 mdio_delay();
152 }
153 /* Shift the command bits out. */
154 for (i = 31; i >= 0; i--) {
155 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
156 iowrite32(MDIO_ENB | dataval, mdio_addr);
157 mdio_delay();
158 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
159 mdio_delay();
160 }
161 /* Clear out extra bits. */
162 for (i = 2; i > 0; i--) {
163 iowrite32(MDIO_ENB_IN, mdio_addr);
164 mdio_delay();
165 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
166 mdio_delay();
167 }
168
169 spin_unlock_irqrestore(&tp->mii_lock, flags);
170 }
171
172
173 /* Set up the transceiver control registers for the selected media type. */
174 void tulip_select_media(struct net_device *dev, int startup)
175 {
176 struct tulip_private *tp = netdev_priv(dev);
177 void __iomem *ioaddr = tp->base_addr;
178 struct mediatable *mtable = tp->mtable;
179 u32 new_csr6;
180 int i;
181
182 if (mtable) {
183 struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
184 unsigned char *p = mleaf->leafdata;
185 switch (mleaf->type) {
186 case 0: /* 21140 non-MII xcvr. */
187 if (tulip_debug > 1)
188 printk(KERN_DEBUG "%s: Using a 21140 non-MII transceiver"
189 " with control setting %2.2x.\n",
190 dev->name, p[1]);
191 dev->if_port = p[0];
192 if (startup)
193 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
194 iowrite32(p[1], ioaddr + CSR12);
195 new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
196 break;
197 case 2: case 4: {
198 u16 setup[5];
199 u32 csr13val, csr14val, csr15dir, csr15val;
200 for (i = 0; i < 5; i++)
201 setup[i] = get_u16(&p[i*2 + 1]);
202
203 dev->if_port = p[0] & MEDIA_MASK;
204 if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
205 tp->full_duplex = 1;
206
207 if (startup && mtable->has_reset) {
208 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
209 unsigned char *rst = rleaf->leafdata;
210 if (tulip_debug > 1)
211 printk(KERN_DEBUG "%s: Resetting the transceiver.\n",
212 dev->name);
213 for (i = 0; i < rst[0]; i++)
214 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
215 }
216 if (tulip_debug > 1)
217 printk(KERN_DEBUG "%s: 21143 non-MII %s transceiver control "
218 "%4.4x/%4.4x.\n",
219 dev->name, medianame[dev->if_port], setup[0], setup[1]);
220 if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
221 csr13val = setup[0];
222 csr14val = setup[1];
223 csr15dir = (setup[3]<<16) | setup[2];
224 csr15val = (setup[4]<<16) | setup[2];
225 iowrite32(0, ioaddr + CSR13);
226 iowrite32(csr14val, ioaddr + CSR14);
227 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
228 iowrite32(csr15val, ioaddr + CSR15); /* Data */
229 iowrite32(csr13val, ioaddr + CSR13);
230 } else {
231 csr13val = 1;
232 csr14val = 0;
233 csr15dir = (setup[0]<<16) | 0x0008;
234 csr15val = (setup[1]<<16) | 0x0008;
235 if (dev->if_port <= 4)
236 csr14val = t21142_csr14[dev->if_port];
237 if (startup) {
238 iowrite32(0, ioaddr + CSR13);
239 iowrite32(csr14val, ioaddr + CSR14);
240 }
241 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
242 iowrite32(csr15val, ioaddr + CSR15); /* Data */
243 if (startup) iowrite32(csr13val, ioaddr + CSR13);
244 }
245 if (tulip_debug > 1)
246 printk(KERN_DEBUG "%s: Setting CSR15 to %8.8x/%8.8x.\n",
247 dev->name, csr15dir, csr15val);
248 if (mleaf->type == 4)
249 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
250 else
251 new_csr6 = 0x82420000;
252 break;
253 }
254 case 1: case 3: {
255 int phy_num = p[0];
256 int init_length = p[1];
257 u16 *misc_info, tmp_info;
258
259 dev->if_port = 11;
260 new_csr6 = 0x020E0000;
261 if (mleaf->type == 3) { /* 21142 */
262 u16 *init_sequence = (u16*)(p+2);
263 u16 *reset_sequence = &((u16*)(p+3))[init_length];
264 int reset_length = p[2 + init_length*2];
265 misc_info = reset_sequence + reset_length;
266 if (startup) {
267 int timeout = 10; /* max 1 ms */
268 for (i = 0; i < reset_length; i++)
269 iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
270
271 /* flush posted writes */
272 ioread32(ioaddr + CSR15);
273
274 /* Sect 3.10.3 in DP83840A.pdf (p39) */
275 udelay(500);
276
277 /* Section 4.2 in DP83840A.pdf (p43) */
278 /* and IEEE 802.3 "22.2.4.1.1 Reset" */
279 while (timeout-- &&
280 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
281 udelay(100);
282 }
283 for (i = 0; i < init_length; i++)
284 iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
285
286 ioread32(ioaddr + CSR15); /* flush posted writes */
287 } else {
288 u8 *init_sequence = p + 2;
289 u8 *reset_sequence = p + 3 + init_length;
290 int reset_length = p[2 + init_length];
291 misc_info = (u16*)(reset_sequence + reset_length);
292 if (startup) {
293 int timeout = 10; /* max 1 ms */
294 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
295 for (i = 0; i < reset_length; i++)
296 iowrite32(reset_sequence[i], ioaddr + CSR12);
297
298 /* flush posted writes */
299 ioread32(ioaddr + CSR12);
300
301 /* Sect 3.10.3 in DP83840A.pdf (p39) */
302 udelay(500);
303
304 /* Section 4.2 in DP83840A.pdf (p43) */
305 /* and IEEE 802.3 "22.2.4.1.1 Reset" */
306 while (timeout-- &&
307 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
308 udelay(100);
309 }
310 for (i = 0; i < init_length; i++)
311 iowrite32(init_sequence[i], ioaddr + CSR12);
312
313 ioread32(ioaddr + CSR12); /* flush posted writes */
314 }
315
316 tmp_info = get_u16(&misc_info[1]);
317 if (tmp_info)
318 tp->advertising[phy_num] = tmp_info | 1;
319 if (tmp_info && startup < 2) {
320 if (tp->mii_advertise == 0)
321 tp->mii_advertise = tp->advertising[phy_num];
322 if (tulip_debug > 1)
323 printk(KERN_DEBUG "%s: Advertising %4.4x on MII %d.\n",
324 dev->name, tp->mii_advertise, tp->phys[phy_num]);
325 tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
326 }
327 break;
328 }
329 case 5: case 6: {
330 u16 setup[5];
331
332 new_csr6 = 0; /* FIXME */
333
334 for (i = 0; i < 5; i++)
335 setup[i] = get_u16(&p[i*2 + 1]);
336
337 if (startup && mtable->has_reset) {
338 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
339 unsigned char *rst = rleaf->leafdata;
340 if (tulip_debug > 1)
341 printk(KERN_DEBUG "%s: Resetting the transceiver.\n",
342 dev->name);
343 for (i = 0; i < rst[0]; i++)
344 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
345 }
346
347 break;
348 }
349 default:
350 printk(KERN_DEBUG "%s: Invalid media table selection %d.\n",
351 dev->name, mleaf->type);
352 new_csr6 = 0x020E0000;
353 }
354 if (tulip_debug > 1)
355 printk(KERN_DEBUG "%s: Using media type %s, CSR12 is %2.2x.\n",
356 dev->name, medianame[dev->if_port],
357 ioread32(ioaddr + CSR12) & 0xff);
358 } else if (tp->chip_id == LC82C168) {
359 if (startup && ! tp->medialock)
360 dev->if_port = tp->mii_cnt ? 11 : 0;
361 if (tulip_debug > 1)
362 printk(KERN_DEBUG "%s: PNIC PHY status is %3.3x, media %s.\n",
363 dev->name, ioread32(ioaddr + 0xB8), medianame[dev->if_port]);
364 if (tp->mii_cnt) {
365 new_csr6 = 0x810C0000;
366 iowrite32(0x0001, ioaddr + CSR15);
367 iowrite32(0x0201B07A, ioaddr + 0xB8);
368 } else if (startup) {
369 /* Start with 10mbps to do autonegotiation. */
370 iowrite32(0x32, ioaddr + CSR12);
371 new_csr6 = 0x00420000;
372 iowrite32(0x0001B078, ioaddr + 0xB8);
373 iowrite32(0x0201B078, ioaddr + 0xB8);
374 } else if (dev->if_port == 3 || dev->if_port == 5) {
375 iowrite32(0x33, ioaddr + CSR12);
376 new_csr6 = 0x01860000;
377 /* Trigger autonegotiation. */
378 iowrite32(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8);
379 } else {
380 iowrite32(0x32, ioaddr + CSR12);
381 new_csr6 = 0x00420000;
382 iowrite32(0x1F078, ioaddr + 0xB8);
383 }
384 } else { /* Unknown chip type with no media table. */
385 if (tp->default_port == 0)
386 dev->if_port = tp->mii_cnt ? 11 : 3;
387 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
388 new_csr6 = 0x020E0000;
389 } else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
390 new_csr6 = 0x02860000;
391 } else
392 new_csr6 = 0x03860000;
393 if (tulip_debug > 1)
394 printk(KERN_DEBUG "%s: No media description table, assuming "
395 "%s transceiver, CSR12 %2.2x.\n",
396 dev->name, medianame[dev->if_port],
397 ioread32(ioaddr + CSR12));
398 }
399
400 tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
401
402 mdelay(1);
403
404 return;
405 }
406
407 /*
408 Check the MII negotiated duplex and change the CSR6 setting if
409 required.
410 Return 0 if everything is OK.
411 Return < 0 if the transceiver is missing or has no link beat.
412 */
413 int tulip_check_duplex(struct net_device *dev)
414 {
415 struct tulip_private *tp = netdev_priv(dev);
416 unsigned int bmsr, lpa, negotiated, new_csr6;
417
418 bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
419 lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
420 if (tulip_debug > 1)
421 printk(KERN_INFO "%s: MII status %4.4x, Link partner report "
422 "%4.4x.\n", dev->name, bmsr, lpa);
423 if (bmsr == 0xffff)
424 return -2;
425 if ((bmsr & BMSR_LSTATUS) == 0) {
426 int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
427 if ((new_bmsr & BMSR_LSTATUS) == 0) {
428 if (tulip_debug > 1)
429 printk(KERN_INFO "%s: No link beat on the MII interface,"
430 " status %4.4x.\n", dev->name, new_bmsr);
431 return -1;
432 }
433 }
434 negotiated = lpa & tp->advertising[0];
435 tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
436
437 new_csr6 = tp->csr6;
438
439 if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
440 else new_csr6 |= TxThreshold;
441 if (tp->full_duplex) new_csr6 |= FullDuplex;
442 else new_csr6 &= ~FullDuplex;
443
444 if (new_csr6 != tp->csr6) {
445 tp->csr6 = new_csr6;
446 tulip_restart_rxtx(tp);
447
448 if (tulip_debug > 0)
449 printk(KERN_INFO "%s: Setting %s-duplex based on MII"
450 "#%d link partner capability of %4.4x.\n",
451 dev->name, tp->full_duplex ? "full" : "half",
452 tp->phys[0], lpa);
453 return 1;
454 }
455
456 return 0;
457 }
458
459 void __devinit tulip_find_mii (struct net_device *dev, int board_idx)
460 {
461 struct tulip_private *tp = netdev_priv(dev);
462 int phyn, phy_idx = 0;
463 int mii_reg0;
464 int mii_advert;
465 unsigned int to_advert, new_bmcr, ane_switch;
466
467 /* Find the connected MII xcvrs.
468 Doing this in open() would allow detecting external xcvrs later,
469 but takes much time. */
470 for (phyn = 1; phyn <= 32 && phy_idx < sizeof (tp->phys); phyn++) {
471 int phy = phyn & 0x1f;
472 int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
473 if ((mii_status & 0x8301) == 0x8001 ||
474 ((mii_status & BMSR_100BASE4) == 0
475 && (mii_status & 0x7800) != 0)) {
476 /* preserve Becker logic, gain indentation level */
477 } else {
478 continue;
479 }
480
481 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
482 mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
483 ane_switch = 0;
484
485 /* if not advertising at all, gen an
486 * advertising value from the capability
487 * bits in BMSR
488 */
489 if ((mii_advert & ADVERTISE_ALL) == 0) {
490 unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
491 mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
492 }
493
494 if (tp->mii_advertise) {
495 tp->advertising[phy_idx] =
496 to_advert = tp->mii_advertise;
497 } else if (tp->advertising[phy_idx]) {
498 to_advert = tp->advertising[phy_idx];
499 } else {
500 tp->advertising[phy_idx] =
501 tp->mii_advertise =
502 to_advert = mii_advert;
503 }
504
505 tp->phys[phy_idx++] = phy;
506
507 printk (KERN_INFO "tulip%d: MII transceiver #%d "
508 "config %4.4x status %4.4x advertising %4.4x.\n",
509 board_idx, phy, mii_reg0, mii_status, mii_advert);
510
511 /* Fixup for DLink with miswired PHY. */
512 if (mii_advert != to_advert) {
513 printk (KERN_DEBUG "tulip%d: Advertising %4.4x on PHY %d,"
514 " previously advertising %4.4x.\n",
515 board_idx, to_advert, phy, mii_advert);
516 tulip_mdio_write (dev, phy, 4, to_advert);
517 }
518
519 /* Enable autonegotiation: some boards default to off. */
520 if (tp->default_port == 0) {
521 new_bmcr = mii_reg0 | BMCR_ANENABLE;
522 if (new_bmcr != mii_reg0) {
523 new_bmcr |= BMCR_ANRESTART;
524 ane_switch = 1;
525 }
526 }
527 /* ...or disable nway, if forcing media */
528 else {
529 new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
530 if (new_bmcr != mii_reg0)
531 ane_switch = 1;
532 }
533
534 /* clear out bits we never want at this point */
535 new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
536 BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
537 BMCR_RESET);
538
539 if (tp->full_duplex)
540 new_bmcr |= BMCR_FULLDPLX;
541 if (tulip_media_cap[tp->default_port] & MediaIs100)
542 new_bmcr |= BMCR_SPEED100;
543
544 if (new_bmcr != mii_reg0) {
545 /* some phys need the ANE switch to
546 * happen before forced media settings
547 * will "take." However, we write the
548 * same value twice in order not to
549 * confuse the sane phys.
550 */
551 if (ane_switch) {
552 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
553 udelay (10);
554 }
555 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
556 }
557 }
558 tp->mii_cnt = phy_idx;
559 if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
560 printk (KERN_INFO "tulip%d: ***WARNING***: No MII transceiver found!\n",
561 board_idx);
562 tp->phys[0] = 1;
563 }
564 }
CJK support for tty framebuffer vt